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diff --git a/lib/isabelle/manual/Manual.thy b/lib/isabelle/manual/Manual.thy index 53175ec9..6cdfbfa1 100644 --- a/lib/isabelle/manual/Manual.thy +++ b/lib/isabelle/manual/Manual.thy @@ -24,7 +24,7 @@ follow the instructions. In order to generate theorem prover definitions, Sail specifications are first translated to Lem, which then generates definitions for Isabelle/HOL. Lem can also generate HOL4 definitions, though we have -not yet tested that for our ISA specifications. To produce Coq +not yet tested that extensively for our ISA specifications. To produce Coq definitions, we envisage implementing a direct Sail-to-Coq backend, to preserve the Sail dependent types (it's possible that the Lem-to-Coq backend, which in general does not produce good Coq definitions, would diff --git a/lib/isabelle/manual/document.pdf b/snapshots/isabelle/Manual.pdf Binary files differindex 200f8e22..62066f8f 100644 --- a/lib/isabelle/manual/document.pdf +++ b/snapshots/isabelle/Manual.pdf diff --git a/snapshots/isabelle/Manual.thy b/snapshots/isabelle/Manual.thy new file mode 100644 index 00000000..c9eaa18a --- /dev/null +++ b/snapshots/isabelle/Manual.thy @@ -0,0 +1,464 @@ +(*<*) +theory Manual + imports + Sail.State_lemmas + Sail.Sail_operators_mwords_lemmas + Sail.Hoare + "riscv/Riscv_duopod_lemmas" +begin + +declare [[show_question_marks = false]] +(*>*) + +section \<open>Getting Started\<close> + +text \<open>This manual describes how to use Sail specifications for reasoning in Isabelle/HOL. +For instructions on how to set up the Sail tool and its dependencies, see @{path INSTALL.md}. +As an additional setup step for Isabelle generation, it is useful to build an Isabelle heap image +of the Sail library. +This will allow you to start Isabelle with the Sail library pre-loaded using the +@{verbatim "-l Sail"} option. +For this purpose, run @{verbatim "make heap-img"} in the @{path "lib/isabelle"} subdirectory of Sail and +follow the instructions. + +In order to generate theorem prover definitions, Sail specifications +are first translated to Lem, which then generates definitions for +Isabelle/HOL. Lem can also generate HOL4 definitions, though we have +not yet tested that extensively for our ISA specifications. To produce Coq +definitions, we envisage implementing a direct Sail-to-Coq backend, to +preserve the Sail dependent types (it's possible that the Lem-to-Coq +backend, which in general does not produce good Coq definitions, would +actually produce usable Coq definitions for a monomorphised ISA +specification, but we have not tested that). + +The translation to Lem is activated by passing the @{verbatim "-lem"} command line flag to Sail. +For example, the following call in the @{path riscv} directory will generate Lem definitions +for the RISC-V "duopod" (a fragment of the RISC-V specification with only two instructions, +used for illustration purposes): +@{verbatim [display] +"sail -lem -o riscv_duopod -lem_mwords -lem_lib Riscv_extras + prelude.sail riscv_duopod.sail"} +This uses the following options: + \<^item> @{verbatim "-lem"} activates the generation of Lem definitions. + \<^item> @{verbatim "-o riscv_duopod"} specifies the prefix for the output filenames. This invocation + of Sail will generate the files + \<^item> @{path riscv_duopod_types.lem}, containing the definitions of the types used in the + specification, + \<^item> @{path riscv_duopod.lem}, containing the main definitions, e.g.~of the instructions, and + \<^item> @{path Riscv_duopod_lemmas.thy} containing generated helper lemmas, (currently) mainly + simplification rules for lifting register reads and writes from the free monad to the + state monad supported by Sail (cf.~Section~\ref{sec:monads}). + \<^item> @{verbatim "-lem_mwords"} specifies that the generated definitions should use the machine + word representation of bitvectors (cf.~Section~\ref{sec:mwords}). This works out-of-the-box + for the RISC-V specification, but might require monomorphisation (e.g.~using the + @{verbatim "-auto_mono"} command line flag) for specifications that have functions that + are polymorphic in bitvector lengths. + \<^item> @{verbatim "-lem_lib Riscv_extras"} specifies an additional Lem library to be imported. + It contains Lem implementations for some wrappers and primitive functions that are declared + as external functions in the Sail source code, such as wrappers for reading and writing memory. + +Isabelle definitions can then be generated by passing the @{verbatim "-isa"} flag to Lem. +In order for Lem to find the Sail library, the subdirectories @{path "src/gen_lib"} and +@{path "src/lem_interp"} of Sail will have to be added to Lem's include path using the +@{verbatim "-lib"} option, e.g. + +@{verbatim [display] +"lem -isa -outdir . -lib ../src/lem_interp -lib ../src/gen_lib + riscv_extras.lem riscv_duopod_types.lem riscv_duopod.lem"} + +For further examples, see the @{path Makefile}s of the other specifications included in the Sail +distribution.\<close> + +section \<open>An Example of a Sail Specification in Isabelle/HOL\<close> + +text \<open>A Sail specification typically comprises a @{term decode} function specifying a mapping from raw +instruction opcodes to a more abstract representation, an @{term execute} function specifying the +behaviour of instructions, further auxiliary functions and datatypes, and register declarations. + +For example, in the RISC-V duopod, there are two instructions: a load instruction and an +add instruction with one register and one immediate operand. Their abstract syntax is represented +using the following datatype: +@{datatype [display] ast} +Both instructions take an immediate 12-bit argument (used as an offset in the case of the load +instruction), and two 5-bit arguments encoding the source and the destination register, +respectively. The @{term ITYPE} instruction takes another argument encoding the type of operation +(where only addition is implemented in the ``duopod'' fragment of RISC-V). + +The function @{term [source] "decode :: 32 word \<Rightarrow> ast option"} is implemented in the Sail source +code using bitvector pattern matching on the opcode. The Lem backend translates this to an +if-then-else-cascade that compares the given opcode against one pattern after another: +@{thm [display] decode_def[of opcode for opcode]} +This decode function is pure, although decoding might be effectful in other specifications (e.g., +because the decoding depends on the register state). Sail uses its effect system to determine +whether a function has side-effects and needs to be be monadic (cf.~Section~\ref{sec:monads} for +more details about the monads). + +The @{term execute} function, for example, is monadic. +Its clause for the load instruction of the RISC-V duopod is defined as follows, where +@{text \<bind>} is infix syntax for the monadic bind: +@{thm [display] execute_LOAD_def[of imm rs rd for imm rs rd]} +The instruction first reads the base address from the source register @{term rs}, then adds the +offset given in the immediate argument @{term imm}, calls the @{term MEMr} auxiliary function to +read eight bytes starting at the calculated address, and writes the result into the destination +register @{term rd}. + +Note that the @{term execute} function is special-cased in that Sail attempts to split it up into +auxiliary functions (one per AST node) in order to avoid letting it become too large. The main +@{term execute} function dispatches its inputs to the auxiliary functions: +@{thm [display] execute.simps[of imm rs rd for imm rs rd]} + +Apart from function and type definitions, Sail source code contains register declarations. +A @{type regstate} record gets generated from these for use in the state monad, e.g. +@{theory_text [display] +\<open>record regstate = + Xs ::" ( 64 Word.word) list " + nextPC ::" 64 Word.word " + PC ::" 64 Word.word "\<close> +} +In the RISC-V specification, the general-purpose register file is declared as one register +@{term Xs} containing the 32 registers of 64 bits each, which gets mapped to a list of +64-bit words (see Section~\ref{sec:types} for more information on vectors and lists in general). +In addition to the register state record, a reference constant is generated for each register, +e.g.~@{term PC_ref}, which is used when the register is passed to Sail functions as an argument. +These constants are records that contain the register name as a string, as well as getter and +setter functions. We discuss them in more detail together with the monads in +Section~\ref{sec:monads}.\<close> + +section \<open>Sail Library\<close> + +text \<open>The overall theory graph of the Sail library is depicted in Figure~\ref{fig:session-graph}. +The library includes mappings of common operations on the basic types (Section~\ref{sec:types}), in +particular bitvector operations for both the bitlist representation and the machine word +representation of bitvectors (Section~\ref{sec:bitvectors}). +It also includes theories defining the two monads currently supported: a state monad with exceptions +and nondeterminism (cf.~Section~\ref{sec:state-monad}), and a free monad of an effects datatype +(Section~\ref{sec:free-monad}).\<close> + +text_raw \<open> +\begin{figure}[p] + \begin{center} + \includegraphics[width=\textwidth,height=\textheight,keepaspectratio]{Sail_session_graph} + \end{center} + \caption{Session graph of the Sail library \label{fig:session-graph}} +\end{figure} +\<close> + +text \<open>The main definitions have been written in Lem and can therefore also be exported to theorem +provers other than Isabelle. The Isabelle-specific parts of the library are contained in the +theories named with the suffix @{path "_lemmas"}. They contain mostly simplification rules, but +also congruence rules for the @{term [source] bind} operations of the monads, for example, which +are needed by the function package when processing recursive monadic functions.\<close> + +subsection \<open>Basic types \label{sec:types}\<close> + +text \<open>The basic Sail types @{verbatim bool}, @{verbatim string}, @{verbatim list}, @{verbatim unit} +and @{verbatim real} are directly mapped to the Isabelle types of the same name. + +The numeric types @{verbatim int}, @{verbatim nat}, @{verbatim atom}, and @{verbatim range} are +treated in Sail as integers with constraints. The latter are not currently translated to Lem +or Isabelle, so these types are all mapped to the Isabelle type @{type int}. + +Bits are represented by a type that can also represent undefined bits: +@{datatype [display] bitU} +This provides one way to handle undefined cases of partial functions, such as division by zero. +In general, the guiding principle in the Sail library is to make partiality of library functions +explicit by returning an option type, and to provide wrappers implementing common ways to handle +undefined cases. For example, the function @{term quot_vec} for bitvector division comes in the +following variants: + \<^item> @{term quot_vec_maybe} returns an option type, with + @{lemma "quot_vec_maybe w 0 = None" by (auto simp: quot_vec_maybe_def quot_bv_def arith_op_bv_no0_def)}. + \<^item> @{term quot_vec_fail} is monadic and either returns the result or raises an exception. + \<^item> @{term quot_vec_oracle} is monadic and uses the @{term Undefined} effect in the exception case + to fill the result with bits drawn from a bitstream oracle. + \<^item> @{term quot_vec} is pure and returns an arbitrary (but fixed) value in the exception case, + currently defined as follows: For the bitlist representation of bitvectors, + @{term "quot_vec w 0"} returns a list filled with @{term BU}, while for the machine word + representation, the function gets mapped to Isabelle's division operation on machine words, + which defines @{lemma "(w :: ('a::len) word) div 0 = 0" by (simp add: word_div_def)}. + +Which variant is to be used for a given specification can be chosen by using the corresponding +binding for the Lem backend in the Sail source (typically in @{verbatim prelude.sail}). + +Vectors in Sail are mapped to lists in Isabelle, except for bitvectors, which are special-cased. +Both increasing and decreasing indexing order are supported by having two versions for each +operation that involves indexing, such as @{term update_list_inc} and @{term update_list_dec}, +or @{term subrange_list_inc} and @{term subrange_list_dec}. These operations are defined in the +theory @{theory Sail_values}, while @{theory Sail_values_lemmas} provides simplification rules +such as + +@{lemma "access_list_inc xs i = xs ! nat i" by auto} \\ +@{thm access_list_dec_nth} + +Note that, while Sail allows functions that are polymorphic in the indexing order, this kind of +polymorphism is not currently supported by the translation to Lem. It is not needed by the +currently existing specifications, however, since the indexing order is always fixed.\<close> + +subsection \<open>Bitvectors \label{sec:bitvectors} \label{sec:mwords}\<close> + +(*subsubsection \<open>Bit Lists \label{sec:bitlists}\<close> + +subsubsection \<open>Machine Words \label{sec:mwords}\<close>*) + +text \<open>The Lem backend of Sail supports two representations of bitvectors: bit lists and machine +words. The former is less convenient for proofs, because it typically leads to many proof +obligations about bitvector lengths. These are avoided with machine words, where length +information is contained in the types, e.g.~@{typ "64 word"}. However, Isabelle/HOL does not support +dependent types, which makes bitvector length polymorphism problematic. Sail includes an analysis +and rewriting pass for monomorphising bitvector lengths, splitting up length-polymorphic functions +into multiple clauses with concrete bitvector lengths. This is not enabled by default, however, +so Sail generates Lem definitions using bit lists unless the @{verbatim "-lem_mwords"} command +line flag is used. + +The theory @{theory Sail_values} defines a (Lem) typeclass @{verbatim Bitvector}, which provides +an interface to some basic bitvector operations and has instantiations for both bit lists and machine +words. It is mainly intended for internal use in the Sail library,\<^footnote>\<open>Lem typeclasses are not very +convenient to use in Isabelle, as they get translated to dictionaries that have to be passed to functions +using the typeclass.\<close> to implement library functions supporting either one of the bitvector +representations. For use in Sail specifications, wrappers are defined in the theories +@{path Sail_operators_bitlists} and @{path Sail_operators_mwords}, respectively. An import of the +right theory is automatically added to the generated files, depending on which bitvector +representation is used. Hence, bitvector operations can be referred to in the Sail source code +using uniform names, e.g.~@{term add_vec}, @{term update_vec_dec}, or @{term subrange_vec_inc}. +The theory @{theory Sail_operators_mwords_lemmas} sets up simplification rules that relate these +operations to the native operations in Isabelle, e.g. + +@{lemma "add_vec l r = l + r" by simp} \\ +@{lemma "and_vec l r = l AND r" by auto} \\ +@{thm access_vec_dec_test_bit}\<close> + +subsection \<open>Monads \label{sec:monads}\<close> + +text \<open>The definitions generated by Sail are designed to support reasoning in both concurrent and +sequential settings. For the former, we use a free monad of an effect datatype that provides +fine-grained information about the register and memory effects of monadic expressions, suitable +for integration with relaxed memory models. For the sequential case, we use a state monad (with +exceptions and nondeterminism). + +The generated definitions use the free monad, and the sequential case is supported via a lifting +to the state monad defined in the theory @{theory State}. Simplification rules are set up in the +theory @{theory State_lemmas}, allowing seamless reasoning about the generated definitions in terms +of the state monad.\<close> + +subsubsection \<open>State Monad \label{sec:state-monad}\<close> + +text \<open>The state monad supports nondeterminism and exceptions and is defined in a standard way: +a monadic expression maps a state to a set of results together with a corresponding successor +state. The type @{typ "('regs, 'a, 'e) monadS"} is a synonym for +@{typeof [display] "returnS a :: ('regs, 'a, 'e) monadS"} +Here, @{typ "'a"} and @{typ "'e"} are parameters for the return value type and the exception type, +respectively. The latter is instantiated in generated definitions with either the type +@{term exception}, if the Sail source code defines that type, or with @{typ unit} otherwise. +A result of a monadic expression can be either a value, a non-recoverable failure, or an +exception thrown (that may be caught using @{term try_catch}): +@{datatype [display] ex} +@{datatype [display, names_short] result} + +The @{type sequential_state} record has the following fields: + \<^item> @{term regstate} contains the register state. + \<^item> @{term memstate} stores the memory, represented as a map from (@{typ int}) addresses to + (@{typ "bitU list"}) bytes. + \<^item> Similarly, @{term tagstate} field stores a single bit per address, used by some specifications + to model tagged memory. + \<^item> The @{term write_ea} field of type @{typeof "write_ea s"} stores the type, address, and size + of the last announced memory write, if any. + \<^item> The @{term last_exclusive_operation_was_load} flag is used to determine whether exclusive + operations can succeed. + \<^item> The function stored in the @{term next_bool} field together with the seed in the @{term seed} + field are used as a random bit generator for undefined values. The @{term next_bool} + function takes the current seed as an argument and returns a @{type bool} and the next seed. + +The library defines several combinators and wrappers in addition to the standard monadic bind and +return (called @{term bindS} and @{term returnS} here, where the suffix @{term S} differentiates them +from the @{term [source] bind} and @{term return} functions of the free monad). The functions +@{term readS} and @{term updateS} provide direct access to the state, but there are more specific +wrappers for common tasks such as + \<^item> @{term read_regS} and @{term write_regS} for accessing registers (taking a register reference + as an argument), + \<^item> @{term read_memS} for reading memory, + \<^item> @{term write_mem_eaS} and @{term write_mem_valS} to announce and perform a memory write, + respectively, and + \<^item> @{term undefined_boolS} gets a value from the random bit generator. + +Nondeterminism can be introduced using @{term chooseS} to pick a value from a set, failure by +@{term failS} or @{term exitS} (with or without failure message, respectively), assertions by +@{term assert_expS} (causing a failure if the assertion fails), and exceptions by @{term throwS}. +The latter can be caught using @{term try_catchS}, which takes a monadic expression and an +exception handler as arguments. + +The exception mechanism is also used to implement early returns by throwing and catching return +values: A function body with one or more early returns of type @{typ 'a} (and exception type +@{typ 'e}) is lifted to a monadic expression with exception type @{typ "('a + 'e)"} using +@{term liftSR}, such that an early return of the value @{term a} throws @{term "Inl a"}, and a +regular exception @{term e} is thrown as @{term "Inr e"}. The function body is then wrapped in +@{term catch_early_returnS} to lower it back to the default monad and exception type. These +liftings and lowerings are automatically inserted by Sail for functions with early returns.\<^footnote>\<open>To be +precise, Sail's Lem backend uses the corresponding constructs for the free monad, but the state +monad version presented here can be obtained using the monad transformation presented in the next +section.\<close> + +Finally, there are the loop combinators @{term foreachS}, @{term whileS}, and @{term untilS}. +Loop bodies are required to be of type @{typ unit} in the Sail source code, but during the +translation to Lem they get rewritten into functions that take a tuple with the current values of +local mutable variables that they might update as an (additional) argument, and return the updated +values. Hence, the type of @{term foreachS}, for example, is +@{term [display, source] "foreachS :: 'a list \<Rightarrow> 'vars \<Rightarrow> ('a \<Rightarrow> 'vars \<Rightarrow> ('regs, 'vars, 'e) monadS) \<Rightarrow> ('regs, 'vars, 'e) monadS"} +Note that there is no general termination proof for @{term whileS} and @{term untilS}, so the +termination predicates @{term "whileS_dom"} or @{term "untilS_dom"} have to be proved for concrete +instances.\<close> + +subsubsection \<open>Free Monad \label{sec:free-monad}\<close> + +text \<open>In addition to the state monad, the theory @{theory Prompt_monad} defines a free monad of an +effect datatype. A monadic expression either returns a pure value @{term a}, denoted +@{term "Done a"}, or it has an effect. The latter can be a failure or an exception, or an effect +together with a continuation. For example, @{term \<open>Read_reg ''PC'' k\<close>} represents a request to +read the register @{term PC} and continue as @{term k}, which is a function that takes the +register value as a parameter and returns another monadic expression. Another example is +@{term "Undefined k"}, which requests a Boolean value from the execution context, e.g.~to resolve +an undefined bit to a concrete value. Again, the value is expected to be passed as an argument to +the continuation @{term k}. The complete set of supported monadic outcomes is captured in the +following datatype: + +@{datatype [display] monad} + +The effects are designed to be usable as an interface to relaxed memory models. For example, +@{term Footprint} tells the memory model that the register footprint of the instruction should be +re-calculated. The Boolean parameters of the continuations of the @{term Write_memv}, +@{term Write_tag}, and @{term Excl_res} effects allow the memory model to inform the instruction +whether a memory write has succeeded (or may succeed). + +The same set of combinators and wrappers as for the state monad is defined for this monad. The +names are the same, but without the suffix @{term S}, e.g.~@{term read_reg}, @{term write_mem_val}, +@{term undefined_bool}, @{term throw}, @{term try_catch}, etc.~(with the exception of the loop +combinators, which are called @{term foreachM}, @{term whileM}, and @{term untilM}; the names +@{term foreach}, @{term [names_short] while}, and @{term until} are reserved for the pure versions +of the loop combinators). + +The monad is parametric in the register type used for the register effects. One technical +complication is that, in general, this requires a single type that can subsume all the types of +registers occurring in a specification. Otherwise, it would not be possible to find a single +instantiation of the @{type monad} type to assign to a function that involves reading or writing +multiple registers with different types, for example. To solve this problem, the translation from +Sail to Lem generates a union type @{typ register_value} with constructors for all register base +types of the given specification and the built-in type constructors @{term vector}, @{type list}, +and @{type option}. In the case of the RISC-V duopod, this is + +@{datatype [display] register_value} + +For example, a value of the (complete) @{term Xs} register file (whose Sail type is +@{verbatim "vector(32, dec, vector(64, dec, bit))"}) is represented as @{term "Regval_vector (32, False, xs)"}, +where @{term xs} is a list of words wrapped in @{term Regval_vector_64_dec_bit}. + +Sail also generates conversion functions to and from @{type register_value}, e.g. + +@{term [source, show_types] "regval_of_vector_64_dec_bit :: 64 word \<Rightarrow> register_value"} \\ +@{term [source, show_types] "vector_64_dec_bit_of_regval :: register_value \<Rightarrow> 64 word option"} + +where the latter is partial. +The conversion functions for @{term Regval_vector}, @{term Regval_list}, and @{term Regval_option} +are higher-order functions that take the corresponding conversion function for the encapsulated +type as a parameter, e.g. + +@{term [source, show_types] "regval_of_vector :: ('a \<Rightarrow> register_value) \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value"} \\ +@{term [source, show_types] "vector_of_regval :: (register_value \<Rightarrow> 'a option) \<Rightarrow> register_value \<Rightarrow> 'a list option"} + +The latter only returns a value if \emph{all} elements of the vector can be successfully converted +from @{typ register_value} to @{typ "'a"}. + +For each register, the matching pair of conversion functions is recorded in its +@{type register_ref} record, e.g. + +@{thm [display] PC_ref_def} +@{thm [display] Xs_ref_def} + +The @{term read_reg} wrapper, for example, takes such a reference as a parameter, generates a +@{term Read_reg} effect with the register name, and casts the register value received as input via +@{term of_regval}. If the latter fails because the environment passed a value of the wrong type +to the continuation, then @{term read_reg} halts with a @{term Failure}. The state monad wrappers +@{term read_regS} and @{term write_regS} also take such a register reference as an argument, but +use the getters and setters in the @{term read_from} and @{term write_to} fields to access the +register state record: +@{thm [display] read_regS_def write_regS_def} + +Sail aims to generate Isabelle definitions that can be used with either the state or the free monad. +To achieve this, the definitions are generated using the free monad, and a lifting to the state +monad is provided together with simplification rules. These include generic simplification rules +(proved in the theory @{theory State_lemmas}) such as +@{thm [display] + liftState_return[where r = "(get_regval, set_regval)"] + liftState_bind[where r = "(get_regval, set_regval)"] + liftState_try_catch[where r = "(get_regval, set_regval)"]} +They also include more specific lemmas about register reads and writes: The lifting of these +involves a back-and-forth conversion between the type of the register and the @{type register_value} +type at the interface between the monads, which can fail in general. As long as the generated +register references are used, however, it is guaranteed to succeed, and this is made explicit in +lemmas such as +@{thm [display] liftS_read_reg_PC liftS_write_reg_PC} +which are generated (together with their proofs) for each register and placed in a theory with +the suffix @{path "_lemmas"}, e.g.~@{path Riscv_duopod_lemmas}. +The aim of these lemmas is to allow a smooth transition from the free to the state monad via +simplification, as in the following example.\<close> + +section \<open>Example Proof \label{sec:ex-proof}\<close> + +text \<open>As a toy example for illustration, we prove that the add instruction in the RISC-V duopod +actually performs an addition. We consider the sequential case and use the state monad. The +theory @{theory Hoare} defines (a shallow embedding of) a simple Hoare logic, where +@{term "PrePost P f Q"} denotes a triple of a precondition @{term P}, monadic expression @{term f}, +and postcondition @{term Q}. Its validity is defined by +@{thm [display] PrePost_def} +There is also a quadruple variant, with separate postconditions for the regular and the exception +case, defined as +@{thm [display, names_short] PrePostE_def} +The theory includes standard proof rules for both of these variants, in particular rules +giving weakest preconditions of the predefined primitives of the monad, collected under the names +@{attribute PrePost_intro} and @{attribute PrePostE_intro}, respectively. + +The instruction we are considering is defined as +@{thm [display] execute_ITYPE.simps[of _ rs for rs]} + +We first declare two simplification rules and an abbreviation, for stating the lemma more +conveniently: @{term "getXs r s"} reads general-purpose register @{term r} in state @{term s}, +where register 0 is special-cased and hard-wired to the constant 0, as defined in the RISC-V +specification.\<close> + +abbreviation "getXs r s \<equiv> if r = 0 then 0 else access_list_dec (Xs (regstate s)) (uint r)" + +lemma EXTS_scast[simp]: "EXTS len w = scast w" + by (simp add: EXTS_def sign_extend_def) + +declare regbits_to_regno_def[simp] + +text \<open>We prove that a postcondition of the instruction is that the destination register holds the +sum of the initial value of the source register and the immediate operand (unless the destination +register is the constant zero register). Moreover, we require the instruction to succeed, so +the postcondition for the exception case is @{term False}. In the precondition, we remember +the initial value @{term v} of the source register for use in the postcondition (since it might get +overwritten if @{term "rs = rd"}). We also explicitly assume that there are 32 general-purpose +registers; due to the use of a list for the @{term Xs} register file, this information is currently +not preserved by the translation.\<close> + +lemma + fixes rs rd :: regbits and v :: "64 word" and imm :: "12 word" + + defines "pre s \<equiv> (getXs rs s = v \<and> length (Xs (regstate s)) = 32)" + defines "instr \<equiv> execute (ITYPE (imm, rs, rd, RISCV_ADDI))" + defines "post a s \<equiv> (rd = 0 \<or> getXs rd s = v + (scast imm))" + + shows "PrePostE pre (liftS instr) post (\<lambda>_ _. False)" + + unfolding pre_def instr_def post_def + by (simp add: rX_def wX_def cong: bindS_cong if_cong split del: if_split) + (rule PrePostE_strengthen_pre, (rule PrePostE_intro)+, auto simp: uint_0_iff) + +text \<open>The proof begins with a simplification step, which not only unfolds the definitions of the +auxiliary functions @{term rX} and @{term wX}, but also performs the lifting from the free monad +to the state monad. We apply the rule @{thm [source] PrePostE_strengthen_pre} (in a +backward manner) to allow a weaker precondition, then use the rules in @{attribute PrePostE_intro} +to derive a weakest precondition, and then use @{method auto} to show that it is implied by +the given precondition. For more serious proofs, one will want to set up specialised proof +tactics. This example uses only basic proof methods, to make the reasoning steps more explicit.\<close> + +(*<*) +end +(*>*) diff --git a/snapshots/isabelle/README.md b/snapshots/isabelle/README.md new file mode 100644 index 00000000..b1d9db23 --- /dev/null +++ b/snapshots/isabelle/README.md @@ -0,0 +1,25 @@ +# Isabelle Snapshots of Sail Specifications + +This directory contains snapshots of the Isabelle theories generated by Sail +for the CHERI-MIPS, RISC-V, and ARM v8.3 specifications, together with +snapshots of the Sail and Lem libraries. These snapshots are provided for +convenience, and are not guaranteed to be up-to-date. + +In order to open a theory of one of the specifications in Isabelle, use the `-l +Sail` command-line flag to load the session containing the Sail library. +Snapshots of the Sail and Lem libraries are in the `lib/sail` and `lib/lem` +directories, respectively. You can tell Isabelle where to find them using the +`-d` flag, as in + +``` +isabelle jedit -l Sail -d lib/lem -d lib/sail riscv/Riscv.thy +``` + +This will open the RISC-V specification. + +The file `Manual.thy` (and its PDF rendering in `Manual.pdf`) contains an +introduction on how to use the Sail specifications in Isabelle. + +The Lem library files in `lib/lem` have been generated from the +[Lem](https://github.com/rems-project/lem) sources. The Lem license can be +found in `lib/lem/LICENSE`. diff --git a/snapshots/isabelle/cheri/Cheri.thy b/snapshots/isabelle/cheri/Cheri.thy new file mode 100644 index 00000000..eed49a23 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri.thy @@ -0,0 +1,10570 @@ +chapter \<open>Generated by Lem from cheri.lem.\<close> + +theory "Cheri" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Cheri_types" + "Mips_extras" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Cheri_types*) +(*open import Mips_extras*) + +definition cap_size :: " int " where + " cap_size = ( (( 32 :: int)::ii))" + + +(*val undefined_option : forall 'a. 'a -> M (maybe 'a)*) + +definition undefined_option :: " 'a \<Rightarrow>((register_value),('a option),(exception))monad " where + " undefined_option typ_a = ( undefined_unit () \<then> internal_pick [None,Some typ_a])" + + + + + + + + +(*val neq_bool : bool -> bool -> bool*) + +definition neq_bool :: " bool \<Rightarrow> bool \<Rightarrow> bool " where + " neq_bool x y = ( \<not> (((x = y))))" + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __MIPS_write : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MIPS_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MIPS_write addr width data = ( + write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data )" + + +(*val __MIPS_read : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MIPS_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MIPS_read addr width = ( + (read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'p8_times_n_::len)Word.word) M))" + + + + +(*val undefined_exception : unit -> M exception*) + +definition undefined_exception :: " unit \<Rightarrow>((register_value),(exception),(exception))monad " where + " undefined_exception _ = ( + (undefined_unit () \<then> + undefined_string () ) \<bind> (\<lambda> (w__0 :: string) . + ((undefined_unit () \<then> + undefined_unit () ) \<then> + undefined_unit () ) \<then> + internal_pick + [ISAException () ,Error_not_implemented w__0,Error_misaligned_access () ,Error_EBREAK () ,Error_internal_error () ]))" + + +(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition sign_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " sign_extend1 (m__tv :: int) v = ( (sign_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +definition zero_extend1 :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " zero_extend1 (m__tv :: int) v = ( (zero_extend0 + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv :: ( 'm::len)Word.word))" + + +(*val zeros : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition zeros0 :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where + " zeros0 (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val ones : forall 'n . Size 'n => integer -> unit -> mword 'n*) + +definition ones :: " int \<Rightarrow> unit \<Rightarrow>('n::len)Word.word " where + " ones (n__tv :: int) _ = ( (replicate_bits (vec_of_bits [B1] :: 1 Word.word) n__tv :: ( 'n::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \<Rightarrow> bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val bits_to_bool : mword ty1 -> bool*) + +definition bits_to_bool :: "(1)Word.word \<Rightarrow> bool " where + " bits_to_bool x = ( bit_to_bool ((access_vec_dec x (( 0 :: int)::ii))))" + + +(* +function{to_bits} converts an integer to a bit vector of given length. If the integer is negative a twos-complement representation is used. If the integer is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. +*) +(*val to_bits : forall 'l. Size 'l => itself 'l -> ii -> mword 'l*) + +definition to_bits :: "('l::len)itself \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where + " to_bits l n = ( + (let l = (size_itself_int l) in + (get_slice_int0 instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 :: int)::ii) :: ( 'l::len)Word.word)))" + + +(*val mask : forall 'm 'n . Size 'm, Size 'n => integer -> mword 'm -> mword 'n*) + +definition mask0 :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('n::len)Word.word " where + " mask0 (n__tv :: int) bs = ( + (subrange_vec_dec bs ((n__tv - (( 1 :: int)::ii))) (( 0 :: int)::ii) :: ( 'n::len)Word.word))" + + +(*val extzv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extzv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extzv (m__tv :: int) v = ( (extz_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val extsv : forall 'n 'm. Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " extsv (m__tv :: int) v = ( (exts_vec m__tv v :: ( 'm::len)Word.word))" + + +(*val slice_mask : forall 'n . Size 'n => integer -> ii -> ii -> mword 'n*) + +definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " slice_mask (n__tv :: int) i l = ( + (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" + + +(*val is_zero_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_zero_subrange xs i j = ( + (((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) = ((extzv ((int (size xs))) (vec_of_bits [B0] :: 1 Word.word) :: ( 'n::len)Word.word))))" + + +(*val is_ones_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> bool*) + +definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " is_ones_subrange xs i j = ( + (let (m :: 'n bits) = ((slice_mask ((int (size xs))) j ((j - i)) :: ( 'n::len)Word.word)) in + (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" + + +(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => integer -> mword 'n -> ii -> ii -> mword 'm -> ii -> ii -> mword 'r*) + +definition slice_slice_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_slice_concat (r__tv :: int) xs i l ys i' l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr ((and_vec ys ((slice_mask ((int (size ys))) i' l' :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) i' + :: ( 'm::len)Word.word)) in + (or_vec ((shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)) ((extzv r__tv ys :: ( 'r::len)Word.word)) + :: ( 'r::len)Word.word))))" + + +(*val slice_zeros_concat : forall 'n 'r . Size 'n, Size 'r => integer -> mword 'n -> ii -> integer -> integer -> mword 'r*) + +definition slice_zeros_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('r::len)Word.word " where + " slice_zeros_concat (r__tv :: int) xs i l l' = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv r__tv xs :: ( 'r::len)Word.word)) l' :: ( 'r::len)Word.word)))" + + +(*val subrange_subrange_eq : forall 'n . Size 'n => mword 'n -> ii -> ii -> mword 'n -> ii -> ii -> bool*) + +definition subrange_subrange_eq :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where + " subrange_subrange_eq xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size xs))) j' ((i' - j')) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + j' + :: ( 'n::len)Word.word)) in + (xs = ys))))" + + +(*val subrange_subrange_concat : forall 'n 'm 's . Size 'm, Size 'n, Size 's => integer -> mword 'n -> integer -> integer -> mword 'm -> integer -> integer -> mword 's*) + +definition subrange_subrange_concat :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('s::len)Word.word " where + " subrange_subrange_concat (s__tv :: int) xs i j ys i' j' = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (let ys = + ((shiftr + ((and_vec ys ((slice_mask ((int (size ys))) j' ((i' - j')) :: ( 'm::len)Word.word)) :: ( 'm::len)Word.word)) + j' + :: ( 'm::len)Word.word)) in + (or_vec + ((sub_vec_int ((shiftl ((extzv s__tv xs :: ( 's::len)Word.word)) i' :: ( 's::len)Word.word)) + ((j' - (( 1 :: int)::ii))) + :: ( 's::len)Word.word)) ((extzv s__tv ys :: ( 's::len)Word.word)) + :: ( 's::len)Word.word))))" + + +(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_subrange :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_subrange (m__tv :: int) xs i j shift = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) j + :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val place_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> ii -> mword 'm*) + +definition place_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " place_slice (m__tv :: int) xs i l shift = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (shiftl ((extzv m__tv xs :: ( 'm::len)Word.word)) shift :: ( 'm::len)Word.word)))" + + +(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition zext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " zext_slice (m__tv :: int) xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + (extzv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> ii -> ii -> mword 'm*) + +definition sext_slice :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('m::len)Word.word " where + " sext_slice (m__tv :: int) xs i l = ( + (let xs = + ((arith_shiftr + ((shiftl ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) + ((((((int (size xs))) - i)) - l)) + :: ( 'n::len)Word.word)) ((((int (size xs))) - l)) + :: ( 'n::len)Word.word)) in + (extsv m__tv xs :: ( 'm::len)Word.word)))" + + +(*val unsigned_slice : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_slice xs i l = ( + (let xs = + ((shiftr ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val unsigned_subrange : forall 'n . Size 'n => mword 'n -> ii -> ii -> ii*) + +definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int " where + " unsigned_subrange xs i j = ( + (let xs = + ((shiftr + ((and_vec xs ((slice_mask ((int (size xs))) j ((i - j)) :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) i + :: ( 'n::len)Word.word)) in + Word.uint xs))" + + +(*val zext_ones : forall 'n . Size 'n => integer -> ii -> mword 'n*) + +definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " zext_ones (n__tv :: int) m = ( + (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" + + +(*val undefined_CauseReg : unit -> M CauseReg*) + +definition undefined_CauseReg :: " unit \<Rightarrow>((register_value),(CauseReg),(exception))monad " where + " undefined_CauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + internal_pick [Mk_CauseReg w__0]))" + + +(*val _get_CauseReg : CauseReg -> mword ty32*) + +fun get_CauseReg :: " CauseReg \<Rightarrow>(32)Word.word " where + " get_CauseReg (Mk_CauseReg (v)) = ( v )" + + +(*val _set_CauseReg : register_ref regstate register_value CauseReg -> mword ty32 -> M unit*) + +definition set_CauseReg :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_CauseReg v) in + write_reg r_ref r)))" + + +(*val _get_CapCauseReg : CapCauseReg -> mword ty16*) + +(*val _set_CapCauseReg : register_ref regstate register_value CapCauseReg -> mword ty16 -> M unit*) + +(*val _get_CauseReg_BD : CauseReg -> mword ty1*) + +fun get_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_BD (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_BD : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_BD :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_BD r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_BD : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_BD :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_BD (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_CE : CauseReg -> mword ty2*) + +fun get_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word " where + " get_CauseReg_CE (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) :: 2 Word.word))" + + +(*val _set_CauseReg_CE : register_ref regstate register_value CauseReg -> mword ty2 -> M unit*) + +definition set_CauseReg_CE :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_CE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_CE : CauseReg -> mword ty2 -> CauseReg*) + +fun update_CauseReg_CE :: " CauseReg \<Rightarrow>(2)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_CE (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IV : CauseReg -> mword ty1*) + +fun get_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_IV (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_IV : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_IV :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_IV r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IV : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_IV :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IV (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_WP : CauseReg -> mword ty1*) + +fun get_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word " where + " get_CauseReg_WP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_CauseReg_WP : register_ref regstate register_value CauseReg -> mword ty1 -> M unit*) + +definition set_CauseReg_WP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_WP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_WP : CauseReg -> mword ty1 -> CauseReg*) + +fun update_CauseReg_WP :: " CauseReg \<Rightarrow>(1)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_WP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_IP : CauseReg -> mword ty8*) + +fun get_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word " where + " get_CauseReg_IP (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CauseReg_IP : register_ref regstate register_value CauseReg -> mword ty8 -> M unit*) + +definition set_CauseReg_IP :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_IP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_IP : CauseReg -> mword ty8 -> CauseReg*) + +fun update_CauseReg_IP :: " CauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_IP (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_CauseReg_ExcCode : CauseReg -> mword ty5*) + +fun get_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word " where + " get_CauseReg_ExcCode (Mk_CauseReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word))" + + +(*val _set_CauseReg_ExcCode : register_ref regstate register_value CauseReg -> mword ty5 -> M unit*) + +definition set_CauseReg_ExcCode :: "((regstate),(register_value),(CauseReg))register_ref \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CauseReg_ExcCode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CauseReg) . + (let r = ((get_CauseReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_CauseReg r)))))" + + +(*val _update_CauseReg_ExcCode : CauseReg -> mword ty5 -> CauseReg*) + +fun update_CauseReg_ExcCode :: " CauseReg \<Rightarrow>(5)Word.word \<Rightarrow> CauseReg " where + " update_CauseReg_ExcCode (Mk_CauseReg (v)) x = ( + Mk_CauseReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _update_CapCauseReg_ExcCode : CapCauseReg -> mword ty8 -> CapCauseReg*) + +(*val _get_CapCauseReg_ExcCode : CapCauseReg -> mword ty8*) + +(*val _set_CapCauseReg_ExcCode : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +(*val undefined_TLBEntryLoReg : unit -> M TLBEntryLoReg*) + +definition undefined_TLBEntryLoReg :: " unit \<Rightarrow>((register_value),(TLBEntryLoReg),(exception))monad " where + " undefined_TLBEntryLoReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryLoReg w__0]))" + + +(*val _get_TLBEntryLoReg : TLBEntryLoReg -> mword ty64*) + +fun get_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryLoReg (Mk_TLBEntryLoReg (v)) = ( v )" + + +(*val _set_TLBEntryLoReg : register_ref regstate register_value TLBEntryLoReg -> mword ty64 -> M unit*) + +definition set_TLBEntryLoReg :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntryLoReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapS : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapS :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapS : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapS :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapS (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_CapL : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_CapL :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_CapL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_CapL : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_CapL :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_CapL (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24*) + +fun get_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word " where + " get_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) = ( + (subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntryLoReg_PFN : register_ref regstate register_value TLBEntryLoReg -> mword ty24 -> M unit*) + +definition set_TLBEntryLoReg_PFN :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_PFN r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_PFN : TLBEntryLoReg -> mword ty24 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_PFN :: " TLBEntryLoReg \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_PFN (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3*) + +fun get_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word " where + " get_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntryLoReg_C : register_ref regstate register_value TLBEntryLoReg -> mword ty3 -> M unit*) + +definition set_TLBEntryLoReg_C :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_C r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_C : TLBEntryLoReg -> mword ty3 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_C :: " TLBEntryLoReg \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_C (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_D : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_D :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_D r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_D : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_D :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_D (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_V : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_V :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_V r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_V : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_V :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_V (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1*) + +fun get_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word " where + " get_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntryLoReg_G : register_ref regstate register_value TLBEntryLoReg -> mword ty1 -> M unit*) + +definition set_TLBEntryLoReg_G :: "((regstate),(register_value),(TLBEntryLoReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryLoReg_G r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryLoReg) . + (let r = ((get_TLBEntryLoReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryLoReg r)))))" + + +(*val _update_TLBEntryLoReg_G : TLBEntryLoReg -> mword ty1 -> TLBEntryLoReg*) + +fun update_TLBEntryLoReg_G :: " TLBEntryLoReg \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntryLoReg " where + " update_TLBEntryLoReg_G (Mk_TLBEntryLoReg (v)) x = ( + Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_TLBEntryHiReg : unit -> M TLBEntryHiReg*) + +definition undefined_TLBEntryHiReg :: " unit \<Rightarrow>((register_value),(TLBEntryHiReg),(exception))monad " where + " undefined_TLBEntryHiReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_TLBEntryHiReg w__0]))" + + +(*val _get_TLBEntryHiReg : TLBEntryHiReg -> mword ty64*) + +fun get_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow>(64)Word.word " where + " get_TLBEntryHiReg (Mk_TLBEntryHiReg (v)) = ( v )" + + +(*val _set_TLBEntryHiReg : register_ref regstate register_value TLBEntryHiReg -> mword ty64 -> M unit*) + +definition set_TLBEntryHiReg :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntryHiReg v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2*) + +fun get_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word " where + " get_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntryHiReg_R : register_ref regstate register_value TLBEntryHiReg -> mword ty2 -> M unit*) + +definition set_TLBEntryHiReg_R :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_R r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_R : TLBEntryHiReg -> mword ty2 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_R :: " TLBEntryHiReg \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_R (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27*) + +fun get_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word " where + " get_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) = ( + (subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntryHiReg_VPN2 : register_ref regstate register_value TLBEntryHiReg -> mword ty27 -> M unit*) + +definition set_TLBEntryHiReg_VPN2 :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_VPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 39 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> mword ty27 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_VPN2 :: " TLBEntryHiReg \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_VPN2 (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8*) + +fun get_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word " where + " get_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntryHiReg_ASID : register_ref regstate register_value TLBEntryHiReg -> mword ty8 -> M unit*) + +definition set_TLBEntryHiReg_ASID :: "((regstate),(register_value),(TLBEntryHiReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntryHiReg_ASID r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let r = ((get_TLBEntryHiReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_TLBEntryHiReg r)))))" + + +(*val _update_TLBEntryHiReg_ASID : TLBEntryHiReg -> mword ty8 -> TLBEntryHiReg*) + +fun update_TLBEntryHiReg_ASID :: " TLBEntryHiReg \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntryHiReg " where + " update_TLBEntryHiReg_ASID (Mk_TLBEntryHiReg (v)) x = ( + Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_ContextReg : unit -> M ContextReg*) + +definition undefined_ContextReg :: " unit \<Rightarrow>((register_value),(ContextReg),(exception))monad " where + " undefined_ContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_ContextReg w__0]))" + + +(*val _get_ContextReg : ContextReg -> mword ty64*) + +fun get_ContextReg :: " ContextReg \<Rightarrow>(64)Word.word " where + " get_ContextReg (Mk_ContextReg (v)) = ( v )" + + +(*val _set_ContextReg : register_ref regstate register_value ContextReg -> mword ty64 -> M unit*) + +definition set_ContextReg :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_ContextReg v) in + write_reg r_ref r)))" + + +(*val _get_ContextReg_PTEBase : ContextReg -> mword ty41*) + +fun get_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word " where + " get_ContextReg_PTEBase (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) :: 41 Word.word))" + + +(*val _set_ContextReg_PTEBase : register_ref regstate register_value ContextReg -> mword ty41 -> M unit*) + +definition set_ContextReg_PTEBase :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(41)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_PTEBase r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_PTEBase : ContextReg -> mword ty41 -> ContextReg*) + +fun update_ContextReg_PTEBase :: " ContextReg \<Rightarrow>(41)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_PTEBase (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_ContextReg_BadVPN2 : ContextReg -> mword ty19*) + +fun get_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word " where + " get_ContextReg_BadVPN2 (Mk_ContextReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) :: 19 Word.word))" + + +(*val _set_ContextReg_BadVPN2 : register_ref regstate register_value ContextReg -> mword ty19 -> M unit*) + +definition set_ContextReg_BadVPN2 :: "((regstate),(register_value),(ContextReg))register_ref \<Rightarrow>(19)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_ContextReg_BadVPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: ContextReg) . + (let r = ((get_ContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_ContextReg r)))))" + + +(*val _update_ContextReg_BadVPN2 : ContextReg -> mword ty19 -> ContextReg*) + +fun update_ContextReg_BadVPN2 :: " ContextReg \<Rightarrow>(19)Word.word \<Rightarrow> ContextReg " where + " update_ContextReg_BadVPN2 (Mk_ContextReg (v)) x = ( + Mk_ContextReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val undefined_XContextReg : unit -> M XContextReg*) + +definition undefined_XContextReg :: " unit \<Rightarrow>((register_value),(XContextReg),(exception))monad " where + " undefined_XContextReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + internal_pick [Mk_XContextReg w__0]))" + + +(*val _get_XContextReg : XContextReg -> mword ty64*) + +fun get_XContextReg :: " XContextReg \<Rightarrow>(64)Word.word " where + " get_XContextReg (Mk_XContextReg (v)) = ( v )" + + +(*val _set_XContextReg : register_ref regstate register_value XContextReg -> mword ty64 -> M unit*) + +definition set_XContextReg :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_XContextReg v) in + write_reg r_ref r)))" + + +(*val _get_XContextReg_XPTEBase : XContextReg -> mword ty31*) + +fun get_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word " where + " get_XContextReg_XPTEBase (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) :: 31 Word.word))" + + +(*val _set_XContextReg_XPTEBase : register_ref regstate register_value XContextReg -> mword ty31 -> M unit*) + +definition set_XContextReg_XPTEBase :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(31)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XPTEBase r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 33 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XPTEBase : XContextReg -> mword ty31 -> XContextReg*) + +fun update_XContextReg_XPTEBase :: " XContextReg \<Rightarrow>(31)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XPTEBase (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 33 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XR : XContextReg -> mword ty2*) + +fun get_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word " where + " get_XContextReg_XR (Mk_XContextReg (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) :: 2 Word.word))" + + +(*val _set_XContextReg_XR : register_ref regstate register_value XContextReg -> mword ty2 -> M unit*) + +definition set_XContextReg_XR :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 31 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XR : XContextReg -> mword ty2 -> XContextReg*) + +fun update_XContextReg_XR :: " XContextReg \<Rightarrow>(2)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XR (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 31 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_XContextReg_XBadVPN2 : XContextReg -> mword ty27*) + +fun get_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word " where + " get_XContextReg_XBadVPN2 (Mk_XContextReg (v)) = ( + (subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) :: 27 Word.word))" + + +(*val _set_XContextReg_XBadVPN2 : register_ref regstate register_value XContextReg -> mword ty27 -> M unit*) + +definition set_XContextReg_XBadVPN2 :: "((regstate),(register_value),(XContextReg))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_XContextReg_XBadVPN2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: XContextReg) . + (let r = ((get_XContextReg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_XContextReg r)))))" + + +(*val _update_XContextReg_XBadVPN2 : XContextReg -> mword ty27 -> XContextReg*) + +fun update_XContextReg_XBadVPN2 :: " XContextReg \<Rightarrow>(27)Word.word \<Rightarrow> XContextReg " where + " update_XContextReg_XBadVPN2 (Mk_XContextReg (v)) x = ( + Mk_XContextReg ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +definition TLBNumEntries :: " int " where + " TLBNumEntries = ( (( 64 :: int)::ii))" + + +definition TLBIndexMax :: "(6)Word.word " where + " TLBIndexMax = ( (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))" + + +(*val MAX : integer -> integer*) + +definition MAX :: " int \<Rightarrow> int " where + " MAX n = ( ((pow2 n)) - (( 1 :: int)::ii))" + + +definition MAX_U64 :: " int " where + " MAX_U64 = ( MAX (( 64 :: int)::ii))" + + +definition MAX_VA :: " int " where + " MAX_VA = ( MAX (( 40 :: int)::ii))" + + +definition MAX_PA :: " int " where + " MAX_PA = ( MAX (( 36 :: int)::ii))" + + +(*val undefined_TLBEntry : unit -> M TLBEntry*) + +definition undefined_TLBEntry :: " unit \<Rightarrow>((register_value),(TLBEntry),(exception))monad " where + " undefined_TLBEntry _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 :: int)::ii) :: ( 117 Word.word) M) \<bind> (\<lambda> (w__0 :: 117 Word.word) . + internal_pick [Mk_TLBEntry w__0]))" + + +(*val _get_TLBEntry : TLBEntry -> mword ty117*) + +fun get_TLBEntry :: " TLBEntry \<Rightarrow>(117)Word.word " where + " get_TLBEntry (Mk_TLBEntry (v)) = ( v )" + + +(*val _set_TLBEntry : register_ref regstate register_value TLBEntry -> mword ty117 -> M unit*) + +definition set_TLBEntry :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(117)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_TLBEntry v) in + write_reg r_ref r)))" + + +(*val _get_TLBEntry_pagemask : TLBEntry -> mword ty16*) + +fun get_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word " where + " get_TLBEntry_pagemask (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) :: 16 Word.word))" + + +(*val _set_TLBEntry_pagemask : register_ref regstate register_value TLBEntry -> mword ty16 -> M unit*) + +definition set_TLBEntry_pagemask :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pagemask r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 116 :: int)::ii) (( 101 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pagemask : TLBEntry -> mword ty16 -> TLBEntry*) + +fun update_TLBEntry_pagemask :: " TLBEntry \<Rightarrow>(16)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pagemask (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 116 :: int)::ii) (( 101 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_r : TLBEntry -> mword ty2*) + +fun get_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word " where + " get_TLBEntry_r (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) :: 2 Word.word))" + + +(*val _set_TLBEntry_r : register_ref regstate register_value TLBEntry -> mword ty2 -> M unit*) + +definition set_TLBEntry_r :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_r r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 100 :: int)::ii) (( 99 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_r : TLBEntry -> mword ty2 -> TLBEntry*) + +fun update_TLBEntry_r :: " TLBEntry \<Rightarrow>(2)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_r (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 100 :: int)::ii) (( 99 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_vpn2 : TLBEntry -> mword ty27*) + +fun get_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word " where + " get_TLBEntry_vpn2 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) :: 27 Word.word))" + + +(*val _set_TLBEntry_vpn2 : register_ref regstate register_value TLBEntry -> mword ty27 -> M unit*) + +definition set_TLBEntry_vpn2 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_vpn2 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 98 :: int)::ii) (( 72 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_vpn2 : TLBEntry -> mword ty27 -> TLBEntry*) + +fun update_TLBEntry_vpn2 :: " TLBEntry \<Rightarrow>(27)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_vpn2 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 98 :: int)::ii) (( 72 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_asid : TLBEntry -> mword ty8*) + +fun get_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word " where + " get_TLBEntry_asid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) :: 8 Word.word))" + + +(*val _set_TLBEntry_asid : register_ref regstate register_value TLBEntry -> mword ty8 -> M unit*) + +definition set_TLBEntry_asid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_asid r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 71 :: int)::ii) (( 64 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_asid : TLBEntry -> mword ty8 -> TLBEntry*) + +fun update_TLBEntry_asid :: " TLBEntry \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_asid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 71 :: int)::ii) (( 64 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_g : TLBEntry -> mword ty1*) + +fun get_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_g (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_g : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_g :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_g r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_g : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_g :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_g (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_valid : TLBEntry -> mword ty1*) + +fun get_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_valid (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_valid : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_valid :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_valid r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 62 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_valid : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_valid :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_valid (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 62 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 61 :: int)::ii) (( 61 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 61 :: int)::ii) (( 61 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 60 :: int)::ii) (( 60 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 60 :: int)::ii) (( 60 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn1 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn1 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 36 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn1 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn1 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 36 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c1 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c1 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_c1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 33 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c1 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c1 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 33 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_d1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 32 :: int)::ii) (( 32 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 32 :: int)::ii) (( 32 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v1 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v1 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v1 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v1 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_v1 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 31 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v1 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v1 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v1 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 31 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_caps0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_caps0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_caps0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_caps0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_caps0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 30 :: int)::ii) (( 30 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_caps0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_caps0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_caps0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 30 :: int)::ii) (( 30 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_capl0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_capl0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_capl0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_capl0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_capl0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 29 :: int)::ii) (( 29 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_capl0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_capl0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_capl0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 29 :: int)::ii) (( 29 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_pfn0 : TLBEntry -> mword ty24*) + +fun get_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word " where + " get_TLBEntry_pfn0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) :: 24 Word.word))" + + +(*val _set_TLBEntry_pfn0 : register_ref regstate register_value TLBEntry -> mword ty24 -> M unit*) + +definition set_TLBEntry_pfn0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(24)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_pfn0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 28 :: int)::ii) (( 5 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_pfn0 : TLBEntry -> mword ty24 -> TLBEntry*) + +fun update_TLBEntry_pfn0 :: " TLBEntry \<Rightarrow>(24)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_pfn0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 28 :: int)::ii) (( 5 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_c0 : TLBEntry -> mword ty3*) + +fun get_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word " where + " get_TLBEntry_c0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word))" + + +(*val _set_TLBEntry_c0 : register_ref regstate register_value TLBEntry -> mword ty3 -> M unit*) + +definition set_TLBEntry_c0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(3)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_c0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 2 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_c0 : TLBEntry -> mword ty3 -> TLBEntry*) + +fun update_TLBEntry_c0 :: " TLBEntry \<Rightarrow>(3)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_c0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 2 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_d0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_d0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_d0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_d0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_d0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_d0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_d0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_d0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 117 Word.word)))" + + +(*val _get_TLBEntry_v0 : TLBEntry -> mword ty1*) + +fun get_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word " where + " get_TLBEntry_v0 (Mk_TLBEntry (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_TLBEntry_v0 : register_ref regstate register_value TLBEntry -> mword ty1 -> M unit*) + +definition set_TLBEntry_v0 :: "((regstate),(register_value),(TLBEntry))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_TLBEntry_v0 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: TLBEntry) . + (let r = ((get_TLBEntry w__0 :: 117 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 117 Word.word)) in + write_reg r_ref (Mk_TLBEntry r)))))" + + +(*val _update_TLBEntry_v0 : TLBEntry -> mword ty1 -> TLBEntry*) + +fun update_TLBEntry_v0 :: " TLBEntry \<Rightarrow>(1)Word.word \<Rightarrow> TLBEntry " where + " update_TLBEntry_v0 (Mk_TLBEntry (v)) x = ( + Mk_TLBEntry ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 117 Word.word)))" + + +definition TLBEntries :: "(((regstate),(register_value),(TLBEntry))register_ref)list " where + " TLBEntries = ( + [TLBEntry63_ref,TLBEntry62_ref,TLBEntry61_ref,TLBEntry60_ref,TLBEntry59_ref,TLBEntry58_ref, + TLBEntry57_ref,TLBEntry56_ref,TLBEntry55_ref,TLBEntry54_ref,TLBEntry53_ref,TLBEntry52_ref, + TLBEntry51_ref,TLBEntry50_ref,TLBEntry49_ref,TLBEntry48_ref,TLBEntry47_ref,TLBEntry46_ref, + TLBEntry45_ref,TLBEntry44_ref,TLBEntry43_ref,TLBEntry42_ref,TLBEntry41_ref,TLBEntry40_ref, + TLBEntry39_ref,TLBEntry38_ref,TLBEntry37_ref,TLBEntry36_ref,TLBEntry35_ref,TLBEntry34_ref, + TLBEntry33_ref,TLBEntry32_ref,TLBEntry31_ref,TLBEntry30_ref,TLBEntry29_ref,TLBEntry28_ref, + TLBEntry27_ref,TLBEntry26_ref,TLBEntry25_ref,TLBEntry24_ref,TLBEntry23_ref,TLBEntry22_ref, + TLBEntry21_ref,TLBEntry20_ref,TLBEntry19_ref,TLBEntry18_ref,TLBEntry17_ref,TLBEntry16_ref, + TLBEntry15_ref,TLBEntry14_ref,TLBEntry13_ref,TLBEntry12_ref,TLBEntry11_ref,TLBEntry10_ref, + TLBEntry09_ref,TLBEntry08_ref,TLBEntry07_ref,TLBEntry06_ref,TLBEntry05_ref,TLBEntry04_ref, + TLBEntry03_ref,TLBEntry02_ref,TLBEntry01_ref,TLBEntry00_ref])" + + +(*val undefined_StatusReg : unit -> M StatusReg*) + +definition undefined_StatusReg :: " unit \<Rightarrow>((register_value),(StatusReg),(exception))monad " where + " undefined_StatusReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + internal_pick [Mk_StatusReg w__0]))" + + +(*val _get_StatusReg : StatusReg -> mword ty32*) + +fun get_StatusReg :: " StatusReg \<Rightarrow>(32)Word.word " where + " get_StatusReg (Mk_StatusReg (v)) = ( v )" + + +(*val _set_StatusReg : register_ref regstate register_value StatusReg -> mword ty32 -> M unit*) + +definition set_StatusReg :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_StatusReg v) in + write_reg r_ref r)))" + + +(*val _get_StatusReg_CU : StatusReg -> mword ty4*) + +fun get_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word " where + " get_StatusReg_CU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word))" + + +(*val _set_StatusReg_CU : register_ref regstate register_value StatusReg -> mword ty4 -> M unit*) + +definition set_StatusReg_CU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_CU r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 31 :: int)::ii) (( 28 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_CU : StatusReg -> mword ty4 -> StatusReg*) + +fun update_StatusReg_CU :: " StatusReg \<Rightarrow>(4)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_CU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 31 :: int)::ii) (( 28 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_BEV : StatusReg -> mword ty1*) + +fun get_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_BEV (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_BEV : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_BEV :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_BEV r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_BEV : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_BEV :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_BEV (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IM : StatusReg -> mword ty8*) + +fun get_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word " where + " get_StatusReg_IM (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +(*val _set_StatusReg_IM : register_ref regstate register_value StatusReg -> mword ty8 -> M unit*) + +definition set_StatusReg_IM :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_IM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IM : StatusReg -> mword ty8 -> StatusReg*) + +fun update_StatusReg_IM :: " StatusReg \<Rightarrow>(8)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IM (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KX : StatusReg -> mword ty1*) + +fun get_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_KX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_KX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_KX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_KX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_KX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_SX : StatusReg -> mword ty1*) + +fun get_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_SX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_SX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_SX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_SX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_SX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_SX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_SX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_UX : StatusReg -> mword ty1*) + +fun get_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_UX (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_UX : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_UX :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_UX r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_UX : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_UX :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_UX (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_KSU : StatusReg -> mword ty2*) + +fun get_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word " where + " get_StatusReg_KSU (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word))" + + +(*val _set_StatusReg_KSU : register_ref regstate register_value StatusReg -> mword ty2 -> M unit*) + +definition set_StatusReg_KSU :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_KSU r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 3 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_KSU : StatusReg -> mword ty2 -> StatusReg*) + +fun update_StatusReg_KSU :: " StatusReg \<Rightarrow>(2)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_KSU (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 3 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_ERL : StatusReg -> mword ty1*) + +fun get_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_ERL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_ERL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_ERL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_ERL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_ERL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_ERL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_ERL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_EXL : StatusReg -> mword ty1*) + +fun get_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_EXL (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_EXL : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_EXL :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_EXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_EXL : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_EXL :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_EXL (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 32 Word.word)))" + + +(*val _get_StatusReg_IE : StatusReg -> mword ty1*) + +fun get_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word " where + " get_StatusReg_IE (Mk_StatusReg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_StatusReg_IE : register_ref regstate register_value StatusReg -> mword ty1 -> M unit*) + +definition set_StatusReg_IE :: "((regstate),(register_value),(StatusReg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_StatusReg_IE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let r = ((get_StatusReg w__0 :: 32 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 32 Word.word)) in + write_reg r_ref (Mk_StatusReg r)))))" + + +(*val _update_StatusReg_IE : StatusReg -> mword ty1 -> StatusReg*) + +fun update_StatusReg_IE :: " StatusReg \<Rightarrow>(1)Word.word \<Rightarrow> StatusReg " where + " update_StatusReg_IE (Mk_StatusReg (v)) x = ( + Mk_StatusReg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 32 Word.word)))" + + +(*val execute_branch : mword ty64 -> M unit*) + +definition execute_branch :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_branch pc = ( + write_reg delayedPC_ref pc \<then> write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val NotWordVal : mword ty64 -> bool*) + +definition NotWordVal :: "(64)Word.word \<Rightarrow> bool " where + " NotWordVal word1 = ( + (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word1 (( 31 :: int)::ii))) :: 1 Word.word)) (( 32 :: int)::ii) + :: 32 Word.word)) \<noteq> ((subrange_vec_dec word1 (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))))" + + +(*val rGPR : mword ty5 -> M (mword ty64)*) + +definition rGPR :: "(5)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " rGPR idx = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . + return ((access_list_dec w__0 i :: 64 Word.word)))))" + + +(*val wGPR : mword ty5 -> mword ty64 -> M unit*) + +definition wGPR :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " wGPR idx v = ( + (let i = (Word.uint idx) in + if (((i = (( 0 :: int)::ii)))) then return () + else + read_reg GPR_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + write_reg GPR_ref ((update_list_dec w__0 i v :: ( 64 Word.word) list)))))" + + + + + + + + + + + + + + + + +(*val Exception_of_num : integer -> Exception*) + +definition Exception_of_num :: " int \<Rightarrow> Exception " where + " Exception_of_num arg0 = ( + (let l__81 = arg0 in + if (((l__81 = (( 0 :: int)::ii)))) then Interrupt + else if (((l__81 = (( 1 :: int)::ii)))) then TLBMod + else if (((l__81 = (( 2 :: int)::ii)))) then TLBL + else if (((l__81 = (( 3 :: int)::ii)))) then TLBS + else if (((l__81 = (( 4 :: int)::ii)))) then AdEL + else if (((l__81 = (( 5 :: int)::ii)))) then AdES + else if (((l__81 = (( 6 :: int)::ii)))) then Sys + else if (((l__81 = (( 7 :: int)::ii)))) then Bp + else if (((l__81 = (( 8 :: int)::ii)))) then ResI + else if (((l__81 = (( 9 :: int)::ii)))) then CpU + else if (((l__81 = (( 10 :: int)::ii)))) then Ov + else if (((l__81 = (( 11 :: int)::ii)))) then Tr + else if (((l__81 = (( 12 :: int)::ii)))) then C2E + else if (((l__81 = (( 13 :: int)::ii)))) then C2Trap + else if (((l__81 = (( 14 :: int)::ii)))) then XTLBRefillL + else if (((l__81 = (( 15 :: int)::ii)))) then XTLBRefillS + else if (((l__81 = (( 16 :: int)::ii)))) then XTLBInvL + else if (((l__81 = (( 17 :: int)::ii)))) then XTLBInvS + else MCheck))" + + +(*val num_of_Exception : Exception -> integer*) + +fun num_of_Exception :: " Exception \<Rightarrow> int " where + " num_of_Exception Interrupt = ( (( 0 :: int)::ii))" +|" num_of_Exception TLBMod = ( (( 1 :: int)::ii))" +|" num_of_Exception TLBL = ( (( 2 :: int)::ii))" +|" num_of_Exception TLBS = ( (( 3 :: int)::ii))" +|" num_of_Exception AdEL = ( (( 4 :: int)::ii))" +|" num_of_Exception AdES = ( (( 5 :: int)::ii))" +|" num_of_Exception Sys = ( (( 6 :: int)::ii))" +|" num_of_Exception Bp = ( (( 7 :: int)::ii))" +|" num_of_Exception ResI = ( (( 8 :: int)::ii))" +|" num_of_Exception CpU = ( (( 9 :: int)::ii))" +|" num_of_Exception Ov = ( (( 10 :: int)::ii))" +|" num_of_Exception Tr = ( (( 11 :: int)::ii))" +|" num_of_Exception C2E = ( (( 12 :: int)::ii))" +|" num_of_Exception C2Trap = ( (( 13 :: int)::ii))" +|" num_of_Exception XTLBRefillL = ( (( 14 :: int)::ii))" +|" num_of_Exception XTLBRefillS = ( (( 15 :: int)::ii))" +|" num_of_Exception XTLBInvL = ( (( 16 :: int)::ii))" +|" num_of_Exception XTLBInvS = ( (( 17 :: int)::ii))" +|" num_of_Exception MCheck = ( (( 18 :: int)::ii))" + + +(*val undefined_Exception : unit -> M Exception*) + +definition undefined_Exception :: " unit \<Rightarrow>((register_value),(Exception),(exception))monad " where + " undefined_Exception _ = ( + internal_pick + [Interrupt,TLBMod,TLBL,TLBS,AdEL,AdES,Sys,Bp,ResI,CpU,Ov,Tr,C2E,C2Trap,XTLBRefillL,XTLBRefillS,XTLBInvL,XTLBInvS,MCheck])" + + +(*val ExceptionCode : Exception -> mword ty5*) + +definition ExceptionCode :: " Exception \<Rightarrow>(5)Word.word " where + " ExceptionCode ex = ( + (let (x :: 8 bits) = + ((case ex of + Interrupt => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + | TLBMod => (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word) + | TLBL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | TLBS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | AdEL => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word) + | AdES => (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word) + | Sys => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word) + | Bp => (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word) + | ResI => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word) + | CpU => (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B1] :: 8 Word.word) + | Ov => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B0] :: 8 Word.word) + | Tr => (vec_of_bits [B0,B0,B0,B0,B1,B1,B0,B1] :: 8 Word.word) + | C2E => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | C2Trap => (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBRefillS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | XTLBInvL => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word) + | XTLBInvS => (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word) + | MCheck => (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word) + )) in + (subrange_vec_dec x (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)))" + + +(*val SignalExceptionMIPS : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionMIPS :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionMIPS ex kccBase = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + ((if ((\<not> ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg inBranchDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + write_reg CP0EPC_ref ((sub_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)) \<then> + set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1] :: 1 Word.word)) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + write_reg CP0EPC_ref w__3 \<then> set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0] :: 1 Word.word))) + else return () ) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__4 :: StatusReg) . + (let vectorOffset = + (if ((bits_to_bool ((get_StatusReg_EXL w__4 :: 1 Word.word)))) then + (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if ((((((ex = XTLBRefillL))) \<or> (((ex = XTLBRefillS)))))) then + (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else if (((ex = C2Trap))) then (vec_of_bits [B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + else (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__5 :: StatusReg) . + (let (vectorBase :: 64 bits) = + (if ((bits_to_bool ((get_StatusReg_BEV w__5 :: 1 Word.word)))) then + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) in + ((write_reg + nextPC_ref + ((sub_vec + ((add_vec vectorBase ((sign_extend1 (( 64 :: int)::ii) vectorOffset :: 64 Word.word)) :: 64 Word.word)) + kccBase + :: 64 Word.word)) \<then> + set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex :: 5 Word.word))) \<then> + set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1] :: 1 Word.word)) \<then> throw (ISAException () )))))))" + + +(*val SignalException : forall 'o. Exception -> M 'o*) + +(*val SignalExceptionBadAddr : forall 'o. Exception -> mword ty64 -> M 'o*) + +(*val capRegToCapStruct : mword ty257 -> CapStruct*) + +definition capRegToCapStruct :: "(257)Word.word \<Rightarrow> CapStruct " where + " capRegToCapStruct capReg = ( + (| CapStruct_tag = ((bit_to_bool ((access_vec_dec capReg (( 256 :: int)::ii))))), + CapStruct_padding = ((subrange_vec_dec capReg (( 255 :: int)::ii) (( 248 :: int)::ii) :: 8 Word.word)), + CapStruct_otype = ((subrange_vec_dec capReg (( 247 :: int)::ii) (( 224 :: int)::ii) :: 24 Word.word)), + CapStruct_uperms = ((subrange_vec_dec capReg (( 223 :: int)::ii) (( 208 :: int)::ii) :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((subrange_vec_dec capReg (( 207 :: int)::ii) (( 204 :: int)::ii) :: 4 Word.word)), + CapStruct_access_system_regs = ((bit_to_bool ((access_vec_dec capReg (( 203 :: int)::ii))))), + CapStruct_permit_unseal = ((bit_to_bool ((access_vec_dec capReg (( 202 :: int)::ii))))), + CapStruct_permit_ccall = ((bit_to_bool ((access_vec_dec capReg (( 201 :: int)::ii))))), + CapStruct_permit_seal = ((bit_to_bool ((access_vec_dec capReg (( 200 :: int)::ii))))), + CapStruct_permit_store_local_cap = ((bit_to_bool ((access_vec_dec capReg (( 199 :: int)::ii))))), + CapStruct_permit_store_cap = ((bit_to_bool ((access_vec_dec capReg (( 198 :: int)::ii))))), + CapStruct_permit_load_cap = ((bit_to_bool ((access_vec_dec capReg (( 197 :: int)::ii))))), + CapStruct_permit_store = ((bit_to_bool ((access_vec_dec capReg (( 196 :: int)::ii))))), + CapStruct_permit_load = ((bit_to_bool ((access_vec_dec capReg (( 195 :: int)::ii))))), + CapStruct_permit_execute = ((bit_to_bool ((access_vec_dec capReg (( 194 :: int)::ii))))), + CapStruct_global = ((bit_to_bool ((access_vec_dec capReg (( 193 :: int)::ii))))), + CapStruct_sealed = ((bit_to_bool ((access_vec_dec capReg (( 192 :: int)::ii))))), + CapStruct_address = ((subrange_vec_dec capReg (( 191 :: int)::ii) (( 128 :: int)::ii) :: 64 Word.word)), + CapStruct_base = ((subrange_vec_dec capReg (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)), + CapStruct_length = ((subrange_vec_dec capReg (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) |) )" + + +(*val getCapPerms : CapStruct -> mword ty31*) + +definition getCapPerms :: " CapStruct \<Rightarrow>(31)Word.word " where + " getCapPerms cap = ( + (concat_vec(CapStruct_uperms cap) + ((concat_vec(CapStruct_perm_reserved11_14 cap) + ((concat_vec ((bool_to_bits(CapStruct_access_system_regs cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_unseal cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_ccall cap) :: 1 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_permit_seal cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_local_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load_cap cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_store cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_load cap) :: 1 Word.word)) + ((concat_vec + ((bool_to_bits(CapStruct_permit_execute cap) + :: 1 Word.word)) + ((bool_to_bits(CapStruct_global cap) :: 1 Word.word)) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 8 Word.word)) + :: 9 Word.word)) + :: 10 Word.word)) + :: 11 Word.word)) + :: 15 Word.word)) + :: 31 Word.word))" + + +(*val capStructToMemBits256 : CapStruct -> mword ty256*) + +definition capStructToMemBits256 :: " CapStruct \<Rightarrow>(256)Word.word " where + " capStructToMemBits256 cap = ( + (concat_vec(CapStruct_padding cap) + ((concat_vec(CapStruct_otype cap) + ((concat_vec ((getCapPerms cap :: 31 Word.word)) + ((concat_vec ((bool_to_bits(CapStruct_sealed cap) :: 1 Word.word)) + ((concat_vec(CapStruct_address cap) + ((concat_vec(CapStruct_base cap)(CapStruct_length cap) :: 128 Word.word)) + :: 192 Word.word)) + :: 193 Word.word)) + :: 224 Word.word)) + :: 248 Word.word)) + :: 256 Word.word))" + + +(*val capStructToCapReg : CapStruct -> mword ty257*) + +definition capStructToCapReg :: " CapStruct \<Rightarrow>(257)Word.word " where + " capStructToCapReg cap = ( + (concat_vec ((bool_to_bits(CapStruct_tag cap) :: 1 Word.word)) + ((capStructToMemBits256 cap :: 256 Word.word)) + :: 257 Word.word))" + + +(*val getCapBase : CapStruct -> integer*) + +definition getCapBase :: " CapStruct \<Rightarrow> int " where + " getCapBase c = ( Word.uint(CapStruct_base c))" + + +definition null_cap :: " CapStruct " where + " null_cap = ( + (| CapStruct_tag = False, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((zeros0 (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((zeros0 (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = False, + CapStruct_permit_unseal = False, + CapStruct_permit_ccall = False, + CapStruct_permit_seal = False, + CapStruct_permit_store_local_cap = False, + CapStruct_permit_store_cap = False, + CapStruct_permit_load_cap = False, + CapStruct_permit_store = False, + CapStruct_permit_load = False, + CapStruct_permit_execute = False, + CapStruct_global = False, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +(*val int_to_cap : mword ty64 -> CapStruct*) + +definition int_to_cap :: "(64)Word.word \<Rightarrow> CapStruct " where + " int_to_cap address = ( (null_cap (| CapStruct_address := address |)))" + + +(* +Set the offset capability of the a capability to given value and return the result, along with a boolean indicating true if the operation preserved the existing bounds of the capability. When using compressed capabilities, setting the offset far outside the capability bounds can cause the result to become unrepresentable (XXX mention guarantees). Additionally in some implementations a fast representablity check may be used that could cause the operation to return failure even though the capability would be representable (XXX provide details). + *) +(*val setCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition setCapOffset :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct " where + " setCapOffset c offset = ( + (True, (c (| CapStruct_address := ((add_vec(CapStruct_base c) offset :: 64 Word.word))|))))" + + +definition SignalException :: " Exception \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalException ex = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + ((if ((\<not> ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> pc . + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (let (success, epcc) = (setCapOffset pcc pc) in + if success then write_reg C31_ref ((capStructToCapReg epcc :: 257 Word.word)) + else + write_reg + C31_ref + ((capStructToCapReg + ((int_to_cap + ((add_vec_int + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase pcc)) + :: 64 Word.word)) ((Word.uint pc)) + :: 64 Word.word)))) + :: 257 Word.word)))))) + else return () ) \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__2 :: CapReg) . + (write_reg nextPCC_ref w__2 \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__3 :: CapReg) . + (write_reg delayedPCC_ref w__3 \<then> + (read_reg C29_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__4 :: 257 Word.word) . + (let base = (getCapBase ((capRegToCapStruct w__4))) in + SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) base :: 64 Word.word))))))))" + + +definition SignalExceptionBadAddr :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionBadAddr ex badAddr = ( write_reg CP0BadVAddr_ref badAddr \<then> SignalException ex )" + + +(*val SignalExceptionTLB : forall 'o. Exception -> mword ty64 -> M 'o*) + +definition SignalExceptionTLB :: " Exception \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " SignalExceptionTLB ex badAddr = ( + (((((write_reg CP0BadVAddr_ref badAddr \<then> + set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 :: int)::ii) (( 13 :: int)::ii) :: 19 Word.word))) \<then> + set_XContextReg_XBadVPN2 TLBXContext_ref + ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \<then> + set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word))) \<then> + SignalException ex )" + + +(*val MemAccessType_of_num : integer -> MemAccessType*) + +definition MemAccessType_of_num :: " int \<Rightarrow> MemAccessType " where + " MemAccessType_of_num arg0 = ( + (let l__79 = arg0 in + if (((l__79 = (( 0 :: int)::ii)))) then Instruction + else if (((l__79 = (( 1 :: int)::ii)))) then LoadData + else StoreData))" + + +(*val num_of_MemAccessType : MemAccessType -> integer*) + +fun num_of_MemAccessType :: " MemAccessType \<Rightarrow> int " where + " num_of_MemAccessType Instruction = ( (( 0 :: int)::ii))" +|" num_of_MemAccessType LoadData = ( (( 1 :: int)::ii))" +|" num_of_MemAccessType StoreData = ( (( 2 :: int)::ii))" + + +(*val undefined_MemAccessType : unit -> M MemAccessType*) + +definition undefined_MemAccessType :: " unit \<Rightarrow>((register_value),(MemAccessType),(exception))monad " where + " undefined_MemAccessType _ = ( internal_pick [Instruction,LoadData,StoreData])" + + +(*val AccessLevel_of_num : integer -> AccessLevel*) + +definition AccessLevel_of_num :: " int \<Rightarrow> AccessLevel " where + " AccessLevel_of_num arg0 = ( + (let l__77 = arg0 in + if (((l__77 = (( 0 :: int)::ii)))) then User + else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + else Kernel))" + + +(*val num_of_AccessLevel : AccessLevel -> integer*) + +fun num_of_AccessLevel :: " AccessLevel \<Rightarrow> int " where + " num_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" num_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" num_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(*val undefined_AccessLevel : unit -> M AccessLevel*) + +definition undefined_AccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel),(exception))monad " where + " undefined_AccessLevel _ = ( internal_pick [User,Supervisor,Kernel])" + + +(*val int_of_AccessLevel : AccessLevel -> ii*) + +fun int_of_AccessLevel :: " AccessLevel \<Rightarrow> int " where + " int_of_AccessLevel User = ( (( 0 :: int)::ii))" +|" int_of_AccessLevel Supervisor = ( (( 1 :: int)::ii))" +|" int_of_AccessLevel Kernel = ( (( 2 :: int)::ii))" + + +(* +Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + *) +(*val grantsAccess : AccessLevel -> AccessLevel -> bool*) + +definition grantsAccess :: " AccessLevel \<Rightarrow> AccessLevel \<Rightarrow> bool " where + " grantsAccess currentLevel requiredLevel = ( + ((int_of_AccessLevel currentLevel)) \<ge> ((int_of_AccessLevel requiredLevel)))" + + +(* +Returns the current effective access level determined by accessing the relevant parts of the MIPS status register. + *) +(*val getAccessLevel : unit -> M AccessLevel*) + +definition getAccessLevel :: " unit \<Rightarrow>((register_value),(AccessLevel),(exception))monad " where + " getAccessLevel _ = ( + or_boolM + (read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_EXL w__0 :: 1 Word.word)))))) + (read_reg CP0Status_ref \<bind> (\<lambda> (w__1 :: StatusReg) . + return ((bits_to_bool ((get_StatusReg_ERL w__1 :: 1 Word.word)))))) \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then return Kernel + else + read_reg CP0Status_ref \<bind> (\<lambda> (w__3 :: StatusReg) . + (let p__133 = ((get_StatusReg_KSU w__3 :: 2 Word.word)) in + (let b__0 = p__133 in + return (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Kernel + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then User + else User))))))" + + +(*val checkCP0Access : unit -> M unit*) + +definition checkCP0Access :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkCP0Access _ = ( + getAccessLevel () \<bind> (\<lambda> accessLevel . + and_boolM (return (((accessLevel \<noteq> Kernel)))) + (read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + return ((\<not> ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii))))))))) \<bind> (\<lambda> (w__1 :: + bool) . + if w__1 then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0,B0] :: 2 Word.word) \<then> SignalException CpU + else return () )))" + + +(*val incrementCP0Count : unit -> M unit*) + +definition incrementCP0Count :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " incrementCP0Count _ = ( + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__1 :: 6 Word.word) . + (if (((w__0 = w__1))) then return TLBIndexMax + else + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> (\<lambda> (w__2 :: 6 Word.word) . + return ((sub_vec_int w__2 (( 1 :: int)::ii) :: 6 Word.word)))) \<bind> (\<lambda> (w__3 :: 6 Word.word) . + (write_reg TLBRandom_ref w__3 \<then> + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (write_reg CP0Count_ref ((add_vec_int w__4 (( 1 :: int)::ii) :: 32 Word.word)) \<then> + (read_reg CP0Count_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 bits) . + (read_reg CP0Compare_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + ((if (((w__5 = w__6))) then + read_reg CP0Cause_ref \<bind> (\<lambda> (w__7 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((or_vec ((get_CauseReg_IP w__7 :: 8 Word.word)) + (vec_of_bits [B1,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word) + :: 8 Word.word))) + else return () ) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__8 :: StatusReg) . + (let ims = ((get_StatusReg_IM w__8 :: 8 Word.word)) in + read_reg CP0Cause_ref \<bind> (\<lambda> (w__9 :: CauseReg) . + (let ips = ((get_CauseReg_IP w__9 :: 8 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__10 :: StatusReg) . + (let ie = ((get_StatusReg_IE w__10 :: 1 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__11 :: StatusReg) . + (let exl = ((get_StatusReg_EXL w__11 :: 1 Word.word)) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__12 :: StatusReg) . + (let erl = ((get_StatusReg_ERL w__12 :: 1 Word.word)) in + if (((((\<not> ((bits_to_bool exl)))) \<and> (((((\<not> ((bits_to_bool erl)))) \<and> (((((bits_to_bool ie)) \<and> (((((and_vec ips ims :: 8 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))))))))) then + SignalException Interrupt + else return () )))))))))))))))))" + + +(*val decode_failure_of_num : integer -> decode_failure*) + +definition decode_failure_of_num :: " int \<Rightarrow> decode_failure " where + " decode_failure_of_num arg0 = ( + (let l__74 = arg0 in + if (((l__74 = (( 0 :: int)::ii)))) then No_matching_pattern + else if (((l__74 = (( 1 :: int)::ii)))) then Unsupported_instruction + else if (((l__74 = (( 2 :: int)::ii)))) then Illegal_instruction + else Internal_error))" + + +(*val num_of_decode_failure : decode_failure -> integer*) + +definition num_of_decode_failure :: " decode_failure \<Rightarrow> int " where + " num_of_decode_failure no_matching_pattern = ( (( 0 :: int)::ii))" + + +(*val undefined_decode_failure : unit -> M decode_failure*) + +definition undefined_decode_failure :: " unit \<Rightarrow>((register_value),(decode_failure),(exception))monad " where + " undefined_decode_failure _ = ( + internal_pick [No_matching_pattern,Unsupported_instruction,Illegal_instruction,Internal_error])" + + +(*val Comparison_of_num : integer -> Comparison*) + +definition Comparison_of_num :: " int \<Rightarrow> Comparison " where + " Comparison_of_num arg0 = ( + (let l__67 = arg0 in + if (((l__67 = (( 0 :: int)::ii)))) then EQ' + else if (((l__67 = (( 1 :: int)::ii)))) then NE + else if (((l__67 = (( 2 :: int)::ii)))) then GE + else if (((l__67 = (( 3 :: int)::ii)))) then GEU + else if (((l__67 = (( 4 :: int)::ii)))) then GT' + else if (((l__67 = (( 5 :: int)::ii)))) then LE + else if (((l__67 = (( 6 :: int)::ii)))) then LT' + else LTU))" + + +(*val num_of_Comparison : Comparison -> integer*) + +fun num_of_Comparison :: " Comparison \<Rightarrow> int " where + " num_of_Comparison EQ' = ( (( 0 :: int)::ii))" +|" num_of_Comparison NE = ( (( 1 :: int)::ii))" +|" num_of_Comparison GE = ( (( 2 :: int)::ii))" +|" num_of_Comparison GEU = ( (( 3 :: int)::ii))" +|" num_of_Comparison GT' = ( (( 4 :: int)::ii))" +|" num_of_Comparison LE = ( (( 5 :: int)::ii))" +|" num_of_Comparison LT' = ( (( 6 :: int)::ii))" +|" num_of_Comparison LTU = ( (( 7 :: int)::ii))" + + +(*val undefined_Comparison : unit -> M Comparison*) + +definition undefined_Comparison :: " unit \<Rightarrow>((register_value),(Comparison),(exception))monad " where + " undefined_Comparison _ = ( internal_pick [EQ',NE,GE,GEU,GT',LE,LT',LTU])" + + +(*val compare : Comparison -> mword ty64 -> mword ty64 -> bool*) + +fun compare :: " Comparison \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow> bool " where + " compare EQ' valA valB = ( (valA = valB))" +|" compare NE valA valB = ( (valA \<noteq> valB))" +|" compare GE valA valB = ( zopz0zKzJ_s valA valB )" +|" compare GEU valA valB = ( zopz0zKzJ_u valA valB )" +|" compare GT' valA valB = ( zopz0zI_s valB valA )" +|" compare LE valA valB = ( zopz0zKzJ_s valB valA )" +|" compare LT' valA valB = ( zopz0zI_s valA valB )" +|" compare LTU valA valB = ( zopz0zI_u valA valB )" + + +(*val WordType_of_num : integer -> WordType*) + +definition WordType_of_num :: " int \<Rightarrow> WordType " where + " WordType_of_num arg0 = ( + (let l__64 = arg0 in + if (((l__64 = (( 0 :: int)::ii)))) then B + else if (((l__64 = (( 1 :: int)::ii)))) then H + else if (((l__64 = (( 2 :: int)::ii)))) then W + else D))" + + +(*val num_of_WordType : WordType -> integer*) + +fun num_of_WordType :: " WordType \<Rightarrow> int " where + " num_of_WordType B = ( (( 0 :: int)::ii))" +|" num_of_WordType H = ( (( 1 :: int)::ii))" +|" num_of_WordType W = ( (( 2 :: int)::ii))" +|" num_of_WordType D = ( (( 3 :: int)::ii))" + + +(*val undefined_WordType : unit -> M WordType*) + +definition undefined_WordType :: " unit \<Rightarrow>((register_value),(WordType),(exception))monad " where + " undefined_WordType _ = ( internal_pick [B,H,W,D])" + + +(*val wordWidthBytes : WordType -> integer*) + +fun wordWidthBytes :: " WordType \<Rightarrow> int " where + " wordWidthBytes B = ( (( 1 :: int)::ii))" +|" wordWidthBytes H = ( (( 2 :: int)::ii))" +|" wordWidthBytes W = ( (( 4 :: int)::ii))" +|" wordWidthBytes D = ( (( 8 :: int)::ii))" + + +definition alignment_width :: " int " where + " alignment_width = ( (( 16 :: int)::ii))" + + +(*val isAddressAligned : mword ty64 -> WordType -> bool*) + +definition isAddressAligned :: "(64)Word.word \<Rightarrow> WordType \<Rightarrow> bool " where + " isAddressAligned addr wordType = ( + (let a = (Word.uint addr) in + (((a div alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 :: int)::ii))) div + alignment_width)))))" + + +(*val MEMr_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_wrapper addr size1 = ( + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val MEMr_reserve_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> M (mword 'p8_times_n_)*) + +definition MEMr_reserve_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('p8_times_n_::len)Word.word),(exception))monad " where + " MEMr_reserve_wrapper addr size1 = ( + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 :: (( 'p8_times_n_::len)Word.word) M) \<bind> (\<lambda> w__0 . + return ((reverse_endianness w__0 :: ( 'p8_times_n_::len)Word.word))))" + + +(*val init_cp0_state : unit -> M unit*) + +definition init_cp0_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_cp0_state _ = ( set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1 :: 1 Word.word)))" + + +(*val init_cp2_state : unit -> M unit*) + +(*val cp2_next_pc : unit -> M unit*) + +(*val dump_cp2_state : unit -> M unit*) + +(*val tlbEntryMatch : mword ty2 -> mword ty27 -> mword ty8 -> TLBEntry -> bool*) + +definition tlbEntryMatch :: "(2)Word.word \<Rightarrow>(27)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> TLBEntry \<Rightarrow> bool " where + " tlbEntryMatch r vpn2 asid entry = ( + (let entryValid = ((get_TLBEntry_valid entry :: 1 Word.word)) in + (let entryR = ((get_TLBEntry_r entry :: 2 Word.word)) in + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let entryVPN = ((get_TLBEntry_vpn2 entry :: 27 Word.word)) in + (let entryASID = ((get_TLBEntry_asid entry :: 8 Word.word)) in + (let entryG = ((get_TLBEntry_g entry :: 1 Word.word)) in + (let (vpnMask :: 27 bits) = + ((not_vec ((zero_extend1 (( 27 :: int)::ii) entryMask :: 27 Word.word)) :: 27 Word.word)) in + (((bits_to_bool entryValid)) \<and> ((((((r = entryR))) \<and> ((((((((and_vec vpn2 vpnMask :: 27 Word.word)) = ((and_vec entryVPN vpnMask :: 27 Word.word))))) \<and> ((((((asid = entryASID))) \<or> ((bits_to_bool entryG))))))))))))))))))))" + + +(*val tlbSearch : mword ty64 -> M (maybe (mword ty6))*) + +definition tlbSearch :: "(64)Word.word \<Rightarrow>((register_value),(((6)Word.word)option),(exception))monad " where + " tlbSearch VAddr = ( + catch_early_return + ((let r = ((subrange_vec_dec VAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let vpn2 = ((subrange_vec_dec VAddr (( 39 :: int)::ii) (( 13 :: int)::ii) :: 27 Word.word)) in + liftR (read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (let asid = ((get_TLBEntryHiReg_ASID w__0 :: 8 Word.word)) in + (foreachM (index_list (( 0 :: int)::ii) (( 63 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> idx unit_var . + liftR (reg_deref ((access_list_dec TLBEntries idx))) \<bind> (\<lambda> (w__1 :: TLBEntry) . + if ((tlbEntryMatch r vpn2 asid w__1)) then + (early_return (Some ((to_bits ((make_the_value (( 6 :: int)::ii) :: 6 itself)) idx :: 6 Word.word))) :: (unit, ( ( 6 Word.word)option)) + MR) + else return () ))) \<then> + return None))))))" + + +(*val TLBTranslate2 : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslate2 :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslate2 vAddr accessType = ( + (tlbSearch vAddr :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> idx . + (case idx of + Some (idx) => + (let i = (Word.uint idx) in + reg_deref ((access_list_dec TLBEntries i)) \<bind> (\<lambda> entry . + (let entryMask = ((get_TLBEntry_pagemask entry :: 16 Word.word)) in + (let b__0 = entryMask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + return (( 12 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) + then + return (( 14 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 16 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 18 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 20 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 22 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 24 :: int)::ii) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 26 :: int)::ii) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) + then + return (( 28 :: int)::ii) + else undefined_range (( 12 :: int)::ii) (( 28 :: int)::ii)) \<bind> (\<lambda> (evenOddBit :: int) . + (let isOdd = (access_vec_dec vAddr evenOddBit) in + (let ((caps :: 1 bits), (capl :: 1 bits), (pfn :: 24 bits), (d :: 1 bits), (v :: 1 bits)) = + (if ((bit_to_bool isOdd)) then + ((get_TLBEntry_caps1 entry :: 1 Word.word), + (get_TLBEntry_capl1 entry :: 1 Word.word), + (get_TLBEntry_pfn1 entry :: 24 Word.word), + (get_TLBEntry_d1 entry :: 1 Word.word), + (get_TLBEntry_v1 entry :: 1 Word.word)) + else + ((get_TLBEntry_caps0 entry :: 1 Word.word), + (get_TLBEntry_capl0 entry :: 1 Word.word), + (get_TLBEntry_pfn0 entry :: 24 Word.word), + (get_TLBEntry_d0 entry :: 1 Word.word), + (get_TLBEntry_v0 entry :: 1 Word.word))) in + if ((\<not> ((bits_to_bool v)))) then + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr + :: (( 64 Word.word * bool)) M) + else if ((((((accessType = StoreData))) \<and> ((\<not> ((bits_to_bool d))))))) then + (SignalExceptionTLB TLBMod vAddr :: (( 64 Word.word * bool)) M) + else + (let (res :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) + ((subrange_subrange_concat + (((((((( 23 :: int)::ii) - + ((((evenOddBit - (( 12 :: int)::ii))) - (( 1 :: int)::ii))))) + + + ((evenOddBit - (( 1 :: int)::ii))))) + - (((( 0 :: int)::ii) - (( 1 :: int)::ii))))) pfn + (( 23 :: int)::ii) ((evenOddBit - (( 12 :: int)::ii))) vAddr + ((evenOddBit - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 36 Word.word)) + :: 64 Word.word)) in + return (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl)))))))))) + | None => + (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr + :: (( 64 Word.word * bool)) M) + )))" + + +(*val TLBTranslateC : mword ty64 -> MemAccessType -> M (mword ty64 * bool)*) + +definition TLBTranslateC :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word*bool),(exception))monad " where + " TLBTranslateC vAddr accessType = ( + getAccessLevel () \<bind> (\<lambda> currentAccessLevel . + (let compat32 = + (((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 31 :: int)::ii) :: 31 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1] + :: 31 Word.word)) in + (let b__0 = ((subrange_vec_dec vAddr (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word)) in + (let ((requiredLevel :: AccessLevel), (addr :: ( 64 bits)option)) = + (if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then + (case (compat32, (subrange_vec_dec vAddr (( 30 :: int)::ii) (( 29 :: int)::ii) :: 2 Word.word)) of + (True, b__1) => + if (((b__1 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then (Kernel, None) + else if (((b__1 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then (Supervisor, None) + else if (((b__1 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + else + (Kernel, + Some ((concat_vec + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) + ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) + ((subrange_vec_dec vAddr (( 28 :: int)::ii) (( 0 :: int)::ii) :: 29 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))) + | (g__131, g__132) => (Kernel, None) + ) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (Kernel, + Some ((concat_vec (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word) + ((subrange_vec_dec vAddr (( 58 :: int)::ii) (( 0 :: int)::ii) :: 59 Word.word)) + :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then (Supervisor, None) + else (User, None)) in + if ((\<not> ((grantsAccess currentAccessLevel requiredLevel)))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else + (case addr of + Some (a) => return (a, False) + | None => + if (((((\<not> compat32)) \<and> ((((Word.uint ((subrange_vec_dec vAddr (( 61 :: int)::ii) (( 0 :: int)::ii) :: 62 Word.word)))) > MAX_VA))))) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else (TLBTranslate2 vAddr accessType :: (( 64 Word.word * bool)) M) + ) \<bind> (\<lambda> varstup . (let ((pa :: 64 bits), (c :: bool)) = varstup in + if ((((Word.uint pa)) > MAX_PA)) then + (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr + :: (( 64 Word.word * bool)) M) + else return (pa, c))))))))" + + +(*val TLBTranslate : mword ty64 -> MemAccessType -> M (mword ty64)*) + +definition TLBTranslate :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " TLBTranslate vAddr accessType = ( + (TLBTranslateC vAddr accessType :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (addr, c) = varstup in + return addr)))" + + +(*val CPtrCmpOp_of_num : integer -> CPtrCmpOp*) + +definition CPtrCmpOp_of_num :: " int \<Rightarrow> CPtrCmpOp " where + " CPtrCmpOp_of_num arg0 = ( + (let l__57 = arg0 in + if (((l__57 = (( 0 :: int)::ii)))) then CEQ + else if (((l__57 = (( 1 :: int)::ii)))) then CNE + else if (((l__57 = (( 2 :: int)::ii)))) then CLT + else if (((l__57 = (( 3 :: int)::ii)))) then CLE + else if (((l__57 = (( 4 :: int)::ii)))) then CLTU + else if (((l__57 = (( 5 :: int)::ii)))) then CLEU + else if (((l__57 = (( 6 :: int)::ii)))) then CEXEQ + else CNEXEQ))" + + +(*val num_of_CPtrCmpOp : CPtrCmpOp -> integer*) + +fun num_of_CPtrCmpOp :: " CPtrCmpOp \<Rightarrow> int " where + " num_of_CPtrCmpOp CEQ = ( (( 0 :: int)::ii))" +|" num_of_CPtrCmpOp CNE = ( (( 1 :: int)::ii))" +|" num_of_CPtrCmpOp CLT = ( (( 2 :: int)::ii))" +|" num_of_CPtrCmpOp CLE = ( (( 3 :: int)::ii))" +|" num_of_CPtrCmpOp CLTU = ( (( 4 :: int)::ii))" +|" num_of_CPtrCmpOp CLEU = ( (( 5 :: int)::ii))" +|" num_of_CPtrCmpOp CEXEQ = ( (( 6 :: int)::ii))" +|" num_of_CPtrCmpOp CNEXEQ = ( (( 7 :: int)::ii))" + + +(*val undefined_CPtrCmpOp : unit -> M CPtrCmpOp*) + +definition undefined_CPtrCmpOp :: " unit \<Rightarrow>((register_value),(CPtrCmpOp),(exception))monad " where + " undefined_CPtrCmpOp _ = ( internal_pick [CEQ,CNE,CLT,CLE,CLTU,CLEU,CEXEQ,CNEXEQ])" + + +(*val ClearRegSet_of_num : integer -> ClearRegSet*) + +definition ClearRegSet_of_num :: " int \<Rightarrow> ClearRegSet " where + " ClearRegSet_of_num arg0 = ( + (let l__54 = arg0 in + if (((l__54 = (( 0 :: int)::ii)))) then GPLo + else if (((l__54 = (( 1 :: int)::ii)))) then GPHi + else if (((l__54 = (( 2 :: int)::ii)))) then CLo + else CHi))" + + +(*val num_of_ClearRegSet : ClearRegSet -> integer*) + +fun num_of_ClearRegSet :: " ClearRegSet \<Rightarrow> int " where + " num_of_ClearRegSet GPLo = ( (( 0 :: int)::ii))" +|" num_of_ClearRegSet GPHi = ( (( 1 :: int)::ii))" +|" num_of_ClearRegSet CLo = ( (( 2 :: int)::ii))" +|" num_of_ClearRegSet CHi = ( (( 3 :: int)::ii))" + + +(*val undefined_ClearRegSet : unit -> M ClearRegSet*) + +definition undefined_ClearRegSet :: " unit \<Rightarrow>((register_value),(ClearRegSet),(exception))monad " where + " undefined_ClearRegSet _ = ( internal_pick [GPLo,GPHi,CLo,CHi])" + + +(*val undefined_CapStruct : unit -> M CapStruct*) + +definition undefined_CapStruct :: " unit \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " undefined_CapStruct _ = ( + undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 :: int)::ii) :: ( 24 Word.word) M) \<bind> (\<lambda> (w__2 :: 24 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__4 :: 4 bits) . + undefined_bool () \<bind> (\<lambda> (w__5 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__6 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__7 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__8 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__9 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__10 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__11 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__12 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__13 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__14 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__15 :: bool) . + undefined_bool () \<bind> (\<lambda> (w__16 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + return ((| CapStruct_tag = w__0, + CapStruct_padding = w__1, + CapStruct_otype = w__2, + CapStruct_uperms = w__3, + CapStruct_perm_reserved11_14 = w__4, + CapStruct_access_system_regs = w__5, + CapStruct_permit_unseal = w__6, + CapStruct_permit_ccall = w__7, + CapStruct_permit_seal = w__8, + CapStruct_permit_store_local_cap = w__9, + CapStruct_permit_store_cap = w__10, + CapStruct_permit_load_cap = w__11, + CapStruct_permit_store = w__12, + CapStruct_permit_load = w__13, + CapStruct_permit_execute = w__14, + CapStruct_global = w__15, + CapStruct_sealed = w__16, + CapStruct_address = w__17, + CapStruct_base = w__18, + CapStruct_length = w__19 |)))))))))))))))))))))))" + + +definition default_cap :: " CapStruct " where + " default_cap = ( + (| CapStruct_tag = True, + CapStruct_padding = ((zeros0 (( 8 :: int)::ii) () :: 8 Word.word)), + CapStruct_otype = ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), + CapStruct_uperms = ((ones (( 16 :: int)::ii) () :: 16 Word.word)), + CapStruct_perm_reserved11_14 = ((ones (( 4 :: int)::ii) () :: 4 Word.word)), + CapStruct_access_system_regs = True, + CapStruct_permit_unseal = True, + CapStruct_permit_ccall = True, + CapStruct_permit_seal = True, + CapStruct_permit_store_local_cap = True, + CapStruct_permit_store_cap = True, + CapStruct_permit_load_cap = True, + CapStruct_permit_store = True, + CapStruct_permit_load = True, + CapStruct_permit_execute = True, + CapStruct_global = True, + CapStruct_sealed = False, + CapStruct_address = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_base = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)), + CapStruct_length = + ((vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] + :: 64 Word.word)) |) )" + + +definition null_cap_bits :: "(256)Word.word " where + " null_cap_bits = ( (capStructToMemBits256 null_cap :: 256 Word.word))" + + +(*val capStructToMemBits : CapStruct -> mword ty256*) + +definition capStructToMemBits :: " CapStruct \<Rightarrow>(256)Word.word " where + " capStructToMemBits cap = ( + (xor_vec ((capStructToMemBits256 cap :: 256 Word.word)) null_cap_bits :: 256 Word.word))" + + +(*val memBitsToCapBits : bool -> mword ty256 -> mword ty257*) + +definition memBitsToCapBits :: " bool \<Rightarrow>(256)Word.word \<Rightarrow>(257)Word.word " where + " memBitsToCapBits tag b = ( + (concat_vec ((bool_to_bits tag :: 1 Word.word)) ((xor_vec b null_cap_bits :: 256 Word.word)) + :: 257 Word.word))" + + +(*val setCapPerms : CapStruct -> mword ty31 -> CapStruct*) + +definition setCapPerms :: " CapStruct \<Rightarrow>(31)Word.word \<Rightarrow> CapStruct " where + " setCapPerms cap perms = ( + (cap (| + CapStruct_uperms := ((subrange_vec_dec perms (( 30 :: int)::ii) (( 15 :: int)::ii) :: 16 Word.word)), CapStruct_perm_reserved11_14 := + ((subrange_vec_dec perms (( 14 :: int)::ii) (( 11 :: int)::ii) :: 4 Word.word)), CapStruct_access_system_regs := + ((bit_to_bool ((access_vec_dec perms (( 10 :: int)::ii))))), CapStruct_permit_unseal := + ((bit_to_bool ((access_vec_dec perms (( 9 :: int)::ii))))), CapStruct_permit_ccall := + ((bit_to_bool ((access_vec_dec perms (( 8 :: int)::ii))))), CapStruct_permit_seal := + ((bit_to_bool ((access_vec_dec perms (( 7 :: int)::ii))))), CapStruct_permit_store_local_cap := + ((bit_to_bool ((access_vec_dec perms (( 6 :: int)::ii))))), CapStruct_permit_store_cap := + ((bit_to_bool ((access_vec_dec perms (( 5 :: int)::ii))))), CapStruct_permit_load_cap := + ((bit_to_bool ((access_vec_dec perms (( 4 :: int)::ii))))), CapStruct_permit_store := + ((bit_to_bool ((access_vec_dec perms (( 3 :: int)::ii))))), CapStruct_permit_load := + ((bit_to_bool ((access_vec_dec perms (( 2 :: int)::ii))))), CapStruct_permit_execute := + ((bit_to_bool ((access_vec_dec perms (( 1 :: int)::ii))))), CapStruct_global := + ((bit_to_bool ((access_vec_dec perms (( 0 :: int)::ii)))))|)))" + + +(*val sealCap : CapStruct -> mword ty24 -> (bool * CapStruct)*) + +definition sealCap :: " CapStruct \<Rightarrow>(24)Word.word \<Rightarrow> bool*CapStruct " where + " sealCap cap otype = ( (True, (cap (| CapStruct_sealed := True, CapStruct_otype := otype |))))" + + +(*val getCapTop : CapStruct -> integer*) + +definition getCapTop :: " CapStruct \<Rightarrow> int " where + " getCapTop c = ( ((Word.uint(CapStruct_base c))) + ((Word.uint(CapStruct_length c))))" + + +(*val getCapOffset : CapStruct -> integer*) + +definition getCapOffset :: " CapStruct \<Rightarrow> int " where + " getCapOffset c = ( + hardware_mod ((((Word.uint(CapStruct_address c))) - ((Word.uint(CapStruct_base c))))) + ((pow2 (( 64 :: int)::ii))))" + + +(*val getCapLength : CapStruct -> integer*) + +definition getCapLength :: " CapStruct \<Rightarrow> int " where + " getCapLength c = ( Word.uint(CapStruct_length c))" + + +(*val getCapCursor : CapStruct -> integer*) + +definition getCapCursor :: " CapStruct \<Rightarrow> int " where + " getCapCursor c = ( Word.uint(CapStruct_address c))" + + +(* +function{incCapOffset} is the same as function{setCapOffset} except that the 64-bit value is added to the current capability offset modulo $2^{64}$ (i.e. signed twos-complement arithemtic). + *) +(*val incCapOffset : CapStruct -> mword ty64 -> (bool * CapStruct)*) + +definition incCapOffset :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow> bool*CapStruct " where + " incCapOffset c delta = ( + (let (newAddr :: 64 bits) = ((add_vec(CapStruct_address c) delta :: 64 Word.word)) in + (True, (c (| CapStruct_address := newAddr |)))))" + + +(* +Returns a capability derived from the given capability by setting the base and top to values provided. The offset of the resulting capability is zero. In case the requested bounds are not exactly representable the returned boolean is false and the returned capability has bounds at least including the region bounded by base and top but rounded to representable values. + *) +(*val setCapBounds : CapStruct -> mword ty64 -> mword ty65 -> (bool * CapStruct)*) + +definition setCapBounds :: " CapStruct \<Rightarrow>(64)Word.word \<Rightarrow>(65)Word.word \<Rightarrow> bool*CapStruct " where + " setCapBounds cap base top1 = ( + (let (length1 :: 65 bits) = + ((sub_vec top1 ((concat_vec (vec_of_bits [B0] :: 1 Word.word) base :: 65 Word.word)) :: 65 Word.word)) in + (True, + (cap (| + CapStruct_base := base, CapStruct_length := + ((subrange_vec_dec length1 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)), CapStruct_address := base |)))))" + + +(*val undefined_ast : unit -> M ast*) + +definition undefined_ast :: " unit \<Rightarrow>((register_value),(ast),(exception))monad " where + " undefined_ast _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__0 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__1 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__3 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__4 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__5 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__6 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__7 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__8 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__9 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__10 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__11 :: 5 Word.word) . + (undefined_bitvector + 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\<bind> (\<lambda> (w__271 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__272 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__273 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__274 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__275 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__276 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__277 :: 11 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__278 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__279 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__280 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__281 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__282 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__283 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__284 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__285 :: 5 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__286 :: bool) . + undefined_ClearRegSet () \<bind> (\<lambda> (w__287 :: ClearRegSet) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__288 :: 16 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__289 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__290 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__291 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__292 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__293 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__294 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__295 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__296 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__297 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__298 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__299 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__300 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__301 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__302 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__303 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__304 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__305 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__306 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__307 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__308 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__309 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__310 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__311 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__312 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__313 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__314 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__315 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__316 :: 11 Word.word) . + (undefined_unit () \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (w__317 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__318 :: 16 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__319 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__320 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__321 :: 16 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__322 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__323 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__324 :: 5 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__325 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__326 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__327 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__328 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__329 :: 8 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__330 :: bool) . + undefined_WordType () \<bind> (\<lambda> (w__331 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__332 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__333 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__334 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__335 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__336 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__337 :: 8 Word.word) . + undefined_WordType () \<bind> (\<lambda> (w__338 :: WordType) . + undefined_bool () \<bind> (\<lambda> (w__339 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__340 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__341 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__342 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__343 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__344 :: 11 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__345 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__346 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__347 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__348 :: 5 Word.word) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 :: int)::ii) :: ( 11 Word.word) M) \<bind> (\<lambda> (w__349 :: 11 Word.word) . + undefined_bool () \<bind> (\<lambda> (w__350 :: bool) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__351 :: 5 Word.word) . + undefined_unit () \<then> + internal_pick + [DADDIU (w__0,w__1,w__2),DADDU (w__3,w__4,w__5),DADDI (w__6,w__7,w__8),DADD (w__9,w__10,w__11),ADD (w__12,w__13,w__14),ADDI (w__15,w__16,w__17),ADDU (w__18,w__19,w__20),ADDIU (w__21,w__22,w__23),DSUBU (w__24,w__25,w__26),DSUB (w__27,w__28,w__29),SUB (w__30,w__31,w__32),SUBU (w__33,w__34,w__35),AND0 (w__36,w__37,w__38),ANDI (w__39,w__40,w__41),OR0 (w__42,w__43,w__44),ORI (w__45,w__46,w__47),NOR (w__48,w__49,w__50),XOR0 (w__51,w__52,w__53),XORI (w__54,w__55,w__56),LUI (w__57,w__58),DSLL (w__59,w__60,w__61),DSLL32 (w__62,w__63,w__64),DSLLV (w__65,w__66,w__67),DSRA (w__68,w__69,w__70),DSRA32 (w__71,w__72,w__73),DSRAV (w__74,w__75,w__76),DSRL (w__77,w__78,w__79),DSRL32 (w__80,w__81,w__82),DSRLV (w__83,w__84,w__85),SLL (w__86,w__87,w__88),SLLV (w__89,w__90,w__91),SRA (w__92,w__93,w__94),SRAV (w__95,w__96,w__97),SRL (w__98,w__99,w__100),SRLV (w__101,w__102,w__103),SLT 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])))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +(*val execute : ast -> M unit*) + +(*val decode : mword ty32 -> maybe ast*) + +definition DDC :: "(5)Word.word " where + " DDC = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" + + +definition IDC :: "(5)Word.word " where + " IDC = ( (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word))" + + +definition KR1C :: "(5)Word.word " where + " KR1C = ( (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word))" + + +definition KR2C :: "(5)Word.word " where + " KR2C = ( (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word))" + + +definition KCC :: "(5)Word.word " where + " KCC = ( (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word))" + + +definition KDC :: "(5)Word.word " where + " KDC = ( (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))" + + +definition EPCC :: "(5)Word.word " where + " EPCC = ( (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word))" + + +definition CapRegs :: "(((regstate),(register_value),((257)Word.word))register_ref)list " where + " CapRegs = ( + [C31_ref,C30_ref,C29_ref,C28_ref,C27_ref,C26_ref,C25_ref,C24_ref,C23_ref,C22_ref,C21_ref,C20_ref, + C19_ref,C18_ref,C17_ref,C16_ref,C15_ref,C14_ref,C13_ref,C12_ref,C11_ref,C10_ref,C09_ref,C08_ref, + C07_ref,C06_ref,C05_ref,C04_ref,C03_ref,C02_ref,C01_ref,C00_ref])" + + +definition max_otype :: " int " where + " max_otype = ( MAX (( 24 :: int)::ii))" + + +definition have_cp2 :: " bool " where + " have_cp2 = ( True )" + + +(* +This function reads a given capability register and returns its contents converted to a CapStruct. +*) +(*val readCapReg : mword ty5 -> M CapStruct*) + +definition readCapReg :: "(5)Word.word \<Rightarrow>((register_value),(CapStruct),(exception))monad " where + " readCapReg n = ( + (let i = (Word.uint n) in + (reg_deref ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + return ((capRegToCapStruct w__0)))))" + + +(*val writeCapReg : mword ty5 -> CapStruct -> M unit*) + +definition writeCapReg :: "(5)Word.word \<Rightarrow> CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where + " writeCapReg n cap = ( + (let i = (Word.uint n) in + write_reg + ((access_list_dec CapRegs i :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((capStructToCapReg cap :: 257 Word.word))))" + + +(*val CapEx_of_num : integer -> CapEx*) + +definition CapEx_of_num :: " int \<Rightarrow> CapEx " where + " CapEx_of_num arg0 = ( + (let l__32 = arg0 in + if (((l__32 = (( 0 :: int)::ii)))) then CapEx_None + else if (((l__32 = (( 1 :: int)::ii)))) then CapEx_LengthViolation + else if (((l__32 = (( 2 :: int)::ii)))) then CapEx_TagViolation + else if (((l__32 = (( 3 :: int)::ii)))) then CapEx_SealViolation + else if (((l__32 = (( 4 :: int)::ii)))) then CapEx_TypeViolation + else if (((l__32 = (( 5 :: int)::ii)))) then CapEx_CallTrap + else if (((l__32 = (( 6 :: int)::ii)))) then CapEx_ReturnTrap + else if (((l__32 = (( 7 :: int)::ii)))) then CapEx_TSSUnderFlow + else if (((l__32 = (( 8 :: int)::ii)))) then CapEx_UserDefViolation + else if (((l__32 = (( 9 :: int)::ii)))) then CapEx_TLBNoStoreCap + else if (((l__32 = (( 10 :: int)::ii)))) then CapEx_InexactBounds + else if (((l__32 = (( 11 :: int)::ii)))) then CapEx_GlobalViolation + else if (((l__32 = (( 12 :: int)::ii)))) then CapEx_PermitExecuteViolation + else if (((l__32 = (( 13 :: int)::ii)))) then CapEx_PermitLoadViolation + else if (((l__32 = (( 14 :: int)::ii)))) then CapEx_PermitStoreViolation + else if (((l__32 = (( 15 :: int)::ii)))) then CapEx_PermitLoadCapViolation + else if (((l__32 = (( 16 :: int)::ii)))) then CapEx_PermitStoreCapViolation + else if (((l__32 = (( 17 :: int)::ii)))) then CapEx_PermitStoreLocalCapViolation + else if (((l__32 = (( 18 :: int)::ii)))) then CapEx_PermitSealViolation + else if (((l__32 = (( 19 :: int)::ii)))) then CapEx_AccessSystemRegsViolation + else if (((l__32 = (( 20 :: int)::ii)))) then CapEx_PermitCCallViolation + else if (((l__32 = (( 21 :: int)::ii)))) then CapEx_AccessCCallIDCViolation + else CapEx_PermitUnsealViolation))" + + +(*val num_of_CapEx : CapEx -> integer*) + +fun num_of_CapEx :: " CapEx \<Rightarrow> int " where + " num_of_CapEx CapEx_None = ( (( 0 :: int)::ii))" +|" num_of_CapEx CapEx_LengthViolation = ( (( 1 :: int)::ii))" +|" num_of_CapEx CapEx_TagViolation = ( (( 2 :: int)::ii))" +|" num_of_CapEx CapEx_SealViolation = ( (( 3 :: int)::ii))" +|" num_of_CapEx CapEx_TypeViolation = ( (( 4 :: int)::ii))" +|" num_of_CapEx CapEx_CallTrap = ( (( 5 :: int)::ii))" +|" num_of_CapEx CapEx_ReturnTrap = ( (( 6 :: int)::ii))" +|" num_of_CapEx CapEx_TSSUnderFlow = ( (( 7 :: int)::ii))" +|" num_of_CapEx CapEx_UserDefViolation = ( (( 8 :: int)::ii))" +|" num_of_CapEx CapEx_TLBNoStoreCap = ( (( 9 :: int)::ii))" +|" num_of_CapEx CapEx_InexactBounds = ( (( 10 :: int)::ii))" +|" num_of_CapEx CapEx_GlobalViolation = ( (( 11 :: int)::ii))" +|" num_of_CapEx CapEx_PermitExecuteViolation = ( (( 12 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadViolation = ( (( 13 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreViolation = ( (( 14 :: int)::ii))" +|" num_of_CapEx CapEx_PermitLoadCapViolation = ( (( 15 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreCapViolation = ( (( 16 :: int)::ii))" +|" num_of_CapEx CapEx_PermitStoreLocalCapViolation = ( (( 17 :: int)::ii))" +|" num_of_CapEx CapEx_PermitSealViolation = ( (( 18 :: int)::ii))" +|" num_of_CapEx CapEx_AccessSystemRegsViolation = ( (( 19 :: int)::ii))" +|" num_of_CapEx CapEx_PermitCCallViolation = ( (( 20 :: int)::ii))" +|" num_of_CapEx CapEx_AccessCCallIDCViolation = ( (( 21 :: int)::ii))" +|" num_of_CapEx CapEx_PermitUnsealViolation = ( (( 22 :: int)::ii))" + + +(*val undefined_CapEx : unit -> M CapEx*) + +definition undefined_CapEx :: " unit \<Rightarrow>((register_value),(CapEx),(exception))monad " where + " undefined_CapEx _ = ( + internal_pick + [CapEx_None,CapEx_LengthViolation,CapEx_TagViolation,CapEx_SealViolation,CapEx_TypeViolation,CapEx_CallTrap,CapEx_ReturnTrap,CapEx_TSSUnderFlow,CapEx_UserDefViolation,CapEx_TLBNoStoreCap,CapEx_InexactBounds,CapEx_GlobalViolation,CapEx_PermitExecuteViolation,CapEx_PermitLoadViolation,CapEx_PermitStoreViolation,CapEx_PermitLoadCapViolation,CapEx_PermitStoreCapViolation,CapEx_PermitStoreLocalCapViolation,CapEx_PermitSealViolation,CapEx_AccessSystemRegsViolation,CapEx_PermitCCallViolation,CapEx_AccessCCallIDCViolation,CapEx_PermitUnsealViolation])" + + +(*val CapExCode : CapEx -> mword ty8*) + +fun CapExCode :: " CapEx \<Rightarrow>(8)Word.word " where + " CapExCode CapEx_None = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_LengthViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_TagViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_SealViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_TypeViolation = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_CallTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_ReturnTrap = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_TSSUnderFlow = ( (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_UserDefViolation = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_TLBNoStoreCap = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_InexactBounds = ( (vec_of_bits [B0,B0,B0,B0,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_GlobalViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitExecuteViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B0,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitLoadCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_PermitStoreLocalCapViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitSealViolation = ( (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessSystemRegsViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitCCallViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B1] :: 8 Word.word))" +|" CapExCode CapEx_AccessCCallIDCViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B0] :: 8 Word.word))" +|" CapExCode CapEx_PermitUnsealViolation = ( (vec_of_bits [B0,B0,B0,B1,B1,B0,B1,B1] :: 8 Word.word))" + + +(*val undefined_CapCauseReg : unit -> M CapCauseReg*) + +definition undefined_CapCauseReg :: " unit \<Rightarrow>((register_value),(CapCauseReg),(exception))monad " where + " undefined_CapCauseReg _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__0 :: 16 Word.word) . + internal_pick [Mk_CapCauseReg w__0]))" + + +fun get_CapCauseReg :: " CapCauseReg \<Rightarrow>(16)Word.word " where + " get_CapCauseReg (Mk_CapCauseReg (v)) = ( v )" + + +definition set_CapCauseReg :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_CapCauseReg v) in + write_reg r_ref r)))" + + +fun get_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word))" + + +definition set_CapCauseReg_ExcCode :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_ExcCode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 8 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +fun update_CapCauseReg_ExcCode :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_ExcCode (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 8 :: int)::ii) x :: 16 Word.word)))" + + +(*val _get_CapCauseReg_RegNum : CapCauseReg -> mword ty8*) + +fun get_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word " where + " get_CapCauseReg_RegNum (Mk_CapCauseReg (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_CapCauseReg_RegNum : register_ref regstate register_value CapCauseReg -> mword ty8 -> M unit*) + +definition set_CapCauseReg_RegNum :: "((regstate),(register_value),(CapCauseReg))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_CapCauseReg_RegNum r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: CapCauseReg) . + (let r = ((get_CapCauseReg w__0 :: 16 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 16 Word.word)) in + write_reg r_ref (Mk_CapCauseReg r)))))" + + +(*val _update_CapCauseReg_RegNum : CapCauseReg -> mword ty8 -> CapCauseReg*) + +fun update_CapCauseReg_RegNum :: " CapCauseReg \<Rightarrow>(8)Word.word \<Rightarrow> CapCauseReg " where + " update_CapCauseReg_RegNum (Mk_CapCauseReg (v)) x = ( + Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 16 Word.word)))" + + +(*val execute_branch_pcc : CapStruct -> M unit*) + +definition execute_branch_pcc :: " CapStruct \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_branch_pcc newPCC = ( + (write_reg + delayedPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset newPCC)) :: 64 Word.word)) \<then> + write_reg delayedPCC_ref ((capStructToCapReg newPCC :: 257 Word.word))) \<then> + write_reg branchPending_ref (vec_of_bits [B1] :: 1 Word.word))" + + +(*val ERETHook : unit -> M unit*) + +definition ERETHook :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " ERETHook _ = ( + (read_reg C31_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (write_reg nextPCC_ref w__0 \<then> + (read_reg C31_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__1 :: CapReg) . write_reg delayedPCC_ref w__1)))" + + +(*val raise_c2_exception8 : forall 'o. CapEx -> mword ty8 -> M 'o*) + +definition raise_c2_exception8 :: " CapEx \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception8 capEx regnum = ( + (set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx :: 8 Word.word)) \<then> + set_CapCauseReg_RegNum CapCause_ref regnum) \<then> + ((let mipsEx = + (if ((((((capEx = CapEx_CallTrap))) \<or> (((capEx = CapEx_ReturnTrap)))))) then C2Trap + else C2E) in + SignalException mipsEx)))" + + +(*val raise_c2_exception : forall 'o. CapEx -> mword ty5 -> M 'o*) + +definition raise_c2_exception :: " CapEx \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception capEx regnum = ( + (let reg8 = ((concat_vec (vec_of_bits [B0,B0,B0] :: 3 Word.word) regnum :: 8 Word.word)) in + if ((((((capEx = CapEx_AccessSystemRegsViolation))) \<and> (((regnum = IDC)))))) then + raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8 + else raise_c2_exception8 capEx reg8))" + + +(*val raise_c2_exception_noreg : forall 'o. CapEx -> M 'o*) + +definition raise_c2_exception_noreg :: " CapEx \<Rightarrow>((register_value),'o,(exception))monad " where + " raise_c2_exception_noreg capEx = ( + raise_c2_exception8 capEx (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word))" + + +(*val pcc_access_system_regs : unit -> M bool*) + +definition pcc_access_system_regs :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " pcc_access_system_regs _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + return(CapStruct_access_system_regs pcc))))" + + +(* +The following function should be called before reading or writing any capability register to check whether it is one of the protected system capabilities. Although it is usually a general purpose capabilty the invoked data capabiltiy (IDC) is restricted in the branch delay slot of the CCall (selector one) instruction to protect the confidentiality and integrity of the invoked sandbox. + *) +(*val register_inaccessible : mword ty5 -> M bool*) + +definition register_inaccessible :: "(5)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " register_inaccessible r = ( + or_boolM + (and_boolM (return (((r = IDC)))) + ((read_reg inCCallDelay_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 Word.word) . + return ((bits_to_bool w__0))))) + (and_boolM + (return ((((((r = KR1C))) \<or> ((((((r = KR2C))) \<or> ((((((r = KDC))) \<or> ((((((r = KCC))) \<or> (((r = EPCC)))))))))))))))) + (pcc_access_system_regs () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))))" + + +(*val MEMr_tagged : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMr_tagged_reserve : mword ty64 -> M (bool * mword ty256)*) + +definition MEMr_tagged_reserve :: "(64)Word.word \<Rightarrow>((register_value),(bool*(256)Word.word),(exception))monad " where + " MEMr_tagged_reserve addr = ( + (assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr) \<bind> (\<lambda> tag . + (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size :: ( 256 Word.word) M) \<bind> (\<lambda> data . + (let ((cast_0 :: bool), (cast_1 :: 256 Word.word)) = (tag, (reverse_endianness data :: 256 Word.word)) in + return (cast_0, (Word.ucast cast_1 :: 256 Word.word))))))" + + +(*val MEMw_tagged : mword ty64 -> bool -> mword ty256 -> M unit*) + +definition MEMw_tagged :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MEMw_tagged addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<then> write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag )" + + +(*val MEMw_tagged_conditional : mword ty64 -> bool -> mword ty256 -> M bool*) + +definition MEMw_tagged_conditional :: "(64)Word.word \<Rightarrow> bool \<Rightarrow>(256)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " MEMw_tagged_conditional addr tag data = ( + ((assert_exp (((((hardware_mod ((Word.uint addr)) cap_size)) = (( 0 :: int)::ii)))) ('''') \<then> + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size) \<then> + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data :: 256 Word.word))) \<bind> (\<lambda> success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else return () ) \<then> return success))" + + +definition cap_addr_mask :: "(64)Word.word " where + " cap_addr_mask = ( + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((((pow2 (( 64 :: int)::ii))) - cap_size)) + :: 64 Word.word))" + + +(*val MEMw_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M unit*) + +definition MEMw_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " MEMw_wrapper addr size1 data = ( + (let ledata = ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word)) in + if (((addr = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + write_reg UART_WDATA_ref ((subrange_vec_dec ledata (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) \<then> + write_reg UART_WRITTEN_ref (vec_of_bits [B1] :: 1 Word.word) + else + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \<then> + MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata) \<then> write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False))" + + +(*val MEMw_conditional_wrapper : forall 'p8_times_n_ . Size 'p8_times_n_ => mword ty64 -> integer -> mword 'p8_times_n_ -> M bool*) + +definition MEMw_conditional_wrapper :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " MEMw_conditional_wrapper addr size1 data = ( + ((assert_exp (((((and_vec addr cap_addr_mask :: 64 Word.word)) = ((and_vec + ((add_vec addr + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((size1 - (( 1 :: int)::ii))) + :: 64 Word.word)) + :: 64 Word.word)) cap_addr_mask + :: 64 Word.word))))) ('''') \<then> + MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1) \<then> + MEMval_conditional + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data :: ( 'p8_times_n_::len)Word.word))) \<bind> (\<lambda> success . + (if success then write_tag_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask :: 64 Word.word)) False + else return () ) \<then> + return success))" + + +(*val addrWrapper : mword ty64 -> MemAccessType -> WordType -> M (mword ty64)*) + +definition addrWrapper :: "(64)Word.word \<Rightarrow> MemAccessType \<Rightarrow> WordType \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " addrWrapper addr accessType width = ( + (let capno = ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)) in + readCapReg capno \<bind> (\<lambda> cap . + ((if ((\<not>(CapStruct_tag cap))) then raise_c2_exception CapEx_TagViolation capno + else if(CapStruct_sealed cap) then raise_c2_exception CapEx_SealViolation capno + else return () ) \<then> + (case accessType of + Instruction => + if ((\<not>(CapStruct_permit_execute cap))) then + raise_c2_exception CapEx_PermitExecuteViolation capno + else return () + | LoadData => + if ((\<not>(CapStruct_permit_load cap))) then raise_c2_exception CapEx_PermitLoadViolation capno + else return () + | StoreData => + if ((\<not>(CapStruct_permit_store cap))) then raise_c2_exception CapEx_PermitStoreViolation capno + else return () + )) \<then> + ((let cursor = (getCapCursor cap) in + (let vAddr = (hardware_mod ((cursor + ((Word.uint addr)))) ((pow2 (( 64 :: int)::ii)))) in + (let size1 = (wordWidthBytes width) in + (let base = (getCapBase cap) in + (let top1 = (getCapTop cap) in + if ((((vAddr + size1)) > top1)) then + (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno :: ( 64 Word.word) M) + else return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)))))))))))" + + +(*val TranslatePC : mword ty64 -> M (mword ty64)*) + +definition TranslatePC :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " TranslatePC vAddr = ( + (incrementCP0Count () \<then> + (read_reg PCC_ref :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__0) in + (let base = (getCapBase pcc) in + (let top1 = (getCapTop pcc) in + (let absPC = (base + ((Word.uint vAddr))) in + if (((((absPC mod (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then + (SignalExceptionBadAddr AdEL + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + :: ( 64 Word.word) M) + else if ((\<not>(CapStruct_tag pcc))) then + (raise_c2_exception_noreg CapEx_TagViolation :: ( 64 Word.word) M) + else if ((((absPC + (( 4 :: int)::ii))) > top1)) then + (raise_c2_exception_noreg CapEx_LengthViolation :: ( 64 Word.word) M) + else + (TLBTranslate ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) absPC :: 64 Word.word)) + Instruction + :: ( 64 Word.word) M)))))))" + + +(* +All capability instrucitons must first check that the capability +co-processor is enabled using the following function that raises a +co-processor unusable exception if a CP0Status.CU2 is not set. This +allows the operating system to only save and restore the full +capability context for processes that use capabilities. +*) +(*val checkCP2usable : unit -> M unit*) + +definition checkCP2usable :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " checkCP2usable _ = ( + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + if ((\<not> ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 2 :: int)::ii))))))) then + set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1,B0] :: 2 Word.word) \<then> SignalException CpU + else return () ))" + + +definition init_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_cp2_state _ = ( + (let defaultBits = ((capStructToCapReg default_cap :: 257 Word.word)) in + ((write_reg PCC_ref defaultBits \<then> + write_reg nextPCC_ref defaultBits) \<then> + write_reg delayedPCC_ref defaultBits) \<then> + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + (let idx = ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) in + writeCapReg idx default_cap)))))" + + +definition cp2_next_pc :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " cp2_next_pc _ = ( + (read_reg nextPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: CapReg) . + (write_reg PCC_ref w__0 \<then> + (read_reg inBranchDelay_ref :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__1 :: 1 Word.word) . + if ((bits_to_bool w__1)) then + (read_reg delayedPCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__2 :: CapReg) . + write_reg nextPCC_ref w__2) + else write_reg inCCallDelay_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val capToString : CapStruct -> M string*) + +definition capToString :: " CapStruct \<Rightarrow>((register_value),(string),(exception))monad " where + " capToString cap = ( + skip () \<then> + return (((op@) ('' t:'') + (((op@) (if(CapStruct_tag cap) then (''1'') else (''0'')) + (((op@) ('' s:'') + (((op@) (if(CapStruct_sealed cap) then (''1'') else (''0'')) + (((op@) ('' perms:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((concat_vec (vec_of_bits [B0] :: 1 Word.word) + ((getCapPerms cap :: 31 Word.word)) + :: 32 Word.word)))) + (((op@) ('' type:'') + (((op@) ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict(CapStruct_otype cap))) + (((op@) ('' offset:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((getCapOffset cap)) + :: 64 Word.word)))) + (((op@) ('' base:'') + (((op@) + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((getCapBase cap)) + :: 64 Word.word)))) + (((op@) ('' length:'') + ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict + ((to_bits + ((make_the_value (( 64 :: int)::ii) + :: 64 itself)) + ((min ((getCapLength cap)) + ((MAX (( 64 :: int)::ii))))) + :: 64 Word.word)))))))))))))))))))))))))))))))" + + +definition dump_cp2_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " dump_cp2_state _ = ( + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__0 :: 257 Word.word) . + capToString ((capRegToCapStruct w__0)) \<bind> (\<lambda> (w__1 :: string) . + (let (_ :: unit) = (prerr_endline (((op@) (''DEBUG CAP PCC'') w__1))) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + readCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) \<bind> (\<lambda> (w__2 :: + CapStruct) . + capToString w__2 \<bind> (\<lambda> (w__3 :: string) . + return ((let _ = + (prerr_endline (((op@) (''DEBUG CAP REG '') (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict i)) w__3))))) in + () ))))))))))" + + +(*val extendLoad : forall 'sz . Size 'sz => mword 'sz -> bool -> mword ty64*) + +definition extendLoad :: "('sz::len)Word.word \<Rightarrow> bool \<Rightarrow>(64)Word.word " where + " extendLoad memResult sign = ( + if sign then (sign_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word) + else (zero_extend1 (( 64 :: int)::ii) memResult :: 64 Word.word))" + + +(*val TLBWriteEntry : mword ty6 -> M unit*) + +definition TLBWriteEntry :: "(6)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " TLBWriteEntry idx = ( + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> (\<lambda> pagemask . + (let b__0 = pagemask in + (if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) + then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word)))) then + return () + else SignalException MCheck) \<then> + ((let i = (Word.uint idx) in + (let entry = (access_list_dec TLBEntries i) in + (set_TLBEntry_pagemask entry pagemask \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0 :: 2 Word.word)) \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__1 :: TLBEntryHiReg) . + (set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1 :: 27 Word.word)) \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__2 :: TLBEntryHiReg) . + (set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2 :: 8 Word.word)) \<then> + and_boolM + (read_reg TLBEntryLo0_ref \<bind> (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__3 :: 1 Word.word)))))) + (read_reg TLBEntryLo1_ref \<bind> (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((bits_to_bool ((get_TLBEntryLoReg_G w__4 :: 1 Word.word))))))) \<bind> (\<lambda> (w__5 :: bool) . + ((set_TLBEntry_g entry ((bool_to_bits w__5 :: 1 Word.word)) \<then> + set_TLBEntry_valid entry ((cast_unit_vec0 B1 :: 1 Word.word))) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__6 :: TLBEntryLoReg) . + (set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__6 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__7 :: TLBEntryLoReg) . + (set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__7 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__8 :: TLBEntryLoReg) . + (set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__8 :: 24 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__9 :: TLBEntryLoReg) . + (set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__9 :: 3 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__10 :: TLBEntryLoReg) . + (set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__10 :: 1 Word.word)) \<then> + read_reg TLBEntryLo0_ref) \<bind> (\<lambda> (w__11 :: TLBEntryLoReg) . + (set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__11 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__12 :: TLBEntryLoReg) . + (set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__12 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__13 :: TLBEntryLoReg) . + (set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__13 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__14 :: TLBEntryLoReg) . + (set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__14 :: 24 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__15 :: TLBEntryLoReg) . + (set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__15 :: 3 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__16 :: TLBEntryLoReg) . + (set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__16 :: 1 Word.word)) \<then> + read_reg TLBEntryLo1_ref) \<bind> (\<lambda> (w__17 :: TLBEntryLoReg) . + set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__17 :: 1 Word.word))))))))))))))))))))))))" + + +definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where + " decode v__0 = ( + if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (DADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DADD (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADD (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (ADDU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ADDIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUB (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SUBU (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (AND0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ANDI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (OR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ORI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (NOR (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (XOR0 (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (XORI (rs,rt,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LUI (rt,imm)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSLL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRA32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: 5 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (DSRL32 (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (DSRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SLL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRA (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRAV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sa :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (SRL (rt,rd,sa))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SRLV (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLT (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTI (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (SLTU (rs,rt,rd))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SLTIU (rs,rt,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVN (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MOVZ (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFHI rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MFLO rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTHI rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 0 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1,B1] + :: 21 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (MTLO rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs,rt,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULT (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DMULTU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADD (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MADDU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUB (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (MSUBU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DIVU (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIV (rs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (DDIVU (rs,rt)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (J offset)) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (offset :: 26 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 0 :: int)::ii) :: 26 Word.word)) in + Some (JAL offset)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 11 :: int)::ii) :: 10 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 10 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + Some (JR rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word)))))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (JALR (rs,rd)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,False,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,False))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BEQ (rs,rt,imm,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LT',True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GE,True,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,GT',False,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (BCMPZ (rs,imm,LE,False,True)))) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1, + B1,B1,B0,B0,B1,B1,B0,B0] + :: 32 Word.word)))) then + Some (SYSCALL_THREAD_START () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + Some (SYSCALL () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + Some (BREAK () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (WAIT () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,LTU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (TRAPREG (rs,rt,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,EQ')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,NE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GE)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,GEU)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LT')))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (TRAPIMM (rs,imm,LTU)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (B,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (H,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (W,True,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Load (D,False,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (B,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (H,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,False,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (W,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (Store (D,True,base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SWR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (LDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B0] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDL (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B0,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (offset :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (SDR (base,rt,offset))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CACHE (base,op1,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1] :: 6 Word.word)))) then + (let (base :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (op1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: imm16) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (PREF (base,op1,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + Some (SYNC () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MFC0 (rt,rd,sel,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word))))))) + then + Some (HCF () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (sel :: 3 bits) = ((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + Some (MTC0 (rt,rd,sel,True))))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B1,B0] + :: 32 Word.word)))) then + Some (TLBWI () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B1,B1,B0] + :: 32 Word.word)))) then + Some (TLBWR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B1] + :: 32 Word.word)))) then + Some (TLBR () ) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (TLBP () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (RDHWR (rt,rd)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B1,B1,B0,B0,B0] + :: 32 Word.word)))) then + Some (ERET () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)))) then + Some (CReturn () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 11 :: int)::ii) :: 21 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 21 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rt)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,ct,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B1,B1] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetCause rd)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CSetCause rs)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCC cd1)) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 16 Word.word))))))) + then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (CJALR ((vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),cb,False))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckPerm (cs,rt)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CCheckType (cs,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CClearTag (cd1,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),False)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CJALR (cd1,cb,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPerm (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetType (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetBase (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetLen (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetTag (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetSealed (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetOffset (rd,cb)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetPCCSetOffset (cd1,rs)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CReadHwr (cd1,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CWriteHwr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (sel :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CGetAddr (cb,sel)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CUnseal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CAndPerm (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetOffset (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBounds (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSetBoundsExact (cd1,cs,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CIncOffset (cd1,cb,rt))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CBuildCap (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCopyType (cd1,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CCSeal (cd1,cs,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CToPtr (rd,cb,ct))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CFromPtr (cd1,cb,rs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSub (rt,cb,cs))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B0] :: 6 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CMOVX (cd1,cs,rs,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLE))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CLEU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CPtrCmp (rd,cb,cs,CNEXEQ))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (ct :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CTestSubset (rd,cb,ct))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,True)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBX (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,False)))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (CBZ (cd1,imm,True)))) + else if (((v__0 = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1, + B1,B1,B1,B1,B1,B1,B1,B1] + :: 32 Word.word)))) then + Some (CReturn () ) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B1] :: 11 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (selector :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CCall (cs,cb,selector))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (GPHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B0] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CLo,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B1,B1,B1,B1,B0,B0,B0,B1,B1] :: 16 Word.word)))) then + (let (imm :: 16 bits) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) in + Some (ClearRegs (CHi,imm))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B1,B1] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CIncOffsetImmediate (cd1,cb,imm))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B1,B0,B0] :: 11 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (imm :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSetBoundsImmediate (cd1,cb,imm))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,True,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CLoad (rd,cb,rt,offset,False,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,B,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B0,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,H,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),True,W,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B0,B1,B1] :: 11 Word.word))))))) then + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLoad (rd,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0] + :: 8 Word.word),False,D,True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,B,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,H,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,W,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B1,B0] :: 6 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 8 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 3 :: int)::ii) :: 8 Word.word)) in + Some (CStore (rs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,D,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),B,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),H,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B0] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),W,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B1,B1] :: 6 Word.word))))))) then + (let (rs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CStore (rs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0, + B0,B0,B0] + :: 8 Word.word),D,True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B1,B0] :: 6 Word.word)))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CSC (cs,cb,rt,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B1,B1] :: 6 Word.word))))))) then + (let (cs :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regno) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 6 :: int)::ii) :: 5 Word.word)) in + Some (CSC (cs,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),rd,(vec_of_bits [B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0] + :: 11 Word.word),True))))) + else if (((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B0] :: 6 Word.word)))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 21 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + (let (offset :: 11 bits) = ((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) in + Some (CLC (cd1,cb,rt,offset,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B1,B0,B0,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 10 :: int)::ii) (( 0 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] :: 11 Word.word))))))) then + (let (cd1 :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + (let (cb :: regno) = ((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 11 :: int)::ii) :: 5 Word.word)) in + Some (CLC (cd1,cb,(vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word),(vec_of_bits [B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 11 Word.word),True)))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 21 :: int)::ii) :: 11 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B1,B0,B0,B0,B1,B0,B0] :: 11 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B0] :: 16 Word.word))))))) + then + (let (rt :: regno) = ((subrange_vec_dec v__0 (( 20 :: int)::ii) (( 16 :: int)::ii) :: 5 Word.word)) in + Some (C2Dump rt)) + else Some (RI () ))" + + +(*val execute_XORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_XORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_XORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_XOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_XOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_XOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((xor_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_WAIT : unit -> M unit*) + +definition execute_WAIT :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_WAIT g__121 = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg nextPC_ref w__0))" + + +(*val execute_TRAPREG : mword ty5 -> mword ty5 -> Comparison -> M unit*) + +definition execute_TRAPREG :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TRAPREG rs rt cmp = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + (let condition = (compare cmp rs_val rt_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TRAPIMM : mword ty5 -> mword ty16 -> Comparison -> M unit*) + +definition execute_TRAPIMM :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TRAPIMM rs imm cmp = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (imm_val :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let condition = (compare cmp rs_val imm_val) in + if condition then SignalException Tr + else return () ))))" + + +(*val execute_TLBWR : unit -> M unit*) + +definition execute_TLBWR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBWR g__125 = ( + (checkCP0Access () \<then> + (read_reg TLBRandom_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBWI : unit -> M unit*) + +definition execute_TLBWI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBWI g__124 = ( + (checkCP0Access () \<then> + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: 6 Word.word) . TLBWriteEntry w__0))" + + +(*val execute_TLBR : unit -> M unit*) + +definition execute_TLBR :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBR g__126 = ( + (checkCP0Access () \<then> + (read_reg TLBIndex_ref :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__0 :: TLBIndexT) . + (let i = (Word.uint w__0) in + reg_deref ((access_list_dec TLBEntries i)) \<bind> (\<lambda> entry . + ((((((((((((((((write_reg TLBPageMask_ref ((get_TLBEntry_pagemask entry :: 16 Word.word)) \<then> + set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry :: 2 Word.word))) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry :: 27 Word.word))) \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry :: 8 Word.word))) \<then> + set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry :: 24 Word.word))) \<then> + set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry :: 3 Word.word))) \<then> + set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry :: 24 Word.word))) \<then> + set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry :: 3 Word.word))) \<then> + set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry :: 1 Word.word))) \<then> + set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry :: 1 Word.word))))))" + + +(*val execute_TLBP : unit -> M unit*) + +definition execute_TLBP :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_TLBP g__127 = ( + (checkCP0Access () \<then> + read_reg TLBEntryHi_ref) \<bind> (\<lambda> (w__0 :: TLBEntryHiReg) . + (tlbSearch ((get_TLBEntryHiReg w__0 :: 64 Word.word)) :: ( ( 6 Word.word)option) M) \<bind> (\<lambda> result . + (case result of + Some (idx) => + write_reg TLBProbe_ref (vec_of_bits [B0] :: 1 Word.word) \<then> write_reg TLBIndex_ref idx + | None => + write_reg TLBProbe_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg TLBIndex_ref (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word) + ))))" + + +(*val execute_Store : WordType -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Store :: " WordType \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_Store width conditional base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData width + :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr + else + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__1 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rt_val + ) + else return False) \<bind> (\<lambda> (success :: bool) . + wGPR rt ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rt_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rt_val + ))))))" + + +(*val execute_SYSCALL_THREAD_START : unit -> unit*) + +definition execute_SYSCALL_THREAD_START :: " unit \<Rightarrow> unit " where + " execute_SYSCALL_THREAD_START g__117 = ( () )" + + +(*val execute_SYSCALL : unit -> M unit*) + +definition execute_SYSCALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SYSCALL g__119 = ( SignalException Sys )" + + +(*val execute_SYNC : unit -> M unit*) + +definition execute_SYNC :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SYNC g__122 = ( MEM_sync () )" + + +(*val execute_SWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__12 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__12 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__12 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__12 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))))))))" + + +(*val execute_SWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__8 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + if (((b__8 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__8 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + else if (((b__8 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_SUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((sub_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (temp33 :: 33 bits) = + ((sub_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec temp33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + if ((NotWordVal temp)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let rt32 = ((subrange_vec_dec temp (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SLTU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val rt_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (immext :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_u rs_val immext)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLTI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SLTI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLTI rs rt imm = ( + (let imm_val = (Word.sint imm) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs_val = (Word.sint w__0) in + wGPR rt + ((zero_extend1 (( 64 :: int)::ii) + (if ((rs_val < imm_val)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word))))))" + + +(*val execute_SLT : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLT rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) + (if ((zopz0zI_s w__0 w__1)) then (vec_of_bits [B1] :: 1 Word.word) + else (vec_of_bits [B0] :: 1 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_SLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLLV rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))))))))" + + +(*val execute_SLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_SLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt32 = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + wGPR rd ((sign_extend1 (( 64 :: int)::ii) w__1 :: 64 Word.word))))))" + + +(*val execute_SDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let wordAddr = + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) in + (let b__40 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__40 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + else if (((b__40 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + else if (((b__40 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper wordAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + else MEMw_wrapper wordAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))))))" + + +(*val execute_SDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_SDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) + StoreData D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__32 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + if (((b__32 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 8 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 7 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 6 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + else if (((b__32 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 5 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 3 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + else if (((b__32 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + else MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word))))))))" + + +(*val execute_RI : unit -> M unit*) + +definition execute_RI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RI g__130 = ( SignalException ResI )" + + +(*val execute_RDHWR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_RDHWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RDHWR rt rd = ( + getAccessLevel () \<bind> (\<lambda> accessLevel . + (let (haveAccessLevel :: bool) = (accessLevel = Kernel) in + read_reg CP0Status_ref \<bind> (\<lambda> (w__0 :: StatusReg) . + (let (haveCU0 :: bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0 :: 4 Word.word)) (( 0 :: int)::ii)))) in + (let rdi = (Word.uint rd) in + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (let (haveHWREna :: bool) = (B1 = ((access_vec_dec w__1 rdi))) in + (if ((\<not> (((haveAccessLevel \<or> (((haveCU0 \<or> haveHWREna)))))))) then SignalException ResI + else return () ) \<then> + ((let b__146 = rd in + (if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . + return ((zero_extend1 (( 64 :: int)::ii) w__2 :: 64 Word.word))) + else if (((b__146 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) then + return ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 64 Word.word)) + else if (((b__146 = (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) + else (SignalException ResI :: ( 64 Word.word) M)) \<bind> (\<lambda> (temp :: 64 bits) . + wGPR rt temp)))))))))))" + + +(*val execute_PREF : mword ty5 -> mword ty5 -> mword ty16 -> unit*) + +definition execute_PREF :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> unit " where + " execute_PREF base op1 imm = ( () )" + + +(*val execute_ORI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ORI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ORI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_OR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_OR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_OR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((or_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_NOR : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_NOR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_NOR rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((not_vec ((or_vec w__0 w__1 :: 64 Word.word)) :: 64 Word.word)))))" + + +(*val execute_MULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (result :: 64 bits) . + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MUL rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (let (result :: 64 bits) = + ((sign_extend1 (( 64 :: int)::ii) + ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd w__1)))))" + + +(*val execute_MTLO : mword ty5 -> M unit*) + +definition execute_MTLO :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTLO rs = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg LO_ref w__0))" + + +(*val execute_MTHI : mword ty5 -> M unit*) + +definition execute_MTHI :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTHI rs = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . write_reg HI_ref w__0))" + + +(*val execute_MTC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MTC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MTC0 rt rd sel double = ( + (checkCP0Access () \<then> + (rGPR rt :: ( 64 Word.word) M)) \<bind> (\<lambda> reg_val . + (case (rd, sel) of + (b__108, b__109) => + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBIndex_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo0_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_TLBEntryLoReg TLBEntryLo1_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_ContextReg_PTEBase TLBContext_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 23 :: int):: ii) :: 41 Word.word)) else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + write_reg CP0UserLocal_ref reg_val else + if ((((((b__108 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBPageMask_ref + ((subrange_vec_dec reg_val (( 28 :: int):: ii) + (( 13 :: int):: ii) :: 16 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg TLBWired_ref + ((mask0 (( 6 :: int):: ii) reg_val :: 6 Word.word)) + \<then> write_reg TLBRandom_ref TLBIndexMax else + if ((((((b__108 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__109 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0HWREna_ref + ((concat_vec + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 29 :: int):: ii) :: 3 Word.word)) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0] :: 25 Word.word) + ((subrange_vec_dec reg_val (( 3 :: int):: ii) + (( 0 :: int):: ii) :: 4 Word.word)) + :: 29 Word.word)) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0Count_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_TLBEntryHiReg_R TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 63 :: int):: ii) + (( 62 :: int):: ii) :: 2 Word.word)) \<then> + set_TLBEntryHiReg_VPN2 TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 39 :: int):: ii) + (( 13 :: int):: ii) :: 27 Word.word))) + \<then> + set_TLBEntryHiReg_ASID TLBEntryHi_ref + ((subrange_vec_dec reg_val (( 7 :: int):: ii) + (( 0 :: int):: ii) :: 8 Word.word)) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (write_reg CP0Compare_ref + ((subrange_vec_dec reg_val (( 31 :: int):: ii) + (( 0 :: int):: ii) :: 32 Word.word)) + \<then> read_reg CP0Cause_ref) \<bind> + (\<lambda> (w__0 :: CauseReg) . + set_CauseReg_IP CP0Cause_ref + ((and_vec + ((get_CauseReg_IP w__0 :: 8 Word.word)) + (vec_of_bits [B0,B1,B1,B1,B1,B1,B1,B1] :: 8 Word.word) + :: 8 Word.word))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + ((((((((set_StatusReg_CU CP0Status_ref + ((subrange_vec_dec reg_val + (( 31 :: int):: ii) + (( 28 :: int):: ii) :: 4 Word.word)) + \<then> + set_StatusReg_BEV CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 22 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_IM CP0Status_ref + ((subrange_vec_dec reg_val + (( 15 :: int):: ii) + (( 8 :: int):: ii) :: 8 Word.word))) + \<then> + set_StatusReg_KX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 7 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_SX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 6 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_UX CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 5 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_KSU CP0Status_ref + ((subrange_vec_dec reg_val + (( 4 :: int):: ii) + (( 3 :: int):: ii) :: 2 Word.word))) + \<then> + set_StatusReg_ERL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 2 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_EXL CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 1 :: int):: ii))) :: 1 Word.word))) + \<then> + set_StatusReg_IE CP0Status_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 0 :: int):: ii))) :: 1 Word.word)) + else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (set_CauseReg_IV CP0Cause_ref + ((cast_unit_vec0 + ((access_vec_dec reg_val + (( 23 :: int):: ii))) :: 1 Word.word)) + \<then> read_reg CP0Cause_ref) \<bind> + (\<lambda> (w__1 :: CauseReg) . + (let ip = ((get_CauseReg_IP w__1 :: 8 Word.word)) in + set_CauseReg_IP CP0Cause_ref + ((concat_vec + ((subrange_vec_dec ip + (( 7 :: int):: ii) + (( 2 :: int):: ii) :: 6 Word.word)) + ((subrange_vec_dec reg_val + (( 9 :: int):: ii) + (( 8 :: int):: ii) :: 2 Word.word)) + :: 8 Word.word)))) else + if ((((((b__108 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + write_reg CP0EPC_ref reg_val else + if ((((((b__108 = + (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return () else + if ((((((b__108 = + (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__109 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + set_XContextReg_XPTEBase + TLBXContext_ref + ((subrange_vec_dec reg_val + (( 63 :: int):: ii) + (( 33 :: int):: ii) :: 31 Word.word)) + else write_reg CP0ErrorEPC_ref reg_val + )))" + + +(*val execute_MSUBU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MSUBU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MSUB : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MSUB rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((sub_vec + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) mul_result + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MOVZ : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVZ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MOVZ rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + if (((w__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MOVN : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_MOVN :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MOVN rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + if (((w__0 \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))) then + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1) + else return () ))" + + +(*val execute_MFLO : mword ty5 -> M unit*) + +definition execute_MFLO :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFLO rd = ( + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFHI : mword ty5 -> M unit*) + +definition execute_MFHI :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFHI rd = ( + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))" + + +(*val execute_MFC0 : mword ty5 -> mword ty5 -> mword ty3 -> bool -> M unit*) + +definition execute_MFC0 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(3)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MFC0 rt rd sel double = ( + (checkCP0Access () \<then> + (case (rd, sel) of + (b__48, b__49) => + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBIndex_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__0 :: TLBIndexT) . + (let (idx :: 31 bits) = ((zero_extend1 (( 31 :: int):: ii) w__0 :: 31 Word.word)) in + (read_reg TLBProbe_ref :: ( 1 Word.word) M) \<bind> + (\<lambda> (w__1 :: 1 bits) . + return + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 32 Word.word) + ((concat_vec w__1 idx :: 32 Word.word)) :: 64 Word.word))))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))) \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBRandom_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__2 :: TLBIndexT) . + return ((zero_extend1 (( 64 :: int):: ii) w__2 :: 64 Word.word))) + else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo0_ref \<bind> + (\<lambda> (w__3 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__3 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryLo1_ref \<bind> + (\<lambda> (w__4 :: TLBEntryLoReg) . + return ((get_TLBEntryLoReg w__4 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBContext_ref \<bind> + (\<lambda> (w__5 :: ContextReg) . + return ((get_ContextReg w__5 :: 64 Word.word))) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B1,B0] :: 3 Word.word))))))) then + (read_reg CP0UserLocal_ref :: ( 64 Word.word) M) else + if ((((((b__48 = (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBPageMask_ref :: ( 16 Word.word) M) \<bind> + (\<lambda> (w__7 :: 16 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((concat_vec w__7 + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 28 Word.word)) :: 64 Word.word))) else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg TLBWired_ref :: ( 6 Word.word) M) \<bind> + (\<lambda> (w__8 :: TLBIndexT) . + return + ((zero_extend1 (( 64 :: int):: ii) w__8 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0HWREna_ref :: ( 32 Word.word) M) \<bind> + (\<lambda> (w__9 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__9 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0BadVAddr_ref :: ( 64 Word.word) M) else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Count_ref :: ( 32 Word.word) M) + \<bind> + (\<lambda> (w__11 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__11 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg TLBEntryHi_ref \<bind> + (\<lambda> (w__12 :: TLBEntryHiReg) . + return + ((get_TLBEntryHiReg w__12 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0Compare_ref :: ( 32 Word.word) M) + \<bind> + (\<lambda> (w__13 :: 32 bits) . + return + ((zero_extend1 (( 64 :: int):: ii) w__13 :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Status_ref \<bind> + (\<lambda> (w__14 :: StatusReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_StatusReg w__14 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + read_reg CP0Cause_ref \<bind> + (\<lambda> (w__15 :: CauseReg) . + return + ((zero_extend1 (( 64 :: int):: ii) + ((get_CauseReg w__15 :: 32 Word.word)) :: 64 Word.word))) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0EPC_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B1,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B0,B1,B1,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 15 Word.word) + ((concat_vec + (vec_of_bits + [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B1,B0] :: 2 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B1] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 15 Word.word)) + :: 16 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B1] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + TLBIndexMax + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ( + ( + concat_vec + ( + ( + bool_to_bits + have_cp2 :: 1 Word.word)) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0] + :: 1 Word.word) + ( + vec_of_bits + [B0] + :: 1 Word.word) + :: 2 Word.word)) + :: 3 Word.word)) + :: 4 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 10 Word.word)) + :: 13 Word.word)) + :: 16 Word.word)) + :: 19 Word.word)) + :: 22 Word.word)) + :: 25 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B1,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + ((concat_vec + (vec_of_bits [B1] :: 1 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0] :: 3 Word.word) + ((concat_vec + (vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ((concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + ( + concat_vec + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + ( + vec_of_bits + [B0,B0,B0,B0] :: 4 Word.word) + :: 8 Word.word)) + :: 12 Word.word)) + :: 16 Word.word)) + :: 20 Word.word)) + :: 24 Word.word)) + :: 28 Word.word)) + :: 31 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B1,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B1,B0,B1] :: 3 Word.word))))))) then + return + (vec_of_bits + [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B0,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + (read_reg CP0LLAddr_ref :: ( 64 Word.word) M) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B0] :: 5 Word.word)))) + \<and> + (((b__49 = + (vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + (vec_of_bits + [B1,B0,B0,B1,B1] :: 5 Word.word)))) + \<and> + (((b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + return + ((zero_extend1 + (( 64 :: int):: ii) + (vec_of_bits + [B0] :: 1 Word.word) :: 64 Word.word)) + else + if ((((((b__48 = + ( + vec_of_bits + [B1,B0,B1,B0,B0] :: 5 Word.word)))) + \<and> + ((( + b__49 = + ( + vec_of_bits + [B0,B0,B0] :: 3 Word.word))))))) then + read_reg + TLBXContext_ref + \<bind> + (\<lambda> (w__18 :: XContextReg) . + return + ((get_XContextReg + w__18 :: 64 Word.word))) + else + (read_reg + CP0ErrorEPC_ref :: ( 64 Word.word) M) + )) \<bind> (\<lambda> (result :: 64 bits) . + wGPR rt + (if double then result + else + (sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))" + + +(*val execute_MADDU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MADDU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mult_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_MADD : mword ty5 -> mword ty5 -> M unit*) + +definition execute_MADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MADD rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> ((NotWordVal rtVal))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) + else + return ((mults_vec ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word))) \<bind> (\<lambda> (mul_result :: 64 bits) . + (read_reg HI_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (read_reg LO_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (let result = + ((add_vec mul_result + ((concat_vec ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec w__2 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word)) + :: 64 Word.word)) in + write_reg + HI_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)) \<then> + write_reg + LO_ref + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))))))" + + +(*val execute_Load : WordType -> bool -> bool -> mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_Load :: " WordType \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_Load width sign linked base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + width + :: ( 64 Word.word) M) \<bind> (\<lambda> (vAddr :: 64 bits) . + if ((\<not> ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr + else + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + (write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (case width of + B => + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . + return ((extendLoad w__1 sign :: 64 Word.word))) + | H => + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + return ((extendLoad w__2 sign :: 64 Word.word))) + | W => + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + return ((extendLoad w__3 sign :: 64 Word.word))) + | D => + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((extendLoad w__4 sign :: 64 Word.word))) + ) + else + (case width of + B => + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__6 :: 8 Word.word) . + return ((extendLoad w__6 sign :: 64 Word.word))) + | H => + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . + return ((extendLoad w__7 sign :: 64 Word.word))) + | W => + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . + return ((extendLoad w__8 sign :: 64 Word.word))) + | D => + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . + return ((extendLoad w__9 sign :: 64 Word.word))) + )) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rt memResult)))))" + + +(*val execute_LWR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LWR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__4 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__4 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else if (((b__4 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 24 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 8 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word) + else mem_val) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LWL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LWL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LWL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + W + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word)) + (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) (( 4 :: int)::ii) + :: ( 32 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__0 = ((subrange_vec_dec vAddr (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) in + (let (result :: 32 bits) = + (if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then mem_val + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 32 Word.word) + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 32 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 32 Word.word)) in + wGPR rt ((sign_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))" + + +(*val execute_LUI : mword ty5 -> mword ty16 -> M unit*) + +definition execute_LUI :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LUI rt imm = ( + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) + :: 32 Word.word)) + :: 64 Word.word)))" + + +(*val execute_LDR : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LDR base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__24 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__24 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 40 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 24 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 48 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 16 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else if (((b__24 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec reg_val (( 63 :: int)::ii) (( 56 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec mem_val (( 63 :: int)::ii) (( 8 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word) + else mem_val))))))))" + + +(*val execute_LDL : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_LDL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LDL base rt offset = ( + (rGPR base :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (addrWrapper ((add_vec ((sign_extend1 (( 64 :: int)::ii) offset :: 64 Word.word)) w__0 :: 64 Word.word)) LoadData + D + :: ( 64 Word.word) M) \<bind> (\<lambda> vAddr . + (TLBTranslate vAddr StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (MEMr_wrapper + ((concat_vec ((subrange_vec_dec pAddr (( 63 :: int)::ii) (( 3 :: int)::ii) :: 61 Word.word)) + (vec_of_bits [B0,B0,B0] :: 3 Word.word) + :: 64 Word.word)) (( 8 :: int)::ii) + :: ( 64 Word.word) M) \<bind> (\<lambda> mem_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> reg_val . + (let b__16 = ((subrange_vec_dec vAddr (( 2 :: int)::ii) (( 0 :: int)::ii) :: 3 Word.word)) in + wGPR rt + (if (((b__16 = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) then mem_val + else if (((b__16 = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + ((subrange_vec_dec reg_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + ((subrange_vec_dec reg_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + ((subrange_vec_dec reg_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec reg_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 23 :: int)::ii) (( 0 :: int)::ii) :: 24 Word.word)) + ((subrange_vec_dec reg_val (( 39 :: int)::ii) (( 0 :: int)::ii) :: 40 Word.word)) + :: 64 Word.word) + else if (((b__16 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then + (concat_vec ((subrange_vec_dec mem_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + ((subrange_vec_dec reg_val (( 47 :: int)::ii) (( 0 :: int)::ii) :: 48 Word.word)) + :: 64 Word.word) + else + (concat_vec ((subrange_vec_dec mem_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((subrange_vec_dec reg_val (( 55 :: int)::ii) (( 0 :: int)::ii) :: 56 Word.word)) + :: 64 Word.word)))))))))" + + +(*val execute_JR : mword ty5 -> M unit*) + +definition execute_JR :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JR rs = ( (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . execute_branch w__0))" + + +(*val execute_JALR : mword ty5 -> mword ty5 -> M unit*) + +definition execute_JALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JALR rs rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (execute_branch w__0 \<then> + (read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_JAL : mword ty26 -> M unit*) + +definition execute_JAL :: "(26)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_JAL offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word)) \<then> + (read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) ((add_vec_int w__1 (( 8 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_J : mword ty26 -> M unit*) + +definition execute_J :: "(26)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_J offset = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + execute_branch + ((concat_vec + ((subrange_vec_dec ((add_vec_int w__0 (( 4 :: int)::ii) :: 64 Word.word)) (( 63 :: int)::ii) (( 28 :: int)::ii) :: 36 Word.word)) + ((concat_vec offset (vec_of_bits [B0,B0] :: 2 Word.word) :: 28 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ImplementationDefinedStopFetching : unit -> unit*) + +definition execute_ImplementationDefinedStopFetching :: " unit \<Rightarrow> unit " where + " execute_ImplementationDefinedStopFetching g__118 = ( () )" + + +(*val execute_HCF : unit -> unit*) + +definition execute_HCF :: " unit \<Rightarrow> unit " where + " execute_HCF g__123 = ( () )" + + +(*val execute_ERET : unit -> M unit*) + +definition execute_ERET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ERET g__128 = ( + (((checkCP0Access () \<then> + ERETHook () ) \<then> + write_reg CP0LLBit_ref (vec_of_bits [B0] :: 1 Word.word)) \<then> + read_reg CP0Status_ref) \<bind> (\<lambda> (w__0 :: StatusReg) . + if (((((bits_to_bool ((get_StatusReg_ERL w__0 :: 1 Word.word)))) = ((bit_to_bool B1))))) then + (read_reg CP0ErrorEPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + write_reg nextPC_ref w__1 \<then> set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word)) + else + (read_reg CP0EPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + write_reg nextPC_ref w__2 \<then> set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0] :: 1 Word.word))))" + + +(*val execute_DSUBU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUBU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSUBU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((sub_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DSUB : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSUB :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSUB rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (temp65 :: 65 bits) = + ((sub_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec temp65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec temp65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DSRLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSRAV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRAV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRAV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let sa = ((subrange_vec_dec w__0 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))))" + + +(*val execute_DSRA32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRA32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (let sa32 = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) in + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0))))" + + +(*val execute_DSRA : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSRA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSRA rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> temp . + (shift_bits_right_arith + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0)))" + + +(*val execute_DSLLV : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLLV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLLV rs rt rd = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: + 64 Word.word) . + wGPR rd w__2))))" + + +(*val execute_DSLL32 : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL32 :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLL32 rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1] :: 1 Word.word) sa :: 6 Word.word)) + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd w__1)))" + + +(*val execute_DSLL : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DSLL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DSLL rt rd sa = ( + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . wGPR rd w__1)))" + + +(*val execute_DMULTU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULTU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DMULTU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let result = ((mult_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DMULT : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DMULT :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DMULT rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let result = ((mults_vec w__0 w__1 :: 128 Word.word)) in + write_reg HI_ref ((subrange_vec_dec result (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + write_reg LO_ref ((subrange_vec_dec result (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_DIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> (((((NotWordVal rtVal)) \<or> (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.uint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.uint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (hardware_mod si ti) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rsVal . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rtVal . + (if (((((NotWordVal rsVal)) \<or> (((((NotWordVal rtVal)) \<or> (((rtVal = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + return (w__0, w__1))) + else + (let si = (Word.sint ((subrange_vec_dec rsVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let ti = (Word.sint ((subrange_vec_dec rtVal (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word))) in + (let qi = (hardware_quot si ti) in + (let ri = (si - ((ti * qi))) in + return ((to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) qi :: 32 Word.word), + (to_bits ((make_the_value (( 32 :: int)::ii) :: 32 itself)) ri :: 32 Word.word))))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg HI_ref ((sign_extend1 (( 64 :: int)::ii) r :: 64 Word.word)) \<then> + write_reg LO_ref ((sign_extend1 (( 64 :: int)::ii) q :: 64 Word.word)))))))" + + +(*val execute_DDIVU : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIVU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DDIVU rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rsVal = (Word.uint w__0) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rtVal = (Word.uint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (hardware_mod rsVal rtVal) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg LO_ref q \<then> write_reg HI_ref r)))))))" + + +(*val execute_DDIV : mword ty5 -> mword ty5 -> M unit*) + +definition execute_DDIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DDIV rs rt = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rsVal = (Word.sint w__0) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rtVal = (Word.sint w__1) in + (if (((rtVal = (( 0 :: int)::ii)))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + return (w__2, w__3))) + else + (let qi = (hardware_quot rsVal rtVal) in + (let ri = (rsVal - ((qi * rtVal))) in + return ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) qi :: 64 Word.word), + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ri :: 64 Word.word))))) \<bind> (\<lambda> varstup . (let (q, r) = varstup in + write_reg LO_ref q \<then> write_reg HI_ref r)))))))" + + +(*val execute_DADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((add_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_DADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_DADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_DADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) imm :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rt ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_DADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_DADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (sum65 :: 65 bits) = + ((add_vec ((sign_extend1 (( 65 :: int)::ii) w__0 :: 65 Word.word)) ((sign_extend1 (( 65 :: int)::ii) w__1 :: 65 Word.word)) + :: 65 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum65 (( 63 :: int)::ii))))))) then + SignalException Ov + else wGPR rd ((subrange_vec_dec sum65 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word))))))" + + +(*val execute_ClearRegs : ClearRegSet -> mword ty16 -> M unit*) + +definition execute_ClearRegs :: " ClearRegSet \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ClearRegs regset m = ( + ((if ((((((regset = CLo))) \<or> (((regset = CHi)))))) then checkCP2usable () + else return () ) \<then> + (if (((regset = CHi))) then + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + (let r = + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) :: 5 Word.word)) in + and_boolM (return ((bit_to_bool ((access_vec_dec m i))))) ((register_inaccessible r)) \<bind> (\<lambda> (w__1 :: + bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation r + else return () )))) + else return () )) \<then> + (foreachM (index_list (( 0 :: int)::ii) (( 15 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> i unit_var . + if ((bit_to_bool ((access_vec_dec m i)))) then + (case regset of + GPLo => + wGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) + ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | GPHi => + wGPR + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word)) + | CLo => + writeCapReg ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) i :: 5 Word.word)) null_cap + | CHi => + writeCapReg + ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) ((i + (( 16 :: int)::ii))) + :: 5 Word.word)) null_cap + ) + else return () )))" + + +(*val execute_CWriteHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CWriteHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CWriteHwr cb sel = ( + checkCP2usable () \<then> + ((let l__24 = (Word.uint sel) in + (if (((l__24 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__24 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__24 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__24 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__24 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cb \<bind> (\<lambda> (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9)))) \<bind> (\<lambda> (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \<bind> (\<lambda> (w__11 :: AccessLevel) . + return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + readCapReg cb \<bind> (\<lambda> capVal . + (let l__16 = (Word.uint sel) in + if (((l__16 = (( 0 :: int)::ii)))) then writeCapReg DDC capVal + else if (((l__16 = (( 1 :: int)::ii)))) then + write_reg CTLSU_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 8 :: int)::ii)))) then + write_reg CTLSP_ref ((capStructToCapReg capVal :: 257 Word.word)) + else if (((l__16 = (( 22 :: int)::ii)))) then writeCapReg KR1C capVal + else if (((l__16 = (( 23 :: int)::ii)))) then writeCapReg KR2C capVal + else if (((l__16 = (( 29 :: int)::ii)))) then writeCapReg KCC capVal + else if (((l__16 = (( 30 :: int)::ii)))) then writeCapReg KDC capVal + else if (((l__16 = (( 31 :: int)::ii)))) then writeCapReg EPCC capVal + else assert_exp False (''should be unreachable code'')))))))))))" + + +(*val execute_CUnseal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CUnseal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CUnseal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if (((ct_cursor \<noteq> ((Word.uint(CapStruct_otype cs_val)))))) then + raise_c2_exception CapEx_TypeViolation ct + else if ((\<not>(CapStruct_permit_unseal ct_val))) then + raise_c2_exception CapEx_PermitUnsealViolation ct + else if ((ct_cursor < ((getCapBase ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ((getCapTop ct_val)))) then + raise_c2_exception CapEx_LengthViolation ct + else + writeCapReg cd1 + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word)), CapStruct_global := + ((((CapStruct_global cs_val) \<and>(CapStruct_global ct_val))))|)))))))))" + + +(*val execute_CToPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CToPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CToPtr rd cb ct = ( + (checkCP2usable () \<then> + readCapReg ct) \<bind> (\<lambda> ct_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let cbBase = (getCapBase cb_val) in + (let cbTop = (getCapTop cb_val) in + (let ctBase = (getCapBase ct_val) in + (let ctTop = (getCapTop ct_val) in + wGPR rd + (if (((((\<not>(CapStruct_tag cb_val))) \<or> (((((cbBase < ctBase)) \<or> ((cbTop > ctTop)))))))) then + (zeros0 (( 64 :: int)::ii) () :: 64 Word.word) + else + (to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ctBase)) + :: 64 Word.word)))))))))))" + + +(*val execute_CTestSubset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CTestSubset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CTestSubset rd cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + (let (result :: 1 bits) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_base < cb_base)) then (vec_of_bits [B0] :: 1 Word.word) + else if ((ct_top > cb_top)) then (vec_of_bits [B0] :: 1 Word.word) + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then + (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) result :: 64 Word.word))))))))))))))" + + +(*val execute_CSub : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSub :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSub rd cb ct = ( + (checkCP2usable () \<then> + readCapReg ct) \<bind> (\<lambda> ct_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + ((((getCapCursor cb_val)) - ((getCapCursor ct_val)))) + :: 64 Word.word)))))))" + + +(*val execute_CStore : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> WordType -> bool -> M unit*) + +definition execute_CStore :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CStore rs cb rt rd offset width conditional = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else + (let size1 = (wordWidthBytes width) in + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + ((size1 * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + size1)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslate vAddr64 StoreData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__2 (( 0 :: int)::ii))))) then + (case width of + B => + MEMw_conditional_wrapper pAddr (( 1 :: int)::ii) + ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => + MEMw_conditional_wrapper pAddr (( 2 :: int)::ii) + ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => + MEMw_conditional_wrapper pAddr (( 4 :: int)::ii) + ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_conditional_wrapper pAddr (( 8 :: int)::ii) rs_val + ) + else return False) \<bind> (\<lambda> (success :: bool) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else + (case width of + B => MEMw_wrapper pAddr (( 1 :: int)::ii) ((subrange_vec_dec rs_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + | H => MEMw_wrapper pAddr (( 2 :: int)::ii) ((subrange_vec_dec rs_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) + | W => MEMw_wrapper pAddr (( 4 :: int)::ii) ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + | D => MEMw_wrapper pAddr (( 8 :: int)::ii) rs_val + )))))))))))" + + +(*val execute_CSetOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetOffset cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CSetCause : mword ty5 -> M unit*) + +definition execute_CSetCause :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetCause rt = ( + (checkCP2usable () \<then> + pcc_access_system_regs () ) \<bind> (\<lambda> (w__0 :: bool) . + if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) \<then> + set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)))))" + + +(*val execute_CSetBoundsImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CSetBoundsImmediate :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBoundsImmediate cd1 cb imm = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let immU = (Word.uint imm) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + immU) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSetBoundsExact : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBoundsExact :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBoundsExact cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (exact, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + if ((\<not> exact)) then raise_c2_exception CapEx_InexactBounds cb + else writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSetBounds : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSetBounds :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSetBounds cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rt_val = (Word.uint w__0) in + (let cursor = (getCapCursor cb_val) in + (let base = (getCapBase cb_val) in + (let top1 = (getCapTop cb_val) in + (let newTop = (cursor + rt_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((newTop > top1)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (_, newCap) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) newTop :: 65 Word.word))) in + writeCapReg cd1 newCap)))))))))))" + + +(*val execute_CSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSeal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag ct_val))) then raise_c2_exception CapEx_TagViolation ct + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\<not>(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\<not> success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CSC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CSC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSC cs cb rt rd offset conditional = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_store cb_val))) then + raise_c2_exception CapEx_PermitStoreViolation cb + else if ((\<not>(CapStruct_permit_store_cap cb_val))) then + raise_c2_exception CapEx_PermitStoreCapViolation cb + else if (((((\<not>(CapStruct_permit_store_local_cap cb_val))) \<and> ((((CapStruct_tag cs_val) \<and> ((\<not>(CapStruct_global cs_val))))))))) then + raise_c2_exception CapEx_PermitStoreLocalCapViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdES vAddr64 + else + (TLBTranslateC vAddr64 StoreData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, noStoreCap) = varstup in + if ((((CapStruct_tag cs_val) \<and> noStoreCap))) then + raise_c2_exception CapEx_TLBNoStoreCap cs + else if conditional then + (read_reg CP0LLBit_ref :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 bits) . + (if ((bit_to_bool ((access_vec_dec w__3 (( 0 :: int)::ii))))) then + MEMw_tagged_conditional pAddr(CapStruct_tag cs_val) + ((capStructToMemBits cs_val :: 256 Word.word)) + else return False) \<bind> (\<lambda> success . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits success :: 1 Word.word)) :: 64 Word.word)))) + else MEMw_tagged pAddr(CapStruct_tag cs_val) ((capStructToMemBits cs_val :: 256 Word.word)))))))))))))" + + +(*val execute_CReturn : unit -> M unit*) + +definition execute_CReturn :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CReturn g__129 = ( checkCP2usable () \<then> raise_c2_exception_noreg CapEx_ReturnTrap )" + + +(*val execute_CReadHwr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CReadHwr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CReadHwr cd1 sel = ( + checkCP2usable () \<then> + ((let l__8 = (Word.uint sel) in + (if (((l__8 = (( 0 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 1 :: int)::ii)))) then return (False, False) + else if (((l__8 = (( 8 :: int)::ii)))) then return (False, True) + else if (((l__8 = (( 22 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 23 :: int)::ii)))) then return (True, False) + else if (((l__8 = (( 29 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 30 :: int)::ii)))) then return (True, True) + else if (((l__8 = (( 31 :: int)::ii)))) then return (True, True) + else SignalException ResI) \<bind> (\<lambda> varstup . (let ((needSup :: bool), (needAccessSys :: bool)) = varstup in + register_inaccessible cd1 \<bind> (\<lambda> (w__8 :: bool) . + if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + and_boolM (return needAccessSys) + (pcc_access_system_regs () \<bind> (\<lambda> (w__9 :: bool) . return ((\<not> w__9)))) \<bind> (\<lambda> (w__10 :: + bool) . + if w__10 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + and_boolM (return needSup) + (getAccessLevel () \<bind> (\<lambda> (w__11 :: AccessLevel) . + return ((\<not> ((grantsAccess w__11 Supervisor)))))) \<bind> (\<lambda> (w__12 :: bool) . + if w__12 then raise_c2_exception CapEx_AccessSystemRegsViolation sel + else + (let l__0 = (Word.uint sel) in + (if (((l__0 = (( 0 :: int)::ii)))) then readCapReg DDC + else if (((l__0 = (( 1 :: int)::ii)))) then + (read_reg CTLSU_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__14 :: 257 Word.word) . + return ((capRegToCapStruct w__14))) + else if (((l__0 = (( 8 :: int)::ii)))) then + (read_reg CTLSP_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__15 :: 257 Word.word) . + return ((capRegToCapStruct w__15))) + else if (((l__0 = (( 22 :: int)::ii)))) then readCapReg KR1C + else if (((l__0 = (( 23 :: int)::ii)))) then readCapReg KR2C + else if (((l__0 = (( 29 :: int)::ii)))) then readCapReg KCC + else if (((l__0 = (( 30 :: int)::ii)))) then readCapReg KDC + else if (((l__0 = (( 31 :: int)::ii)))) then readCapReg EPCC + else assert_exp False (''should be unreachable code'') \<then> undefined_CapStruct () ) \<bind> (\<lambda> (capVal :: + CapStruct) . + writeCapReg cd1 capVal))))))))))" + + +(*val execute_CPtrCmp : mword ty5 -> mword ty5 -> mword ty5 -> CPtrCmpOp -> M unit*) + +definition execute_CPtrCmp :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> CPtrCmpOp \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CPtrCmp rd cb ct op1 = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else + readCapReg cb \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let equal = False in + (let ltu = False in + (let lts = False in + (let ((equal :: bool), (lts :: bool), (ltu :: bool)) = + (if ((neq_bool(CapStruct_tag cb_val)(CapStruct_tag ct_val))) then + (let ((lts :: bool), (ltu :: bool)) = + (if ((\<not>(CapStruct_tag cb_val))) then + (let (ltu :: bool) = True in + (let (lts :: bool) = True in + (lts, ltu))) + else (lts, ltu)) in + (equal, lts, ltu)) + else + (let cursor1 = (getCapCursor cb_val) in + (let cursor2 = (getCapCursor ct_val) in + (let (equal :: bool) = (cursor1 = cursor2) in + (let (ltu :: bool) = (cursor1 < cursor2) in + (let (lts :: bool) = + (zopz0zI_s ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor1 :: 64 Word.word)) + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) cursor2 :: 64 Word.word))) in + (equal, lts, ltu))))))) in + (let (cmp :: bool) = + ((case op1 of + CEQ => equal + | CNE => \<not> equal + | CLT => lts + | CLE => (lts \<or> equal) + | CLTU => ltu + | CLEU => (ltu \<or> equal) + | CEXEQ => (cb_val = ct_val) + | CNEXEQ => (cb_val \<noteq> ct_val) + )) in + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits cmp :: 1 Word.word)) :: 64 Word.word))))))))))))" + + +(*val execute_CMOVX : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CMOVX :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CMOVX cd1 cb rt ismovn = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec + ((bool_to_bits (((w__2 = ((zeros0 (( 64 :: int)::ii) () :: 64 Word.word))))) :: 1 Word.word)) + ((bool_to_bits ismovn :: 1 Word.word)) + :: 1 Word.word)))) then + readCapReg cb \<bind> (\<lambda> (w__3 :: CapStruct) . writeCapReg cd1 w__3) + else return () ))))" + + +(*val execute_CLoad : mword ty5 -> mword ty5 -> mword ty5 -> mword ty8 -> bool -> WordType -> bool -> M unit*) + +definition execute_CLoad :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(8)Word.word \<Rightarrow> bool \<Rightarrow> WordType \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CLoad arg0 arg1 arg2 arg3 arg4 arg5 arg6 = ( + (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in + (case merge_var of + (rd, cb, rt, offset, signext, B, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 1 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 1 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__2 :: 8 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 1 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, D, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 8 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 8 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, H, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 2 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 2 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__2 :: 16 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 2 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + | (rd, cb, rt, offset, signext, W, linked) => + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cb \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__1)))) + (((( 4 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + (( 4 :: int)::ii))) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if ((\<not> ((isAddressAligned vAddr64 W)))) then SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslate vAddr64 LoadData :: ( 64 Word.word) M) \<bind> (\<lambda> pAddr . + (if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_reserve_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + return ((extendLoad w__2 signext :: 64 Word.word))) + else + (MEMr_wrapper pAddr (( 4 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + return ((extendLoad w__3 signext :: 64 Word.word)))) \<bind> (\<lambda> (memResult :: 64 bits) . + wGPR rd memResult)))))))) + )))" + + +(*val execute_CLC : mword ty5 -> mword ty5 -> mword ty5 -> mword ty11 -> bool -> M unit*) + +definition execute_CLC :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CLC cd1 cb rt offset linked = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_load cb_val))) then + raise_c2_exception CapEx_PermitLoadViolation cb + else + (let cursor = (getCapCursor cb_val) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let vAddr = + (hardware_mod + ((((cursor + ((Word.uint w__2)))) + (((( 16 :: int)::ii) * ((Word.sint offset)))))) + ((pow2 (( 64 :: int)::ii)))) in + (let vAddr64 = ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) vAddr :: 64 Word.word)) in + if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then + raise_c2_exception CapEx_LengthViolation cb + else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod vAddr cap_size)) \<noteq> (( 0 :: int)::ii)))) then + SignalExceptionBadAddr AdEL vAddr64 + else + (TLBTranslateC vAddr64 LoadData :: (( 64 Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (pAddr, suppressTag) = varstup in + (let cd1 = (Word.uint cd1) in + if linked then + ((write_reg CP0LLBit_ref (vec_of_bits [B1] :: 1 Word.word) \<then> + write_reg CP0LLAddr_ref pAddr) \<then> + (MEMr_tagged_reserve pAddr :: ((bool * 256 Word.word)) M)) \<bind> (\<lambda> varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \<and> ((((CapStruct_permit_load_cap cb_val) \<and> ((\<not> suppressTag)))))))) + mem + :: 257 Word.word)))) + else + (MEMr_tagged pAddr :: ((bool * 256 Word.word)) M) \<bind> (\<lambda> varstup . (let (tag, mem) = varstup in + write_reg + ((access_list_dec CapRegs cd1 :: (regstate, register_value, ( 257 Word.word)) register_ref)) + ((memBitsToCapBits + (((tag \<and> ((((CapStruct_permit_load_cap cb_val) \<and> ((\<not> suppressTag)))))))) + mem + :: 257 Word.word)))))))))))))))" + + +(*val execute_CJALR : mword ty5 -> mword ty5 -> bool -> M unit*) + +definition execute_CJALR :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CJALR cd1 cb link = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let cb_ptr = (getCapCursor cb_val) in + (let cb_top = (getCapTop cb_val) in + (let cb_base = (getCapBase cb_val) in + and_boolM (return link) ((register_inaccessible cd1)) \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((\<not>(CapStruct_permit_execute cb_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((((cb_ptr + (( 4 :: int)::ii))) > cb_top)) then + raise_c2_exception CapEx_LengthViolation cb + else if (((((hardware_mod cb_ptr (( 4 :: int)::ii))) \<noteq> (( 0 :: int)::ii)))) then SignalException AdEL + else + (if link then + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__3 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__3) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + (let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__4 (( 8 :: int)::ii) :: 64 Word.word))) in + if success then writeCapReg cd1 linkCap + else assert_exp False (''''))))) + else return () ) \<then> + execute_branch_pcc cb_val)))))))" + + +(*val execute_CIncOffsetImmediate : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CIncOffsetImmediate :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CIncOffsetImmediate cd1 cb imm = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (let (imm64 :: 64 bits) = ((sign_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and>(CapStruct_sealed cb_val)))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val imm64) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) imm64 + :: 64 Word.word))))))))))" + + +(*val execute_CIncOffset : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CIncOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CIncOffset cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((((CapStruct_tag cb_val) \<and> ((((CapStruct_sealed cb_val) \<and> (((rt_val \<noteq> (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)))))))))) then + raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (incCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CGetType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetType rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + (if(CapStruct_sealed capVal) then (zero_extend1 (( 64 :: int)::ii)(CapStruct_otype capVal) :: 64 Word.word) + else (replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))" + + +(*val execute_CGetTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetTag rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_tag capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetSealed : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetSealed :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetSealed rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((zero_extend1 (( 64 :: int)::ii) ((bool_to_bits(CapStruct_sealed capVal) :: 1 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPerm rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms capVal :: 31 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetPCCSetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetPCCSetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPCCSetOffset cd1 rs = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (success, newPCC) = (setCapOffset pcc rs_val) in + if success then writeCapReg cd1 newPCC + else writeCapReg cd1 ((int_to_cap rs_val))))))))" + + +(*val execute_CGetPCC : mword ty5 -> M unit*) + +definition execute_CGetPCC :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetPCC cd1 = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + (read_reg PCC_ref :: ( 257 Word.word) M) \<bind> (\<lambda> (w__1 :: 257 Word.word) . + (let pcc = (capRegToCapStruct w__1) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (let (success, pcc2) = (setCapOffset pcc w__2) in + assert_exp success ('''') \<then> writeCapReg cd1 pcc2))))))" + + +(*val execute_CGetOffset : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetOffset :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetOffset rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapOffset capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetLen : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetLen :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetLen rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + (let len65 = (getCapLength capVal) in + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + (if ((len65 > MAX_U64)) then MAX_U64 + else len65) + :: 64 Word.word))))))" + + +(*val execute_CGetCause : mword ty5 -> M unit*) + +definition execute_CGetCause :: "(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetCause rd = ( + (checkCP2usable () \<then> + pcc_access_system_regs () ) \<bind> (\<lambda> (w__0 :: bool) . + if ((\<not> w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation + else + read_reg CapCause_ref \<bind> (\<lambda> (w__1 :: CapCauseReg) . + wGPR rd ((zero_extend1 (( 64 :: int)::ii) ((get_CapCauseReg w__1 :: 16 Word.word)) :: 64 Word.word)))))" + + +(*val execute_CGetBase : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetBase :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetBase rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase capVal)) :: 64 Word.word)))))" + + +(*val execute_CGetAddr : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CGetAddr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CGetAddr rd cb = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> capVal . + wGPR rd + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapCursor capVal)) :: 64 Word.word)))))" + + +(*val execute_CFromPtr : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CFromPtr :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CFromPtr cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if (((rt = (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))) then writeCapReg cd1 null_cap + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let (success, newCap) = (setCapOffset cb_val rt_val) in + if success then writeCapReg cd1 newCap + else + writeCapReg cd1 + ((int_to_cap + ((add_vec + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((getCapBase cb_val)) + :: 64 Word.word)) rt_val + :: 64 Word.word))))))))))" + + +(*val execute_CCopyType : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCopyType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCopyType cd1 cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let cb_base = (getCapBase cb_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_otype = (Word.uint(CapStruct_otype ct_val)) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if(CapStruct_sealed ct_val) then + if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_otype \<ge> cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else + (let (success, cap) = + (setCapOffset cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((ct_otype - cb_base)) + :: 64 Word.word))) in + assert_exp success ('''') \<then> writeCapReg cd1 cap) + else + writeCapReg cd1 + ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))))))" + + +(*val execute_CClearTag : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CClearTag :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CClearTag cd1 cb = ( + (checkCP2usable () \<then> + register_inaccessible cd1) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else readCapReg cb \<bind> (\<lambda> cb_val . writeCapReg cd1 (cb_val (| CapStruct_tag := False |))))))" + + +(*val execute_CCheckType : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckType :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCheckType cs cb = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else return () )))))" + + +(*val execute_CCheckPerm : mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCheckPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCheckPerm cs rt = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + (let (cs_perms :: 64 bits) = + ((zero_extend1 (( 64 :: int)::ii) ((getCapPerms cs_val :: 31 Word.word)) :: 64 Word.word)) in + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_perms . + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((and_vec cs_perms rt_perms :: 64 Word.word)) \<noteq> rt_perms))) then + raise_c2_exception CapEx_UserDefViolation cs + else return () )))))" + + +(*val execute_CCall : mword ty5 -> mword ty5 -> mword ty11 -> M unit*) + +definition execute_CCall :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(11)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCall cs cb b__151 = ( + if (((b__151 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 11 Word.word)))) then + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\<not>(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \<ge> ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else raise_c2_exception CapEx_CallTrap cs))))) + else + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg cb \<bind> (\<lambda> cb_val . + (let cs_cursor = (getCapCursor cs_val) in + register_inaccessible cs \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible cb \<bind> (\<lambda> (w__3 :: bool) . + if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if ((\<not>(CapStruct_sealed cs_val))) then raise_c2_exception CapEx_SealViolation cs + else if ((\<not>(CapStruct_sealed cb_val))) then raise_c2_exception CapEx_SealViolation cb + else if ((((CapStruct_otype cs_val) \<noteq>(CapStruct_otype cb_val)))) then + raise_c2_exception CapEx_TypeViolation cs + else if ((\<not>(CapStruct_permit_ccall cs_val))) then + raise_c2_exception CapEx_PermitCCallViolation cs + else if ((\<not>(CapStruct_permit_ccall cb_val))) then + raise_c2_exception CapEx_PermitCCallViolation cb + else if ((\<not>(CapStruct_permit_execute cs_val))) then + raise_c2_exception CapEx_PermitExecuteViolation cs + else if(CapStruct_permit_execute cb_val) then + raise_c2_exception CapEx_PermitExecuteViolation cb + else if ((cs_cursor < ((getCapBase cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else if ((cs_cursor \<ge> ((getCapTop cs_val)))) then + raise_c2_exception CapEx_LengthViolation cs + else + (execute_branch_pcc + (cs_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) \<then> + write_reg inCCallDelay_ref (vec_of_bits [B1] :: 1 Word.word)) \<then> + write_reg + C26_ref + ((capStructToCapReg + (cb_val (| + CapStruct_sealed := False, CapStruct_otype := ((zeros0 (( 24 :: int)::ii) () :: 24 Word.word))|)) + :: 257 Word.word))))))))" + + +(*val execute_CCSeal : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CCSeal :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CCSeal cd1 cs ct = ( + (checkCP2usable () \<then> + readCapReg cs) \<bind> (\<lambda> cs_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let ct_cursor = (getCapCursor ct_val) in + (let ct_top = (getCapTop ct_val) in + (let ct_base = (getCapBase ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cs \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cs_val))) then raise_c2_exception CapEx_TagViolation cs + else if (((((\<not>(CapStruct_tag ct_val))) \<or> (((((getCapCursor ct_val)) = ((Word.uint ((replicate_bits ((cast_unit_vec0 B1 :: 1 Word.word)) (( 64 :: int)::ii) :: 64 Word.word)))))))))) + then + writeCapReg cd1 cs_val + else if(CapStruct_sealed cs_val) then raise_c2_exception CapEx_SealViolation cs + else if(CapStruct_sealed ct_val) then raise_c2_exception CapEx_SealViolation ct + else if ((\<not>(CapStruct_permit_seal ct_val))) then + raise_c2_exception CapEx_PermitSealViolation ct + else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor \<ge> ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct + else + (let (success, newCap) = + (sealCap cs_val + ((to_bits ((make_the_value (( 24 :: int)::ii) :: 24 itself)) ct_cursor :: 24 Word.word))) in + if ((\<not> success)) then raise_c2_exception CapEx_InexactBounds cs + else writeCapReg cd1 newCap))))))))))" + + +(*val execute_CBuildCap : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CBuildCap :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBuildCap cd1 cb ct = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + readCapReg ct \<bind> (\<lambda> ct_val . + (let cb_base = (getCapBase cb_val) in + (let ct_base = (getCapBase ct_val) in + (let cb_top = (getCapTop cb_val) in + (let ct_top = (getCapTop ct_val) in + (let cb_perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let ct_perms = ((getCapPerms ct_val :: 31 Word.word)) in + (let ct_offset = (getCapOffset ct_val) in + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + register_inaccessible ct \<bind> (\<lambda> (w__2 :: bool) . + if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb + else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct + else if (((((and_vec ct_perms cb_perms :: 31 Word.word)) \<noteq> ct_perms))) then + raise_c2_exception CapEx_UserDefViolation cb + else + (let (exact, cd11) = + (setCapBounds cb_val + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_base :: 64 Word.word)) + ((to_bits ((make_the_value (( 65 :: int)::ii) :: 65 itself)) ct_top :: 65 Word.word))) in + (let (representable, cd2) = + (setCapOffset cd11 + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ct_offset :: 64 Word.word))) in + (let cd3 = (setCapPerms cd2 ct_perms) in + (assert_exp exact ('''') \<then> assert_exp representable ('''')) \<then> writeCapReg cd1 cd3))))))))))))))))" + + +(*val execute_CBZ : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBZ cb imm notzero = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__1 = null_cap))) :: 1 Word.word)) + ((bool_to_bits notzero :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CBX : mword ty5 -> mword ty16 -> bool -> M unit*) + +definition execute_CBX :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CBX cb imm notset = ( + (checkCP2usable () \<then> + register_inaccessible cb) \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else + readCapReg cb \<bind> (\<lambda> (w__1 :: CapStruct) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits(CapStruct_tag w__1) :: 1 Word.word)) + ((bool_to_bits notset :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else return () )))" + + +(*val execute_CAndPerm : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_CAndPerm :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CAndPerm cd1 cb rt = ( + (checkCP2usable () \<then> + readCapReg cb) \<bind> (\<lambda> cb_val . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> rt_val . + register_inaccessible cd1 \<bind> (\<lambda> (w__0 :: bool) . + if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd1 + else + register_inaccessible cb \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb + else if ((\<not>(CapStruct_tag cb_val))) then raise_c2_exception CapEx_TagViolation cb + else if(CapStruct_sealed cb_val) then raise_c2_exception CapEx_SealViolation cb + else + (let perms = ((getCapPerms cb_val :: 31 Word.word)) in + (let newCap = + (setCapPerms cb_val + ((and_vec perms ((subrange_vec_dec rt_val (( 30 :: int)::ii) (( 0 :: int)::ii) :: 31 Word.word)) :: 31 Word.word))) in + writeCapReg cd1 newCap)))))))" + + +(*val execute_CACHE : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_CACHE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CACHE base op1 imm = ( checkCP0Access () )" + + +(*val execute_C2Dump : mword ty5 -> unit*) + +definition execute_C2Dump :: "(5)Word.word \<Rightarrow> unit " where + " execute_C2Dump rt = ( () )" + + +(*val execute_BREAK : unit -> M unit*) + +definition execute_BREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BREAK g__120 = ( SignalException Bp )" + + +(*val execute_BEQ : mword ty5 -> mword ty5 -> mword ty16 -> bool -> bool -> M unit*) + +definition execute_BEQ :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BEQ rs rd imm ne likely = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rd :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + if ((bits_to_bool + ((xor_vec ((bool_to_bits (((w__0 = w__1))) :: 1 Word.word)) + ((bool_to_bits ne :: 1 Word.word)) + :: 1 Word.word)))) then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + execute_branch ((add_vec w__2 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__3 (( 8 :: int)::ii) :: 64 Word.word))) + else return () )))" + + +(*val execute_BCMPZ : mword ty5 -> mword ty16 -> Comparison -> bool -> bool -> M unit*) + +definition execute_BCMPZ :: "(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow> Comparison \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BCMPZ rs imm cmp link likely = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (let linkVal = ((add_vec_int w__0 (( 8 :: int)::ii) :: 64 Word.word)) in + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> regVal . + (let condition = + (compare cmp regVal ((zero_extend1 (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (if condition then + (let (offset :: 64 bits) = + ((add_vec_int + ((sign_extend1 (( 64 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0] :: 2 Word.word) :: 18 Word.word)) + :: 64 Word.word)) (( 4 :: int)::ii) + :: 64 Word.word)) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + execute_branch ((add_vec w__1 offset :: 64 Word.word)))) + else if likely then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec_int w__2 (( 8 :: int)::ii) :: 64 Word.word))) + else return () ) \<then> + (if link then wGPR (vec_of_bits [B1,B1,B1,B1,B1] :: 5 Word.word) linkVal + else return () ))))))" + + +(*val execute_ANDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ANDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ANDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))))" + + +(*val execute_AND : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_AND :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_AND rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + wGPR rd ((and_vec w__0 w__1 :: 64 Word.word)))))" + + +(*val execute_ADDU : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADDU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDU rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> opB . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word)))))" + + +(*val execute_ADDIU : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDIU :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDIU rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) + ((add_vec ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + ((sign_extend1 (( 32 :: int)::ii) imm :: 32 Word.word)) + :: 32 Word.word)) + :: 64 Word.word))))" + + +(*val execute_ADDI : mword ty5 -> mword ty5 -> mword ty16 -> M unit*) + +definition execute_ADDI :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDI rs rt imm = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> opA . + if ((NotWordVal opA)) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rt w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) imm :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rt + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + + +(*val execute_ADD : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_ADD :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADD rs rt rd = ( + (rGPR rs :: ( 64 Word.word) M) \<bind> (\<lambda> (opA :: 64 bits) . + (rGPR rt :: ( 64 Word.word) M) \<bind> (\<lambda> (opB :: 64 bits) . + if (((((NotWordVal opA)) \<or> ((NotWordVal opB))))) then + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . wGPR rd w__0) + else + (let (sum33 :: 33 bits) = + ((add_vec + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opA (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + ((sign_extend1 (( 33 :: int)::ii) ((subrange_vec_dec opB (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 33 Word.word)) + :: 33 Word.word)) in + if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 :: int)::ii))))) + ((bit_to_bool ((access_vec_dec sum33 (( 31 :: int)::ii))))))) then + SignalException Ov + else + wGPR rd + ((sign_extend1 (( 64 :: int)::ii) ((subrange_vec_dec sum33 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word))))))" + + +fun execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute (DADDIU (rs,rt,imm)) = ( execute_DADDIU rs rt imm )" +|" execute (DADDU (rs,rt,rd)) = ( execute_DADDU rs rt rd )" +|" execute (DADDI (rs,rt,imm)) = ( execute_DADDI rs rt imm )" +|" execute (DADD (rs,rt,rd)) = ( execute_DADD rs rt rd )" +|" execute (ADD (rs,rt,rd)) = ( execute_ADD rs rt rd )" +|" execute (ADDI (rs,rt,imm)) = ( execute_ADDI rs rt imm )" +|" execute (ADDU (rs,rt,rd)) = ( execute_ADDU rs rt rd )" +|" execute (ADDIU (rs,rt,imm)) = ( execute_ADDIU rs rt imm )" +|" execute (DSUBU (rs,rt,rd)) = ( execute_DSUBU rs rt rd )" +|" execute (DSUB (rs,rt,rd)) = ( execute_DSUB rs rt rd )" +|" execute (SUB (rs,rt,rd)) = ( execute_SUB rs rt rd )" +|" execute (SUBU (rs,rt,rd)) = ( execute_SUBU rs rt rd )" +|" execute (AND0 (rs,rt,rd)) = ( execute_AND rs rt rd )" +|" execute (ANDI (rs,rt,imm)) = ( execute_ANDI rs rt imm )" +|" execute (OR0 (rs,rt,rd)) = ( execute_OR rs rt rd )" +|" execute (ORI (rs,rt,imm)) = ( execute_ORI rs rt imm )" +|" execute (NOR (rs,rt,rd)) = ( execute_NOR rs rt rd )" +|" execute (XOR0 (rs,rt,rd)) = ( execute_XOR rs rt rd )" +|" execute (XORI (rs,rt,imm)) = ( execute_XORI rs rt imm )" +|" execute (LUI (rt,imm)) = ( execute_LUI rt imm )" +|" execute (DSLL (rt,rd,sa)) = ( execute_DSLL rt rd sa )" +|" execute (DSLL32 (rt,rd,sa)) = ( execute_DSLL32 rt rd sa )" +|" execute (DSLLV (rs,rt,rd)) = ( execute_DSLLV rs rt rd )" +|" execute (DSRA (rt,rd,sa)) = ( execute_DSRA rt rd sa )" +|" execute (DSRA32 (rt,rd,sa)) = ( execute_DSRA32 rt rd sa )" +|" execute (DSRAV (rs,rt,rd)) = ( execute_DSRAV rs rt rd )" +|" execute (DSRL (rt,rd,sa)) = ( execute_DSRL rt rd sa )" +|" execute (DSRL32 (rt,rd,sa)) = ( execute_DSRL32 rt rd sa )" +|" execute (DSRLV (rs,rt,rd)) = ( execute_DSRLV rs rt rd )" +|" execute (SLL (rt,rd,sa)) = ( execute_SLL rt rd sa )" +|" execute (SLLV (rs,rt,rd)) = ( execute_SLLV rs rt rd )" +|" execute (SRA (rt,rd,sa)) = ( execute_SRA rt rd sa )" +|" execute (SRAV (rs,rt,rd)) = ( execute_SRAV rs rt rd )" +|" execute (SRL (rt,rd,sa)) = ( execute_SRL rt rd sa )" +|" execute (SRLV (rs,rt,rd)) = ( execute_SRLV rs rt rd )" +|" execute (SLT (rs,rt,rd)) = ( execute_SLT rs rt rd )" +|" execute (SLTI (rs,rt,imm)) = ( execute_SLTI rs rt imm )" +|" execute (SLTU (rs,rt,rd)) = ( execute_SLTU rs rt rd )" +|" execute (SLTIU (rs,rt,imm)) = ( execute_SLTIU rs rt imm )" +|" execute (MOVN (rs,rt,rd)) = ( execute_MOVN rs rt rd )" +|" execute (MOVZ (rs,rt,rd)) = ( execute_MOVZ rs rt rd )" +|" execute (MFHI (rd)) = ( execute_MFHI rd )" +|" execute (MFLO (rd)) = ( execute_MFLO rd )" +|" execute (MTHI (rs)) = ( execute_MTHI rs )" +|" execute (MTLO (rs)) = ( execute_MTLO rs )" +|" execute (MUL (rs,rt,rd)) = ( execute_MUL rs rt rd )" +|" execute (MULT (rs,rt)) = ( execute_MULT rs rt )" +|" execute (MULTU (rs,rt)) = ( execute_MULTU rs rt )" +|" execute (DMULT (rs,rt)) = ( execute_DMULT rs rt )" +|" execute (DMULTU (rs,rt)) = ( execute_DMULTU rs rt )" +|" execute (MADD (rs,rt)) = ( execute_MADD rs rt )" +|" execute (MADDU (rs,rt)) = ( execute_MADDU rs rt )" +|" execute (MSUB (rs,rt)) = ( execute_MSUB rs rt )" +|" execute (MSUBU (rs,rt)) = ( execute_MSUBU rs rt )" +|" execute (DIV (rs,rt)) = ( execute_DIV rs rt )" +|" execute (DIVU (rs,rt)) = ( execute_DIVU rs rt )" +|" execute (DDIV (rs,rt)) = ( execute_DDIV rs rt )" +|" execute (DDIVU (rs,rt)) = ( execute_DDIVU rs rt )" +|" execute (J (offset)) = ( execute_J offset )" +|" execute (JAL (offset)) = ( execute_JAL offset )" +|" execute (JR (rs)) = ( execute_JR rs )" +|" execute (JALR (rs,rd)) = ( execute_JALR rs rd )" +|" execute (BEQ (rs,rd,imm,ne,likely)) = ( execute_BEQ rs rd imm ne likely )" +|" execute (BCMPZ (rs,imm,cmp,link,likely)) = ( execute_BCMPZ rs imm cmp link likely )" +|" execute (SYSCALL_THREAD_START (g__117)) = ( return ((execute_SYSCALL_THREAD_START g__117)))" +|" execute (ImplementationDefinedStopFetching (g__118)) = ( + return ((execute_ImplementationDefinedStopFetching g__118)))" +|" execute (SYSCALL (g__119)) = ( execute_SYSCALL g__119 )" +|" execute (BREAK (g__120)) = ( execute_BREAK g__120 )" +|" execute (WAIT (g__121)) = ( execute_WAIT g__121 )" +|" execute (TRAPREG (rs,rt,cmp)) = ( execute_TRAPREG rs rt cmp )" +|" execute (TRAPIMM (rs,imm,cmp)) = ( execute_TRAPIMM rs imm cmp )" +|" execute (Load (width,sign,linked,base,rt,offset)) = ( execute_Load width sign linked base rt offset )" +|" execute (Store (width,conditional,base,rt,offset)) = ( execute_Store width conditional base rt offset )" +|" execute (LWL (base,rt,offset)) = ( execute_LWL base rt offset )" +|" execute (LWR (base,rt,offset)) = ( execute_LWR base rt offset )" +|" execute (SWL (base,rt,offset)) = ( execute_SWL base rt offset )" +|" execute (SWR (base,rt,offset)) = ( execute_SWR base rt offset )" +|" execute (LDL (base,rt,offset)) = ( execute_LDL base rt offset )" +|" execute (LDR (base,rt,offset)) = ( execute_LDR base rt offset )" +|" execute (SDL (base,rt,offset)) = ( execute_SDL base rt offset )" +|" execute (SDR (base,rt,offset)) = ( execute_SDR base rt offset )" +|" execute (CACHE (base,op1,imm)) = ( execute_CACHE base op1 imm )" +|" execute (PREF (base,op1,imm)) = ( return ((execute_PREF base op1 imm)))" +|" execute (SYNC (g__122)) = ( execute_SYNC g__122 )" +|" execute (MFC0 (rt,rd,sel,double)) = ( execute_MFC0 rt rd sel double )" +|" execute (HCF (g__123)) = ( return ((execute_HCF g__123)))" +|" execute (MTC0 (rt,rd,sel,double)) = ( execute_MTC0 rt rd sel double )" +|" execute (TLBWI (g__124)) = ( execute_TLBWI g__124 )" +|" execute (TLBWR (g__125)) = ( execute_TLBWR g__125 )" +|" execute (TLBR (g__126)) = ( execute_TLBR g__126 )" +|" execute (TLBP (g__127)) = ( execute_TLBP g__127 )" +|" execute (RDHWR (rt,rd)) = ( execute_RDHWR rt rd )" +|" execute (ERET (g__128)) = ( execute_ERET g__128 )" +|" execute (CGetPerm (rd,cb)) = ( execute_CGetPerm rd cb )" +|" execute (CGetType (rd,cb)) = ( execute_CGetType rd cb )" +|" execute (CGetBase (rd,cb)) = ( execute_CGetBase rd cb )" +|" execute (CGetOffset (rd,cb)) = ( execute_CGetOffset rd cb )" +|" execute (CGetLen (rd,cb)) = ( execute_CGetLen rd cb )" +|" execute (CGetTag (rd,cb)) = ( execute_CGetTag rd cb )" +|" execute (CGetSealed (rd,cb)) = ( execute_CGetSealed rd cb )" +|" execute (CGetAddr (rd,cb)) = ( execute_CGetAddr rd cb )" +|" execute (CGetPCC (cd1)) = ( execute_CGetPCC cd1 )" +|" execute (CGetPCCSetOffset (cd1,rs)) = ( execute_CGetPCCSetOffset cd1 rs )" +|" execute (CGetCause (rd)) = ( execute_CGetCause rd )" +|" execute (CSetCause (rt)) = ( execute_CSetCause rt )" +|" execute (CReadHwr (cd1,sel)) = ( execute_CReadHwr cd1 sel )" +|" execute (CWriteHwr (cb,sel)) = ( execute_CWriteHwr cb sel )" +|" execute (CAndPerm (cd1,cb,rt)) = ( execute_CAndPerm cd1 cb rt )" +|" execute (CToPtr (rd,cb,ct)) = ( execute_CToPtr rd cb ct )" +|" execute (CSub (rd,cb,ct)) = ( execute_CSub rd cb ct )" +|" execute (CPtrCmp (rd,cb,ct,op1)) = ( execute_CPtrCmp rd cb ct op1 )" +|" execute (CIncOffset (cd1,cb,rt)) = ( execute_CIncOffset cd1 cb rt )" +|" execute (CIncOffsetImmediate (cd1,cb,imm)) = ( execute_CIncOffsetImmediate cd1 cb imm )" +|" execute (CSetOffset (cd1,cb,rt)) = ( execute_CSetOffset cd1 cb rt )" +|" execute (CSetBounds (cd1,cb,rt)) = ( execute_CSetBounds cd1 cb rt )" +|" execute (CSetBoundsImmediate (cd1,cb,imm)) = ( execute_CSetBoundsImmediate cd1 cb imm )" +|" execute (CSetBoundsExact (cd1,cb,rt)) = ( execute_CSetBoundsExact cd1 cb rt )" +|" execute (CClearTag (cd1,cb)) = ( execute_CClearTag cd1 cb )" +|" execute (CMOVX (cd1,cb,rt,ismovn)) = ( execute_CMOVX cd1 cb rt ismovn )" +|" execute (ClearRegs (regset,m)) = ( execute_ClearRegs regset m )" +|" execute (CFromPtr (cd1,cb,rt)) = ( execute_CFromPtr cd1 cb rt )" +|" execute (CBuildCap (cd1,cb,ct)) = ( execute_CBuildCap cd1 cb ct )" +|" execute (CCopyType (cd1,cb,ct)) = ( execute_CCopyType cd1 cb ct )" +|" execute (CCheckPerm (cs,rt)) = ( execute_CCheckPerm cs rt )" +|" execute (CCheckType (cs,cb)) = ( execute_CCheckType cs cb )" +|" execute (CTestSubset (rd,cb,ct)) = ( execute_CTestSubset rd cb ct )" +|" execute (CSeal (cd1,cs,ct)) = ( execute_CSeal cd1 cs ct )" +|" execute (CCSeal (cd1,cs,ct)) = ( execute_CCSeal cd1 cs ct )" +|" execute (CUnseal (cd1,cs,ct)) = ( execute_CUnseal cd1 cs ct )" +|" execute (CCall (cs,cb,b__151)) = ( execute_CCall cs cb b__151 )" +|" execute (CReturn (g__129)) = ( execute_CReturn g__129 )" +|" execute (CBX (cb,imm,notset)) = ( execute_CBX cb imm notset )" +|" execute (CBZ (cb,imm,notzero)) = ( execute_CBZ cb imm notzero )" +|" execute (CJALR (cd1,cb,link)) = ( execute_CJALR cd1 cb link )" +|" execute (CLoad (rd,cb,rt,offset,signext,arg5,linked)) = ( + execute_CLoad rd cb rt offset signext arg5 linked )" +|" execute (CStore (rs,cb,rt,rd,offset,width,conditional)) = ( + execute_CStore rs cb rt rd offset width conditional )" +|" execute (CSC (cs,cb,rt,rd,offset,conditional)) = ( execute_CSC cs cb rt rd offset conditional )" +|" execute (CLC (cd1,cb,rt,offset,linked)) = ( execute_CLC cd1 cb rt offset linked )" +|" execute (C2Dump (rt)) = ( return ((execute_C2Dump rt)))" +|" execute (RI (g__130)) = ( execute_RI g__130 )" + + +(*val supported_instructions : ast -> maybe ast*) + +definition supported_instructions :: " ast \<Rightarrow>(ast)option " where + " supported_instructions instr = ( Some instr )" + + +(*val fetch_and_execute : unit -> M unit*) + +definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " fetch_and_execute _ = ( + catch_early_return + (((whileM () + (\<lambda> unit_var . return True) + (\<lambda> unit_var . + liftR ((read_reg nextPC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 bits) . + (liftR (write_reg PC_ref w__0) \<then> + liftR ((read_reg branchPending_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__1 :: 1 bits) . + ((liftR (write_reg inBranchDelay_ref w__1) \<then> + liftR (write_reg branchPending_ref (vec_of_bits [B0] :: 1 Word.word))) \<then> + liftR ((read_reg inBranchDelay_ref :: ( 1 Word.word) M))) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (if ((bits_to_bool w__2)) then liftR ((read_reg delayedPC_ref :: ( 64 Word.word) M)) + else + liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return ((add_vec_int w__4 (( 4 :: int)::ii) :: 64 Word.word)))) \<bind> (\<lambda> (w__5 :: 64 Word.word) . + ((liftR (write_reg nextPC_ref w__5) \<then> + liftR (cp2_next_pc () )) \<then> + liftR (read_reg instCount_ref)) \<bind> (\<lambda> (w__6 :: ii) . + (liftR (write_reg instCount_ref ((w__6 + (( 1 :: int)::ii)))) \<then> + liftR ((read_reg PC_ref :: ( 64 Word.word) M))) \<bind> (\<lambda> (w__7 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''PC: '') w__7) in + try_catchR (liftR ((read_reg PC_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 Word.word) . + liftR ((TranslatePC w__8 :: ( 64 Word.word) M)) \<bind> (\<lambda> pc_pa . + liftR ((MEMr_wrapper pc_pa (( 4 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> instr . + (let instr_ast = (decode instr) in + (case instr_ast of + Some ((HCF (_))) => + (let (_ :: unit) = + (prerr_endline (''simulation stopped due to halt instruction.'')) in + (early_return () :: (unit, unit) MR)) + | Some (ast) => liftR (execute ast) + | None => + (let (_ :: unit) = (prerr_endline (''Decode failed'')) in + liftR (exit0 () )) + )))))) (\<lambda>x . + (case x of ISAException (_) => return ((prerr_endline (''EXCEPTION''))) ))))))))))) \<then> + liftR (skip () )) \<then> liftR (skip () )))" + + +(*val main : unit -> M unit*) + +(*val dump_mips_state : unit -> M unit*) + +definition dump_mips_state :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " dump_mips_state _ = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (let (_ :: unit) = (print_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict (''DEBUG MIPS PC '') w__0) in + (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () + (\<lambda> idx unit_var . + (rGPR ((to_bits ((make_the_value (( 5 :: int)::ii) :: 5 itself)) idx :: 5 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: + 64 Word.word) . + return ((let _ = + (prerr_endline + (((op@) (''DEBUG MIPS REG '') + (((op@) ((string_of_int + instance_Show_Show_Num_integer_dict idx)) (((op@) ('' '') ((string_of_bits + instance_Sail_values_Bitvector_Machine_word_mword_dict w__1))))))))) in + () ))))))))" + + +definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " main _ = ( + ((init_cp0_state () \<then> + init_cp2_state () ) \<then> + write_reg + nextPC_ref + ((to_bits ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) :: 64 Word.word))) \<then> + ((let startTime = (get_time_ns () ) in + fetch_and_execute () \<then> + ((let endTime = (get_time_ns () ) in + (let elapsed = (endTime - startTime) in + read_reg instCount_ref \<bind> (\<lambda> (w__0 :: ii) . + (let inst_1e9 = (w__0 * (( 1000000000 :: int)::ii)) in + (let ips = (inst_1e9 div elapsed) in + ((dump_mips_state () \<then> + dump_cp2_state () ) \<then> + read_reg instCount_ref) \<bind> (\<lambda> (w__1 :: ii) . + (let (_ :: unit) = (print_int (''Executed instructions: '') w__1) in + (let (_ :: unit) = (print_int (''Nanoseconds elapsed: '') elapsed) in + return ((print_int (''Instructions per second: '') ips))))))))))))))" + + +(*val initialize_registers : unit -> M unit*) + +definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " initialize_registers _ = ( + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (write_reg PC_ref w__0 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . + (write_reg nextPC_ref w__1 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__2 :: 1 bits) . + (write_reg TLBProbe_ref w__2 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__3 :: TLBIndexT) . + (write_reg TLBIndex_ref w__3 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__4 :: TLBIndexT) . + (write_reg TLBRandom_ref w__4 \<then> + undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__5 :: TLBEntryLoReg) . + (write_reg TLBEntryLo0_ref w__5 \<then> + undefined_TLBEntryLoReg () ) \<bind> (\<lambda> (w__6 :: TLBEntryLoReg) . + (write_reg TLBEntryLo1_ref w__6 \<then> + undefined_ContextReg () ) \<bind> (\<lambda> (w__7 :: ContextReg) . + (write_reg TLBContext_ref w__7 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__8 :: 16 bits) . + (write_reg TLBPageMask_ref w__8 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 :: int)::ii) :: ( 6 Word.word) M)) \<bind> (\<lambda> (w__9 :: TLBIndexT) . + (write_reg TLBWired_ref w__9 \<then> + undefined_TLBEntryHiReg () ) \<bind> (\<lambda> (w__10 :: TLBEntryHiReg) . + (write_reg TLBEntryHi_ref w__10 \<then> + undefined_XContextReg () ) \<bind> (\<lambda> (w__11 :: XContextReg) . + (write_reg TLBXContext_ref w__11 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__12 :: TLBEntry) . + (write_reg TLBEntry00_ref w__12 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__13 :: TLBEntry) . + (write_reg TLBEntry01_ref w__13 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__14 :: TLBEntry) . + (write_reg TLBEntry02_ref w__14 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__15 :: TLBEntry) . + (write_reg TLBEntry03_ref w__15 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__16 :: TLBEntry) . + (write_reg TLBEntry04_ref w__16 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__17 :: TLBEntry) . + (write_reg TLBEntry05_ref w__17 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__18 :: TLBEntry) . + (write_reg TLBEntry06_ref w__18 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__19 :: TLBEntry) . + (write_reg TLBEntry07_ref w__19 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__20 :: TLBEntry) . + (write_reg TLBEntry08_ref w__20 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__21 :: TLBEntry) . + (write_reg TLBEntry09_ref w__21 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__22 :: TLBEntry) . + (write_reg TLBEntry10_ref w__22 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__23 :: TLBEntry) . + (write_reg TLBEntry11_ref w__23 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__24 :: TLBEntry) . + (write_reg TLBEntry12_ref w__24 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__25 :: TLBEntry) . + (write_reg TLBEntry13_ref w__25 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__26 :: TLBEntry) . + (write_reg TLBEntry14_ref w__26 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__27 :: TLBEntry) . + (write_reg TLBEntry15_ref w__27 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__28 :: TLBEntry) . + (write_reg TLBEntry16_ref w__28 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__29 :: TLBEntry) . + (write_reg TLBEntry17_ref w__29 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__30 :: TLBEntry) . + (write_reg TLBEntry18_ref w__30 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__31 :: TLBEntry) . + (write_reg TLBEntry19_ref w__31 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__32 :: TLBEntry) . + (write_reg TLBEntry20_ref w__32 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__33 :: TLBEntry) . + (write_reg TLBEntry21_ref w__33 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__34 :: TLBEntry) . + (write_reg TLBEntry22_ref w__34 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__35 :: TLBEntry) . + (write_reg TLBEntry23_ref w__35 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__36 :: TLBEntry) . + (write_reg TLBEntry24_ref w__36 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__37 :: TLBEntry) . + (write_reg TLBEntry25_ref w__37 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__38 :: TLBEntry) . + (write_reg TLBEntry26_ref w__38 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__39 :: TLBEntry) . + (write_reg TLBEntry27_ref w__39 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__40 :: TLBEntry) . + (write_reg TLBEntry28_ref w__40 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__41 :: TLBEntry) . + (write_reg TLBEntry29_ref w__41 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__42 :: TLBEntry) . + (write_reg TLBEntry30_ref w__42 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__43 :: TLBEntry) . + (write_reg TLBEntry31_ref w__43 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__44 :: TLBEntry) . + (write_reg TLBEntry32_ref w__44 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__45 :: TLBEntry) . + (write_reg TLBEntry33_ref w__45 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__46 :: TLBEntry) . + (write_reg TLBEntry34_ref w__46 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__47 :: TLBEntry) . + (write_reg TLBEntry35_ref w__47 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__48 :: TLBEntry) . + (write_reg TLBEntry36_ref w__48 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__49 :: TLBEntry) . + (write_reg TLBEntry37_ref w__49 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__50 :: TLBEntry) . + (write_reg TLBEntry38_ref w__50 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__51 :: TLBEntry) . + (write_reg TLBEntry39_ref w__51 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__52 :: TLBEntry) . + (write_reg TLBEntry40_ref w__52 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__53 :: TLBEntry) . + (write_reg TLBEntry41_ref w__53 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__54 :: TLBEntry) . + (write_reg TLBEntry42_ref w__54 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__55 :: TLBEntry) . + (write_reg TLBEntry43_ref w__55 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__56 :: TLBEntry) . + (write_reg TLBEntry44_ref w__56 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__57 :: TLBEntry) . + (write_reg TLBEntry45_ref w__57 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__58 :: TLBEntry) . + (write_reg TLBEntry46_ref w__58 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__59 :: TLBEntry) . + (write_reg TLBEntry47_ref w__59 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__60 :: TLBEntry) . + (write_reg TLBEntry48_ref w__60 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__61 :: TLBEntry) . + (write_reg TLBEntry49_ref w__61 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__62 :: TLBEntry) . + (write_reg TLBEntry50_ref w__62 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__63 :: TLBEntry) . + (write_reg TLBEntry51_ref w__63 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__64 :: TLBEntry) . + (write_reg TLBEntry52_ref w__64 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__65 :: TLBEntry) . + (write_reg TLBEntry53_ref w__65 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__66 :: TLBEntry) . + (write_reg TLBEntry54_ref w__66 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__67 :: TLBEntry) . + (write_reg TLBEntry55_ref w__67 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__68 :: TLBEntry) . + (write_reg TLBEntry56_ref w__68 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__69 :: TLBEntry) . + (write_reg TLBEntry57_ref w__69 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__70 :: TLBEntry) . + (write_reg TLBEntry58_ref w__70 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__71 :: TLBEntry) . + (write_reg TLBEntry59_ref w__71 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__72 :: TLBEntry) . + (write_reg TLBEntry60_ref w__72 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__73 :: TLBEntry) . + (write_reg TLBEntry61_ref w__73 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__74 :: TLBEntry) . + (write_reg TLBEntry62_ref w__74 \<then> + undefined_TLBEntry () ) \<bind> (\<lambda> (w__75 :: TLBEntry) . + (write_reg TLBEntry63_ref w__75 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . + (write_reg CP0Compare_ref w__76 \<then> + undefined_CauseReg () ) \<bind> (\<lambda> (w__77 :: CauseReg) . + (write_reg CP0Cause_ref w__77 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__78 :: 64 bits) . + (write_reg CP0EPC_ref w__78 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__79 :: 64 bits) . + (write_reg CP0ErrorEPC_ref w__79 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__80 :: 1 bits) . + (write_reg CP0LLBit_ref w__80 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__81 :: 64 bits) . + (write_reg CP0LLAddr_ref w__81 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__82 :: 64 bits) . + (write_reg CP0BadVAddr_ref w__82 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . + (write_reg CP0Count_ref w__83 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . + (write_reg CP0HWREna_ref w__84 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__85 :: 64 bits) . + (write_reg CP0UserLocal_ref w__85 \<then> + undefined_StatusReg () ) \<bind> (\<lambda> (w__86 :: StatusReg) . + (write_reg CP0Status_ref w__86 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__87 :: 1 bits) . + (write_reg branchPending_ref w__87 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__88 :: 1 bits) . + (write_reg inBranchDelay_ref w__88 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . + (write_reg delayedPC_ref w__89 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__90 :: 64 bits) . + (write_reg HI_ref w__90 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__91 :: 64 bits) . + (write_reg LO_ref w__91 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__92 :: 64 Word.word) . + (undefined_vector (( 32 :: int)::ii) w__92 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__93 :: ( 64 bits) list) . + (write_reg GPR_ref w__93 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__94 :: 8 bits) . + (write_reg UART_WDATA_ref w__94 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__95 :: 1 bits) . + (write_reg UART_WRITTEN_ref w__95 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (w__96 :: 8 bits) . + (write_reg UART_RDATA_ref w__96 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__97 :: 1 bits) . + (write_reg UART_RVALID_ref w__97 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__98 :: CapReg) . + (write_reg PCC_ref w__98 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__99 :: CapReg) . + (write_reg nextPCC_ref w__99 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__100 :: CapReg) . + (write_reg delayedPCC_ref w__100 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__101 :: 1 bits) . + (write_reg inCCallDelay_ref w__101 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__102 :: CapReg) . + (write_reg C00_ref w__102 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__103 :: CapReg) . + (write_reg C01_ref w__103 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__104 :: CapReg) . + (write_reg C02_ref w__104 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__105 :: CapReg) . + (write_reg C03_ref w__105 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__106 :: CapReg) . + (write_reg C04_ref w__106 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__107 :: CapReg) . + (write_reg C05_ref w__107 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__108 :: CapReg) . + (write_reg C06_ref w__108 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__109 :: CapReg) . + (write_reg C07_ref w__109 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__110 :: CapReg) . + (write_reg C08_ref w__110 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__111 :: CapReg) . + (write_reg C09_ref w__111 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__112 :: CapReg) . + (write_reg C10_ref w__112 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__113 :: CapReg) . + (write_reg C11_ref w__113 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__114 :: CapReg) . + (write_reg C12_ref w__114 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__115 :: CapReg) . + (write_reg C13_ref w__115 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__116 :: CapReg) . + (write_reg C14_ref w__116 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__117 :: CapReg) . + (write_reg C15_ref w__117 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__118 :: CapReg) . + (write_reg C16_ref w__118 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__119 :: CapReg) . + (write_reg C17_ref w__119 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__120 :: CapReg) . + (write_reg C18_ref w__120 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__121 :: CapReg) . + (write_reg C19_ref w__121 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__122 :: CapReg) . + (write_reg C20_ref w__122 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__123 :: CapReg) . + (write_reg C21_ref w__123 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__124 :: CapReg) . + (write_reg C22_ref w__124 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__125 :: CapReg) . + (write_reg C23_ref w__125 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__126 :: CapReg) . + (write_reg C24_ref w__126 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__127 :: CapReg) . + (write_reg C25_ref w__127 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__128 :: CapReg) . + (write_reg C26_ref w__128 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__129 :: CapReg) . + (write_reg C27_ref w__129 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__130 :: CapReg) . + (write_reg C28_ref w__130 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__131 :: CapReg) . + (write_reg C29_ref w__131 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__132 :: CapReg) . + (write_reg C30_ref w__132 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__133 :: CapReg) . + (write_reg C31_ref w__133 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__134 :: CapReg) . + (write_reg CTLSU_ref w__134 \<then> + (undefined_bitvector + instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 :: int)::ii) :: ( 257 Word.word) M)) \<bind> (\<lambda> (w__135 :: CapReg) . + (write_reg CTLSP_ref w__135 \<then> + undefined_CapCauseReg () ) \<bind> (\<lambda> (w__136 :: CapCauseReg) . + (write_reg CapCause_ref w__136 \<then> + undefined_int () ) \<bind> (\<lambda> (w__137 :: ii) . write_reg instCount_ref w__137)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| instCount = ((( 0 :: int)::ii)), + CapCause = + (Mk_CapCauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + CTLSP = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + CTLSU = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C31 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C30 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C29 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C28 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C27 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C26 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C25 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C24 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C23 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C22 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C21 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C20 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C19 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C18 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C17 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C16 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C15 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C14 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C13 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C12 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C11 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C10 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C09 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C08 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C07 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C06 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C05 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C04 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C03 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C02 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C01 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + C00 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + inCCallDelay = ((vec_of_bits [B0] :: 1 Word.word)), + delayedPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + nextPCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + PCC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 257 Word.word)), + UART_RVALID = ((vec_of_bits [B0] :: 1 Word.word)), + UART_RDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + UART_WRITTEN = ((vec_of_bits [B0] :: 1 Word.word)), + UART_WDATA = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)), + GPR = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + LO = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + HI = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + delayedPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + inBranchDelay = ((vec_of_bits [B0] :: 1 Word.word)), + branchPending = ((vec_of_bits [B0] :: 1 Word.word)), + CP0Status = + (Mk_StatusReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0UserLocal = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0HWREna = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Count = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0BadVAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLAddr = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0LLBit = ((vec_of_bits [B0] :: 1 Word.word)), + CP0ErrorEPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0EPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + CP0Cause = + (Mk_CauseReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + CP0Compare = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0] + :: 32 Word.word)), + TLBEntry63 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry62 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry61 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry60 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry59 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry58 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry57 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry56 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry55 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry54 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry53 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry52 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry51 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry50 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry49 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry48 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry47 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry46 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry45 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry44 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry43 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry42 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry41 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry40 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry39 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry38 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry37 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry36 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry35 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry34 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry33 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry32 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry31 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry30 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry29 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry28 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry27 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry26 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry25 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry24 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry23 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry22 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry21 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry20 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry19 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry18 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry17 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry16 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry15 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry14 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry13 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry12 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry11 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry10 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry09 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry08 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry07 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry06 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry05 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry04 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry03 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry02 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry01 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBEntry00 = + (Mk_TLBEntry (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0] + :: 117 Word.word)), + TLBXContext = + (Mk_XContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryHi = + (Mk_TLBEntryHiReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBWired = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBPageMask = ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)), + TLBContext = + (Mk_ContextReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + TLBEntryLo1 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBEntryLo0 = + (Mk_TLBEntryLoReg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0] + :: 64 Word.word)), + TLBRandom = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBIndex = ((vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)), + TLBProbe = ((vec_of_bits [B0] :: 1 Word.word)), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/cheri/Cheri_lemmas.thy b/snapshots/isabelle/cheri/Cheri_lemmas.thy new file mode 100644 index 00000000..6dbee433 --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_lemmas.thy @@ -0,0 +1,1205 @@ +theory Cheri_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Cheri +begin + +abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def instCount_ref_def CapCause_ref_def + CTLSP_ref_def CTLSU_ref_def C30_ref_def C28_ref_def C27_ref_def C26_ref_def C25_ref_def + C24_ref_def C23_ref_def C22_ref_def C21_ref_def C20_ref_def C19_ref_def C18_ref_def C17_ref_def + C16_ref_def C15_ref_def C14_ref_def C13_ref_def C12_ref_def C11_ref_def C10_ref_def C09_ref_def + C08_ref_def C07_ref_def C06_ref_def C05_ref_def C04_ref_def C03_ref_def C02_ref_def C01_ref_def + C00_ref_def inCCallDelay_ref_def nextPCC_ref_def delayedPCC_ref_def PCC_ref_def C31_ref_def + C29_ref_def UART_RVALID_ref_def UART_RDATA_ref_def UART_WRITTEN_ref_def UART_WDATA_ref_def + GPR_ref_def LO_ref_def HI_ref_def delayedPC_ref_def inBranchDelay_ref_def branchPending_ref_def + CP0Status_ref_def CP0UserLocal_ref_def CP0HWREna_ref_def CP0Count_ref_def CP0BadVAddr_ref_def + CP0LLAddr_ref_def CP0LLBit_ref_def CP0ErrorEPC_ref_def CP0EPC_ref_def CP0Cause_ref_def + CP0Compare_ref_def TLBEntry63_ref_def TLBEntry62_ref_def TLBEntry61_ref_def TLBEntry60_ref_def + TLBEntry59_ref_def TLBEntry58_ref_def TLBEntry57_ref_def TLBEntry56_ref_def TLBEntry55_ref_def + TLBEntry54_ref_def TLBEntry53_ref_def TLBEntry52_ref_def TLBEntry51_ref_def TLBEntry50_ref_def + TLBEntry49_ref_def TLBEntry48_ref_def TLBEntry47_ref_def TLBEntry46_ref_def TLBEntry45_ref_def + TLBEntry44_ref_def TLBEntry43_ref_def TLBEntry42_ref_def TLBEntry41_ref_def TLBEntry40_ref_def + TLBEntry39_ref_def TLBEntry38_ref_def TLBEntry37_ref_def TLBEntry36_ref_def TLBEntry35_ref_def + TLBEntry34_ref_def TLBEntry33_ref_def TLBEntry32_ref_def TLBEntry31_ref_def TLBEntry30_ref_def + TLBEntry29_ref_def TLBEntry28_ref_def TLBEntry27_ref_def TLBEntry26_ref_def TLBEntry25_ref_def + TLBEntry24_ref_def TLBEntry23_ref_def TLBEntry22_ref_def TLBEntry21_ref_def TLBEntry20_ref_def + TLBEntry19_ref_def TLBEntry18_ref_def TLBEntry17_ref_def TLBEntry16_ref_def TLBEntry15_ref_def + TLBEntry14_ref_def TLBEntry13_ref_def TLBEntry12_ref_def TLBEntry11_ref_def TLBEntry10_ref_def + TLBEntry09_ref_def TLBEntry08_ref_def TLBEntry07_ref_def TLBEntry06_ref_def TLBEntry05_ref_def + TLBEntry04_ref_def TLBEntry03_ref_def TLBEntry02_ref_def TLBEntry01_ref_def TLBEntry00_ref_def + TLBXContext_ref_def TLBEntryHi_ref_def TLBWired_ref_def TLBPageMask_ref_def TLBContext_ref_def + TLBEntryLo1_ref_def TLBEntryLo0_ref_def TLBRandom_ref_def TLBIndex_ref_def TLBProbe_ref_def + nextPC_ref_def PC_ref_def + +lemma regval_CapCauseReg[simp]: + "CapCauseReg_of_regval (regval_of_CapCauseReg v) = Some v" + by (auto simp: regval_of_CapCauseReg_def) + +lemma regval_CauseReg[simp]: + "CauseReg_of_regval (regval_of_CauseReg v) = Some v" + by (auto simp: regval_of_CauseReg_def) + +lemma regval_ContextReg[simp]: + "ContextReg_of_regval (regval_of_ContextReg v) = Some v" + by (auto simp: regval_of_ContextReg_def) + +lemma regval_StatusReg[simp]: + "StatusReg_of_regval (regval_of_StatusReg v) = Some v" + by (auto simp: regval_of_StatusReg_def) + +lemma regval_TLBEntry[simp]: + "TLBEntry_of_regval (regval_of_TLBEntry v) = Some v" + by (auto simp: regval_of_TLBEntry_def) + +lemma regval_TLBEntryHiReg[simp]: + "TLBEntryHiReg_of_regval (regval_of_TLBEntryHiReg v) = Some v" + by (auto simp: regval_of_TLBEntryHiReg_def) + +lemma regval_TLBEntryLoReg[simp]: + "TLBEntryLoReg_of_regval (regval_of_TLBEntryLoReg v) = Some v" + by (auto simp: regval_of_TLBEntryLoReg_def) + +lemma regval_XContextReg[simp]: + "XContextReg_of_regval (regval_of_XContextReg v) = Some v" + by (auto simp: regval_of_XContextReg_def) + +lemma regval_int[simp]: + "int_of_regval (regval_of_int v) = Some v" + by (auto simp: regval_of_int_def) + +lemma regval_vector_16_dec_bit[simp]: + "vector_16_dec_bit_of_regval (regval_of_vector_16_dec_bit v) = Some v" + by (auto simp: regval_of_vector_16_dec_bit_def) + +lemma regval_vector_1_dec_bit[simp]: + "vector_1_dec_bit_of_regval (regval_of_vector_1_dec_bit v) = Some v" + by (auto simp: regval_of_vector_1_dec_bit_def) + +lemma regval_vector_257_dec_bit[simp]: + "vector_257_dec_bit_of_regval (regval_of_vector_257_dec_bit v) = Some v" + by (auto simp: regval_of_vector_257_dec_bit_def) + +lemma regval_vector_32_dec_bit[simp]: + "vector_32_dec_bit_of_regval (regval_of_vector_32_dec_bit v) = Some v" + by (auto simp: regval_of_vector_32_dec_bit_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma regval_vector_6_dec_bit[simp]: + "vector_6_dec_bit_of_regval (regval_of_vector_6_dec_bit v) = Some v" + by (auto simp: regval_of_vector_6_dec_bit_def) + +lemma regval_vector_8_dec_bit[simp]: + "vector_8_dec_bit_of_regval (regval_of_vector_8_dec_bit v) = Some v" + by (auto simp: regval_of_vector_8_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_instCount[simp]: + "liftS (read_reg instCount_ref) = readS (instCount \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_instCount[simp]: + "liftS (write_reg instCount_ref v) = updateS (regstate_update (instCount_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CapCause[simp]: + "liftS (read_reg CapCause_ref) = readS (CapCause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CapCause[simp]: + "liftS (write_reg CapCause_ref v) = updateS (regstate_update (CapCause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSP[simp]: + "liftS (read_reg CTLSP_ref) = readS (CTLSP \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSP[simp]: + "liftS (write_reg CTLSP_ref v) = updateS (regstate_update (CTLSP_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CTLSU[simp]: + "liftS (read_reg CTLSU_ref) = readS (CTLSU \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CTLSU[simp]: + "liftS (write_reg CTLSU_ref v) = updateS (regstate_update (CTLSU_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C30[simp]: + "liftS (read_reg C30_ref) = readS (C30 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C30[simp]: + "liftS (write_reg C30_ref v) = updateS (regstate_update (C30_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C28[simp]: + "liftS (read_reg C28_ref) = readS (C28 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C28[simp]: + "liftS (write_reg C28_ref v) = updateS (regstate_update (C28_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C27[simp]: + "liftS (read_reg C27_ref) = readS (C27 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C27[simp]: + "liftS (write_reg C27_ref v) = updateS (regstate_update (C27_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C26[simp]: + "liftS (read_reg C26_ref) = readS (C26 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C26[simp]: + "liftS (write_reg C26_ref v) = updateS (regstate_update (C26_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C25[simp]: + "liftS (read_reg C25_ref) = readS (C25 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C25[simp]: + "liftS (write_reg C25_ref v) = updateS (regstate_update (C25_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C24[simp]: + "liftS (read_reg C24_ref) = readS (C24 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C24[simp]: + "liftS (write_reg C24_ref v) = updateS (regstate_update (C24_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C23[simp]: + "liftS (read_reg C23_ref) = readS (C23 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C23[simp]: + "liftS (write_reg C23_ref v) = updateS (regstate_update (C23_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C22[simp]: + "liftS (read_reg C22_ref) = readS (C22 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C22[simp]: + "liftS (write_reg C22_ref v) = updateS (regstate_update (C22_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C21[simp]: + "liftS (read_reg C21_ref) = readS (C21 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C21[simp]: + "liftS (write_reg C21_ref v) = updateS (regstate_update (C21_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C20[simp]: + "liftS (read_reg C20_ref) = readS (C20 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C20[simp]: + "liftS (write_reg C20_ref v) = updateS (regstate_update (C20_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C19[simp]: + "liftS (read_reg C19_ref) = readS (C19 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C19[simp]: + "liftS (write_reg C19_ref v) = updateS (regstate_update (C19_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C18[simp]: + "liftS (read_reg C18_ref) = readS (C18 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C18[simp]: + "liftS (write_reg C18_ref v) = updateS (regstate_update (C18_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C17[simp]: + "liftS (read_reg C17_ref) = readS (C17 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C17[simp]: + "liftS (write_reg C17_ref v) = updateS (regstate_update (C17_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C16[simp]: + "liftS (read_reg C16_ref) = readS (C16 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C16[simp]: + "liftS (write_reg C16_ref v) = updateS (regstate_update (C16_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C15[simp]: + "liftS (read_reg C15_ref) = readS (C15 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C15[simp]: + "liftS (write_reg C15_ref v) = updateS (regstate_update (C15_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C14[simp]: + "liftS (read_reg C14_ref) = readS (C14 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C14[simp]: + "liftS (write_reg C14_ref v) = updateS (regstate_update (C14_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C13[simp]: + "liftS (read_reg C13_ref) = readS (C13 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C13[simp]: + "liftS (write_reg C13_ref v) = updateS (regstate_update (C13_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C12[simp]: + "liftS (read_reg C12_ref) = readS (C12 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C12[simp]: + "liftS (write_reg C12_ref v) = updateS (regstate_update (C12_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C11[simp]: + "liftS (read_reg C11_ref) = readS (C11 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C11[simp]: + "liftS (write_reg C11_ref v) = updateS (regstate_update (C11_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C10[simp]: + "liftS (read_reg C10_ref) = readS (C10 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C10[simp]: + "liftS (write_reg C10_ref v) = updateS (regstate_update (C10_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C09[simp]: + "liftS (read_reg C09_ref) = readS (C09 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C09[simp]: + "liftS (write_reg C09_ref v) = updateS (regstate_update (C09_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C08[simp]: + "liftS (read_reg C08_ref) = readS (C08 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C08[simp]: + "liftS (write_reg C08_ref v) = updateS (regstate_update (C08_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C07[simp]: + "liftS (read_reg C07_ref) = readS (C07 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C07[simp]: + "liftS (write_reg C07_ref v) = updateS (regstate_update (C07_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C06[simp]: + "liftS (read_reg C06_ref) = readS (C06 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C06[simp]: + "liftS (write_reg C06_ref v) = updateS (regstate_update (C06_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C05[simp]: + "liftS (read_reg C05_ref) = readS (C05 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C05[simp]: + "liftS (write_reg C05_ref v) = updateS (regstate_update (C05_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C04[simp]: + "liftS (read_reg C04_ref) = readS (C04 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C04[simp]: + "liftS (write_reg C04_ref v) = updateS (regstate_update (C04_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C03[simp]: + "liftS (read_reg C03_ref) = readS (C03 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C03[simp]: + "liftS (write_reg C03_ref v) = updateS (regstate_update (C03_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C02[simp]: + "liftS (read_reg C02_ref) = readS (C02 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C02[simp]: + "liftS (write_reg C02_ref v) = updateS (regstate_update (C02_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C01[simp]: + "liftS (read_reg C01_ref) = readS (C01 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C01[simp]: + "liftS (write_reg C01_ref v) = updateS (regstate_update (C01_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C00[simp]: + "liftS (read_reg C00_ref) = readS (C00 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C00[simp]: + "liftS (write_reg C00_ref v) = updateS (regstate_update (C00_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inCCallDelay[simp]: + "liftS (read_reg inCCallDelay_ref) = readS (inCCallDelay \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inCCallDelay[simp]: + "liftS (write_reg inCCallDelay_ref v) = updateS (regstate_update (inCCallDelay_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPCC[simp]: + "liftS (read_reg nextPCC_ref) = readS (nextPCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPCC[simp]: + "liftS (write_reg nextPCC_ref v) = updateS (regstate_update (nextPCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPCC[simp]: + "liftS (read_reg delayedPCC_ref) = readS (delayedPCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPCC[simp]: + "liftS (write_reg delayedPCC_ref v) = updateS (regstate_update (delayedPCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PCC[simp]: + "liftS (read_reg PCC_ref) = readS (PCC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PCC[simp]: + "liftS (write_reg PCC_ref v) = updateS (regstate_update (PCC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C31[simp]: + "liftS (read_reg C31_ref) = readS (C31 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C31[simp]: + "liftS (write_reg C31_ref v) = updateS (regstate_update (C31_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_C29[simp]: + "liftS (read_reg C29_ref) = readS (C29 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_C29[simp]: + "liftS (write_reg C29_ref v) = updateS (regstate_update (C29_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RVALID[simp]: + "liftS (read_reg UART_RVALID_ref) = readS (UART_RVALID \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RVALID[simp]: + "liftS (write_reg UART_RVALID_ref v) = updateS (regstate_update (UART_RVALID_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_RDATA[simp]: + "liftS (read_reg UART_RDATA_ref) = readS (UART_RDATA \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_RDATA[simp]: + "liftS (write_reg UART_RDATA_ref v) = updateS (regstate_update (UART_RDATA_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WRITTEN[simp]: + "liftS (read_reg UART_WRITTEN_ref) = readS (UART_WRITTEN \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WRITTEN[simp]: + "liftS (write_reg UART_WRITTEN_ref v) = updateS (regstate_update (UART_WRITTEN_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_UART_WDATA[simp]: + "liftS (read_reg UART_WDATA_ref) = readS (UART_WDATA \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_UART_WDATA[simp]: + "liftS (write_reg UART_WDATA_ref v) = updateS (regstate_update (UART_WDATA_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_GPR[simp]: + "liftS (read_reg GPR_ref) = readS (GPR \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_GPR[simp]: + "liftS (write_reg GPR_ref v) = updateS (regstate_update (GPR_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_LO[simp]: + "liftS (read_reg LO_ref) = readS (LO \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_LO[simp]: + "liftS (write_reg LO_ref v) = updateS (regstate_update (LO_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_HI[simp]: + "liftS (read_reg HI_ref) = readS (HI \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_HI[simp]: + "liftS (write_reg HI_ref v) = updateS (regstate_update (HI_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_delayedPC[simp]: + "liftS (read_reg delayedPC_ref) = readS (delayedPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_delayedPC[simp]: + "liftS (write_reg delayedPC_ref v) = updateS (regstate_update (delayedPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_inBranchDelay[simp]: + "liftS (read_reg inBranchDelay_ref) = readS (inBranchDelay \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_inBranchDelay[simp]: + "liftS (write_reg inBranchDelay_ref v) = updateS (regstate_update (inBranchDelay_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_branchPending[simp]: + "liftS (read_reg branchPending_ref) = readS (branchPending \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_branchPending[simp]: + "liftS (write_reg branchPending_ref v) = updateS (regstate_update (branchPending_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Status[simp]: + "liftS (read_reg CP0Status_ref) = readS (CP0Status \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Status[simp]: + "liftS (write_reg CP0Status_ref v) = updateS (regstate_update (CP0Status_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0UserLocal[simp]: + "liftS (read_reg CP0UserLocal_ref) = readS (CP0UserLocal \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0UserLocal[simp]: + "liftS (write_reg CP0UserLocal_ref v) = updateS (regstate_update (CP0UserLocal_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0HWREna[simp]: + "liftS (read_reg CP0HWREna_ref) = readS (CP0HWREna \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0HWREna[simp]: + "liftS (write_reg CP0HWREna_ref v) = updateS (regstate_update (CP0HWREna_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Count[simp]: + "liftS (read_reg CP0Count_ref) = readS (CP0Count \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Count[simp]: + "liftS (write_reg CP0Count_ref v) = updateS (regstate_update (CP0Count_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0BadVAddr[simp]: + "liftS (read_reg CP0BadVAddr_ref) = readS (CP0BadVAddr \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0BadVAddr[simp]: + "liftS (write_reg CP0BadVAddr_ref v) = updateS (regstate_update (CP0BadVAddr_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLAddr[simp]: + "liftS (read_reg CP0LLAddr_ref) = readS (CP0LLAddr \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLAddr[simp]: + "liftS (write_reg CP0LLAddr_ref v) = updateS (regstate_update (CP0LLAddr_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0LLBit[simp]: + "liftS (read_reg CP0LLBit_ref) = readS (CP0LLBit \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0LLBit[simp]: + "liftS (write_reg CP0LLBit_ref v) = updateS (regstate_update (CP0LLBit_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0ErrorEPC[simp]: + "liftS (read_reg CP0ErrorEPC_ref) = readS (CP0ErrorEPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0ErrorEPC[simp]: + "liftS (write_reg CP0ErrorEPC_ref v) = updateS (regstate_update (CP0ErrorEPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0EPC[simp]: + "liftS (read_reg CP0EPC_ref) = readS (CP0EPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0EPC[simp]: + "liftS (write_reg CP0EPC_ref v) = updateS (regstate_update (CP0EPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Cause[simp]: + "liftS (read_reg CP0Cause_ref) = readS (CP0Cause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Cause[simp]: + "liftS (write_reg CP0Cause_ref v) = updateS (regstate_update (CP0Cause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_CP0Compare[simp]: + "liftS (read_reg CP0Compare_ref) = readS (CP0Compare \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_CP0Compare[simp]: + "liftS (write_reg CP0Compare_ref v) = updateS (regstate_update (CP0Compare_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry63[simp]: + "liftS (read_reg TLBEntry63_ref) = readS (TLBEntry63 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry63[simp]: + "liftS (write_reg TLBEntry63_ref v) = updateS (regstate_update (TLBEntry63_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry62[simp]: + "liftS (read_reg TLBEntry62_ref) = readS (TLBEntry62 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry62[simp]: + "liftS (write_reg TLBEntry62_ref v) = updateS (regstate_update (TLBEntry62_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry61[simp]: + "liftS (read_reg TLBEntry61_ref) = readS (TLBEntry61 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry61[simp]: + "liftS (write_reg TLBEntry61_ref v) = updateS (regstate_update (TLBEntry61_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry60[simp]: + "liftS (read_reg TLBEntry60_ref) = readS (TLBEntry60 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry60[simp]: + "liftS (write_reg TLBEntry60_ref v) = updateS (regstate_update (TLBEntry60_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry59[simp]: + "liftS (read_reg TLBEntry59_ref) = readS (TLBEntry59 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry59[simp]: + "liftS (write_reg TLBEntry59_ref v) = updateS (regstate_update (TLBEntry59_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry58[simp]: + "liftS (read_reg TLBEntry58_ref) = readS (TLBEntry58 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry58[simp]: + "liftS (write_reg TLBEntry58_ref v) = updateS (regstate_update (TLBEntry58_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry57[simp]: + "liftS (read_reg TLBEntry57_ref) = readS (TLBEntry57 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry57[simp]: + "liftS (write_reg TLBEntry57_ref v) = updateS (regstate_update (TLBEntry57_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry56[simp]: + "liftS (read_reg TLBEntry56_ref) = readS (TLBEntry56 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry56[simp]: + "liftS (write_reg TLBEntry56_ref v) = updateS (regstate_update (TLBEntry56_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry55[simp]: + "liftS (read_reg TLBEntry55_ref) = readS (TLBEntry55 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry55[simp]: + "liftS (write_reg TLBEntry55_ref v) = updateS (regstate_update (TLBEntry55_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry54[simp]: + "liftS (read_reg TLBEntry54_ref) = readS (TLBEntry54 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry54[simp]: + "liftS (write_reg TLBEntry54_ref v) = updateS (regstate_update (TLBEntry54_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry53[simp]: + "liftS (read_reg TLBEntry53_ref) = readS (TLBEntry53 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry53[simp]: + "liftS (write_reg TLBEntry53_ref v) = updateS (regstate_update (TLBEntry53_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry52[simp]: + "liftS (read_reg TLBEntry52_ref) = readS (TLBEntry52 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry52[simp]: + "liftS (write_reg TLBEntry52_ref v) = updateS (regstate_update (TLBEntry52_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry51[simp]: + "liftS (read_reg TLBEntry51_ref) = readS (TLBEntry51 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry51[simp]: + "liftS (write_reg TLBEntry51_ref v) = updateS (regstate_update (TLBEntry51_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry50[simp]: + "liftS (read_reg TLBEntry50_ref) = readS (TLBEntry50 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry50[simp]: + "liftS (write_reg TLBEntry50_ref v) = updateS (regstate_update (TLBEntry50_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry49[simp]: + "liftS (read_reg TLBEntry49_ref) = readS (TLBEntry49 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry49[simp]: + "liftS (write_reg TLBEntry49_ref v) = updateS (regstate_update (TLBEntry49_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry48[simp]: + "liftS (read_reg TLBEntry48_ref) = readS (TLBEntry48 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry48[simp]: + "liftS (write_reg TLBEntry48_ref v) = updateS (regstate_update (TLBEntry48_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry47[simp]: + "liftS (read_reg TLBEntry47_ref) = readS (TLBEntry47 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry47[simp]: + "liftS (write_reg TLBEntry47_ref v) = updateS (regstate_update (TLBEntry47_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry46[simp]: + "liftS (read_reg TLBEntry46_ref) = readS (TLBEntry46 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry46[simp]: + "liftS (write_reg TLBEntry46_ref v) = updateS (regstate_update (TLBEntry46_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry45[simp]: + "liftS (read_reg TLBEntry45_ref) = readS (TLBEntry45 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry45[simp]: + "liftS (write_reg TLBEntry45_ref v) = updateS (regstate_update (TLBEntry45_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry44[simp]: + "liftS (read_reg TLBEntry44_ref) = readS (TLBEntry44 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry44[simp]: + "liftS (write_reg TLBEntry44_ref v) = updateS (regstate_update (TLBEntry44_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry43[simp]: + "liftS (read_reg TLBEntry43_ref) = readS (TLBEntry43 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry43[simp]: + "liftS (write_reg TLBEntry43_ref v) = updateS (regstate_update (TLBEntry43_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry42[simp]: + "liftS (read_reg TLBEntry42_ref) = readS (TLBEntry42 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry42[simp]: + "liftS (write_reg TLBEntry42_ref v) = updateS (regstate_update (TLBEntry42_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry41[simp]: + "liftS (read_reg TLBEntry41_ref) = readS (TLBEntry41 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry41[simp]: + "liftS (write_reg TLBEntry41_ref v) = updateS (regstate_update (TLBEntry41_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry40[simp]: + "liftS (read_reg TLBEntry40_ref) = readS (TLBEntry40 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry40[simp]: + "liftS (write_reg TLBEntry40_ref v) = updateS (regstate_update (TLBEntry40_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry39[simp]: + "liftS (read_reg TLBEntry39_ref) = readS (TLBEntry39 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry39[simp]: + "liftS (write_reg TLBEntry39_ref v) = updateS (regstate_update (TLBEntry39_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry38[simp]: + "liftS (read_reg TLBEntry38_ref) = readS (TLBEntry38 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry38[simp]: + "liftS (write_reg TLBEntry38_ref v) = updateS (regstate_update (TLBEntry38_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry37[simp]: + "liftS (read_reg TLBEntry37_ref) = readS (TLBEntry37 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry37[simp]: + "liftS (write_reg TLBEntry37_ref v) = updateS (regstate_update (TLBEntry37_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry36[simp]: + "liftS (read_reg TLBEntry36_ref) = readS (TLBEntry36 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry36[simp]: + "liftS (write_reg TLBEntry36_ref v) = updateS (regstate_update (TLBEntry36_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry35[simp]: + "liftS (read_reg TLBEntry35_ref) = readS (TLBEntry35 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry35[simp]: + "liftS (write_reg TLBEntry35_ref v) = updateS (regstate_update (TLBEntry35_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry34[simp]: + "liftS (read_reg TLBEntry34_ref) = readS (TLBEntry34 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry34[simp]: + "liftS (write_reg TLBEntry34_ref v) = updateS (regstate_update (TLBEntry34_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry33[simp]: + "liftS (read_reg TLBEntry33_ref) = readS (TLBEntry33 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry33[simp]: + "liftS (write_reg TLBEntry33_ref v) = updateS (regstate_update (TLBEntry33_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry32[simp]: + "liftS (read_reg TLBEntry32_ref) = readS (TLBEntry32 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry32[simp]: + "liftS (write_reg TLBEntry32_ref v) = updateS (regstate_update (TLBEntry32_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry31[simp]: + "liftS (read_reg TLBEntry31_ref) = readS (TLBEntry31 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry31[simp]: + "liftS (write_reg TLBEntry31_ref v) = updateS (regstate_update (TLBEntry31_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry30[simp]: + "liftS (read_reg TLBEntry30_ref) = readS (TLBEntry30 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry30[simp]: + "liftS (write_reg TLBEntry30_ref v) = updateS (regstate_update (TLBEntry30_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry29[simp]: + "liftS (read_reg TLBEntry29_ref) = readS (TLBEntry29 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry29[simp]: + "liftS (write_reg TLBEntry29_ref v) = updateS (regstate_update (TLBEntry29_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry28[simp]: + "liftS (read_reg TLBEntry28_ref) = readS (TLBEntry28 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry28[simp]: + "liftS (write_reg TLBEntry28_ref v) = updateS (regstate_update (TLBEntry28_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry27[simp]: + "liftS (read_reg TLBEntry27_ref) = readS (TLBEntry27 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry27[simp]: + "liftS (write_reg TLBEntry27_ref v) = updateS (regstate_update (TLBEntry27_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry26[simp]: + "liftS (read_reg TLBEntry26_ref) = readS (TLBEntry26 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry26[simp]: + "liftS (write_reg TLBEntry26_ref v) = updateS (regstate_update (TLBEntry26_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry25[simp]: + "liftS (read_reg TLBEntry25_ref) = readS (TLBEntry25 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry25[simp]: + "liftS (write_reg TLBEntry25_ref v) = updateS (regstate_update (TLBEntry25_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry24[simp]: + "liftS (read_reg TLBEntry24_ref) = readS (TLBEntry24 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry24[simp]: + "liftS (write_reg TLBEntry24_ref v) = updateS (regstate_update (TLBEntry24_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry23[simp]: + "liftS (read_reg TLBEntry23_ref) = readS (TLBEntry23 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry23[simp]: + "liftS (write_reg TLBEntry23_ref v) = updateS (regstate_update (TLBEntry23_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry22[simp]: + "liftS (read_reg TLBEntry22_ref) = readS (TLBEntry22 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry22[simp]: + "liftS (write_reg TLBEntry22_ref v) = updateS (regstate_update (TLBEntry22_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry21[simp]: + "liftS (read_reg TLBEntry21_ref) = readS (TLBEntry21 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry21[simp]: + "liftS (write_reg TLBEntry21_ref v) = updateS (regstate_update (TLBEntry21_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry20[simp]: + "liftS (read_reg TLBEntry20_ref) = readS (TLBEntry20 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry20[simp]: + "liftS (write_reg TLBEntry20_ref v) = updateS (regstate_update (TLBEntry20_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry19[simp]: + "liftS (read_reg TLBEntry19_ref) = readS (TLBEntry19 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry19[simp]: + "liftS (write_reg TLBEntry19_ref v) = updateS (regstate_update (TLBEntry19_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry18[simp]: + "liftS (read_reg TLBEntry18_ref) = readS (TLBEntry18 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry18[simp]: + "liftS (write_reg TLBEntry18_ref v) = updateS (regstate_update (TLBEntry18_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry17[simp]: + "liftS (read_reg TLBEntry17_ref) = readS (TLBEntry17 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry17[simp]: + "liftS (write_reg TLBEntry17_ref v) = updateS (regstate_update (TLBEntry17_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry16[simp]: + "liftS (read_reg TLBEntry16_ref) = readS (TLBEntry16 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry16[simp]: + "liftS (write_reg TLBEntry16_ref v) = updateS (regstate_update (TLBEntry16_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry15[simp]: + "liftS (read_reg TLBEntry15_ref) = readS (TLBEntry15 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry15[simp]: + "liftS (write_reg TLBEntry15_ref v) = updateS (regstate_update (TLBEntry15_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry14[simp]: + "liftS (read_reg TLBEntry14_ref) = readS (TLBEntry14 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry14[simp]: + "liftS (write_reg TLBEntry14_ref v) = updateS (regstate_update (TLBEntry14_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry13[simp]: + "liftS (read_reg TLBEntry13_ref) = readS (TLBEntry13 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry13[simp]: + "liftS (write_reg TLBEntry13_ref v) = updateS (regstate_update (TLBEntry13_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry12[simp]: + "liftS (read_reg TLBEntry12_ref) = readS (TLBEntry12 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry12[simp]: + "liftS (write_reg TLBEntry12_ref v) = updateS (regstate_update (TLBEntry12_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry11[simp]: + "liftS (read_reg TLBEntry11_ref) = readS (TLBEntry11 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry11[simp]: + "liftS (write_reg TLBEntry11_ref v) = updateS (regstate_update (TLBEntry11_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry10[simp]: + "liftS (read_reg TLBEntry10_ref) = readS (TLBEntry10 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry10[simp]: + "liftS (write_reg TLBEntry10_ref v) = updateS (regstate_update (TLBEntry10_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry09[simp]: + "liftS (read_reg TLBEntry09_ref) = readS (TLBEntry09 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry09[simp]: + "liftS (write_reg TLBEntry09_ref v) = updateS (regstate_update (TLBEntry09_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry08[simp]: + "liftS (read_reg TLBEntry08_ref) = readS (TLBEntry08 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry08[simp]: + "liftS (write_reg TLBEntry08_ref v) = updateS (regstate_update (TLBEntry08_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry07[simp]: + "liftS (read_reg TLBEntry07_ref) = readS (TLBEntry07 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry07[simp]: + "liftS (write_reg TLBEntry07_ref v) = updateS (regstate_update (TLBEntry07_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry06[simp]: + "liftS (read_reg TLBEntry06_ref) = readS (TLBEntry06 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry06[simp]: + "liftS (write_reg TLBEntry06_ref v) = updateS (regstate_update (TLBEntry06_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry05[simp]: + "liftS (read_reg TLBEntry05_ref) = readS (TLBEntry05 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry05[simp]: + "liftS (write_reg TLBEntry05_ref v) = updateS (regstate_update (TLBEntry05_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry04[simp]: + "liftS (read_reg TLBEntry04_ref) = readS (TLBEntry04 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry04[simp]: + "liftS (write_reg TLBEntry04_ref v) = updateS (regstate_update (TLBEntry04_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry03[simp]: + "liftS (read_reg TLBEntry03_ref) = readS (TLBEntry03 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry03[simp]: + "liftS (write_reg TLBEntry03_ref v) = updateS (regstate_update (TLBEntry03_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry02[simp]: + "liftS (read_reg TLBEntry02_ref) = readS (TLBEntry02 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry02[simp]: + "liftS (write_reg TLBEntry02_ref v) = updateS (regstate_update (TLBEntry02_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry01[simp]: + "liftS (read_reg TLBEntry01_ref) = readS (TLBEntry01 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry01[simp]: + "liftS (write_reg TLBEntry01_ref v) = updateS (regstate_update (TLBEntry01_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntry00[simp]: + "liftS (read_reg TLBEntry00_ref) = readS (TLBEntry00 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntry00[simp]: + "liftS (write_reg TLBEntry00_ref v) = updateS (regstate_update (TLBEntry00_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBXContext[simp]: + "liftS (read_reg TLBXContext_ref) = readS (TLBXContext \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBXContext[simp]: + "liftS (write_reg TLBXContext_ref v) = updateS (regstate_update (TLBXContext_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryHi[simp]: + "liftS (read_reg TLBEntryHi_ref) = readS (TLBEntryHi \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryHi[simp]: + "liftS (write_reg TLBEntryHi_ref v) = updateS (regstate_update (TLBEntryHi_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBWired[simp]: + "liftS (read_reg TLBWired_ref) = readS (TLBWired \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBWired[simp]: + "liftS (write_reg TLBWired_ref v) = updateS (regstate_update (TLBWired_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBPageMask[simp]: + "liftS (read_reg TLBPageMask_ref) = readS (TLBPageMask \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBPageMask[simp]: + "liftS (write_reg TLBPageMask_ref v) = updateS (regstate_update (TLBPageMask_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBContext[simp]: + "liftS (read_reg TLBContext_ref) = readS (TLBContext \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBContext[simp]: + "liftS (write_reg TLBContext_ref v) = updateS (regstate_update (TLBContext_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo1[simp]: + "liftS (read_reg TLBEntryLo1_ref) = readS (TLBEntryLo1 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo1[simp]: + "liftS (write_reg TLBEntryLo1_ref v) = updateS (regstate_update (TLBEntryLo1_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBEntryLo0[simp]: + "liftS (read_reg TLBEntryLo0_ref) = readS (TLBEntryLo0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBEntryLo0[simp]: + "liftS (write_reg TLBEntryLo0_ref v) = updateS (regstate_update (TLBEntryLo0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBRandom[simp]: + "liftS (read_reg TLBRandom_ref) = readS (TLBRandom \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBRandom[simp]: + "liftS (write_reg TLBRandom_ref v) = updateS (regstate_update (TLBRandom_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBIndex[simp]: + "liftS (read_reg TLBIndex_ref) = readS (TLBIndex \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBIndex[simp]: + "liftS (write_reg TLBIndex_ref v) = updateS (regstate_update (TLBIndex_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_TLBProbe[simp]: + "liftS (read_reg TLBProbe_ref) = readS (TLBProbe \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_TLBProbe[simp]: + "liftS (write_reg TLBProbe_ref v) = updateS (regstate_update (TLBProbe_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/cheri/Cheri_types.thy b/snapshots/isabelle/cheri/Cheri_types.thy new file mode 100644 index 00000000..4139164a --- /dev/null +++ b/snapshots/isabelle/cheri/Cheri_types.thy @@ -0,0 +1,2432 @@ +chapter \<open>Generated by Lem from cheri_types.lem.\<close> + +theory "Cheri_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from cheri.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +datatype exception = + ISAException " (unit)" + | Error_not_implemented " (string)" + | Error_misaligned_access " (unit)" + | Error_EBREAK " (unit)" + | Error_internal_error " (unit)" + + + +datatype CauseReg = Mk_CauseReg " ( 32 Word.word)" + + + +datatype CapCauseReg = Mk_CapCauseReg " ( 16 Word.word)" + + + +datatype TLBEntryLoReg = Mk_TLBEntryLoReg " ( 64 Word.word)" + + + +datatype TLBEntryHiReg = Mk_TLBEntryHiReg " ( 64 Word.word)" + + + +datatype ContextReg = Mk_ContextReg " ( 64 Word.word)" + + + +datatype XContextReg = Mk_XContextReg " ( 64 Word.word)" + + + +type_synonym TLBIndexT =" 6 bits " + +datatype TLBEntry = Mk_TLBEntry " ( 117 Word.word)" + + + +datatype StatusReg = Mk_StatusReg " ( 32 Word.word)" + + + +datatype Exception = + Interrupt + | TLBMod + | TLBL + | TLBS + | AdEL + | AdES + | Sys + | Bp + | ResI + | CpU + | Ov + | Tr + | C2E + | C2Trap + | XTLBRefillL + | XTLBRefillS + | XTLBInvL + | XTLBInvS + | MCheck + + + +type_synonym CapReg =" 257 bits " + +record CapStruct = + + CapStruct_tag ::" bool " + + CapStruct_padding ::" 8 bits " + + CapStruct_otype ::" 24 bits " + + CapStruct_uperms ::" 16 bits " + + CapStruct_perm_reserved11_14 ::" 4 bits " + + CapStruct_access_system_regs ::" bool " + + CapStruct_permit_unseal ::" bool " + + CapStruct_permit_ccall ::" bool " + + CapStruct_permit_seal ::" bool " + + CapStruct_permit_store_local_cap ::" bool " + + CapStruct_permit_store_cap ::" bool " + + CapStruct_permit_load_cap ::" bool " + + CapStruct_permit_store ::" bool " + + CapStruct_permit_load ::" bool " + + CapStruct_permit_execute ::" bool " + + CapStruct_global ::" bool " + + CapStruct_sealed ::" bool " + + CapStruct_address ::" 64 bits " + + CapStruct_base ::" 64 bits " + + CapStruct_length ::" 64 bits " + + + +datatype MemAccessType = Instruction | LoadData | StoreData + + + +datatype AccessLevel = User | Supervisor | Kernel + + + +type_synonym regno =" 5 bits " + +type_synonym imm16 =" 16 bits " + +type_synonym regregreg =" (regno * regno * regno)" + +type_synonym regregimm16 =" (regno * regno * imm16)" + +datatype decode_failure = + No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error + + + +datatype Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU + + + +datatype WordType = B | H | W | D + + + +type_synonym CapLen =" int " + +type_synonym uint64 =" int " + +datatype CPtrCmpOp = CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ + + + +datatype ClearRegSet = GPLo | GPHi | CLo | CHi + + + +datatype (plugins only: size) ast = + DADDIU " ((regno * regno * imm16))" + | DADDU " ((regno * regno * regno))" + | DADDI " ((regno * regno * 16 bits))" + | DADD " ((regno * regno * regno))" + | ADD " ((regno * regno * regno))" + | ADDI " ((regno * regno * 16 bits))" + | ADDU " ((regno * regno * regno))" + | ADDIU " ((regno * regno * 16 bits))" + | DSUBU " ((regno * regno * regno))" + | DSUB " ((regno * regno * regno))" + | SUB " ((regno * regno * regno))" + | SUBU " ((regno * regno * regno))" + | AND0 " ((regno * regno * regno))" + | ANDI " ((regno * regno * 16 bits))" + | OR0 " ((regno * regno * regno))" + | ORI " ((regno * regno * 16 bits))" + | NOR " ((regno * regno * regno))" + | XOR0 " ((regno * regno * regno))" + | XORI " ((regno * regno * 16 bits))" + | LUI " ((regno * imm16))" + | DSLL " ((regno * regno * regno))" + | DSLL32 " ((regno * regno * regno))" + | DSLLV " ((regno * regno * regno))" + | DSRA " ((regno * regno * regno))" + | DSRA32 " ((regno * regno * regno))" + | DSRAV " ((regno * regno * regno))" + | DSRL " ((regno * regno * regno))" + | DSRL32 " ((regno * regno * regno))" + | DSRLV " ((regno * regno * regno))" + | SLL " ((regno * regno * regno))" + | SLLV " ((regno * regno * regno))" + | SRA " ((regno * regno * regno))" + | SRAV " ((regno * regno * regno))" + | SRL " ((regno * regno * regno))" + | SRLV " ((regno * regno * regno))" + | SLT " ((regno * regno * regno))" + | SLTI " ((regno * regno * 16 bits))" + | SLTU " ((regno * regno * regno))" + | SLTIU " ((regno * regno * 16 bits))" + | MOVN " ((regno * regno * regno))" + | MOVZ " ((regno * regno * regno))" + | MFHI " (regno)" + | MFLO " (regno)" + | MTHI " (regno)" + | MTLO " (regno)" + | MUL " ((regno * regno * regno))" + | MULT " ((regno * regno))" + | MULTU " ((regno * regno))" + | DMULT " ((regno * regno))" + | DMULTU " ((regno * regno))" + | MADD " ((regno * regno))" + | MADDU " ((regno * regno))" + | MSUB " ((regno * regno))" + | MSUBU " ((regno * regno))" + | DIV " ((regno * regno))" + | DIVU " ((regno * regno))" + | DDIV " ((regno * regno))" + | DDIVU " ((regno * regno))" + | J " ( 26 bits)" + | JAL " ( 26 bits)" + | JR " (regno)" + | JALR " ((regno * regno))" + | BEQ " ((regno * regno * imm16 * bool * bool))" + | BCMPZ " ((regno * imm16 * Comparison * bool * bool))" + | SYSCALL_THREAD_START " (unit)" + | ImplementationDefinedStopFetching " (unit)" + | SYSCALL " (unit)" + | BREAK " (unit)" + | WAIT " (unit)" + | TRAPREG " ((regno * regno * Comparison))" + | TRAPIMM " ((regno * imm16 * Comparison))" + | Load " ((WordType * bool * bool * regno * regno * imm16))" + | Store " ((WordType * bool * regno * regno * imm16))" + | LWL " ((regno * regno * 16 bits))" + | LWR " ((regno * regno * 16 bits))" + | SWL " ((regno * regno * 16 bits))" + | SWR " ((regno * regno * 16 bits))" + | LDL " ((regno * regno * 16 bits))" + | LDR " ((regno * regno * 16 bits))" + | SDL " ((regno * regno * 16 bits))" + | SDR " ((regno * regno * 16 bits))" + | CACHE " ((regno * regno * 16 bits))" + | PREF " ((regno * regno * 16 bits))" + | SYNC " (unit)" + | MFC0 " ((regno * regno * 3 bits * bool))" + | HCF " (unit)" + | MTC0 " ((regno * regno * 3 bits * bool))" + | TLBWI " (unit)" + | TLBWR " (unit)" + | TLBR " (unit)" + | TLBP " (unit)" + | RDHWR " ((regno * regno))" + | ERET " (unit)" + | CGetPerm " ((regno * regno))" + | CGetType " ((regno * regno))" + | CGetBase " ((regno * regno))" + | CGetLen " ((regno * regno))" + | CGetTag " ((regno * regno))" + | CGetSealed " ((regno * regno))" + | CGetOffset " ((regno * regno))" + | CGetAddr " ((regno * regno))" + | CGetPCC " (regno)" + | CGetPCCSetOffset " ((regno * regno))" + | CGetCause " (regno)" + | CSetCause " (regno)" + | CReadHwr " ((regno * regno))" + | CWriteHwr " ((regno * regno))" + | CAndPerm " ((regno * regno * regno))" + | CToPtr " ((regno * regno * regno))" + | CSub " ((regno * regno * regno))" + | CPtrCmp " ((regno * regno * regno * CPtrCmpOp))" + | CIncOffset " ((regno * regno * regno))" + | CIncOffsetImmediate " ((regno * regno * 11 bits))" + | CSetOffset " ((regno * regno * regno))" + | CSetBounds " ((regno * regno * regno))" + | CSetBoundsImmediate " ((regno * regno * 11 bits))" + | CSetBoundsExact " ((regno * regno * regno))" + | CClearTag " ((regno * regno))" + | CMOVX " ((regno * regno * regno * bool))" + | ClearRegs " ((ClearRegSet * 16 bits))" + | CFromPtr " ((regno * regno * regno))" + | CBuildCap " ((regno * regno * regno))" + | CCopyType " ((regno * regno * regno))" + | CCheckPerm " ((regno * regno))" + | CCheckType " ((regno * regno))" + | CTestSubset " ((regno * regno * regno))" + | CSeal " ((regno * regno * regno))" + | CCSeal " ((regno * regno * regno))" + | CUnseal " ((regno * regno * regno))" + | CCall " ((regno * regno * 11 bits))" + | CReturn " (unit)" + | CBX " ((regno * 16 bits * bool))" + | CBZ " ((regno * 16 bits * bool))" + | CJALR " ((regno * regno * bool))" + | CLoad " ((regno * regno * regno * 8 bits * bool * WordType * bool))" + | CStore " ((regno * regno * regno * regno * 8 bits * WordType * bool))" + | CSC " ((regno * regno * regno * regno * 11 bits * bool))" + | CLC " ((regno * regno * regno * 11 bits * bool))" + | C2Dump " (regno)" + | RI " (unit)" + + + +datatype CapEx = + CapEx_None + | CapEx_LengthViolation + | CapEx_TagViolation + | CapEx_SealViolation + | CapEx_TypeViolation + | CapEx_CallTrap + | CapEx_ReturnTrap + | CapEx_TSSUnderFlow + | CapEx_UserDefViolation + | CapEx_TLBNoStoreCap + | CapEx_InexactBounds + | CapEx_GlobalViolation + | CapEx_PermitExecuteViolation + | CapEx_PermitLoadViolation + | CapEx_PermitStoreViolation + | CapEx_PermitLoadCapViolation + | CapEx_PermitStoreCapViolation + | CapEx_PermitStoreLocalCapViolation + | CapEx_PermitSealViolation + | CapEx_AccessSystemRegsViolation + | CapEx_PermitCCallViolation + | CapEx_AccessCCallIDCViolation + | CapEx_PermitUnsealViolation + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_CapCauseReg " (CapCauseReg)" + | Regval_CauseReg " (CauseReg)" + | Regval_ContextReg " (ContextReg)" + | Regval_StatusReg " (StatusReg)" + | Regval_TLBEntry " (TLBEntry)" + | Regval_TLBEntryHiReg " (TLBEntryHiReg)" + | Regval_TLBEntryLoReg " (TLBEntryLoReg)" + | Regval_XContextReg " (XContextReg)" + | Regval_int " (ii)" + | Regval_vector_16_dec_bit " ( 16 Word.word)" + | Regval_vector_1_dec_bit " ( 1 Word.word)" + | Regval_vector_257_dec_bit " ( 257 Word.word)" + | Regval_vector_32_dec_bit " ( 32 Word.word)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + | Regval_vector_6_dec_bit " ( 6 Word.word)" + | Regval_vector_8_dec_bit " ( 8 Word.word)" + + + +record regstate = + + instCount ::" ii " + + CapCause ::" CapCauseReg " + + CTLSP ::" 257 Word.word " + + CTLSU ::" 257 Word.word " + + C31 ::" 257 Word.word " + + C30 ::" 257 Word.word " + + C29 ::" 257 Word.word " + + C28 ::" 257 Word.word " + + C27 ::" 257 Word.word " + + C26 ::" 257 Word.word " + + C25 ::" 257 Word.word " + + C24 ::" 257 Word.word " + + C23 ::" 257 Word.word " + + C22 ::" 257 Word.word " + + C21 ::" 257 Word.word " + + C20 ::" 257 Word.word " + + C19 ::" 257 Word.word " + + C18 ::" 257 Word.word " + + C17 ::" 257 Word.word " + + C16 ::" 257 Word.word " + + C15 ::" 257 Word.word " + + C14 ::" 257 Word.word " + + C13 ::" 257 Word.word " + + C12 ::" 257 Word.word " + + C11 ::" 257 Word.word " + + C10 ::" 257 Word.word " + + C09 ::" 257 Word.word " + + C08 ::" 257 Word.word " + + C07 ::" 257 Word.word " + + C06 ::" 257 Word.word " + + C05 ::" 257 Word.word " + + C04 ::" 257 Word.word " + + C03 ::" 257 Word.word " + + C02 ::" 257 Word.word " + + C01 ::" 257 Word.word " + + C00 ::" 257 Word.word " + + inCCallDelay ::" 1 Word.word " + + delayedPCC ::" 257 Word.word " + + nextPCC ::" 257 Word.word " + + PCC ::" 257 Word.word " + + UART_RVALID ::" 1 Word.word " + + UART_RDATA ::" 8 Word.word " + + UART_WRITTEN ::" 1 Word.word " + + UART_WDATA ::" 8 Word.word " + + GPR ::" ( 64 Word.word) list " + + LO ::" 64 Word.word " + + HI ::" 64 Word.word " + + delayedPC ::" 64 Word.word " + + inBranchDelay ::" 1 Word.word " + + branchPending ::" 1 Word.word " + + CP0Status ::" StatusReg " + + CP0UserLocal ::" 64 Word.word " + + CP0HWREna ::" 32 Word.word " + + CP0Count ::" 32 Word.word " + + CP0BadVAddr ::" 64 Word.word " + + CP0LLAddr ::" 64 Word.word " + + CP0LLBit ::" 1 Word.word " + + CP0ErrorEPC ::" 64 Word.word " + + CP0EPC ::" 64 Word.word " + + CP0Cause ::" CauseReg " + + CP0Compare ::" 32 Word.word " + + TLBEntry63 ::" TLBEntry " + + TLBEntry62 ::" TLBEntry " + + TLBEntry61 ::" TLBEntry " + + TLBEntry60 ::" TLBEntry " + + TLBEntry59 ::" TLBEntry " + + TLBEntry58 ::" TLBEntry " + + TLBEntry57 ::" TLBEntry " + + TLBEntry56 ::" TLBEntry " + + TLBEntry55 ::" TLBEntry " + + TLBEntry54 ::" TLBEntry " + + TLBEntry53 ::" TLBEntry " + + TLBEntry52 ::" TLBEntry " + + TLBEntry51 ::" TLBEntry " + + TLBEntry50 ::" TLBEntry " + + TLBEntry49 ::" TLBEntry " + + TLBEntry48 ::" TLBEntry " + + TLBEntry47 ::" TLBEntry " + + TLBEntry46 ::" TLBEntry " + + TLBEntry45 ::" TLBEntry " + + TLBEntry44 ::" TLBEntry " + + TLBEntry43 ::" TLBEntry " + + TLBEntry42 ::" TLBEntry " + + TLBEntry41 ::" TLBEntry " + + TLBEntry40 ::" TLBEntry " + + TLBEntry39 ::" TLBEntry " + + TLBEntry38 ::" TLBEntry " + + TLBEntry37 ::" TLBEntry " + + TLBEntry36 ::" TLBEntry " + + TLBEntry35 ::" TLBEntry " + + TLBEntry34 ::" TLBEntry " + + TLBEntry33 ::" TLBEntry " + + TLBEntry32 ::" TLBEntry " + + TLBEntry31 ::" TLBEntry " + + TLBEntry30 ::" TLBEntry " + + TLBEntry29 ::" TLBEntry " + + TLBEntry28 ::" TLBEntry " + + TLBEntry27 ::" TLBEntry " + + TLBEntry26 ::" TLBEntry " + + TLBEntry25 ::" TLBEntry " + + TLBEntry24 ::" TLBEntry " + + TLBEntry23 ::" TLBEntry " + + TLBEntry22 ::" TLBEntry " + + TLBEntry21 ::" TLBEntry " + + TLBEntry20 ::" TLBEntry " + + TLBEntry19 ::" TLBEntry " + + TLBEntry18 ::" TLBEntry " + + TLBEntry17 ::" TLBEntry " + + TLBEntry16 ::" TLBEntry " + + TLBEntry15 ::" TLBEntry " + + TLBEntry14 ::" TLBEntry " + + TLBEntry13 ::" TLBEntry " + + TLBEntry12 ::" TLBEntry " + + TLBEntry11 ::" TLBEntry " + + TLBEntry10 ::" TLBEntry " + + TLBEntry09 ::" TLBEntry " + + TLBEntry08 ::" TLBEntry " + + TLBEntry07 ::" TLBEntry " + + TLBEntry06 ::" TLBEntry " + + TLBEntry05 ::" TLBEntry " + + TLBEntry04 ::" TLBEntry " + + TLBEntry03 ::" TLBEntry " + + TLBEntry02 ::" TLBEntry " + + TLBEntry01 ::" TLBEntry " + + TLBEntry00 ::" TLBEntry " + + TLBXContext ::" XContextReg " + + TLBEntryHi ::" TLBEntryHiReg " + + TLBWired ::" 6 Word.word " + + TLBPageMask ::" 16 Word.word " + + TLBContext ::" ContextReg " + + TLBEntryLo1 ::" TLBEntryLoReg " + + TLBEntryLo0 ::" TLBEntryLoReg " + + TLBRandom ::" 6 Word.word " + + TLBIndex ::" 6 Word.word " + + TLBProbe ::" 1 Word.word " + + nextPC ::" 64 Word.word " + + PC ::" 64 Word.word " + + + + + +(*val CapCauseReg_of_regval : register_value -> maybe CapCauseReg*) + +fun CapCauseReg_of_regval :: " register_value \<Rightarrow>(CapCauseReg)option " where + " CapCauseReg_of_regval (Regval_CapCauseReg (v)) = ( Some v )" +|" CapCauseReg_of_regval g__114 = ( None )" + + +(*val regval_of_CapCauseReg : CapCauseReg -> register_value*) + +definition regval_of_CapCauseReg :: " CapCauseReg \<Rightarrow> register_value " where + " regval_of_CapCauseReg v = ( Regval_CapCauseReg v )" + + +(*val CauseReg_of_regval : register_value -> maybe CauseReg*) + +fun CauseReg_of_regval :: " register_value \<Rightarrow>(CauseReg)option " where + " CauseReg_of_regval (Regval_CauseReg (v)) = ( Some v )" +|" CauseReg_of_regval g__113 = ( None )" + + +(*val regval_of_CauseReg : CauseReg -> register_value*) + +definition regval_of_CauseReg :: " CauseReg \<Rightarrow> register_value " where + " regval_of_CauseReg v = ( Regval_CauseReg v )" + + +(*val ContextReg_of_regval : register_value -> maybe ContextReg*) + +fun ContextReg_of_regval :: " register_value \<Rightarrow>(ContextReg)option " where + " ContextReg_of_regval (Regval_ContextReg (v)) = ( Some v )" +|" ContextReg_of_regval g__112 = ( None )" + + +(*val regval_of_ContextReg : ContextReg -> register_value*) + +definition regval_of_ContextReg :: " ContextReg \<Rightarrow> register_value " where + " regval_of_ContextReg v = ( Regval_ContextReg v )" + + +(*val StatusReg_of_regval : register_value -> maybe StatusReg*) + +fun StatusReg_of_regval :: " register_value \<Rightarrow>(StatusReg)option " where + " StatusReg_of_regval (Regval_StatusReg (v)) = ( Some v )" +|" StatusReg_of_regval g__111 = ( None )" + + +(*val regval_of_StatusReg : StatusReg -> register_value*) + +definition regval_of_StatusReg :: " StatusReg \<Rightarrow> register_value " where + " regval_of_StatusReg v = ( Regval_StatusReg v )" + + +(*val TLBEntry_of_regval : register_value -> maybe TLBEntry*) + +fun TLBEntry_of_regval :: " register_value \<Rightarrow>(TLBEntry)option " where + " TLBEntry_of_regval (Regval_TLBEntry (v)) = ( Some v )" +|" TLBEntry_of_regval g__110 = ( None )" + + +(*val regval_of_TLBEntry : TLBEntry -> register_value*) + +definition regval_of_TLBEntry :: " TLBEntry \<Rightarrow> register_value " where + " regval_of_TLBEntry v = ( Regval_TLBEntry v )" + + +(*val TLBEntryHiReg_of_regval : register_value -> maybe TLBEntryHiReg*) + +fun TLBEntryHiReg_of_regval :: " register_value \<Rightarrow>(TLBEntryHiReg)option " where + " TLBEntryHiReg_of_regval (Regval_TLBEntryHiReg (v)) = ( Some v )" +|" TLBEntryHiReg_of_regval g__109 = ( None )" + + +(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*) + +definition regval_of_TLBEntryHiReg :: " TLBEntryHiReg \<Rightarrow> register_value " where + " regval_of_TLBEntryHiReg v = ( Regval_TLBEntryHiReg v )" + + +(*val TLBEntryLoReg_of_regval : register_value -> maybe TLBEntryLoReg*) + +fun TLBEntryLoReg_of_regval :: " register_value \<Rightarrow>(TLBEntryLoReg)option " where + " TLBEntryLoReg_of_regval (Regval_TLBEntryLoReg (v)) = ( Some v )" +|" TLBEntryLoReg_of_regval g__108 = ( None )" + + +(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*) + +definition regval_of_TLBEntryLoReg :: " TLBEntryLoReg \<Rightarrow> register_value " where + " regval_of_TLBEntryLoReg v = ( Regval_TLBEntryLoReg v )" + + +(*val XContextReg_of_regval : register_value -> maybe XContextReg*) + +fun XContextReg_of_regval :: " register_value \<Rightarrow>(XContextReg)option " where + " XContextReg_of_regval (Regval_XContextReg (v)) = ( Some v )" +|" XContextReg_of_regval g__107 = ( None )" + + +(*val regval_of_XContextReg : XContextReg -> register_value*) + +definition regval_of_XContextReg :: " XContextReg \<Rightarrow> register_value " where + " regval_of_XContextReg v = ( Regval_XContextReg v )" + + +(*val int_of_regval : register_value -> maybe ii*) + +fun int_of_regval :: " register_value \<Rightarrow>(int)option " where + " int_of_regval (Regval_int (v)) = ( Some v )" +|" int_of_regval g__106 = ( None )" + + +(*val regval_of_int : ii -> register_value*) + +definition regval_of_int :: " int \<Rightarrow> register_value " where + " regval_of_int v = ( Regval_int v )" + + +(*val vector_16_dec_bit_of_regval : register_value -> maybe (mword ty16)*) + +fun vector_16_dec_bit_of_regval :: " register_value \<Rightarrow>((16)Word.word)option " where + " vector_16_dec_bit_of_regval (Regval_vector_16_dec_bit (v)) = ( Some v )" +|" vector_16_dec_bit_of_regval g__105 = ( None )" + + +(*val regval_of_vector_16_dec_bit : mword ty16 -> register_value*) + +definition regval_of_vector_16_dec_bit :: "(16)Word.word \<Rightarrow> register_value " where + " regval_of_vector_16_dec_bit v = ( Regval_vector_16_dec_bit v )" + + +(*val vector_1_dec_bit_of_regval : register_value -> maybe (mword ty1)*) + +fun vector_1_dec_bit_of_regval :: " register_value \<Rightarrow>((1)Word.word)option " where + " vector_1_dec_bit_of_regval (Regval_vector_1_dec_bit (v)) = ( Some v )" +|" vector_1_dec_bit_of_regval g__104 = ( None )" + + +(*val regval_of_vector_1_dec_bit : mword ty1 -> register_value*) + +definition regval_of_vector_1_dec_bit :: "(1)Word.word \<Rightarrow> register_value " where + " regval_of_vector_1_dec_bit v = ( Regval_vector_1_dec_bit v )" + + +(*val vector_257_dec_bit_of_regval : register_value -> maybe (mword ty257)*) + +fun vector_257_dec_bit_of_regval :: " register_value \<Rightarrow>((257)Word.word)option " where + " vector_257_dec_bit_of_regval (Regval_vector_257_dec_bit (v)) = ( Some v )" +|" vector_257_dec_bit_of_regval g__103 = ( None )" + + +(*val regval_of_vector_257_dec_bit : mword ty257 -> register_value*) + +definition regval_of_vector_257_dec_bit :: "(257)Word.word \<Rightarrow> register_value " where + " regval_of_vector_257_dec_bit v = ( Regval_vector_257_dec_bit v )" + + +(*val vector_32_dec_bit_of_regval : register_value -> maybe (mword ty32)*) + +fun vector_32_dec_bit_of_regval :: " register_value \<Rightarrow>((32)Word.word)option " where + " vector_32_dec_bit_of_regval (Regval_vector_32_dec_bit (v)) = ( Some v )" +|" vector_32_dec_bit_of_regval g__102 = ( None )" + + +(*val regval_of_vector_32_dec_bit : mword ty32 -> register_value*) + +definition regval_of_vector_32_dec_bit :: "(32)Word.word \<Rightarrow> register_value " where + " regval_of_vector_32_dec_bit v = ( Regval_vector_32_dec_bit v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__101 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + +(*val vector_6_dec_bit_of_regval : register_value -> maybe (mword ty6)*) + +fun vector_6_dec_bit_of_regval :: " register_value \<Rightarrow>((6)Word.word)option " where + " vector_6_dec_bit_of_regval (Regval_vector_6_dec_bit (v)) = ( Some v )" +|" vector_6_dec_bit_of_regval g__100 = ( None )" + + +(*val regval_of_vector_6_dec_bit : mword ty6 -> register_value*) + +definition regval_of_vector_6_dec_bit :: "(6)Word.word \<Rightarrow> register_value " where + " regval_of_vector_6_dec_bit v = ( Regval_vector_6_dec_bit v )" + + +(*val vector_8_dec_bit_of_regval : register_value -> maybe (mword ty8)*) + +fun vector_8_dec_bit_of_regval :: " register_value \<Rightarrow>((8)Word.word)option " where + " vector_8_dec_bit_of_regval (Regval_vector_8_dec_bit (v)) = ( Some v )" +|" vector_8_dec_bit_of_regval g__99 = ( None )" + + +(*val regval_of_vector_8_dec_bit : mword ty8 -> register_value*) + +definition regval_of_vector_8_dec_bit :: "(8)Word.word \<Rightarrow> register_value " where + " regval_of_vector_8_dec_bit v = ( Regval_vector_8_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " vector_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " list_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where + " option_of_regval of_regval1 = ( \<lambda>x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition instCount_ref :: "((regstate),(register_value),(int))register_ref " where + " instCount_ref = ( (| + name = (''instCount''), + read_from = (\<lambda> s . (instCount s)), + write_to = (\<lambda> v s . (( s (| instCount := v |)))), + of_regval = (\<lambda> v . int_of_regval v), + regval_of = (\<lambda> v . regval_of_int v) |) )" + + +definition CapCause_ref :: "((regstate),(register_value),(CapCauseReg))register_ref " where + " CapCause_ref = ( (| + name = (''CapCause''), + read_from = (\<lambda> s . (CapCause s)), + write_to = (\<lambda> v s . (( s (| CapCause := v |)))), + of_regval = (\<lambda> v . CapCauseReg_of_regval v), + regval_of = (\<lambda> v . regval_of_CapCauseReg v) |) )" + + +definition CTLSP_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSP_ref = ( (| + name = (''CTLSP''), + read_from = (\<lambda> s . (CTLSP s)), + write_to = (\<lambda> v s . (( s (| CTLSP := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition CTLSU_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " CTLSU_ref = ( (| + name = (''CTLSU''), + read_from = (\<lambda> s . (CTLSU s)), + write_to = (\<lambda> v s . (( s (| CTLSU := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C30_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C30_ref = ( (| + name = (''C30''), + read_from = (\<lambda> s . (C30 s)), + write_to = (\<lambda> v s . (( s (| C30 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C28_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C28_ref = ( (| + name = (''C28''), + read_from = (\<lambda> s . (C28 s)), + write_to = (\<lambda> v s . (( s (| C28 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C27_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C27_ref = ( (| + name = (''C27''), + read_from = (\<lambda> s . (C27 s)), + write_to = (\<lambda> v s . (( s (| C27 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C26_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C26_ref = ( (| + name = (''C26''), + read_from = (\<lambda> s . (C26 s)), + write_to = (\<lambda> v s . (( s (| C26 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C25_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C25_ref = ( (| + name = (''C25''), + read_from = (\<lambda> s . (C25 s)), + write_to = (\<lambda> v s . (( s (| C25 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C24_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C24_ref = ( (| + name = (''C24''), + read_from = (\<lambda> s . (C24 s)), + write_to = (\<lambda> v s . (( s (| C24 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C23_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C23_ref = ( (| + name = (''C23''), + read_from = (\<lambda> s . (C23 s)), + write_to = (\<lambda> v s . (( s (| C23 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C22_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C22_ref = ( (| + name = (''C22''), + read_from = (\<lambda> s . (C22 s)), + write_to = (\<lambda> v s . (( s (| C22 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C21_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C21_ref = ( (| + name = (''C21''), + read_from = (\<lambda> s . (C21 s)), + write_to = (\<lambda> v s . (( s (| C21 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C20_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C20_ref = ( (| + name = (''C20''), + read_from = (\<lambda> s . (C20 s)), + write_to = (\<lambda> v s . (( s (| C20 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C19_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C19_ref = ( (| + name = (''C19''), + read_from = (\<lambda> s . (C19 s)), + write_to = (\<lambda> v s . (( s (| C19 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C18_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C18_ref = ( (| + name = (''C18''), + read_from = (\<lambda> s . (C18 s)), + write_to = (\<lambda> v s . (( s (| C18 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C17_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C17_ref = ( (| + name = (''C17''), + read_from = (\<lambda> s . (C17 s)), + write_to = (\<lambda> v s . (( s (| C17 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C16_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C16_ref = ( (| + name = (''C16''), + read_from = (\<lambda> s . (C16 s)), + write_to = (\<lambda> v s . (( s (| C16 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C15_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C15_ref = ( (| + name = (''C15''), + read_from = (\<lambda> s . (C15 s)), + write_to = (\<lambda> v s . (( s (| C15 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C14_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C14_ref = ( (| + name = (''C14''), + read_from = (\<lambda> s . (C14 s)), + write_to = (\<lambda> v s . (( s (| C14 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C13_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C13_ref = ( (| + name = (''C13''), + read_from = (\<lambda> s . (C13 s)), + write_to = (\<lambda> v s . (( s (| C13 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C12_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C12_ref = ( (| + name = (''C12''), + read_from = (\<lambda> s . (C12 s)), + write_to = (\<lambda> v s . (( s (| C12 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C11_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C11_ref = ( (| + name = (''C11''), + read_from = (\<lambda> s . (C11 s)), + write_to = (\<lambda> v s . (( s (| C11 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C10_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C10_ref = ( (| + name = (''C10''), + read_from = (\<lambda> s . (C10 s)), + write_to = (\<lambda> v s . (( s (| C10 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C09_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C09_ref = ( (| + name = (''C09''), + read_from = (\<lambda> s . (C09 s)), + write_to = (\<lambda> v s . (( s (| C09 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C08_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C08_ref = ( (| + name = (''C08''), + read_from = (\<lambda> s . (C08 s)), + write_to = (\<lambda> v s . (( s (| C08 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C07_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C07_ref = ( (| + name = (''C07''), + read_from = (\<lambda> s . (C07 s)), + write_to = (\<lambda> v s . (( s (| C07 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C06_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C06_ref = ( (| + name = (''C06''), + read_from = (\<lambda> s . (C06 s)), + write_to = (\<lambda> v s . (( s (| C06 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C05_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C05_ref = ( (| + name = (''C05''), + read_from = (\<lambda> s . (C05 s)), + write_to = (\<lambda> v s . (( s (| C05 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C04_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C04_ref = ( (| + name = (''C04''), + read_from = (\<lambda> s . (C04 s)), + write_to = (\<lambda> v s . (( s (| C04 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C03_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C03_ref = ( (| + name = (''C03''), + read_from = (\<lambda> s . (C03 s)), + write_to = (\<lambda> v s . (( s (| C03 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C02_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C02_ref = ( (| + name = (''C02''), + read_from = (\<lambda> s . (C02 s)), + write_to = (\<lambda> v s . (( s (| C02 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C01_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C01_ref = ( (| + name = (''C01''), + read_from = (\<lambda> s . (C01 s)), + write_to = (\<lambda> v s . (( s (| C01 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C00_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C00_ref = ( (| + name = (''C00''), + read_from = (\<lambda> s . (C00 s)), + write_to = (\<lambda> v s . (( s (| C00 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition inCCallDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inCCallDelay_ref = ( (| + name = (''inCCallDelay''), + read_from = (\<lambda> s . (inCCallDelay s)), + write_to = (\<lambda> v s . (( s (| inCCallDelay := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " nextPCC_ref = ( (| + name = (''nextPCC''), + read_from = (\<lambda> s . (nextPCC s)), + write_to = (\<lambda> v s . (( s (| nextPCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition delayedPCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " delayedPCC_ref = ( (| + name = (''delayedPCC''), + read_from = (\<lambda> s . (delayedPCC s)), + write_to = (\<lambda> v s . (( s (| delayedPCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition PCC_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " PCC_ref = ( (| + name = (''PCC''), + read_from = (\<lambda> s . (PCC s)), + write_to = (\<lambda> v s . (( s (| PCC := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C31_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C31_ref = ( (| + name = (''C31''), + read_from = (\<lambda> s . (C31 s)), + write_to = (\<lambda> v s . (( s (| C31 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition C29_ref :: "((regstate),(register_value),((257)Word.word))register_ref " where + " C29_ref = ( (| + name = (''C29''), + read_from = (\<lambda> s . (C29 s)), + write_to = (\<lambda> v s . (( s (| C29 := v |)))), + of_regval = (\<lambda> v . vector_257_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_257_dec_bit v) |) )" + + +definition UART_RVALID_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_RVALID_ref = ( (| + name = (''UART_RVALID''), + read_from = (\<lambda> s . (UART_RVALID s)), + write_to = (\<lambda> v s . (( s (| UART_RVALID := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_RDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_RDATA_ref = ( (| + name = (''UART_RDATA''), + read_from = (\<lambda> s . (UART_RDATA s)), + write_to = (\<lambda> v s . (( s (| UART_RDATA := v |)))), + of_regval = (\<lambda> v . vector_8_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_8_dec_bit v) |) )" + + +definition UART_WRITTEN_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " UART_WRITTEN_ref = ( (| + name = (''UART_WRITTEN''), + read_from = (\<lambda> s . (UART_WRITTEN s)), + write_to = (\<lambda> v s . (( s (| UART_WRITTEN := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition UART_WDATA_ref :: "((regstate),(register_value),((8)Word.word))register_ref " where + " UART_WDATA_ref = ( (| + name = (''UART_WDATA''), + read_from = (\<lambda> s . (UART_WDATA s)), + write_to = (\<lambda> v s . (( s (| UART_WDATA := v |)))), + of_regval = (\<lambda> v . vector_8_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_8_dec_bit v) |) )" + + +definition GPR_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " GPR_ref = ( (| + name = (''GPR''), + read_from = (\<lambda> s . (GPR s)), + write_to = (\<lambda> v s . (( s (| GPR := v |)))), + of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v), + regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition LO_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " LO_ref = ( (| + name = (''LO''), + read_from = (\<lambda> s . (LO s)), + write_to = (\<lambda> v s . (( s (| LO := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition HI_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " HI_ref = ( (| + name = (''HI''), + read_from = (\<lambda> s . (HI s)), + write_to = (\<lambda> v s . (( s (| HI := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition delayedPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " delayedPC_ref = ( (| + name = (''delayedPC''), + read_from = (\<lambda> s . (delayedPC s)), + write_to = (\<lambda> v s . (( s (| delayedPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition inBranchDelay_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " inBranchDelay_ref = ( (| + name = (''inBranchDelay''), + read_from = (\<lambda> s . (inBranchDelay s)), + write_to = (\<lambda> v s . (( s (| inBranchDelay := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition branchPending_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " branchPending_ref = ( (| + name = (''branchPending''), + read_from = (\<lambda> s . (branchPending s)), + write_to = (\<lambda> v s . (( s (| branchPending := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0Status_ref :: "((regstate),(register_value),(StatusReg))register_ref " where + " CP0Status_ref = ( (| + name = (''CP0Status''), + read_from = (\<lambda> s . (CP0Status s)), + write_to = (\<lambda> v s . (( s (| CP0Status := v |)))), + of_regval = (\<lambda> v . StatusReg_of_regval v), + regval_of = (\<lambda> v . regval_of_StatusReg v) |) )" + + +definition CP0UserLocal_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0UserLocal_ref = ( (| + name = (''CP0UserLocal''), + read_from = (\<lambda> s . (CP0UserLocal s)), + write_to = (\<lambda> v s . (( s (| CP0UserLocal := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0HWREna_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0HWREna_ref = ( (| + name = (''CP0HWREna''), + read_from = (\<lambda> s . (CP0HWREna s)), + write_to = (\<lambda> v s . (( s (| CP0HWREna := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0Count_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Count_ref = ( (| + name = (''CP0Count''), + read_from = (\<lambda> s . (CP0Count s)), + write_to = (\<lambda> v s . (( s (| CP0Count := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition CP0BadVAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0BadVAddr_ref = ( (| + name = (''CP0BadVAddr''), + read_from = (\<lambda> s . (CP0BadVAddr s)), + write_to = (\<lambda> v s . (( s (| CP0BadVAddr := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLAddr_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0LLAddr_ref = ( (| + name = (''CP0LLAddr''), + read_from = (\<lambda> s . (CP0LLAddr s)), + write_to = (\<lambda> v s . (( s (| CP0LLAddr := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0LLBit_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " CP0LLBit_ref = ( (| + name = (''CP0LLBit''), + read_from = (\<lambda> s . (CP0LLBit s)), + write_to = (\<lambda> v s . (( s (| CP0LLBit := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition CP0ErrorEPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0ErrorEPC_ref = ( (| + name = (''CP0ErrorEPC''), + read_from = (\<lambda> s . (CP0ErrorEPC s)), + write_to = (\<lambda> v s . (( s (| CP0ErrorEPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0EPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " CP0EPC_ref = ( (| + name = (''CP0EPC''), + read_from = (\<lambda> s . (CP0EPC s)), + write_to = (\<lambda> v s . (( s (| CP0EPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition CP0Cause_ref :: "((regstate),(register_value),(CauseReg))register_ref " where + " CP0Cause_ref = ( (| + name = (''CP0Cause''), + read_from = (\<lambda> s . (CP0Cause s)), + write_to = (\<lambda> v s . (( s (| CP0Cause := v |)))), + of_regval = (\<lambda> v . CauseReg_of_regval v), + regval_of = (\<lambda> v . regval_of_CauseReg v) |) )" + + +definition CP0Compare_ref :: "((regstate),(register_value),((32)Word.word))register_ref " where + " CP0Compare_ref = ( (| + name = (''CP0Compare''), + read_from = (\<lambda> s . (CP0Compare s)), + write_to = (\<lambda> v s . (( s (| CP0Compare := v |)))), + of_regval = (\<lambda> v . vector_32_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_32_dec_bit v) |) )" + + +definition TLBEntry63_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry63_ref = ( (| + name = (''TLBEntry63''), + read_from = (\<lambda> s . (TLBEntry63 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry63 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry62_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry62_ref = ( (| + name = (''TLBEntry62''), + read_from = (\<lambda> s . (TLBEntry62 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry62 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry61_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry61_ref = ( (| + name = (''TLBEntry61''), + read_from = (\<lambda> s . (TLBEntry61 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry61 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry60_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry60_ref = ( (| + name = (''TLBEntry60''), + read_from = (\<lambda> s . (TLBEntry60 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry60 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry59_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry59_ref = ( (| + name = (''TLBEntry59''), + read_from = (\<lambda> s . (TLBEntry59 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry59 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry58_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry58_ref = ( (| + name = (''TLBEntry58''), + read_from = (\<lambda> s . (TLBEntry58 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry58 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry57_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry57_ref = ( (| + name = (''TLBEntry57''), + read_from = (\<lambda> s . (TLBEntry57 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry57 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry56_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry56_ref = ( (| + name = (''TLBEntry56''), + read_from = (\<lambda> s . (TLBEntry56 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry56 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry55_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry55_ref = ( (| + name = (''TLBEntry55''), + read_from = (\<lambda> s . (TLBEntry55 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry55 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry54_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry54_ref = ( (| + name = (''TLBEntry54''), + read_from = (\<lambda> s . (TLBEntry54 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry54 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry53_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry53_ref = ( (| + name = (''TLBEntry53''), + read_from = (\<lambda> s . (TLBEntry53 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry53 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry52_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry52_ref = ( (| + name = (''TLBEntry52''), + read_from = (\<lambda> s . (TLBEntry52 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry52 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry51_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry51_ref = ( (| + name = (''TLBEntry51''), + read_from = (\<lambda> s . (TLBEntry51 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry51 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry50_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry50_ref = ( (| + name = (''TLBEntry50''), + read_from = (\<lambda> s . (TLBEntry50 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry50 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry49_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry49_ref = ( (| + name = (''TLBEntry49''), + read_from = (\<lambda> s . (TLBEntry49 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry49 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry48_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry48_ref = ( (| + name = (''TLBEntry48''), + read_from = (\<lambda> s . (TLBEntry48 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry48 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry47_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry47_ref = ( (| + name = (''TLBEntry47''), + read_from = (\<lambda> s . (TLBEntry47 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry47 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry46_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry46_ref = ( (| + name = (''TLBEntry46''), + read_from = (\<lambda> s . (TLBEntry46 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry46 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry45_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry45_ref = ( (| + name = (''TLBEntry45''), + read_from = (\<lambda> s . (TLBEntry45 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry45 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry44_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry44_ref = ( (| + name = (''TLBEntry44''), + read_from = (\<lambda> s . (TLBEntry44 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry44 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry43_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry43_ref = ( (| + name = (''TLBEntry43''), + read_from = (\<lambda> s . (TLBEntry43 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry43 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry42_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry42_ref = ( (| + name = (''TLBEntry42''), + read_from = (\<lambda> s . (TLBEntry42 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry42 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry41_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry41_ref = ( (| + name = (''TLBEntry41''), + read_from = (\<lambda> s . (TLBEntry41 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry41 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry40_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry40_ref = ( (| + name = (''TLBEntry40''), + read_from = (\<lambda> s . (TLBEntry40 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry40 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry39_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry39_ref = ( (| + name = (''TLBEntry39''), + read_from = (\<lambda> s . (TLBEntry39 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry39 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry38_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry38_ref = ( (| + name = (''TLBEntry38''), + read_from = (\<lambda> s . (TLBEntry38 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry38 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry37_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry37_ref = ( (| + name = (''TLBEntry37''), + read_from = (\<lambda> s . (TLBEntry37 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry37 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry36_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry36_ref = ( (| + name = (''TLBEntry36''), + read_from = (\<lambda> s . (TLBEntry36 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry36 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry35_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry35_ref = ( (| + name = (''TLBEntry35''), + read_from = (\<lambda> s . (TLBEntry35 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry35 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry34_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry34_ref = ( (| + name = (''TLBEntry34''), + read_from = (\<lambda> s . (TLBEntry34 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry34 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry33_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry33_ref = ( (| + name = (''TLBEntry33''), + read_from = (\<lambda> s . (TLBEntry33 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry33 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry32_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry32_ref = ( (| + name = (''TLBEntry32''), + read_from = (\<lambda> s . (TLBEntry32 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry32 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry31_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry31_ref = ( (| + name = (''TLBEntry31''), + read_from = (\<lambda> s . (TLBEntry31 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry31 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry30_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry30_ref = ( (| + name = (''TLBEntry30''), + read_from = (\<lambda> s . (TLBEntry30 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry30 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry29_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry29_ref = ( (| + name = (''TLBEntry29''), + read_from = (\<lambda> s . (TLBEntry29 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry29 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry28_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry28_ref = ( (| + name = (''TLBEntry28''), + read_from = (\<lambda> s . (TLBEntry28 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry28 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry27_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry27_ref = ( (| + name = (''TLBEntry27''), + read_from = (\<lambda> s . (TLBEntry27 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry27 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry26_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry26_ref = ( (| + name = (''TLBEntry26''), + read_from = (\<lambda> s . (TLBEntry26 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry26 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry25_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry25_ref = ( (| + name = (''TLBEntry25''), + read_from = (\<lambda> s . (TLBEntry25 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry25 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry24_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry24_ref = ( (| + name = (''TLBEntry24''), + read_from = (\<lambda> s . (TLBEntry24 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry24 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry23_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry23_ref = ( (| + name = (''TLBEntry23''), + read_from = (\<lambda> s . (TLBEntry23 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry23 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry22_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry22_ref = ( (| + name = (''TLBEntry22''), + read_from = (\<lambda> s . (TLBEntry22 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry22 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry21_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry21_ref = ( (| + name = (''TLBEntry21''), + read_from = (\<lambda> s . (TLBEntry21 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry21 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry20_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry20_ref = ( (| + name = (''TLBEntry20''), + read_from = (\<lambda> s . (TLBEntry20 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry20 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry19_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry19_ref = ( (| + name = (''TLBEntry19''), + read_from = (\<lambda> s . (TLBEntry19 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry19 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry18_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry18_ref = ( (| + name = (''TLBEntry18''), + read_from = (\<lambda> s . (TLBEntry18 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry18 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry17_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry17_ref = ( (| + name = (''TLBEntry17''), + read_from = (\<lambda> s . (TLBEntry17 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry17 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry16_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry16_ref = ( (| + name = (''TLBEntry16''), + read_from = (\<lambda> s . (TLBEntry16 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry16 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry15_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry15_ref = ( (| + name = (''TLBEntry15''), + read_from = (\<lambda> s . (TLBEntry15 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry15 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry14_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry14_ref = ( (| + name = (''TLBEntry14''), + read_from = (\<lambda> s . (TLBEntry14 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry14 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry13_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry13_ref = ( (| + name = (''TLBEntry13''), + read_from = (\<lambda> s . (TLBEntry13 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry13 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry12_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry12_ref = ( (| + name = (''TLBEntry12''), + read_from = (\<lambda> s . (TLBEntry12 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry12 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry11_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry11_ref = ( (| + name = (''TLBEntry11''), + read_from = (\<lambda> s . (TLBEntry11 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry11 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry10_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry10_ref = ( (| + name = (''TLBEntry10''), + read_from = (\<lambda> s . (TLBEntry10 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry10 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry09_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry09_ref = ( (| + name = (''TLBEntry09''), + read_from = (\<lambda> s . (TLBEntry09 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry09 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry08_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry08_ref = ( (| + name = (''TLBEntry08''), + read_from = (\<lambda> s . (TLBEntry08 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry08 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry07_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry07_ref = ( (| + name = (''TLBEntry07''), + read_from = (\<lambda> s . (TLBEntry07 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry07 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry06_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry06_ref = ( (| + name = (''TLBEntry06''), + read_from = (\<lambda> s . (TLBEntry06 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry06 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry05_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry05_ref = ( (| + name = (''TLBEntry05''), + read_from = (\<lambda> s . (TLBEntry05 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry05 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry04_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry04_ref = ( (| + name = (''TLBEntry04''), + read_from = (\<lambda> s . (TLBEntry04 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry04 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry03_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry03_ref = ( (| + name = (''TLBEntry03''), + read_from = (\<lambda> s . (TLBEntry03 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry03 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry02_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry02_ref = ( (| + name = (''TLBEntry02''), + read_from = (\<lambda> s . (TLBEntry02 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry02 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry01_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry01_ref = ( (| + name = (''TLBEntry01''), + read_from = (\<lambda> s . (TLBEntry01 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry01 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBEntry00_ref :: "((regstate),(register_value),(TLBEntry))register_ref " where + " TLBEntry00_ref = ( (| + name = (''TLBEntry00''), + read_from = (\<lambda> s . (TLBEntry00 s)), + write_to = (\<lambda> v s . (( s (| TLBEntry00 := v |)))), + of_regval = (\<lambda> v . TLBEntry_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntry v) |) )" + + +definition TLBXContext_ref :: "((regstate),(register_value),(XContextReg))register_ref " where + " TLBXContext_ref = ( (| + name = (''TLBXContext''), + read_from = (\<lambda> s . (TLBXContext s)), + write_to = (\<lambda> v s . (( s (| TLBXContext := v |)))), + of_regval = (\<lambda> v . XContextReg_of_regval v), + regval_of = (\<lambda> v . regval_of_XContextReg v) |) )" + + +definition TLBEntryHi_ref :: "((regstate),(register_value),(TLBEntryHiReg))register_ref " where + " TLBEntryHi_ref = ( (| + name = (''TLBEntryHi''), + read_from = (\<lambda> s . (TLBEntryHi s)), + write_to = (\<lambda> v s . (( s (| TLBEntryHi := v |)))), + of_regval = (\<lambda> v . TLBEntryHiReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryHiReg v) |) )" + + +definition TLBWired_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBWired_ref = ( (| + name = (''TLBWired''), + read_from = (\<lambda> s . (TLBWired s)), + write_to = (\<lambda> v s . (( s (| TLBWired := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBPageMask_ref :: "((regstate),(register_value),((16)Word.word))register_ref " where + " TLBPageMask_ref = ( (| + name = (''TLBPageMask''), + read_from = (\<lambda> s . (TLBPageMask s)), + write_to = (\<lambda> v s . (( s (| TLBPageMask := v |)))), + of_regval = (\<lambda> v . vector_16_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_16_dec_bit v) |) )" + + +definition TLBContext_ref :: "((regstate),(register_value),(ContextReg))register_ref " where + " TLBContext_ref = ( (| + name = (''TLBContext''), + read_from = (\<lambda> s . (TLBContext s)), + write_to = (\<lambda> v s . (( s (| TLBContext := v |)))), + of_regval = (\<lambda> v . ContextReg_of_regval v), + regval_of = (\<lambda> v . regval_of_ContextReg v) |) )" + + +definition TLBEntryLo1_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo1_ref = ( (| + name = (''TLBEntryLo1''), + read_from = (\<lambda> s . (TLBEntryLo1 s)), + write_to = (\<lambda> v s . (( s (| TLBEntryLo1 := v |)))), + of_regval = (\<lambda> v . TLBEntryLoReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBEntryLo0_ref :: "((regstate),(register_value),(TLBEntryLoReg))register_ref " where + " TLBEntryLo0_ref = ( (| + name = (''TLBEntryLo0''), + read_from = (\<lambda> s . (TLBEntryLo0 s)), + write_to = (\<lambda> v s . (( s (| TLBEntryLo0 := v |)))), + of_regval = (\<lambda> v . TLBEntryLoReg_of_regval v), + regval_of = (\<lambda> v . regval_of_TLBEntryLoReg v) |) )" + + +definition TLBRandom_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBRandom_ref = ( (| + name = (''TLBRandom''), + read_from = (\<lambda> s . (TLBRandom s)), + write_to = (\<lambda> v s . (( s (| TLBRandom := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBIndex_ref :: "((regstate),(register_value),((6)Word.word))register_ref " where + " TLBIndex_ref = ( (| + name = (''TLBIndex''), + read_from = (\<lambda> s . (TLBIndex s)), + write_to = (\<lambda> v s . (( s (| TLBIndex := v |)))), + of_regval = (\<lambda> v . vector_6_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_6_dec_bit v) |) )" + + +definition TLBProbe_ref :: "((regstate),(register_value),((1)Word.word))register_ref " where + " TLBProbe_ref = ( (| + name = (''TLBProbe''), + read_from = (\<lambda> s . (TLBProbe s)), + write_to = (\<lambda> v s . (( s (| TLBProbe := v |)))), + of_regval = (\<lambda> v . vector_1_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_1_dec_bit v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\<lambda> s . (nextPC s)), + write_to = (\<lambda> v s . (( s (| nextPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\<lambda> s . (PC s)), + write_to = (\<lambda> v s . (( s (| PC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''instCount'') then Some ((regval_of instCount_ref) ((read_from instCount_ref) s)) else + if reg_name = (''CapCause'') then Some ((regval_of CapCause_ref) ((read_from CapCause_ref) s)) else + if reg_name = (''CTLSP'') then Some ((regval_of CTLSP_ref) ((read_from CTLSP_ref) s)) else + if reg_name = (''CTLSU'') then Some ((regval_of CTLSU_ref) ((read_from CTLSU_ref) s)) else + if reg_name = (''C30'') then Some ((regval_of C30_ref) ((read_from C30_ref) s)) else + if reg_name = (''C28'') then Some ((regval_of C28_ref) ((read_from C28_ref) s)) else + if reg_name = (''C27'') then Some ((regval_of C27_ref) ((read_from C27_ref) s)) else + if reg_name = (''C26'') then Some ((regval_of C26_ref) ((read_from C26_ref) s)) else + if reg_name = (''C25'') then Some ((regval_of C25_ref) ((read_from C25_ref) s)) else + if reg_name = (''C24'') then Some ((regval_of C24_ref) ((read_from C24_ref) s)) else + if reg_name = (''C23'') then Some ((regval_of C23_ref) ((read_from C23_ref) s)) else + if reg_name = (''C22'') then Some ((regval_of C22_ref) ((read_from C22_ref) s)) else + if reg_name = (''C21'') then Some ((regval_of C21_ref) ((read_from C21_ref) s)) else + if reg_name = (''C20'') then Some ((regval_of C20_ref) ((read_from C20_ref) s)) else + if reg_name = (''C19'') then Some ((regval_of C19_ref) ((read_from C19_ref) s)) else + if reg_name = (''C18'') then Some ((regval_of C18_ref) ((read_from C18_ref) s)) else + if reg_name = (''C17'') then Some ((regval_of C17_ref) ((read_from C17_ref) s)) else + if reg_name = (''C16'') then Some ((regval_of C16_ref) ((read_from C16_ref) s)) else + if reg_name = (''C15'') then Some ((regval_of C15_ref) ((read_from C15_ref) s)) else + if reg_name = (''C14'') then Some ((regval_of C14_ref) ((read_from C14_ref) s)) else + if reg_name = (''C13'') then Some ((regval_of C13_ref) ((read_from C13_ref) s)) else + if reg_name = (''C12'') then Some ((regval_of C12_ref) ((read_from C12_ref) s)) else + if reg_name = (''C11'') then Some ((regval_of C11_ref) ((read_from C11_ref) s)) else + if reg_name = (''C10'') then Some ((regval_of C10_ref) ((read_from C10_ref) s)) else + if reg_name = (''C09'') then Some ((regval_of C09_ref) ((read_from C09_ref) s)) else + if reg_name = (''C08'') then Some ((regval_of C08_ref) ((read_from C08_ref) s)) else + if reg_name = (''C07'') then Some ((regval_of C07_ref) ((read_from C07_ref) s)) else + if reg_name = (''C06'') then Some ((regval_of C06_ref) ((read_from C06_ref) s)) else + if reg_name = (''C05'') then Some ((regval_of C05_ref) ((read_from C05_ref) s)) else + if reg_name = (''C04'') then Some ((regval_of C04_ref) ((read_from C04_ref) s)) else + if reg_name = (''C03'') then Some ((regval_of C03_ref) ((read_from C03_ref) s)) else + if reg_name = (''C02'') then Some ((regval_of C02_ref) ((read_from C02_ref) s)) else + if reg_name = (''C01'') then Some ((regval_of C01_ref) ((read_from C01_ref) s)) else + if reg_name = (''C00'') then Some ((regval_of C00_ref) ((read_from C00_ref) s)) else + if reg_name = (''inCCallDelay'') then Some ((regval_of inCCallDelay_ref) ((read_from inCCallDelay_ref) s)) else + if reg_name = (''nextPCC'') then Some ((regval_of nextPCC_ref) ((read_from nextPCC_ref) s)) else + if reg_name = (''delayedPCC'') then Some ((regval_of delayedPCC_ref) ((read_from delayedPCC_ref) s)) else + if reg_name = (''PCC'') then Some ((regval_of PCC_ref) ((read_from PCC_ref) s)) else + if reg_name = (''C31'') then Some ((regval_of C31_ref) ((read_from C31_ref) s)) else + if reg_name = (''C29'') then Some ((regval_of C29_ref) ((read_from C29_ref) s)) else + if reg_name = (''UART_RVALID'') then Some ((regval_of UART_RVALID_ref) ((read_from UART_RVALID_ref) s)) else + if reg_name = (''UART_RDATA'') then Some ((regval_of UART_RDATA_ref) ((read_from UART_RDATA_ref) s)) else + if reg_name = (''UART_WRITTEN'') then Some ((regval_of UART_WRITTEN_ref) ((read_from UART_WRITTEN_ref) s)) else + if reg_name = (''UART_WDATA'') then Some ((regval_of UART_WDATA_ref) ((read_from UART_WDATA_ref) s)) else + if reg_name = (''GPR'') then Some ((regval_of GPR_ref) ((read_from GPR_ref) s)) else + if reg_name = (''LO'') then Some ((regval_of LO_ref) ((read_from LO_ref) s)) else + if reg_name = (''HI'') then Some ((regval_of HI_ref) ((read_from HI_ref) s)) else + if reg_name = (''delayedPC'') then Some ((regval_of delayedPC_ref) ((read_from delayedPC_ref) s)) else + if reg_name = (''inBranchDelay'') then Some ((regval_of inBranchDelay_ref) ((read_from inBranchDelay_ref) s)) else + if reg_name = (''branchPending'') then Some ((regval_of branchPending_ref) ((read_from branchPending_ref) s)) else + if reg_name = (''CP0Status'') then Some ((regval_of CP0Status_ref) ((read_from CP0Status_ref) s)) else + if reg_name = (''CP0UserLocal'') then Some ((regval_of CP0UserLocal_ref) ((read_from CP0UserLocal_ref) s)) else + if reg_name = (''CP0HWREna'') then Some ((regval_of CP0HWREna_ref) ((read_from CP0HWREna_ref) s)) else + if reg_name = (''CP0Count'') then Some ((regval_of CP0Count_ref) ((read_from CP0Count_ref) s)) else + if reg_name = (''CP0BadVAddr'') then Some ((regval_of CP0BadVAddr_ref) ((read_from CP0BadVAddr_ref) s)) else + if reg_name = (''CP0LLAddr'') then Some ((regval_of CP0LLAddr_ref) ((read_from CP0LLAddr_ref) s)) else + if reg_name = (''CP0LLBit'') then Some ((regval_of CP0LLBit_ref) ((read_from CP0LLBit_ref) s)) else + if reg_name = (''CP0ErrorEPC'') then Some ((regval_of CP0ErrorEPC_ref) ((read_from CP0ErrorEPC_ref) s)) else + if reg_name = (''CP0EPC'') then Some ((regval_of CP0EPC_ref) ((read_from CP0EPC_ref) s)) else + if reg_name = (''CP0Cause'') then Some ((regval_of CP0Cause_ref) ((read_from CP0Cause_ref) s)) else + if reg_name = (''CP0Compare'') then Some ((regval_of CP0Compare_ref) ((read_from CP0Compare_ref) s)) else + if reg_name = (''TLBEntry63'') then Some ((regval_of TLBEntry63_ref) ((read_from TLBEntry63_ref) s)) else + if reg_name = (''TLBEntry62'') then Some ((regval_of TLBEntry62_ref) ((read_from TLBEntry62_ref) s)) else + if reg_name = (''TLBEntry61'') then Some ((regval_of TLBEntry61_ref) ((read_from TLBEntry61_ref) s)) else + if reg_name = (''TLBEntry60'') then Some ((regval_of TLBEntry60_ref) ((read_from TLBEntry60_ref) s)) else + if reg_name = (''TLBEntry59'') then Some ((regval_of TLBEntry59_ref) ((read_from TLBEntry59_ref) s)) else + if reg_name = (''TLBEntry58'') then Some ((regval_of TLBEntry58_ref) ((read_from TLBEntry58_ref) s)) else + if reg_name = (''TLBEntry57'') then Some ((regval_of TLBEntry57_ref) ((read_from TLBEntry57_ref) s)) else + if reg_name = (''TLBEntry56'') then Some ((regval_of TLBEntry56_ref) ((read_from TLBEntry56_ref) s)) else + if reg_name = (''TLBEntry55'') then Some ((regval_of TLBEntry55_ref) ((read_from TLBEntry55_ref) s)) else + if reg_name = (''TLBEntry54'') then Some ((regval_of TLBEntry54_ref) ((read_from TLBEntry54_ref) s)) else + if reg_name = (''TLBEntry53'') then Some ((regval_of TLBEntry53_ref) ((read_from TLBEntry53_ref) s)) else + if reg_name = (''TLBEntry52'') then Some ((regval_of TLBEntry52_ref) ((read_from TLBEntry52_ref) s)) else + if reg_name = (''TLBEntry51'') then Some ((regval_of TLBEntry51_ref) ((read_from TLBEntry51_ref) s)) else + if reg_name = (''TLBEntry50'') then Some ((regval_of TLBEntry50_ref) ((read_from TLBEntry50_ref) s)) else + if reg_name = (''TLBEntry49'') then Some ((regval_of TLBEntry49_ref) ((read_from TLBEntry49_ref) s)) else + if reg_name = (''TLBEntry48'') then Some ((regval_of TLBEntry48_ref) ((read_from TLBEntry48_ref) s)) else + if reg_name = (''TLBEntry47'') then Some ((regval_of TLBEntry47_ref) ((read_from TLBEntry47_ref) s)) else + if reg_name = (''TLBEntry46'') then Some ((regval_of TLBEntry46_ref) ((read_from TLBEntry46_ref) s)) else + if reg_name = (''TLBEntry45'') then Some ((regval_of TLBEntry45_ref) ((read_from TLBEntry45_ref) s)) else + if reg_name = (''TLBEntry44'') then Some ((regval_of TLBEntry44_ref) ((read_from TLBEntry44_ref) s)) else + if reg_name = (''TLBEntry43'') then Some ((regval_of TLBEntry43_ref) ((read_from TLBEntry43_ref) s)) else + if reg_name = (''TLBEntry42'') then Some ((regval_of TLBEntry42_ref) ((read_from TLBEntry42_ref) s)) else + if reg_name = (''TLBEntry41'') then Some ((regval_of TLBEntry41_ref) ((read_from TLBEntry41_ref) s)) else + if reg_name = (''TLBEntry40'') then Some ((regval_of TLBEntry40_ref) ((read_from TLBEntry40_ref) s)) else + if reg_name = (''TLBEntry39'') then Some ((regval_of TLBEntry39_ref) ((read_from TLBEntry39_ref) s)) else + if reg_name = (''TLBEntry38'') then Some ((regval_of TLBEntry38_ref) ((read_from TLBEntry38_ref) s)) else + if reg_name = (''TLBEntry37'') then Some ((regval_of TLBEntry37_ref) ((read_from TLBEntry37_ref) s)) else + if reg_name = (''TLBEntry36'') then Some ((regval_of TLBEntry36_ref) ((read_from TLBEntry36_ref) s)) else + if reg_name = (''TLBEntry35'') then Some ((regval_of TLBEntry35_ref) ((read_from TLBEntry35_ref) s)) else + if reg_name = (''TLBEntry34'') then Some ((regval_of TLBEntry34_ref) ((read_from TLBEntry34_ref) s)) else + if reg_name = (''TLBEntry33'') then Some ((regval_of TLBEntry33_ref) ((read_from TLBEntry33_ref) s)) else + if reg_name = (''TLBEntry32'') then Some ((regval_of TLBEntry32_ref) ((read_from TLBEntry32_ref) s)) else + if reg_name = (''TLBEntry31'') then Some ((regval_of TLBEntry31_ref) ((read_from TLBEntry31_ref) s)) else + if reg_name = (''TLBEntry30'') then Some ((regval_of TLBEntry30_ref) ((read_from TLBEntry30_ref) s)) else + if reg_name = (''TLBEntry29'') then Some ((regval_of TLBEntry29_ref) ((read_from TLBEntry29_ref) s)) else + if reg_name = (''TLBEntry28'') then Some ((regval_of TLBEntry28_ref) ((read_from TLBEntry28_ref) s)) else + if reg_name = (''TLBEntry27'') then Some ((regval_of TLBEntry27_ref) ((read_from TLBEntry27_ref) s)) else + if reg_name = (''TLBEntry26'') then Some ((regval_of TLBEntry26_ref) ((read_from TLBEntry26_ref) s)) else + if reg_name = (''TLBEntry25'') then Some ((regval_of TLBEntry25_ref) ((read_from TLBEntry25_ref) s)) else + if reg_name = (''TLBEntry24'') then Some ((regval_of TLBEntry24_ref) ((read_from TLBEntry24_ref) s)) else + if reg_name = (''TLBEntry23'') then Some ((regval_of TLBEntry23_ref) ((read_from TLBEntry23_ref) s)) else + if reg_name = (''TLBEntry22'') then Some ((regval_of TLBEntry22_ref) ((read_from TLBEntry22_ref) s)) else + if reg_name = (''TLBEntry21'') then Some ((regval_of TLBEntry21_ref) ((read_from TLBEntry21_ref) s)) else + if reg_name = (''TLBEntry20'') then Some ((regval_of TLBEntry20_ref) ((read_from TLBEntry20_ref) s)) else + if reg_name = (''TLBEntry19'') then Some ((regval_of TLBEntry19_ref) ((read_from TLBEntry19_ref) s)) else + if reg_name = (''TLBEntry18'') then Some ((regval_of TLBEntry18_ref) ((read_from TLBEntry18_ref) s)) else + if reg_name = (''TLBEntry17'') then Some ((regval_of TLBEntry17_ref) ((read_from TLBEntry17_ref) s)) else + if reg_name = (''TLBEntry16'') then Some ((regval_of TLBEntry16_ref) ((read_from TLBEntry16_ref) s)) else + if reg_name = (''TLBEntry15'') then Some ((regval_of TLBEntry15_ref) ((read_from TLBEntry15_ref) s)) else + if reg_name = (''TLBEntry14'') then Some ((regval_of TLBEntry14_ref) ((read_from TLBEntry14_ref) s)) else + if reg_name = (''TLBEntry13'') then Some ((regval_of TLBEntry13_ref) ((read_from TLBEntry13_ref) s)) else + if reg_name = (''TLBEntry12'') then Some ((regval_of TLBEntry12_ref) ((read_from TLBEntry12_ref) s)) else + if reg_name = (''TLBEntry11'') then Some ((regval_of TLBEntry11_ref) ((read_from TLBEntry11_ref) s)) else + if reg_name = (''TLBEntry10'') then Some ((regval_of TLBEntry10_ref) ((read_from TLBEntry10_ref) s)) else + if reg_name = (''TLBEntry09'') then Some ((regval_of TLBEntry09_ref) ((read_from TLBEntry09_ref) s)) else + if reg_name = (''TLBEntry08'') then Some ((regval_of TLBEntry08_ref) ((read_from TLBEntry08_ref) s)) else + if reg_name = (''TLBEntry07'') then Some ((regval_of TLBEntry07_ref) ((read_from TLBEntry07_ref) s)) else + if reg_name = (''TLBEntry06'') then Some ((regval_of TLBEntry06_ref) ((read_from TLBEntry06_ref) s)) else + if reg_name = (''TLBEntry05'') then Some ((regval_of TLBEntry05_ref) ((read_from TLBEntry05_ref) s)) else + if reg_name = (''TLBEntry04'') then Some ((regval_of TLBEntry04_ref) ((read_from TLBEntry04_ref) s)) else + if reg_name = (''TLBEntry03'') then Some ((regval_of TLBEntry03_ref) ((read_from TLBEntry03_ref) s)) else + if reg_name = (''TLBEntry02'') then Some ((regval_of TLBEntry02_ref) ((read_from TLBEntry02_ref) s)) else + if reg_name = (''TLBEntry01'') then Some ((regval_of TLBEntry01_ref) ((read_from TLBEntry01_ref) s)) else + if reg_name = (''TLBEntry00'') then Some ((regval_of TLBEntry00_ref) ((read_from TLBEntry00_ref) s)) else + if reg_name = (''TLBXContext'') then Some ((regval_of TLBXContext_ref) ((read_from TLBXContext_ref) s)) else + if reg_name = (''TLBEntryHi'') then Some ((regval_of TLBEntryHi_ref) ((read_from TLBEntryHi_ref) s)) else + if reg_name = (''TLBWired'') then Some ((regval_of TLBWired_ref) ((read_from TLBWired_ref) s)) else + if reg_name = (''TLBPageMask'') then Some ((regval_of TLBPageMask_ref) ((read_from TLBPageMask_ref) s)) else + if reg_name = (''TLBContext'') then Some ((regval_of TLBContext_ref) ((read_from TLBContext_ref) s)) else + if reg_name = (''TLBEntryLo1'') then Some ((regval_of TLBEntryLo1_ref) ((read_from TLBEntryLo1_ref) s)) else + if reg_name = (''TLBEntryLo0'') then Some ((regval_of TLBEntryLo0_ref) ((read_from TLBEntryLo0_ref) s)) else + if reg_name = (''TLBRandom'') then Some ((regval_of TLBRandom_ref) ((read_from TLBRandom_ref) s)) else + if reg_name = (''TLBIndex'') then Some ((regval_of TLBIndex_ref) ((read_from TLBIndex_ref) s)) else + if reg_name = (''TLBProbe'') then Some ((regval_of TLBProbe_ref) ((read_from TLBProbe_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''instCount'') then map_option (\<lambda> v . (write_to instCount_ref) v s) ((of_regval instCount_ref) v) else + if reg_name = (''CapCause'') then map_option (\<lambda> v . (write_to CapCause_ref) v s) ((of_regval CapCause_ref) v) else + if reg_name = (''CTLSP'') then map_option (\<lambda> v . (write_to CTLSP_ref) v s) ((of_regval CTLSP_ref) v) else + if reg_name = (''CTLSU'') then map_option (\<lambda> v . (write_to CTLSU_ref) v s) ((of_regval CTLSU_ref) v) else + if reg_name = (''C30'') then map_option (\<lambda> v . (write_to C30_ref) v s) ((of_regval C30_ref) v) else + if reg_name = (''C28'') then map_option (\<lambda> v . (write_to C28_ref) v s) ((of_regval C28_ref) v) else + if reg_name = (''C27'') then map_option (\<lambda> v . (write_to C27_ref) v s) ((of_regval C27_ref) v) else + if reg_name = (''C26'') then map_option (\<lambda> v . (write_to C26_ref) v s) ((of_regval C26_ref) v) else + if reg_name = (''C25'') then map_option (\<lambda> v . (write_to C25_ref) v s) ((of_regval C25_ref) v) else + if reg_name = (''C24'') then map_option (\<lambda> v . (write_to C24_ref) v s) ((of_regval C24_ref) v) else + if reg_name = (''C23'') then map_option (\<lambda> v . (write_to C23_ref) v s) ((of_regval C23_ref) v) else + if reg_name = (''C22'') then map_option (\<lambda> v . (write_to C22_ref) v s) ((of_regval C22_ref) v) else + if reg_name = (''C21'') then map_option (\<lambda> v . (write_to C21_ref) v s) ((of_regval C21_ref) v) else + if reg_name = (''C20'') then map_option (\<lambda> v . (write_to C20_ref) v s) ((of_regval C20_ref) v) else + if reg_name = (''C19'') then map_option (\<lambda> v . (write_to C19_ref) v s) ((of_regval C19_ref) v) else + if reg_name = (''C18'') then map_option (\<lambda> v . (write_to C18_ref) v s) ((of_regval C18_ref) v) else + if reg_name = (''C17'') then map_option (\<lambda> v . (write_to C17_ref) v s) ((of_regval C17_ref) v) else + if reg_name = (''C16'') then map_option (\<lambda> v . (write_to C16_ref) v s) ((of_regval C16_ref) v) else + if reg_name = (''C15'') then map_option (\<lambda> v . (write_to C15_ref) v s) ((of_regval C15_ref) v) else + if reg_name = (''C14'') then map_option (\<lambda> v . (write_to C14_ref) v s) ((of_regval C14_ref) v) else + if reg_name = (''C13'') then map_option (\<lambda> v . (write_to C13_ref) v s) ((of_regval C13_ref) v) else + if reg_name = (''C12'') then map_option (\<lambda> v . (write_to C12_ref) v s) ((of_regval C12_ref) v) else + if reg_name = (''C11'') then map_option (\<lambda> v . (write_to C11_ref) v s) ((of_regval C11_ref) v) else + if reg_name = (''C10'') then map_option (\<lambda> v . (write_to C10_ref) v s) ((of_regval C10_ref) v) else + if reg_name = (''C09'') then map_option (\<lambda> v . (write_to C09_ref) v s) ((of_regval C09_ref) v) else + if reg_name = (''C08'') then map_option (\<lambda> v . (write_to C08_ref) v s) ((of_regval C08_ref) v) else + if reg_name = (''C07'') then map_option (\<lambda> v . (write_to C07_ref) v s) ((of_regval C07_ref) v) else + if reg_name = (''C06'') then map_option (\<lambda> v . (write_to C06_ref) v s) ((of_regval C06_ref) v) else + if reg_name = (''C05'') then map_option (\<lambda> v . (write_to C05_ref) v s) ((of_regval C05_ref) v) else + if reg_name = (''C04'') then map_option (\<lambda> v . (write_to C04_ref) v s) ((of_regval C04_ref) v) else + if reg_name = (''C03'') then map_option (\<lambda> v . (write_to C03_ref) v s) ((of_regval C03_ref) v) else + if reg_name = (''C02'') then map_option (\<lambda> v . (write_to C02_ref) v s) ((of_regval C02_ref) v) else + if reg_name = (''C01'') then map_option (\<lambda> v . (write_to C01_ref) v s) ((of_regval C01_ref) v) else + if reg_name = (''C00'') then map_option (\<lambda> v . (write_to C00_ref) v s) ((of_regval C00_ref) v) else + if reg_name = (''inCCallDelay'') then map_option (\<lambda> v . (write_to inCCallDelay_ref) v s) ((of_regval inCCallDelay_ref) v) else + if reg_name = (''nextPCC'') then map_option (\<lambda> v . (write_to nextPCC_ref) v s) ((of_regval nextPCC_ref) v) else + if reg_name = (''delayedPCC'') then map_option (\<lambda> v . (write_to delayedPCC_ref) v s) ((of_regval delayedPCC_ref) v) else + if reg_name = (''PCC'') then map_option (\<lambda> v . (write_to PCC_ref) v s) ((of_regval PCC_ref) v) else + if reg_name = (''C31'') then map_option (\<lambda> v . (write_to C31_ref) v s) ((of_regval C31_ref) v) else + if reg_name = (''C29'') then map_option (\<lambda> v . (write_to C29_ref) v s) ((of_regval C29_ref) v) else + if reg_name = (''UART_RVALID'') then map_option (\<lambda> v . (write_to UART_RVALID_ref) v s) ((of_regval UART_RVALID_ref) v) else + if reg_name = (''UART_RDATA'') then map_option (\<lambda> v . (write_to UART_RDATA_ref) v s) ((of_regval UART_RDATA_ref) v) else + if reg_name = (''UART_WRITTEN'') then map_option (\<lambda> v . (write_to UART_WRITTEN_ref) v s) ((of_regval UART_WRITTEN_ref) v) else + if reg_name = (''UART_WDATA'') then map_option (\<lambda> v . (write_to UART_WDATA_ref) v s) ((of_regval UART_WDATA_ref) v) else + if reg_name = (''GPR'') then map_option (\<lambda> v . (write_to GPR_ref) v s) ((of_regval GPR_ref) v) else + if reg_name = (''LO'') then map_option (\<lambda> v . (write_to LO_ref) v s) ((of_regval LO_ref) v) else + if reg_name = (''HI'') then map_option (\<lambda> v . (write_to HI_ref) v s) ((of_regval HI_ref) v) else + if reg_name = (''delayedPC'') then map_option (\<lambda> v . (write_to delayedPC_ref) v s) ((of_regval delayedPC_ref) v) else + if reg_name = (''inBranchDelay'') then map_option (\<lambda> v . (write_to inBranchDelay_ref) v s) ((of_regval inBranchDelay_ref) v) else + if reg_name = (''branchPending'') then map_option (\<lambda> v . (write_to branchPending_ref) v s) ((of_regval branchPending_ref) v) else + if reg_name = (''CP0Status'') then map_option (\<lambda> v . (write_to CP0Status_ref) v s) ((of_regval CP0Status_ref) v) else + if reg_name = (''CP0UserLocal'') then map_option (\<lambda> v . (write_to CP0UserLocal_ref) v s) ((of_regval CP0UserLocal_ref) v) else + if reg_name = (''CP0HWREna'') then map_option (\<lambda> v . (write_to CP0HWREna_ref) v s) ((of_regval CP0HWREna_ref) v) else + if reg_name = (''CP0Count'') then map_option (\<lambda> v . (write_to CP0Count_ref) v s) ((of_regval CP0Count_ref) v) else + if reg_name = (''CP0BadVAddr'') then map_option (\<lambda> v . (write_to CP0BadVAddr_ref) v s) ((of_regval CP0BadVAddr_ref) v) else + if reg_name = (''CP0LLAddr'') then map_option (\<lambda> v . (write_to CP0LLAddr_ref) v s) ((of_regval CP0LLAddr_ref) v) else + if reg_name = (''CP0LLBit'') then map_option (\<lambda> v . (write_to CP0LLBit_ref) v s) ((of_regval CP0LLBit_ref) v) else + if reg_name = (''CP0ErrorEPC'') then map_option (\<lambda> v . (write_to CP0ErrorEPC_ref) v s) ((of_regval CP0ErrorEPC_ref) v) else + if reg_name = (''CP0EPC'') then map_option (\<lambda> v . (write_to CP0EPC_ref) v s) ((of_regval CP0EPC_ref) v) else + if reg_name = (''CP0Cause'') then map_option (\<lambda> v . (write_to CP0Cause_ref) v s) ((of_regval CP0Cause_ref) v) else + if reg_name = (''CP0Compare'') then map_option (\<lambda> v . (write_to CP0Compare_ref) v s) ((of_regval CP0Compare_ref) v) else + if reg_name = (''TLBEntry63'') then map_option (\<lambda> v . (write_to TLBEntry63_ref) v s) ((of_regval TLBEntry63_ref) v) else + if reg_name = (''TLBEntry62'') then map_option (\<lambda> v . (write_to TLBEntry62_ref) v s) ((of_regval TLBEntry62_ref) v) else + if reg_name = (''TLBEntry61'') then map_option (\<lambda> v . (write_to TLBEntry61_ref) v s) ((of_regval TLBEntry61_ref) v) else + if reg_name = (''TLBEntry60'') then map_option (\<lambda> v . (write_to TLBEntry60_ref) v s) ((of_regval TLBEntry60_ref) v) else + if reg_name = (''TLBEntry59'') then map_option (\<lambda> v . (write_to TLBEntry59_ref) v s) ((of_regval TLBEntry59_ref) v) else + if reg_name = (''TLBEntry58'') then map_option (\<lambda> v . (write_to TLBEntry58_ref) v s) ((of_regval TLBEntry58_ref) v) else + if reg_name = (''TLBEntry57'') then map_option (\<lambda> v . (write_to TLBEntry57_ref) v s) ((of_regval TLBEntry57_ref) v) else + if reg_name = (''TLBEntry56'') then map_option (\<lambda> v . (write_to TLBEntry56_ref) v s) ((of_regval TLBEntry56_ref) v) else + if reg_name = (''TLBEntry55'') then map_option (\<lambda> v . (write_to TLBEntry55_ref) v s) ((of_regval TLBEntry55_ref) v) else + if reg_name = (''TLBEntry54'') then map_option (\<lambda> v . (write_to TLBEntry54_ref) v s) ((of_regval TLBEntry54_ref) v) else + if reg_name = (''TLBEntry53'') then map_option (\<lambda> v . (write_to TLBEntry53_ref) v s) ((of_regval TLBEntry53_ref) v) else + if reg_name = (''TLBEntry52'') then map_option (\<lambda> v . (write_to TLBEntry52_ref) v s) ((of_regval TLBEntry52_ref) v) else + if reg_name = (''TLBEntry51'') then map_option (\<lambda> v . (write_to TLBEntry51_ref) v s) ((of_regval TLBEntry51_ref) v) else + if reg_name = (''TLBEntry50'') then map_option (\<lambda> v . (write_to TLBEntry50_ref) v s) ((of_regval TLBEntry50_ref) v) else + if reg_name = (''TLBEntry49'') then map_option (\<lambda> v . (write_to TLBEntry49_ref) v s) ((of_regval TLBEntry49_ref) v) else + if reg_name = (''TLBEntry48'') then map_option (\<lambda> v . (write_to TLBEntry48_ref) v s) ((of_regval TLBEntry48_ref) v) else + if reg_name = (''TLBEntry47'') then map_option (\<lambda> v . (write_to TLBEntry47_ref) v s) ((of_regval TLBEntry47_ref) v) else + if reg_name = (''TLBEntry46'') then map_option (\<lambda> v . (write_to TLBEntry46_ref) v s) ((of_regval TLBEntry46_ref) v) else + if reg_name = (''TLBEntry45'') then map_option (\<lambda> v . (write_to TLBEntry45_ref) v s) ((of_regval TLBEntry45_ref) v) else + if reg_name = (''TLBEntry44'') then map_option (\<lambda> v . (write_to TLBEntry44_ref) v s) ((of_regval TLBEntry44_ref) v) else + if reg_name = (''TLBEntry43'') then map_option (\<lambda> v . (write_to TLBEntry43_ref) v s) ((of_regval TLBEntry43_ref) v) else + if reg_name = (''TLBEntry42'') then map_option (\<lambda> v . (write_to TLBEntry42_ref) v s) ((of_regval TLBEntry42_ref) v) else + if reg_name = (''TLBEntry41'') then map_option (\<lambda> v . (write_to TLBEntry41_ref) v s) ((of_regval TLBEntry41_ref) v) else + if reg_name = (''TLBEntry40'') then map_option (\<lambda> v . (write_to TLBEntry40_ref) v s) ((of_regval TLBEntry40_ref) v) else + if reg_name = (''TLBEntry39'') then map_option (\<lambda> v . (write_to TLBEntry39_ref) v s) ((of_regval TLBEntry39_ref) v) else + if reg_name = (''TLBEntry38'') then map_option (\<lambda> v . (write_to TLBEntry38_ref) v s) ((of_regval TLBEntry38_ref) v) else + if reg_name = (''TLBEntry37'') then map_option (\<lambda> v . (write_to TLBEntry37_ref) v s) ((of_regval TLBEntry37_ref) v) else + if reg_name = (''TLBEntry36'') then map_option (\<lambda> v . (write_to TLBEntry36_ref) v s) ((of_regval TLBEntry36_ref) v) else + if reg_name = (''TLBEntry35'') then map_option (\<lambda> v . (write_to TLBEntry35_ref) v s) ((of_regval TLBEntry35_ref) v) else + if reg_name = (''TLBEntry34'') then map_option (\<lambda> v . (write_to TLBEntry34_ref) v s) ((of_regval TLBEntry34_ref) v) else + if reg_name = (''TLBEntry33'') then map_option (\<lambda> v . (write_to TLBEntry33_ref) v s) ((of_regval TLBEntry33_ref) v) else + if reg_name = (''TLBEntry32'') then map_option (\<lambda> v . (write_to TLBEntry32_ref) v s) ((of_regval TLBEntry32_ref) v) else + if reg_name = (''TLBEntry31'') then map_option (\<lambda> v . (write_to TLBEntry31_ref) v s) ((of_regval TLBEntry31_ref) v) else + if reg_name = (''TLBEntry30'') then map_option (\<lambda> v . (write_to TLBEntry30_ref) v s) ((of_regval TLBEntry30_ref) v) else + if reg_name = (''TLBEntry29'') then map_option (\<lambda> v . (write_to TLBEntry29_ref) v s) ((of_regval TLBEntry29_ref) v) else + if reg_name = (''TLBEntry28'') then map_option (\<lambda> v . (write_to TLBEntry28_ref) v s) ((of_regval TLBEntry28_ref) v) else + if reg_name = (''TLBEntry27'') then map_option (\<lambda> v . (write_to TLBEntry27_ref) v s) ((of_regval TLBEntry27_ref) v) else + if reg_name = (''TLBEntry26'') then map_option (\<lambda> v . (write_to TLBEntry26_ref) v s) ((of_regval TLBEntry26_ref) v) else + if reg_name = (''TLBEntry25'') then map_option (\<lambda> v . (write_to TLBEntry25_ref) v s) ((of_regval TLBEntry25_ref) v) else + if reg_name = (''TLBEntry24'') then map_option (\<lambda> v . (write_to TLBEntry24_ref) v s) ((of_regval TLBEntry24_ref) v) else + if reg_name = (''TLBEntry23'') then map_option (\<lambda> v . (write_to TLBEntry23_ref) v s) ((of_regval TLBEntry23_ref) v) else + if reg_name = (''TLBEntry22'') then map_option (\<lambda> v . (write_to TLBEntry22_ref) v s) ((of_regval TLBEntry22_ref) v) else + if reg_name = (''TLBEntry21'') then map_option (\<lambda> v . (write_to TLBEntry21_ref) v s) ((of_regval TLBEntry21_ref) v) else + if reg_name = (''TLBEntry20'') then map_option (\<lambda> v . (write_to TLBEntry20_ref) v s) ((of_regval TLBEntry20_ref) v) else + if reg_name = (''TLBEntry19'') then map_option (\<lambda> v . (write_to TLBEntry19_ref) v s) ((of_regval TLBEntry19_ref) v) else + if reg_name = (''TLBEntry18'') then map_option (\<lambda> v . (write_to TLBEntry18_ref) v s) ((of_regval TLBEntry18_ref) v) else + if reg_name = (''TLBEntry17'') then map_option (\<lambda> v . (write_to TLBEntry17_ref) v s) ((of_regval TLBEntry17_ref) v) else + if reg_name = (''TLBEntry16'') then map_option (\<lambda> v . (write_to TLBEntry16_ref) v s) ((of_regval TLBEntry16_ref) v) else + if reg_name = (''TLBEntry15'') then map_option (\<lambda> v . (write_to TLBEntry15_ref) v s) ((of_regval TLBEntry15_ref) v) else + if reg_name = (''TLBEntry14'') then map_option (\<lambda> v . (write_to TLBEntry14_ref) v s) ((of_regval TLBEntry14_ref) v) else + if reg_name = (''TLBEntry13'') then map_option (\<lambda> v . (write_to TLBEntry13_ref) v s) ((of_regval TLBEntry13_ref) v) else + if reg_name = (''TLBEntry12'') then map_option (\<lambda> v . (write_to TLBEntry12_ref) v s) ((of_regval TLBEntry12_ref) v) else + if reg_name = (''TLBEntry11'') then map_option (\<lambda> v . (write_to TLBEntry11_ref) v s) ((of_regval TLBEntry11_ref) v) else + if reg_name = (''TLBEntry10'') then map_option (\<lambda> v . (write_to TLBEntry10_ref) v s) ((of_regval TLBEntry10_ref) v) else + if reg_name = (''TLBEntry09'') then map_option (\<lambda> v . (write_to TLBEntry09_ref) v s) ((of_regval TLBEntry09_ref) v) else + if reg_name = (''TLBEntry08'') then map_option (\<lambda> v . (write_to TLBEntry08_ref) v s) ((of_regval TLBEntry08_ref) v) else + if reg_name = (''TLBEntry07'') then map_option (\<lambda> v . (write_to TLBEntry07_ref) v s) ((of_regval TLBEntry07_ref) v) else + if reg_name = (''TLBEntry06'') then map_option (\<lambda> v . (write_to TLBEntry06_ref) v s) ((of_regval TLBEntry06_ref) v) else + if reg_name = (''TLBEntry05'') then map_option (\<lambda> v . (write_to TLBEntry05_ref) v s) ((of_regval TLBEntry05_ref) v) else + if reg_name = (''TLBEntry04'') then map_option (\<lambda> v . (write_to TLBEntry04_ref) v s) ((of_regval TLBEntry04_ref) v) else + if reg_name = (''TLBEntry03'') then map_option (\<lambda> v . (write_to TLBEntry03_ref) v s) ((of_regval TLBEntry03_ref) v) else + if reg_name = (''TLBEntry02'') then map_option (\<lambda> v . (write_to TLBEntry02_ref) v s) ((of_regval TLBEntry02_ref) v) else + if reg_name = (''TLBEntry01'') then map_option (\<lambda> v . (write_to TLBEntry01_ref) v s) ((of_regval TLBEntry01_ref) v) else + if reg_name = (''TLBEntry00'') then map_option (\<lambda> v . (write_to TLBEntry00_ref) v s) ((of_regval TLBEntry00_ref) v) else + if reg_name = (''TLBXContext'') then map_option (\<lambda> v . (write_to TLBXContext_ref) v s) ((of_regval TLBXContext_ref) v) else + if reg_name = (''TLBEntryHi'') then map_option (\<lambda> v . (write_to TLBEntryHi_ref) v s) ((of_regval TLBEntryHi_ref) v) else + if reg_name = (''TLBWired'') then map_option (\<lambda> v . (write_to TLBWired_ref) v s) ((of_regval TLBWired_ref) v) else + if reg_name = (''TLBPageMask'') then map_option (\<lambda> v . (write_to TLBPageMask_ref) v s) ((of_regval TLBPageMask_ref) v) else + if reg_name = (''TLBContext'') then map_option (\<lambda> v . (write_to TLBContext_ref) v s) ((of_regval TLBContext_ref) v) else + if reg_name = (''TLBEntryLo1'') then map_option (\<lambda> v . (write_to TLBEntryLo1_ref) v s) ((of_regval TLBEntryLo1_ref) v) else + if reg_name = (''TLBEntryLo0'') then map_option (\<lambda> v . (write_to TLBEntryLo0_ref) v s) ((of_regval TLBEntryLo0_ref) v) else + if reg_name = (''TLBRandom'') then map_option (\<lambda> v . (write_to TLBRandom_ref) v s) ((of_regval TLBRandom_ref) v) else + if reg_name = (''TLBIndex'') then map_option (\<lambda> v . (write_to TLBIndex_ref) v s) ((of_regval TLBIndex_ref) v) else + if reg_name = (''TLBProbe'') then map_option (\<lambda> v . (write_to TLBProbe_ref) v s) ((of_regval TLBProbe_ref) v) else + if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end diff --git a/snapshots/isabelle/cheri/Mips_extras.thy b/snapshots/isabelle/cheri/Mips_extras.thy new file mode 100644 index 00000000..c0379d3a --- /dev/null +++ b/snapshots/isabelle/cheri/Mips_extras.thy @@ -0,0 +1,251 @@ +chapter \<open>Generated by Lem from /auto/homes/tb592/REMS/rems/sail/mips/mips_extras.lem.\<close> + +theory "Mips_extras" + +imports + Main + "Lem_pervasives" + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Prompt_monad" + "Prompt" + "Sail_operators" + +begin + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(*val MEMr : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval 'b 'e*) +(*val MEMr_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) +(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> monad 'regval (bool * 'b) 'e*) + +definition MEMr :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where + " MEMr dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 )" + +definition MEMr_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,'b,'e)monad " where + " MEMr_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( read_mem + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1 )" + + +(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> monad 'regval bool 'e*) +definition read_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regval,(bool),'e)monad " where + " read_tag_bool dict_Sail_values_Bitvector_a addr = ( + read_tag dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + maybe_fail (''read_tag_bool'') (bool_of_bitU t)))" + + +(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> monad 'regval unit 'e*) +definition write_tag_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow>('regval,(unit),'e)monad " where + " write_tag_bool dict_Sail_values_Bitvector_a addr t = ( write_tag + dict_Sail_values_Bitvector_a addr (bitU_of_bool t) \<bind> + (\<lambda>x . (case x of _ => return () )) )" + + +definition MEMr_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where + " MEMr_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + return (t, v))))" + + +definition MEMr_tag_reserve :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(bool*'b),'e)monad " where + " MEMr_tag_reserve dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 = ( + read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1 \<bind> (\<lambda> v . + read_tag_bool dict_Sail_values_Bitvector_a addr \<bind> (\<lambda> t . + return (t, v))))" + + + +(*val MEMea : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) +(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> integer -> monad 'regval unit 'e*) + +definition MEMea :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + +definition MEMea_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_tag dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_plain addr size1 )" + +definition MEMea_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regval,(unit),'e)monad " where + " MEMea_tag_conditional dict_Sail_values_Bitvector_a addr size1 = ( write_mem_ea + dict_Sail_values_Bitvector_a Write_conditional addr size1 )" + + + +(*val MEMval : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval unit 'e*) +(*val MEMval_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> 'b -> monad 'regval bool 'e*) +(*val MEMval_tag : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval unit 'e*) +(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> integer -> bool -> 'b -> monad 'regval bool 'e*) + +definition MEMval :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where + " MEMval dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of _ => return () )) )" + +definition MEMval_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where + " MEMval_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . return (if b then True else False)))" + +definition MEMval_tag :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(unit),'e)monad " where + " MEMval_tag dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda>x . (case x of + _ => write_tag_bool dict_Sail_values_Bitvector_a addr t + \<bind> + (\<lambda>x . (case x of _ => return () )) + )) )" + +definition MEMval_tag_conditional :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'b \<Rightarrow>('regval,(bool),'e)monad " where + " MEMval_tag_conditional dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v = ( write_mem_val + dict_Sail_values_Bitvector_b v \<bind> (\<lambda> b . write_tag_bool + dict_Sail_values_Bitvector_a addr t \<bind> (\<lambda>x . (case x of _ => return (if b then True else False) ))))" + + +(*val MEM_sync : forall 'regval 'e. unit -> monad 'regval unit 'e*) + +definition MEM_sync :: " unit \<Rightarrow>('regval,(unit),'e)monad " where + " MEM_sync _ = ( barrier Barrier_MIPS_SYNC )" + + +(* Some wrappers copied from aarch64_extras *) +(* TODO: Harmonise into a common library *) + +definition get_slice_int_bl :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bool)list " where + " get_slice_int_bl len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + subrange_list False bs hi lo)))" + + +(*val get_slice_int : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +definition get_slice_int0 :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where + " get_slice_int0 dict_Sail_values_Bitvector_a len n lo = ( + (of_bools_method dict_Sail_values_Bitvector_a) (get_slice_int_bl len n lo))" + + +definition write_ram :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'b \<Rightarrow> 'a \<Rightarrow>('d,(unit),'c)monad " where + " write_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data = ( + MEMea dict_Sail_values_Bitvector_b addr size1 \<then> + MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data )" + + +definition read_ram :: " 'a Bitvector_class \<Rightarrow> 'c Bitvector_class \<Rightarrow> 'e \<Rightarrow> int \<Rightarrow> 'f \<Rightarrow> 'a \<Rightarrow>('d,'c,'b)monad " where + " read_ram dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr = ( MEMr + dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1 )" + + +definition string_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where + " string_of_bits dict_Sail_values_Bitvector_a bs = ( string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) ((bits_of_method dict_Sail_values_Bitvector_a) bs))" + +definition string_of_int :: " 'a Show_class \<Rightarrow> 'a \<Rightarrow> string " where + " string_of_int dict_Show_Show_a = ((show_method dict_Show_Show_a))" + + +definition sign_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where + " sign_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (exts_bv dict_Sail_values_Bitvector_a len bits)))" + +definition zero_extend0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b " where + " zero_extend0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_b) (extz_bv dict_Sail_values_Bitvector_a len bits)))" + + +definition shift_bits_left :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_left dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftl_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_left'') r))" + +definition shift_bits_right :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_right dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right'') r))" + +definition shift_bits_right_arith :: " 'b Bitvector_class \<Rightarrow> 'd Bitvector_class \<Rightarrow> 'e Bitvector_class \<Rightarrow> 'd \<Rightarrow> 'e \<Rightarrow>('c,'b,'a)monad " where + " shift_bits_right_arith dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n = ( + (let r = (Option.bind ( + (unsigned_method dict_Sail_values_Bitvector_e) n) (\<lambda> n . (of_bits_method dict_Sail_values_Bitvector_b) (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in + maybe_fail (''shift_bits_right_arith'') r))" + + +(* Use constants for undefined values for now *) +definition internal_pick :: " 'a list \<Rightarrow>('c,'a,'b)monad " where + " internal_pick vs = ( return (List.hd vs))" + +definition undefined_string :: " unit \<Rightarrow>('b,(string),'a)monad " where + " undefined_string _ = ( return (''''))" + +definition undefined_unit :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " undefined_unit _ = ( return () )" + +definition undefined_int :: " unit \<Rightarrow>('b,(int),'a)monad " where + " undefined_int _ = ( return (( 0 :: int)::ii))" + +(*val undefined_vector : forall 'rv 'a 'e. integer -> 'a -> monad 'rv (list 'a) 'e*) +definition undefined_vector :: " int \<Rightarrow> 'a \<Rightarrow>('rv,('a list),'e)monad " where + " undefined_vector len u = ( return (repeat [u] len))" + +(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bitvector :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where + " undefined_bitvector dict_Sail_values_Bitvector_a len = ( return ( + (of_bools_method dict_Sail_values_Bitvector_a) (repeat [False] len)))" + +(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => integer -> monad 'rv 'a 'e*) +definition undefined_bits :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow>('rv,'a,'e)monad " where + " undefined_bits dict_Sail_values_Bitvector_a = ( + undefined_bitvector dict_Sail_values_Bitvector_a )" + +definition undefined_bit :: " unit \<Rightarrow>('b,(bitU),'a)monad " where + " undefined_bit _ = ( return B0 )" + +definition undefined_real :: " unit \<Rightarrow>('b,(real),'a)monad " where + " undefined_real _ = ( return (realFromFrac(( 0 :: int))(( 1 :: int))))" + +definition undefined_range :: " 'a \<Rightarrow> 'd \<Rightarrow>('c,'a,'b)monad " where + " undefined_range i j = ( return i )" + +definition undefined_atom :: " 'a \<Rightarrow>('c,'a,'b)monad " where + " undefined_atom i = ( return i )" + +definition undefined_nat :: " unit \<Rightarrow>('b,(int),'a)monad " where + " undefined_nat _ = ( return (( 0 :: int)::ii))" + + +definition skip :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " skip _ = ( return () )" + + +(*val elf_entry : unit -> integer*) +definition elf_entry :: " unit \<Rightarrow> int " where + " elf_entry _ = (( 0 :: int))" + + +definition print_bits :: " 'a Bitvector_class \<Rightarrow> string \<Rightarrow> 'a \<Rightarrow> unit " where + " print_bits dict_Sail_values_Bitvector_a msg bs = ( prerr_endline (msg @ (string_of_bits + dict_Sail_values_Bitvector_a bs)))" + + +(*val get_time_ns : unit -> integer*) +definition get_time_ns :: " unit \<Rightarrow> int " where + " get_time_ns _ = (( 0 :: int))" + +end diff --git a/snapshots/isabelle/lib/lem/LICENSE b/snapshots/isabelle/lib/lem/LICENSE new file mode 100644 index 00000000..06f7abfe --- /dev/null +++ b/snapshots/isabelle/lib/lem/LICENSE @@ -0,0 +1,524 @@ + Lem + +All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} +are distributed under the following license: + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. 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See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with this library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, + MA 02111-1307, USA + +Also add information on how to contact you by electronic and paper mail. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the library, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the + library `Frob' (a library for tweaking knobs) written by James Random Hacker. + + <signature of Ty Coon>, 1 April 1990 + Ty Coon, President of Vice + +That's all there is to it! diff --git a/snapshots/isabelle/lib/lem/Lem.thy b/snapshots/isabelle/lib/lem/Lem.thy new file mode 100644 index 00000000..c6a2a883 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem.thy @@ -0,0 +1,108 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* Brian Campbell, University of Edinburgh *) +(* Shaked Flur, University of Cambridge *) +(* Thomas Bauereiss, University of Cambridge *) +(* Stephen Kell, University of Cambridge *) +(* Thomas Williams *) +(* Lars Hupel *) +(* Basile Clement *) +(* *) +(* The Lem sources are copyright 2010-2018 *) +(* by the authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + +chapter\<open>Mappings of Syntax needed by Lem\<close> + +theory "Lem" + +imports + LemExtraDefs + "~~/src/HOL/Word/Word" +begin + +type_synonym numeral = nat + +subsection \<open>Finite Maps\<close> + +abbreviation (input) "map_find k m \<equiv> the (m k)" +abbreviation (input) "map_update k v m \<equiv> m (k \<mapsto> v)" +abbreviation (input) "map_remove k m \<equiv> m |` (- {k})" +abbreviation (input) "map_any P m \<equiv> \<exists> (k, v) \<in> map_to_set m. P k v" +abbreviation (input) "map_all P m \<equiv> \<forall> (k, v) \<in> map_to_set m. P k v" + +subsection \<open>Lists\<close> + +abbreviation (input) "list_mem e l \<equiv> (e \<in> set l)" +abbreviation (input) "list_forall P l \<equiv> (\<forall>e\<in>set l. P e)" +abbreviation (input) "list_exists P l \<equiv> (\<exists>e\<in>set l. P e)" +abbreviation (input) "list_unzip l \<equiv> (map fst l, map snd l)" + +subsection \<open>Sets\<close> + +abbreviation (input) "set_filter P (s::'a set) \<equiv> {x \<in> s. P x}" +abbreviation (input) "set_bigunion S \<equiv> \<Union> S" +abbreviation (input) "set_biginter S \<equiv> \<Inter> S" + +subsection \<open>Natural numbers\<close> + +subsection \<open>Integers\<close> + + +subsection \<open>Dummy\<close> + +consts + bitwise_xor :: "nat \<Rightarrow> nat \<Rightarrow> nat" + num_asr :: "nat \<Rightarrow> nat \<Rightarrow> nat" + num_lsl :: "nat \<Rightarrow> nat \<Rightarrow> nat" + bitwise_or :: "nat \<Rightarrow> nat \<Rightarrow> nat" + bitwise_not :: "nat \<Rightarrow> nat" + bitwise_and :: "nat \<Rightarrow> nat \<Rightarrow> nat" + +subsection \<open>Machine words\<close> + +definition word_update :: "'a::len word \<Rightarrow> nat \<Rightarrow> nat \<Rightarrow> 'b::len word \<Rightarrow> 'a word" where + "word_update v lo hi w = + (let sz = size v in + of_bl (take (sz-hi-1) (to_bl v) @ to_bl w @ drop (sz-lo) (to_bl v)))" + +end diff --git a/snapshots/isabelle/lib/lem/LemExtraDefs.thy b/snapshots/isabelle/lib/lem/LemExtraDefs.thy new file mode 100644 index 00000000..c14a669f --- /dev/null +++ b/snapshots/isabelle/lib/lem/LemExtraDefs.thy @@ -0,0 +1,1259 @@ +(*========================================================================*) +(* Lem *) +(* *) +(* Dominic Mulligan, University of Cambridge *) +(* Francesco Zappa Nardelli, INRIA Paris-Rocquencourt *) +(* Gabriel Kerneis, University of Cambridge *) +(* Kathy Gray, University of Cambridge *) +(* Peter Boehm, University of Cambridge (while working on Lem) *) +(* Peter Sewell, University of Cambridge *) +(* Scott Owens, University of Kent *) +(* Thomas Tuerk, University of Cambridge *) +(* Brian Campbell, University of Edinburgh *) +(* Shaked Flur, University of Cambridge *) +(* Thomas Bauereiss, University of Cambridge *) +(* Stephen Kell, University of Cambridge *) +(* Thomas Williams *) +(* Lars Hupel *) +(* Basile Clement *) +(* *) +(* The Lem sources are copyright 2010-2018 *) +(* by the authors above and Institut National de Recherche en *) +(* Informatique et en Automatique (INRIA). *) +(* *) +(* All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli} *) +(* are distributed under the license below. The former are distributed *) +(* under the LGPLv2, as in the LICENSE file. *) +(* *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in the *) +(* documentation and/or other materials provided with the distribution. *) +(* 3. The names of the authors may not be used to endorse or promote *) +(* products derived from this software without specific prior written *) +(* permission. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS *) +(* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED *) +(* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *) +(* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY *) +(* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL *) +(* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE *) +(* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *) +(* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER *) +(* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *) +(* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN *) +(* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *) +(*========================================================================*) + +chapter \<open>Auxiliary Definitions needed by Lem\<close> + +theory "LemExtraDefs" + +imports + Main + "~~/src/HOL/Library/Permutation" + "~~/src/HOL/Library/While_Combinator" +begin + +subsection \<open>General\<close> + +consts failwith :: " 'a \<Rightarrow> 'b" + +subsection \<open>Lists\<close> + +fun index :: " 'a list \<Rightarrow> nat \<Rightarrow> 'a option " where + "index [] n = None" + | "index (x # xs) 0 = Some x" + | "index (x # xs) (Suc n) = index xs n" + +lemma index_eq_some [simp]: + "index l n = Some x \<longleftrightarrow> (n < length l \<and> (x = l ! n))" +proof (induct l arbitrary: n x) + case Nil thus ?case by simp +next + case (Cons e es n x) + note ind_hyp = this + + show ?case + proof (cases n) + case 0 thus ?thesis by auto + next + case (Suc n') + with ind_hyp show ?thesis by simp + qed +qed + +lemma index_eq_none [simp]: + "index l n = None \<longleftrightarrow> length l \<le> n" +by (rule iffD1[OF Not_eq_iff]) auto + + +lemma index_simps [simp]: + "length l \<le> n \<Longrightarrow> index l n = None" + "n < length l \<Longrightarrow> index l n = Some (l ! n)" +by (simp_all) + +fun find_indices :: "('a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> nat list" where + "find_indices P [] = []" + | "find_indices P (x # xs) = (if P x then 0 # (map Suc (find_indices P xs)) else (map Suc (find_indices P xs)))" + +lemma length_find_indices : + "length (find_indices P l) \<le> length l" +by (induct l) auto + +lemma sorted_map_suc : + "sorted l \<Longrightarrow> sorted (map Suc l)" +by (induct l) (simp_all add: sorted_Cons) + +lemma sorted_find_indices : + "sorted (find_indices P xs)" +proof (induct xs) + case Nil thus ?case by simp +next + case (Cons x xs) + from sorted_map_suc[OF this] + show ?case + by (simp add: sorted_Cons) +qed + +lemma find_indices_set [simp] : + "set (find_indices P l) = {i. i < length l \<and> P (l ! i)}" +proof (intro set_eqI) + fix i + show "i \<in> set (find_indices P l) \<longleftrightarrow> (i \<in> {i. i < length l \<and> P (l ! i)})" + proof (induct l arbitrary: i) + case Nil thus ?case by simp + next + case (Cons x l' i) + note ind_hyp = this + show ?case + proof (cases i) + case 0 thus ?thesis by auto + next + case (Suc i') with ind_hyp[of i'] show ?thesis by auto + qed + qed +qed + +definition find_index where + "find_index P xs = (case find_indices P xs of + [] \<Rightarrow> None + | i # _ \<Rightarrow> Some i)" + +lemma find_index_eq_some [simp] : + "(find_index P xs = Some ii) \<longleftrightarrow> (ii < length xs \<and> P (xs ! ii) \<and> (\<forall>i' < ii. \<not>(P (xs ! i'))))" + (is "?lhs = ?rhs") +proof (cases "find_indices P xs") + case Nil + with find_indices_set[of P xs] + show ?thesis + unfolding find_index_def by auto +next + case (Cons i il) note find_indices_eq = this + + from sorted_find_indices[of P xs] find_indices_eq + have "sorted (i # il)" by simp + hence i_leq: "\<And>i'. i' \<in> set (i # il) \<Longrightarrow> i \<le> i'" unfolding sorted_Cons by auto + + from find_indices_set[of P xs, unfolded find_indices_eq] + have set_i_il_eq:"\<And>i'. i' \<in> set (i # il) = (i' < length xs \<and> P (xs ! i'))" + by simp + + have lhs_eq: "find_index P xs = Some i" + unfolding find_index_def find_indices_eq by simp + + show ?thesis + proof (intro iffI) + assume ?lhs + with lhs_eq have ii_eq[simp]: "ii = i" by simp + + from set_i_il_eq[of i] i_leq[unfolded set_i_il_eq] + show ?rhs by auto (metis leD less_trans) + next + assume ?rhs + with set_i_il_eq[of ii] + have "ii \<in> set (i # il) \<and> (ii \<le> i)" + by (metis leI length_pos_if_in_set nth_Cons_0 nth_mem set_i_il_eq) + + with i_leq [of ii] have "i = ii" by simp + thus ?lhs unfolding lhs_eq by simp + qed +qed + +lemma find_index_eq_none [simp] : + "(find_index P xs = None) \<longleftrightarrow> (\<forall>x \<in> set xs. \<not>(P x))" (is "?lhs = ?rhs") +proof (rule iffD1[OF Not_eq_iff], intro iffI) + assume "\<not> ?lhs" + then obtain i where "find_index P xs = Some i" by auto + hence "i < length xs \<and> P (xs ! i)" by simp + thus "\<not> ?rhs" by auto +next + let ?p = "(\<lambda>i. i < length xs \<and> P(xs ! i))" + + assume "\<not> ?rhs" + then obtain i where "?p i" + by (metis in_set_conv_nth) + + from LeastI [of ?p, OF \<open>?p i\<close>] + have "?p (Least ?p)" . + + hence "find_index P xs = Some (Least ?p)" + by (subst find_index_eq_some) (metis (mono_tags) less_trans not_less_Least) + + thus "\<not> ?lhs" by blast +qed + +definition genlist where + "genlist f n = map f (upt 0 n)" + +lemma genlist_length [simp] : + "length (genlist f n) = n" +unfolding genlist_def by simp + +lemma genlist_simps [simp]: + "genlist f 0 = []" + "genlist f (Suc n) = genlist f n @ [f n]" +unfolding genlist_def by auto + +definition split_at where + "split_at n l = (take n l, drop n l)" + +fun delete_first :: "('a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> ('a list) option " where + "delete_first P [] = None" + | "delete_first P (x # xs) = + (if (P x) then Some xs else + map_option (\<lambda>xs'. x # xs') (delete_first P xs))" +declare delete_first.simps [simp del] + +lemma delete_first_simps [simp] : + "delete_first P [] = None" + "P x \<Longrightarrow> delete_first P (x # xs) = Some xs" + "\<not>(P x) \<Longrightarrow> delete_first P (x # xs) = map_option (\<lambda>xs'. x # xs') (delete_first P xs)" +unfolding delete_first.simps by auto + +lemmas delete_first_unroll = delete_first.simps(2) + + +lemma delete_first_eq_none [simp] : + "delete_first P l = None \<longleftrightarrow> (\<forall>x \<in> set l. \<not> (P x))" +by (induct l) (auto simp add: delete_first_unroll) + +lemma delete_first_eq_some : + "delete_first P l = (Some l') \<longleftrightarrow> (\<exists>l1 x l2. P x \<and> (\<forall>x \<in> set l1. \<not>(P x)) \<and> (l = l1 @ (x # l2)) \<and> (l' = l1 @ l2))" + (is "?lhs l l' = (\<exists>l1 x l2. ?rhs_body l1 x l2 l l')") +proof (induct l arbitrary: l') + case Nil thus ?case by simp +next + case (Cons e l l') + note ind_hyp = this + + show ?case + proof (cases "P e") + case True + show ?thesis + proof (rule iffI) + assume "?lhs (e # l) l'" + with \<open>P e\<close> have "l = l'" by simp + with \<open>P e\<close> have "?rhs_body [] e l' (e # l) l'" by simp + thus "\<exists>l1 x l2. ?rhs_body l1 x l2 (e # l) l'" by blast + next + assume "\<exists>l1 x l2. ?rhs_body l1 x l2 (e # l) l'" + then obtain l1 x l2 where body_ok: "?rhs_body l1 x l2 (e # l) l'" by blast + + from body_ok \<open>P e\<close> have l1_eq[simp]: "l = l'" + by (cases l1) (simp_all) + with \<open>P e\<close> show "?lhs (e # l) l'" by simp + qed + next + case False + define rhs_pred where "rhs_pred \<equiv> \<lambda>l1 x l2 l l'. ?rhs_body l1 x l2 l l'" + have rhs_fold: "\<And>l1 x l2 l l'. ?rhs_body l1 x l2 l l' = rhs_pred l1 x l2 l l'" + unfolding rhs_pred_def by simp + + have "(\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l') = (\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l')" + proof (intro iffI) + assume "\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l'" + then obtain z l1 x l2 where "rhs_pred l1 x l2 l z" and l'_eq: "l' = e # z" by auto + with \<open>\<not>(P e)\<close> have "rhs_pred (e # l1) x l2 (e # l) l'" + unfolding rhs_pred_def by simp + thus "\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l'" by blast + next + assume "\<exists>l1 x l2. rhs_pred l1 x l2 (e # l) l'" + then obtain l1 x l2 where "rhs_pred l1 x l2 (e # l) l'" by blast + with \<open>\<not> (P e)\<close> obtain l1' where l1_eq[simp]: "l1 = e # l1'" + unfolding rhs_pred_def by (cases l1) (auto) + + with \<open>rhs_pred l1 x l2 (e # l) l'\<close> + have "rhs_pred l1' x l2 l (l1' @ l2) \<and> e # (l1' @ l2) = l'" + unfolding rhs_pred_def by (simp) + thus "\<exists>z l1 x l2. rhs_pred l1 x l2 l z \<and> e # z = l'" by blast + qed + with \<open>\<not> P e\<close> show ?thesis + unfolding rhs_fold + by (simp add: ind_hyp[unfolded rhs_fold]) + qed +qed + + +lemma perm_eval [code] : + "perm [] l \<longleftrightarrow> l = []" (is ?g1) + "perm (x # xs) l \<longleftrightarrow> (case delete_first (\<lambda>e. e = x) l of + None => False + | Some l' => perm xs l')" (is ?g2) +proof - + show ?g1 by auto +next + show ?g2 + proof (cases "delete_first (\<lambda>e. e = x) l") + case None note del_eq = this + hence "x \<notin> set l" by auto + with perm_set_eq [of "x # xs" l] + have "\<not> perm (x # xs) l" by auto + thus ?thesis unfolding del_eq by simp + next + case (Some l') note del_eq = this + + from del_eq[unfolded delete_first_eq_some] + obtain l1 l2 where l_eq: "l = l1 @ [x] @ l2" and l'_eq: "l' = l1 @ l2" by auto + + have "(x # xs <~~> l1 @ x # l2) = (xs <~~> l1 @ l2)" + proof - + from perm_append_swap [of l1 "[x]"] + perm_append2 [of "l1 @ [x]" "x # l1" l2] + have "l1 @ x # l2 <~~> x # (l1 @ l2)" by simp + hence "x # xs <~~> l1 @ x # l2 \<longleftrightarrow> x # xs <~~> x # (l1 @ l2)" + by (metis perm.trans perm_sym) + thus ?thesis by simp + qed + with del_eq l_eq l'_eq show ?thesis by simp + qed +qed + + +fun sorted_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> bool " where + "sorted_by cmp [] = True" + | "sorted_by cmp [_] = True" + | "sorted_by cmp (x1 # x2 # xs) = ((cmp x1 x2) \<and> sorted_by cmp (x2 # xs))" + +lemma sorted_by_lesseq [simp] : + "sorted_by ((op \<le>) :: ('a::{linorder}) => 'a => bool) = sorted" +proof (rule ext) + fix l :: "'a list" + show "sorted_by (op \<le>) l = sorted l" + proof (induct l) + case Nil thus ?case by simp + next + case (Cons x xs) + thus ?case by (cases xs) (simp_all) + qed +qed + +lemma sorted_by_cons_imp : + "sorted_by cmp (x # xs) \<Longrightarrow> sorted_by cmp xs" +by (cases xs) simp_all + +lemma sorted_by_cons_trans : + assumes trans_cmp: "transp cmp" + shows "sorted_by cmp (x # xs) = ((\<forall>x' \<in> set xs . cmp x x') \<and> sorted_by cmp xs)" +proof (induct xs arbitrary: x) + case Nil thus ?case by simp +next + case (Cons x2 xs x1) + note ind_hyp = this + + from trans_cmp + show ?case + by (auto simp add: ind_hyp transp_def) +qed + + +fun insert_sort_insert_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where + "insert_sort_insert_by cmp e ([]) = ( [e])" +| "insert_sort_insert_by cmp e (x # xs) = ( if cmp e x then (e # (x # xs)) else x # (insert_sort_insert_by cmp e xs))" + + +lemma insert_sort_insert_by_length [simp] : + "length (insert_sort_insert_by cmp e l) = Suc (length l)" +by (induct l) auto + +lemma insert_sort_insert_by_set [simp] : + "set (insert_sort_insert_by cmp e l) = insert e (set l)" +by (induct l) auto + +lemma insert_sort_insert_by_perm : + "(insert_sort_insert_by cmp e l) <~~> (e # l)" +proof (induct l) + case Nil thus ?case by simp +next + case (Cons e2 l') + note ind_hyp = this + + have "e2 # e # l' <~~> e # e2 # l'" by (rule perm.swap) + hence "e2 # insert_sort_insert_by cmp e l' <~~> e # e2 # l'" + using ind_hyp by (metis cons_perm_eq perm.trans) + thus ?case by simp +qed + + +lemma insert_sort_insert_by_sorted_by : +assumes cmp_cases: "\<And>y. y \<in> set l \<Longrightarrow> \<not> (cmp e y) \<Longrightarrow> cmp y e" +assumes cmp_trans: "transp cmp" +shows "sorted_by cmp l \<Longrightarrow> sorted_by cmp (insert_sort_insert_by cmp e l)" +using cmp_cases +proof (induct l) + case Nil thus ?case by simp +next + case (Cons x1 l') + note ind_hyp = Cons(1) + note sorted_x1_l' = Cons(2) + note cmp_cases = Cons(3) + + show ?case + proof (cases l') + case Nil with cmp_cases show ?thesis by simp + next + case (Cons x2 l'') note l'_eq = this + + from l'_eq sorted_x1_l' have "cmp x1 x2" "sorted_by cmp l'" by simp_all + + show ?thesis + proof (cases "cmp e x1") + case True + with \<open>cmp x1 x2\<close> \<open>sorted_by cmp l'\<close> + have "sorted_by cmp (x1 # l')" + unfolding l'_eq by (simp) + with \<open>cmp e x1\<close> + show ?thesis by simp + next + case False + + with cmp_cases have "cmp x1 e" by simp + have "\<And>x'. x' \<in> set l' \<Longrightarrow> cmp x1 x'" + proof - + fix x' + assume "x' \<in> set l'" + hence "x' = x2 \<or> cmp x2 x'" + using \<open>sorted_by cmp l'\<close> l'_eq sorted_by_cons_trans [OF cmp_trans, of x2 l''] + by auto + with transpD[OF cmp_trans, of x1 x2 x'] \<open>cmp x1 x2\<close> + show "cmp x1 x'" by blast + qed + hence "sorted_by cmp (x1 # insert_sort_insert_by cmp e l')" + using ind_hyp [OF \<open>sorted_by cmp l'\<close>] \<open>cmp x1 e\<close> cmp_cases + unfolding sorted_by_cons_trans[OF cmp_trans] + by simp + with \<open>\<not>(cmp e x1)\<close> + show ?thesis by simp + qed + qed +qed + + + +fun insert_sort_by :: "('a \<Rightarrow> 'a \<Rightarrow> bool) \<Rightarrow> 'a list \<Rightarrow> 'a list " where + "insert_sort_by cmp [] = []" + | "insert_sort_by cmp (x # xs) = insert_sort_insert_by cmp x (insert_sort_by cmp xs)" + + +lemma insert_sort_by_perm : + "(insert_sort_by cmp l) <~~> l" +proof (induct l) + case Nil thus ?case by simp +next + case (Cons x l) + thus ?case + by simp (metis cons_perm_eq insert_sort_insert_by_perm perm.trans) +qed + +lemma insert_sort_by_length [simp]: + "length (insert_sort_by cmp l) = length l" +by (induct l) auto + +lemma insert_sort_by_set [simp]: + "set (insert_sort_by cmp l) = set l" +by (induct l) auto + +definition sort_by where + "sort_by = insert_sort_by" + +lemma sort_by_simps [simp]: + "length (sort_by cmp l) = length l" + "set (sort_by cmp l) = set l" +unfolding sort_by_def by simp_all + +lemma sort_by_perm : + "sort_by cmp l <~~> l" +unfolding sort_by_def +by (simp add: insert_sort_by_perm) + +subsection \<open>Maps\<close> + +definition map_image :: "('v \<Rightarrow> 'w) \<Rightarrow> ('k, 'v) map \<Rightarrow> ('k, 'w) map" where + "map_image f m = (\<lambda>k. map_option f (m k))" + +definition map_domain_image :: "('k \<Rightarrow> 'v \<Rightarrow> 'w) \<Rightarrow> ('k, 'v) map \<Rightarrow> ('k, 'w) map" where + "map_domain_image f m = (\<lambda>k. map_option (f k) (m k))" + + +lemma map_image_simps [simp]: + "(map_image f m) k = None \<longleftrightarrow> m k = None" + "(map_image f m) k = Some x \<longleftrightarrow> (\<exists>x'. (m k = Some x') \<and> (x = f x'))" + "(map_image f Map.empty) = Map.empty" + "(map_image f (m (k \<mapsto> v)) = (map_image f m) (k \<mapsto> f v))" +unfolding map_image_def by auto + +lemma map_image_dom_ran [simp]: + "dom (map_image f m) = dom m" + "ran (map_image f m) = f ` (ran m)" +unfolding dom_def ran_def by auto + +definition map_to_set :: "('k, 'v) map \<Rightarrow> ('k * 'v) set" where + "map_to_set m = { (k, v) . m k = Some v }" + +lemma map_to_set_simps [simp] : + "map_to_set Map.empty = {}" (is ?g1) + "map_to_set (m ((k::'k) \<mapsto> (v::'v))) = (insert (k, v) (map_to_set (m |` (- {k}))))" (is ?g2) +proof - + show ?g1 unfolding map_to_set_def by simp +next + show ?g2 + proof (rule set_eqI) + fix kv :: "('k * 'v)" + obtain k' v' where kv_eq[simp]: "kv = (k', v')" by (rule prod.exhaust) + + show "(kv \<in> map_to_set (m(k \<mapsto> v))) = (kv \<in> insert (k, v) (map_to_set (m |` (- {k}))))" + by (auto simp add: map_to_set_def) + qed +qed + + +subsection \<open>Sets\<close> + +definition "set_choose s \<equiv> (SOME x. (x \<in> s))" + +definition without_trans_edges :: "('a \<times> 'a) set \<Rightarrow> ('a \<times> 'a) set" where + "without_trans_edges S \<equiv> + let ts = trancl S in + { (x, y) \<in> S. \<forall>z \<in> snd ` S. x \<noteq> z \<and> y \<noteq> z \<longrightarrow> \<not> ((x, z) \<in> ts \<and> (z, y) \<in> ts)}" + +definition unbounded_lfp :: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where + "unbounded_lfp S f \<equiv> + while (\<lambda>x. x \<subset> S) f S" + +definition unbounded_gfp :: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where + "unbounded_gfp S f \<equiv> + while (\<lambda>x. S \<subset> x) f S" + +lemma set_choose_thm[simp]: + "s \<noteq> {} \<Longrightarrow> (set_choose s) \<in> s" +unfolding set_choose_def +by (rule someI_ex) auto + +lemma set_choose_sing [simp]: + "set_choose {x} = x" + unfolding set_choose_def + by auto + +lemma set_choose_code [code]: + "set_choose (set [x]) = x" +by auto + +lemma set_choose_in [intro] : + assumes "s \<noteq> {}" + shows "set_choose s \<in> s" +proof - + from \<open>s \<noteq> {}\<close> + obtain x where "x \<in> s" by auto + thus ?thesis + unfolding set_choose_def + by (rule someI) +qed + + +definition set_case where + "set_case s c_empty c_sing c_else = + (if (s = {}) then c_empty else + (if (card s = 1) then c_sing (set_choose s) else + c_else))" + +lemma set_case_simps [simp] : + "set_case {} c_empty c_sing c_else = c_empty" + "set_case {x} c_empty c_sing c_else = c_sing x" + "card s > 1 \<Longrightarrow> set_case s c_empty c_sing c_else = c_else" + "\<not>(finite s) \<Longrightarrow> set_case s c_empty c_sing c_else = c_else" +unfolding set_case_def by auto + +lemma set_case_simp_insert2 [simp] : +assumes x12_neq: "x1 \<noteq> x2" +shows "set_case (insert x1 (insert x2 xs)) c_empty c_sing c_else = c_else" +proof (cases "finite xs") + case False thus ?thesis by (simp) +next + case True note fin_xs = this + + have "card {x1,x2} \<le> card (insert x1 (insert x2 xs))" + by (rule card_mono) (auto simp add: fin_xs) + with x12_neq have "1 < card (insert x1 (insert x2 xs))" by simp + thus ?thesis by auto +qed + +lemma set_case_code [code] : + "set_case (set []) c_empty c_sing c_else = c_empty" + "set_case (set [x]) c_empty c_sing c_else = c_sing x" + "set_case (set (x1 # x2 # xs)) c_empty c_sing c_else = + (if (x1 = x2) then + set_case (set (x2 # xs)) c_empty c_sing c_else + else + c_else)" +by auto + +definition set_lfp:: "'a set \<Rightarrow> ('a set \<Rightarrow> 'a set) \<Rightarrow> 'a set" where + "set_lfp s f = lfp (\<lambda>s'. f s' \<union> s)" + +lemma set_lfp_tail_rec_def : +assumes mono_f: "mono f" +shows "set_lfp s f = (if (f s) \<subseteq> s then s else (set_lfp (s \<union> f s) f))" (is "?ls = ?rs") +proof (cases "f s \<subseteq> s") + case True note fs_sub_s = this + + from fs_sub_s have "\<Inter>{u. f u \<union> s \<subseteq> u} = s" by auto + hence "?ls = s" unfolding set_lfp_def lfp_def . + with fs_sub_s show "?ls = ?rs" by simp +next + case False note not_fs_sub_s = this + + from mono_f have mono_f': "mono (\<lambda>s'. f s' \<union> s)" + unfolding mono_def by auto + + have "\<Inter>{u. f u \<union> s \<subseteq> u} = \<Inter>{u. f u \<union> (s \<union> f s) \<subseteq> u}" (is "\<Inter>?S1 = \<Inter>?S2") + proof + have "?S2 \<subseteq> ?S1" by auto + thus "\<Inter>?S1 \<subseteq> \<Inter>?S2" by (rule Inf_superset_mono) + next + { fix e + assume "e \<in> \<Inter>?S2" + hence S2_prop: "\<And>s'. f s' \<subseteq> s' \<Longrightarrow> s \<subseteq> s' \<Longrightarrow> f s \<subseteq> s' \<Longrightarrow> e \<in> s'" by simp + + { fix s' + assume "f s' \<subseteq> s'" "s \<subseteq> s'" + + from mono_f \<open>s \<subseteq> s'\<close> + have "f s \<subseteq> f s'" unfolding mono_def by simp + with \<open>f s' \<subseteq> s'\<close> have "f s \<subseteq> s'" by simp + with \<open>f s' \<subseteq> s'\<close> \<open>s \<subseteq> s'\<close> S2_prop + have "e \<in> s'" by simp + } + hence "e \<in> \<Inter>?S1" by simp + } + thus "\<Inter>?S2 \<subseteq> \<Inter>?S1" by auto + qed + hence "?ls = (set_lfp (s \<union> f s) f)" + unfolding set_lfp_def lfp_def . + with not_fs_sub_s show "?ls = ?rs" by simp +qed + +lemma set_lfp_simps [simp] : +"mono f \<Longrightarrow> f s \<subseteq> s \<Longrightarrow> set_lfp s f = s" +"mono f \<Longrightarrow> \<not>(f s \<subseteq> s) \<Longrightarrow> set_lfp s f = (set_lfp (s \<union> f s) f)" +by (metis set_lfp_tail_rec_def)+ + + +fun insert_in_list_at_arbitrary_pos where + "insert_in_list_at_arbitrary_pos x [] = {[x]}" + | "insert_in_list_at_arbitrary_pos x (y # ys) = + insert (x # y # ys) ((\<lambda>l. y # l) ` (insert_in_list_at_arbitrary_pos x ys))" + +lemma insert_in_list_at_arbitrary_pos_thm : + "xl \<in> insert_in_list_at_arbitrary_pos x l \<longleftrightarrow> + (\<exists>l1 l2. l = l1 @ l2 \<and> xl = l1 @ [x] @ l2)" +proof (induct l arbitrary: xl) + case Nil thus ?case by simp +next + case (Cons y l xyl) + note ind_hyp = this + + show ?case + proof (rule iffI) + assume xyl_in: "xyl \<in> insert_in_list_at_arbitrary_pos x (y # l)" + show "\<exists>l1 l2. y # l = l1 @ l2 \<and> xyl = l1 @ [x] @ l2" + proof (cases "xyl = x # y # l") + case True + hence "y # l = [] @ (y # l) \<and> xyl = [] @ [x] @ (y # l)" by simp + thus ?thesis by blast + next + case False + with xyl_in have "xyl \<in> op # y ` insert_in_list_at_arbitrary_pos x l" by simp + with ind_hyp obtain l1 l2 where "l = l1 @ l2 \<and> xyl = y # l1 @ x # l2" + by (auto simp add: image_def Bex_def) + hence "y # l = (y # l1) @ l2 \<and> xyl = (y # l1) @ [x] @ l2" by simp + thus ?thesis by blast + qed + next + assume "\<exists>l1 l2. y # l = l1 @ l2 \<and> xyl = l1 @ [x] @ l2" + then obtain l1 l2 where yl_eq: "y # l = l1 @ l2" and xyl_eq: "xyl = l1 @ [x] @ l2" by blast + show "xyl \<in> insert_in_list_at_arbitrary_pos x (y # l)" + proof (cases l1) + case Nil + with yl_eq xyl_eq + have "xyl = x # y # l" by simp + thus ?thesis by simp + next + case (Cons y' l1') + with yl_eq have l1_eq: "l1 = y # l1'" and l_eq: "l = l1' @ l2" by simp_all + + have "\<exists>l1'' l2''. l = l1'' @ l2'' \<and> l1' @ [x] @ l2 = l1'' @ [x] @ l2''" + apply (rule_tac exI[where x = l1']) + apply (rule_tac exI [where x = l2]) + apply (simp add: l_eq) + done + hence "(l1' @ [x] @ l2) \<in> insert_in_list_at_arbitrary_pos x l" + unfolding ind_hyp by blast + hence "\<exists>l'. l' \<in> insert_in_list_at_arbitrary_pos x l \<and> l1 @ x # l2 = y # l'" + by (rule_tac exI [where x = "l1' @ [x] @ l2"]) (simp add: l1_eq) + thus ?thesis + by (simp add: image_def Bex_def xyl_eq) + qed + qed +qed + +definition list_of_set_set :: "'a set \<Rightarrow> ('a list) set" where +"list_of_set_set s = { l . (set l = s) \<and> distinct l }" + +lemma list_of_set_set_empty [simp]: + "list_of_set_set {} = {[]}" +unfolding list_of_set_set_def by auto + +lemma list_of_set_set_insert [simp] : + "list_of_set_set (insert x s) = + \<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x})))" + (is "?lhs = ?rhs") +proof (intro set_eqI) + fix l + + have "(set l = insert x s \<and> distinct l) \<longleftrightarrow> (\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2)" + proof (intro iffI) + assume "set l = insert x s \<and> distinct l" + hence set_l_eq: "set l = insert x s" and "distinct l" by simp_all + + from \<open>set l = insert x s\<close> + have "x \<in> set l" by simp + then obtain l1 l2 where l_eq: "l = l1 @ x # l2" + unfolding in_set_conv_decomp by blast + + from \<open>distinct l\<close> l_eq + have "distinct (l1 @ l2)" and x_nin: "x \<notin> set (l1 @ l2)" + by auto + + from x_nin set_l_eq[unfolded l_eq] + have set_l12_eq: "set (l1 @ l2) = s - {x}" + by auto + + from \<open>distinct (l1 @ l2)\<close> l_eq set_l12_eq + show "\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2" + by blast + next + assume "\<exists>l1 l2. set (l1 @ l2) = s - {x} \<and> distinct (l1 @ l2) \<and> l = l1 @ x # l2" + then obtain l1 l2 where "set (l1 @ l2) = s - {x}" "distinct (l1 @ l2)" "l = l1 @ x # l2" + by blast + thus "set l = insert x s \<and> distinct l" + by auto + qed + + thus "l \<in> list_of_set_set (insert x s) \<longleftrightarrow> l \<in> (\<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set (s - {x}))))" + unfolding list_of_set_set_def + by (simp add: insert_in_list_at_arbitrary_pos_thm ex_simps[symmetric] del: ex_simps) +qed + +lemma list_of_set_set_code [code]: + "list_of_set_set (set []) = {[]}" + "list_of_set_set (set (x # xs)) = + \<Union> ((insert_in_list_at_arbitrary_pos x) ` (list_of_set_set ((set xs) - {x})))" +by simp_all + +lemma list_of_set_set_is_empty : + "list_of_set_set s = {} \<longleftrightarrow> \<not> (finite s)" +proof - + have "finite s \<longleftrightarrow> (\<exists>l. set l = s \<and> distinct l)" + proof (rule iffI) + assume "\<exists>l. set l = s \<and> distinct l" then + obtain l where "s = set l" by blast + thus "finite s" by simp + next + assume "finite s" + thus "\<exists>l. set l = s \<and> distinct l" + proof (induct s) + case empty + show ?case by auto + next + case (insert e s) + note e_nin_s = insert(2) + from insert(3) obtain l where set_l: "set l = s" and dist_l: "distinct l" by blast + + from set_l have set_el: "set (e # l) = insert e s" by auto + from dist_l set_l e_nin_s have dist_el: "distinct (e # l)" by simp + + from set_el dist_el show ?case by blast + qed + qed + thus ?thesis + unfolding list_of_set_set_def by simp +qed + +definition list_of_set :: "'a set \<Rightarrow> 'a list" where + "list_of_set s = set_choose (list_of_set_set s)" + +lemma list_of_set [simp] : + assumes fin_s: "finite s" + shows "set (list_of_set s) = s" + "distinct (list_of_set s)" +proof - + from fin_s list_of_set_set_is_empty[of s] + have "\<not> (list_of_set_set s = {})" by simp + hence "list_of_set s \<in> list_of_set_set s" + unfolding list_of_set_def + by (rule set_choose_thm) + thus "set (list_of_set s) = s" + "distinct (list_of_set s)" unfolding list_of_set_set_def + by simp_all +qed + +lemma list_of_set_in: + "finite s \<Longrightarrow> list_of_set s \<in> list_of_set_set s" +unfolding list_of_set_def +by (metis list_of_set_set_is_empty set_choose_thm) + +definition ordered_list_of_set where + "ordered_list_of_set cmp s = set_choose (sort_by cmp ` list_of_set_set s)" + +subsection \<open>sum\<close> + +find_consts "'a list => ('a list * _)" + +fun sum_partition :: "('a + 'b) list \<Rightarrow> 'a list * 'b list" where + "sum_partition [] = ([], [])" +| "sum_partition ((Inl l) # lrs) = + (let (ll, rl) = sum_partition lrs in + (l # ll, rl))" +| "sum_partition ((Inr r) # lrs) = + (let (ll, rl) = sum_partition lrs in + (ll, r # rl))" + +lemma sum_partition_length : + "List.length lrs = List.length (fst (sum_partition lrs)) + List.length (snd (sum_partition lrs))" +proof (induct lrs) + case Nil thus ?case by simp +next + case (Cons lr lrs) thus ?case + by (cases lr) (auto split: prod.split) +qed + +subsection \<open>sorting\<close> + +subsection \<open>Strings\<close> + +lemma explode_str_simp [simp] : + "String.explode (STR l) = l" +by (metis STR_inverse UNIV_I) + +declare String.literal.explode_inverse [simp] + +subsection \<open>num to string conversions\<close> + +definition nat_list_to_string :: "nat list \<Rightarrow> string" where + "nat_list_to_string nl = map char_of_nat nl" + +definition is_digit where + "is_digit (n::nat) = (n < 10)" + +lemma is_digit_simps[simp] : + "n < 10 \<Longrightarrow> is_digit n" + "\<not>(n < 10) \<Longrightarrow> \<not>(is_digit n)" +unfolding is_digit_def by simp_all + +lemma is_digit_expand : + "is_digit n \<longleftrightarrow> + (n = 0) \<or> (n = 1) \<or> (n = 2) \<or> (n = 3) \<or> (n = 4) \<or> + (n = 5) \<or> (n = 6) \<or> (n = 7) \<or> (n = 8) \<or> (n = 9)" +unfolding is_digit_def by auto + +lemmas is_digitE = is_digit_expand[THEN iffD1,elim_format] +lemmas is_digitI = is_digit_expand[THEN iffD2,rule_format] + +definition is_digit_char where + "is_digit_char c \<longleftrightarrow> + (c = CHR ''0'') \<or> (c = CHR ''5'') \<or> + (c = CHR ''1'') \<or> (c = CHR ''6'') \<or> + (c = CHR ''2'') \<or> (c = CHR ''7'') \<or> + (c = CHR ''3'') \<or> (c = CHR ''8'') \<or> + (c = CHR ''4'') \<or> (c = CHR ''9'')" + +lemma is_digit_char_simps[simp] : + "is_digit_char (CHR ''0'')" + "is_digit_char (CHR ''1'')" + "is_digit_char (CHR ''2'')" + "is_digit_char (CHR ''3'')" + "is_digit_char (CHR ''4'')" + "is_digit_char (CHR ''5'')" + "is_digit_char (CHR ''6'')" + "is_digit_char (CHR ''7'')" + "is_digit_char (CHR ''8'')" + "is_digit_char (CHR ''9'')" +unfolding is_digit_char_def by simp_all + +lemmas is_digit_charE = is_digit_char_def[THEN iffD1,elim_format] +lemmas is_digit_charI = is_digit_char_def[THEN iffD2,rule_format] + +definition digit_to_char :: "nat \<Rightarrow> char" where + "digit_to_char n = ( + if n = 0 then CHR ''0'' + else if n = 1 then CHR ''1'' + else if n = 2 then CHR ''2'' + else if n = 3 then CHR ''3'' + else if n = 4 then CHR ''4'' + else if n = 5 then CHR ''5'' + else if n = 6 then CHR ''6'' + else if n = 7 then CHR ''7'' + else if n = 8 then CHR ''8'' + else if n = 9 then CHR ''9'' + else CHR ''X'')" + +lemma digit_to_char_simps [simp]: + "digit_to_char 0 = CHR ''0''" + "digit_to_char (Suc 0) = CHR ''1''" + "digit_to_char 2 = CHR ''2''" + "digit_to_char 3 = CHR ''3''" + "digit_to_char 4 = CHR ''4''" + "digit_to_char 5 = CHR ''5''" + "digit_to_char 6 = CHR ''6''" + "digit_to_char 7 = CHR ''7''" + "digit_to_char 8 = CHR ''8''" + "digit_to_char 9 = CHR ''9''" + "n > 9 \<Longrightarrow> digit_to_char n = CHR ''X''" +unfolding digit_to_char_def +by simp_all + +definition char_to_digit :: "char \<Rightarrow> nat" where + "char_to_digit c = ( + if c = CHR ''0'' then 0 + else if c = CHR ''1'' then 1 + else if c = CHR ''2'' then 2 + else if c = CHR ''3'' then 3 + else if c = CHR ''4'' then 4 + else if c = CHR ''5'' then 5 + else if c = CHR ''6'' then 6 + else if c = CHR ''7'' then 7 + else if c = CHR ''8'' then 8 + else if c = CHR ''9'' then 9 + else 10)" + +lemma char_to_digit_simps [simp]: + "char_to_digit (CHR ''0'') = 0" + "char_to_digit (CHR ''1'') = 1" + "char_to_digit (CHR ''2'') = 2" + "char_to_digit (CHR ''3'') = 3" + "char_to_digit (CHR ''4'') = 4" + "char_to_digit (CHR ''5'') = 5" + "char_to_digit (CHR ''6'') = 6" + "char_to_digit (CHR ''7'') = 7" + "char_to_digit (CHR ''8'') = 8" + "char_to_digit (CHR ''9'') = 9" +unfolding char_to_digit_def by simp_all + + +lemma diget_to_char_inv[simp]: +assumes is_digit: "is_digit n" +shows "char_to_digit (digit_to_char n) = n" +using is_digit unfolding is_digit_expand by auto + +lemma char_to_diget_inv[simp]: +assumes is_digit: "is_digit_char c" +shows "digit_to_char (char_to_digit c) = c" +using is_digit +unfolding char_to_digit_def is_digit_char_def +by auto + +lemma char_to_digit_div_mod [simp]: +assumes is_digit: "is_digit_char c" +shows "char_to_digit c < 10" +using is_digit +unfolding char_to_digit_def is_digit_char_def +by auto + + +lemma is_digit_char_intro[simp]: + "is_digit (char_to_digit c) = is_digit_char c" +unfolding char_to_digit_def is_digit_char_def is_digit_expand +by auto + +lemma is_digit_intro[simp]: + "is_digit_char (digit_to_char n) = is_digit n" +unfolding digit_to_char_def is_digit_char_def is_digit_expand +by auto + +lemma digit_to_char_11: +"digit_to_char n1 = digit_to_char n2 \<Longrightarrow> + (is_digit n1 = is_digit n2) \<and> (is_digit n1 \<longrightarrow> (n1 = n2))" +by (metis diget_to_char_inv is_digit_intro) + +lemma char_to_digit_11: +"char_to_digit c1 = char_to_digit c2 \<Longrightarrow> + (is_digit_char c1 = is_digit_char c2) \<and> (is_digit_char c1 \<longrightarrow> (c1 = c2))" +by (metis char_to_diget_inv is_digit_char_intro) + +function nat_to_string :: "nat \<Rightarrow> string" where + "nat_to_string n = + (if (is_digit n) then [digit_to_char n] else + nat_to_string (n div 10) @ [digit_to_char (n mod 10)])" +by auto +termination + by (relation "measure id") (auto simp add: is_digit_def) + +definition int_to_string :: "int \<Rightarrow> string" where + "int_to_string i \<equiv> + if i < 0 then + ''-'' @ nat_to_string (nat (abs i)) + else + nat_to_string (nat i)" + +lemma nat_to_string_simps[simp]: + "is_digit n \<Longrightarrow> nat_to_string n = [digit_to_char n]" + "\<not>(is_digit n) \<Longrightarrow> nat_to_string n = nat_to_string (n div 10) @ [digit_to_char (n mod 10)]" +by simp_all +declare nat_to_string.simps[simp del] + +lemma nat_to_string_neq_nil[simp]: + "nat_to_string n \<noteq> []" + by (cases "is_digit n") simp_all + +lemmas nat_to_string_neq_nil2[simp] = nat_to_string_neq_nil[symmetric] + +lemma nat_to_string_char_to_digit [simp]: + "is_digit_char c \<Longrightarrow> nat_to_string (char_to_digit c) = [c]" +by auto + +lemma nat_to_string_11[simp] : + "(nat_to_string n1 = nat_to_string n2) \<longleftrightarrow> n1 = n2" +proof (rule iffI) + assume "n1 = n2" + thus "nat_to_string n1 = nat_to_string n2" by simp +next + assume "nat_to_string n1 = nat_to_string n2" + thus "n1 = n2" + proof (induct n2 arbitrary: n1 rule: less_induct) + case (less n2') + note ind_hyp = this(1) + note n2s_eq = less(2) + + have is_dig_eq: "is_digit n2' = is_digit n1" using n2s_eq + apply (cases "is_digit n2'") + apply (case_tac [!] "is_digit n1") + apply (simp_all) + done + + show ?case + proof (cases "is_digit n2'") + case True with n2s_eq is_dig_eq show ?thesis by simp (metis digit_to_char_11) + next + case False + with is_dig_eq have not_digs : "\<not> (is_digit n1)" "\<not> (is_digit n2')" by simp_all + + from not_digs(2) have "n2' div 10 < n2'" unfolding is_digit_def by auto + note ind_hyp' = ind_hyp [OF this, of "n1 div 10"] + + from not_digs n2s_eq ind_hyp' digit_to_char_11[of "n1 mod 10" "n2' mod 10"] + have "(n1 mod 10) = (n2' mod 10)" "n1 div 10 = n2' div 10" by simp_all + thus "n1 = n2'" by (metis div_mult_mod_eq) + qed + qed +qed + +definition "is_nat_string s \<equiv> (\<forall>c\<in>set s. is_digit_char c)" +definition "is_strong_nat_string s \<equiv> is_nat_string s \<and> (s \<noteq> []) \<and> (hd s = CHR ''0'' \<longrightarrow> length s = 1)" + +lemma is_nat_string_simps[simp]: + "is_nat_string []" + "is_nat_string (c # s) \<longleftrightarrow> is_digit_char c \<and> is_nat_string s" +unfolding is_nat_string_def by simp_all + +lemma is_strong_nat_string_simps[simp]: + "\<not>(is_strong_nat_string [])" + "is_strong_nat_string (c # s) \<longleftrightarrow> is_digit_char c \<and> is_nat_string s \<and> + (c = CHR ''0'' \<longrightarrow> s = [])" +unfolding is_strong_nat_string_def by simp_all + +fun string_to_nat_aux :: "nat \<Rightarrow> string \<Rightarrow> nat" where + "string_to_nat_aux n [] = n" + | "string_to_nat_aux n (d#ds) = + string_to_nat_aux (n*10 + char_to_digit d) ds" + +definition string_to_nat :: "string \<Rightarrow> nat option" where + "string_to_nat s \<equiv> + (if is_nat_string s then Some (string_to_nat_aux 0 s) else None)" + +definition string_to_nat' :: "string \<Rightarrow> nat" where + "string_to_nat' s \<equiv> the (string_to_nat s)" + +lemma string_to_nat_aux_inv : +assumes "is_nat_string s" +assumes "n > 0 \<or> is_strong_nat_string s" +shows "nat_to_string (string_to_nat_aux n s) = +(if n = 0 then '''' else nat_to_string n) @ s" +using assms +proof (induct s arbitrary: n) + case Nil + thus ?case + by (simp add: is_strong_nat_string_def) +next + case (Cons c s n) + from Cons(2) have "is_digit_char c" "is_nat_string s" by simp_all + note cs_ok = Cons(3) + let ?m = "n*10 + char_to_digit c" + note ind_hyp = Cons(1)[OF \<open>is_nat_string s\<close>, of ?m] + + from \<open>is_digit_char c\<close> have m_div: "?m div 10 = n" and + m_mod: "?m mod 10 = char_to_digit c" + unfolding is_digit_char_def + by auto + + show ?case + proof (cases "?m = 0") + case True + with \<open>is_digit_char c\<close> + have "n = 0" "c = CHR ''0''" unfolding is_digit_char_def by auto + moreover with cs_ok have "s = []" by simp + ultimately show ?thesis by simp + next + case False note m_neq_0 = this + with ind_hyp have ind_hyp': + "nat_to_string (string_to_nat_aux ?m s) = (nat_to_string ?m) @ s" by auto + + hence "nat_to_string (string_to_nat_aux n (c # s)) = (nat_to_string ?m) @ s" + by simp + + with \<open>is_digit_char c\<close> m_div show ?thesis by simp + qed +qed + +lemma string_to_nat_inv : +assumes strong_nat_s: "is_strong_nat_string s" +assumes s2n_s: "string_to_nat s = Some n" +shows "nat_to_string n = s" +proof - + from strong_nat_s have nat_s: "is_nat_string s" unfolding is_strong_nat_string_def by simp + with s2n_s have n_eq: "n = string_to_nat_aux 0 s" unfolding string_to_nat_def by simp + + from string_to_nat_aux_inv[of s 0, folded n_eq] nat_s strong_nat_s + show ?thesis by simp +qed + +lemma nat_to_string_induct [case_names "digit" "non_digit"]: +assumes digit: "\<And>d. is_digit d \<Longrightarrow> P d" +assumes not_digit: "\<And>n. \<not>(is_digit n) \<Longrightarrow> P (n div 10) \<Longrightarrow> P (n mod 10) \<Longrightarrow> P n" +shows "P n" +proof (induct n rule: less_induct) + case (less n) + note ind_hyp = this + + show ?case + proof (cases "is_digit n") + case True with digit show ?thesis by simp + next + case False note not_dig = this + hence "n div 10 < n" "n mod 10 < n" unfolding is_digit_def by auto + with not_dig ind_hyp not_digit show ?thesis by simp + qed +qed + +lemma nat_to_string___is_nat_string [simp]: + "is_nat_string (nat_to_string n)" +unfolding is_nat_string_def +proof (induct n rule: nat_to_string_induct) + case (digit d) + thus ?case by simp +next + case (non_digit n) + thus ?case by simp +qed + +lemma nat_to_string___eq_0 [simp]: + "(nat_to_string n = (CHR ''0'')#s) \<longleftrightarrow> (n = 0 \<and> s = [])" +unfolding is_nat_string_def +proof (induct n arbitrary: s rule: nat_to_string_induct) + case (digit d) thus ?case unfolding is_digit_expand by auto +next + case (non_digit n) + + obtain c s' where ns_eq: "nat_to_string (n div 10) = c # s'" + by (cases "nat_to_string (n div 10)") auto + + from non_digit(1) have "n div 10 \<noteq> 0" unfolding is_digit_def by auto + with non_digit(2) ns_eq have c_neq: "c \<noteq> CHR ''0''" by auto + + from \<open>\<not> (is_digit n)\<close> c_neq ns_eq + show ?case by auto +qed + +lemma nat_to_string___is_strong_nat_string: + "is_strong_nat_string (nat_to_string n)" +proof (cases "is_digit n") + case True thus ?thesis by simp +next + case False note not_digit = this + + obtain c s' where ns_eq: "nat_to_string n = c # s'" + by (cases "nat_to_string n") auto + + from not_digit have "0 < n" unfolding is_digit_def by simp + with ns_eq have c_neq: "c \<noteq> CHR ''0''" by auto + hence "hd (nat_to_string n) \<noteq> CHR ''0''" unfolding ns_eq by simp + + thus ?thesis unfolding is_strong_nat_string_def + by simp +qed + +lemma nat_to_string_inv : + "string_to_nat (nat_to_string n) = Some n" +by (metis nat_to_string_11 + nat_to_string___is_nat_string + nat_to_string___is_strong_nat_string + string_to_nat_def + string_to_nat_inv) + +definition The_opt where + "The_opt p = (if (\<exists>!x. p x) then Some (The p) else None)" + +lemma The_opt_eq_some [simp] : +"((The_opt p) = (Some x)) \<longleftrightarrow> ((p x) \<and> ((\<forall> y. p y \<longrightarrow> (x = y))))" + (is "?lhs = ?rhs") +proof (cases "\<exists>!x. p x") + case True + note exists_unique = this + then obtain x where p_x: "p x" by auto + + from the1_equality[of p x] exists_unique p_x + have the_opt_eq: "The_opt p = Some x" + unfolding The_opt_def by simp + + from exists_unique the_opt_eq p_x show ?thesis + by auto +next + case False + note not_unique = this + + hence "The_opt p = None" + unfolding The_opt_def by simp + with not_unique show ?thesis by auto +qed + +lemma The_opt_eq_none [simp] : +"((The_opt p) = None) \<longleftrightarrow> \<not>(\<exists>!x. p x)" +unfolding The_opt_def by auto + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_assert_extra.thy b/snapshots/isabelle/lib/lem/Lem_assert_extra.thy new file mode 100644 index 00000000..b56e5a19 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_assert_extra.thy @@ -0,0 +1,45 @@ +chapter \<open>Generated by Lem from assert_extra.lem.\<close> + +theory "Lem_assert_extra" + +imports + Main + "Lem" + +begin + + +(*open import {ocaml} `Xstring`*) +(*open import {hol} `stringTheory` `lemTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------------------ *) +(* failing with a proper error message *) +(* ------------------------------------ *) + +(*val failwith: forall 'a. string -> 'a*) + +(* ------------------------------------ *) +(* failing without an error message *) +(* ------------------------------------ *) + +(*val fail : forall 'a. 'a*) +definition fail :: " 'a " where + " fail = ( failwith (''fail''))" + + +(* ------------------------------------- *) +(* assertions *) +(* ------------------------------------- *) + +(*val ensure : bool -> string -> unit*) +definition ensure :: " bool \<Rightarrow> string \<Rightarrow> unit " where + " ensure test msg = ( + if test then + () + else + failwith msg )" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_basic_classes.thy b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy new file mode 100644 index 00000000..c2032dc1 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_basic_classes.thy @@ -0,0 +1,500 @@ +chapter \<open>Generated by Lem from basic_classes.lem.\<close> + +theory "Lem_basic_classes" + +imports + Main + "Lem_bool" + +begin + +(******************************************************************************) +(* Basic Type Classes *) +(******************************************************************************) + +(*open import Bool*) + +(*open import {coq} `Coq.Strings.Ascii`*) + +(* ========================================================================== *) +(* Equality *) +(* ========================================================================== *) + +(* Lem`s default equality (=) is defined by the following type-class Eq. + This typeclass should define equality on an abstract datatype 'a. It should + always coincide with the default equality of Coq, HOL and Isabelle. + For OCaml, it might be different, since abstract datatypes like sets + might have fancy equalities. *) + +(*class ( Eq 'a ) + val = [isEqual] : 'a -> 'a -> bool + val <> [isInequal] : 'a -> 'a -> bool +end*) + + +(* (=) should for all instances be an equivalence relation + The isEquivalence predicate of relations could be used here. + However, this would lead to a cyclic dependency. *) + +(* TODO: add later, once lemmata can be assigned to classes +lemma eq_equiv: ((forall x. (x = x)) && + (forall x y. (x = y) <-> (y = x)) && + (forall x y z. ((x = y) && (y = z)) --> (x = z))) +*) + +(* Structural equality *) + +(* Sometimes, it is also handy to be able to use structural equality. + This equality is mapped to the build-in equality of backends. This equality + differs significantly for each backend. For example, OCaml can`t check equality + of function types, whereas HOL can. When using structural equality, one should + know what one is doing. The only guarentee is that is behaves like + the native backend equality. + + A lengthy name for structural equality is used to discourage its direct use. + It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions + for equality *) +(*val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool*) + +(*val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool*) +(*let unsafe_structural_inequality x y= not (unsafe_structural_equality x y)*) + + +(* ========================================================================== *) +(* Orderings *) +(* ========================================================================== *) + +(* The type-class Ord represents total orders (also called linear orders) *) +datatype ordering = LT | EQ | GT + +fun orderingIsLess :: " ordering \<Rightarrow> bool " where + " orderingIsLess LT = ( True )" +|" orderingIsLess _ = ( False )" + +fun orderingIsGreater :: " ordering \<Rightarrow> bool " where + " orderingIsGreater GT = ( True )" +|" orderingIsGreater _ = ( False )" + +fun orderingIsEqual :: " ordering \<Rightarrow> bool " where + " orderingIsEqual EQ = ( True )" +|" orderingIsEqual _ = ( False )" + + +definition ordering_cases :: " ordering \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where + " ordering_cases r lt eq gt = ( + if orderingIsLess r then lt else + if orderingIsEqual r then eq else gt )" + + + +(*val orderingEqual : ordering -> ordering -> bool*) + +record 'a Ord_class= + + compare_method ::" 'a \<Rightarrow> 'a \<Rightarrow> ordering " + + isLess_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool " + + isLessEqual_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool " + + isGreater_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool " + + isGreaterEqual_method ::" 'a \<Rightarrow> 'a \<Rightarrow> bool " + + + + +(* Ocaml provides default, polymorphic compare functions. Let's use them + as the default. However, because used perhaps in a typeclass they must be + defined for all targets. So, explicitly declare them as undefined for + all other targets. If explictly declare undefined, the type-checker won't complain and + an error will only be raised when trying to actually output the function for a certain + target. *) +(*val defaultCompare : forall 'a. 'a -> 'a -> ordering*) +(*val defaultLess : forall 'a. 'a -> 'a -> bool*) +(*val defaultLessEq : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreater : forall 'a. 'a -> 'a -> bool*) +(*val defaultGreaterEq : forall 'a. 'a -> 'a -> bool*) + + +definition genericCompare :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where + " genericCompare (less1:: 'a \<Rightarrow> 'a \<Rightarrow> bool) (equal:: 'a \<Rightarrow> 'a \<Rightarrow> bool) (x :: 'a) (y :: 'a) = ( + if less1 x y then + LT + else if equal x y then + EQ + else + GT )" + + + +(* +(* compare should really be a total order *) +lemma ord_OK_1: ( + (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) && + (forall x y. (compare x y = LT) <-> (compare y x = GT))) + +lemma ord_OK_2: ( + (forall x y z. (x <= y) && (y <= z) --> (x <= z)) && + (forall x y. (x <= y) || (y <= x)) +) +*) + +(* let's derive a compare function from the Ord type-class *) +(*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*) +definition ordCompare :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where + " ordCompare dict_Basic_classes_Ord_a x y = ( + if ((isLess_method dict_Basic_classes_Ord_a) x y) then LT else + if (x = y) then EQ else GT )" + + +record 'a OrdMaxMin_class= + + max_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + min_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +(*val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) + +(*val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*) + +(*val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +(*val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a*) + +definition instance_Basic_classes_OrdMaxMin_var_dict :: " 'a Ord_class \<Rightarrow> 'a OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_var_dict dict_Basic_classes_Ord_a = ((| + + max_method = ((\<lambda> x y. if ( + (isLessEqual_method dict_Basic_classes_Ord_a) y x) then x else y)), + + min_method = ((\<lambda> x y. if ( + (isLessEqual_method dict_Basic_classes_Ord_a) x y) then x else y))|) )" + + + +(* ========================================================================== *) +(* SetTypes *) +(* ========================================================================== *) + +(* Set implementations use often an order on the elements. This allows the OCaml implementation + to use trees for implementing them. At least, one needs to be able to check equality on sets. + One could use the Ord type-class for sets. However, defining a special typeclass is cleaner + and allows more flexibility. One can make e.g. sure, that this type-class is ignored for + backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate + the functions <, <= ... *) + +(*class ( SetType 'a ) + val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering +end*) + +fun boolCompare :: " bool \<Rightarrow> bool \<Rightarrow> ordering " where + " boolCompare True True = ( EQ )" +|" boolCompare True False = ( GT )" +|" boolCompare False True = ( LT )" +|" boolCompare False False = ( EQ )" + + +(* strings *) + +(*val charEqual : char -> char -> bool*) + +(*val stringEquality : string -> string -> bool*) + +(* pairs *) + +(*val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool*) +(*let pairEqual (a1, b1) (a2, b2)= (a1 = a2) && (b1 = b2)*) + +(*val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool*) + +(*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*) +fun pairCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> ordering " where + " pairCompare cmpa cmpb (a1, b1) (a2, b2) = ( + (case cmpa a1 a2 of + LT => LT + | GT => GT + | EQ => cmpb b1 b2 + ))" + + +fun pairLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'b*'a \<Rightarrow> 'b*'a \<Rightarrow> bool " where + " pairLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( ( + (isLess_method dict_Basic_classes_Ord_b) x1 y1) \<or> (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \<and> ((isLess_method dict_Basic_classes_Ord_a) x2 y2)))" + +fun pairLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'b*'a \<Rightarrow> 'b*'a \<Rightarrow> bool " where + " pairLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2) = ( ( + (isLess_method dict_Basic_classes_Ord_b) x1 y1) \<or> (((isLessEqual_method dict_Basic_classes_Ord_b) x1 y1) \<and> ((isLessEqual_method dict_Basic_classes_Ord_a) x2 y2)))" + + +definition pairGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> bool " where + " pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLess + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )" + +definition pairGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'a*'b \<Rightarrow> 'a*'b \<Rightarrow> bool " where + " pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12 = ( pairLessEq + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12 )" + + +definition instance_Basic_classes_Ord_tup2_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow>('a*'b)Ord_class " where + " instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b = ((| + + compare_method = (pairCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b)), + + isLess_method = + (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isLessEqual_method = + (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreater_method = + (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b), + + isGreaterEqual_method = + (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b) |) )" + + + +(* triples *) + +(*val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool*) +(*let tripleEqual (x1, x2, x3) (y1, y2, y3)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))*) + +(*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*) +fun tripleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> ordering " where + " tripleCompare cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2) = ( + pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2)))" + + +fun tripleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> bool " where + " tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))" + +fun tripleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'a*'b*'c \<Rightarrow> 'a*'b*'c \<Rightarrow> bool " where + " tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3)))" + + +definition tripleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'c*'b*'a \<Rightarrow> 'c*'b*'a \<Rightarrow> bool " where + " tripleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLess + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )" + +definition tripleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'c*'b*'a \<Rightarrow> 'c*'b*'a \<Rightarrow> bool " where + " tripleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123 = ( tripleLessEq + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123 )" + + +definition instance_Basic_classes_Ord_tup3_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow>('a*'b*'c)Ord_class " where + " instance_Basic_classes_Ord_tup3_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c = ((| + + compare_method = (tripleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c)), + + isLess_method = + (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c), + + isLessEqual_method = + (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c), + + isGreater_method = + (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a) |) )" + + +(* quadruples *) + +(*val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool*) +(*let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))*) + +(*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*) +fun quadrupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> ordering " where + " quadrupleCompare cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2))))" + + +fun quadrupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> bool " where + " quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))" + +fun quadrupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> 'a*'b*'c*'d \<Rightarrow> bool " where + " quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))" + + +definition quadrupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> bool " where + " quadrupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLess + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )" + +definition quadrupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> 'd*'c*'b*'a \<Rightarrow> bool " where + " quadrupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234 = ( quadrupleLessEq + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234 )" + + +definition instance_Basic_classes_Ord_tup4_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow>('a*'b*'c*'d)Ord_class " where + " instance_Basic_classes_Ord_tup4_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d = ((| + + compare_method = (quadrupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d)), + + isLess_method = + (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d), + + isLessEqual_method = + (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d), + + isGreater_method = + (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )" + + +(* quintuples *) + +(*val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool*) +(*let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))*) + +(*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*) +fun quintupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow>('e \<Rightarrow> 'e \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> ordering " where + " quintupleCompare cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2)))))" + + +fun quintupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> bool " where + " quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))" + +fun quintupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> 'a*'b*'c*'d*'e \<Rightarrow> bool " where + " quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))" + + +definition quintupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> bool " where + " quintupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLess + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )" + +definition quintupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> 'e*'d*'c*'b*'a \<Rightarrow> bool " where + " quintupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345 = ( quintupleLessEq + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345 )" + + +definition instance_Basic_classes_Ord_tup5_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow>('a*'b*'c*'d*'e)Ord_class " where + " instance_Basic_classes_Ord_tup5_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e = ((| + + compare_method = (quintupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e)), + + isLess_method = + (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e), + + isLessEqual_method = + (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e), + + isGreater_method = + (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_a) |) )" + + +(* sextuples *) + +(*val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool*) +(*let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)= ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))*) + +(*val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> + ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) -> + ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*) +fun sextupleCompare :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'c \<Rightarrow> ordering)\<Rightarrow>('d \<Rightarrow> 'd \<Rightarrow> ordering)\<Rightarrow>('e \<Rightarrow> 'e \<Rightarrow> ordering)\<Rightarrow>('f \<Rightarrow> 'f \<Rightarrow> ordering)\<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> ordering " where + " sextupleCompare cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2) = ( + pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2))))))" + + +fun sextupleLess :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> bool " where + " sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLess + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))" + +fun sextupleLessEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> 'a*'b*'c*'d*'e*'f \<Rightarrow> bool " where + " sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6) = ( pairLessEq + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d + (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))" + + +definition sextupleGreater :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> bool " where + " sextupleGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLess + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )" + +definition sextupleGreaterEq :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> 'f*'e*'d*'c*'b*'a \<Rightarrow> bool " where + " sextupleGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456 = ( sextupleLessEq + dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456 )" + + +definition instance_Basic_classes_Ord_tup6_dict :: " 'a Ord_class \<Rightarrow> 'b Ord_class \<Rightarrow> 'c Ord_class \<Rightarrow> 'd Ord_class \<Rightarrow> 'e Ord_class \<Rightarrow> 'f Ord_class \<Rightarrow>('a*'b*'c*'d*'e*'f)Ord_class " where + " instance_Basic_classes_Ord_tup6_dict dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f = ((| + + compare_method = (sextupleCompare + (compare_method dict_Basic_classes_Ord_a) (compare_method dict_Basic_classes_Ord_b) (compare_method dict_Basic_classes_Ord_c) (compare_method dict_Basic_classes_Ord_d) (compare_method dict_Basic_classes_Ord_e) (compare_method dict_Basic_classes_Ord_f)), + + isLess_method = + (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f), + + isLessEqual_method = + (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b + dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d + dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f), + + isGreater_method = + (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a), + + isGreaterEqual_method = + (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e + dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c + dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a) |) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_bool.thy b/snapshots/isabelle/lib/lem/Lem_bool.thy new file mode 100644 index 00000000..75142160 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_bool.thy @@ -0,0 +1,75 @@ +chapter \<open>Generated by Lem from bool.lem.\<close> + +theory "Lem_bool" + +imports + Main + +begin + + + +(* The type bool is hard-coded, so are true and false *) + +(* ----------------------- *) +(* not *) +(* ----------------------- *) + +(*val not : bool -> bool*) +(*let not b= match b with + | true -> false + | false -> true +end*) + +(* ----------------------- *) +(* and *) +(* ----------------------- *) + +(*val && [and] : bool -> bool -> bool*) +(*let && b1 b2= match (b1, b2) with + | (true, true) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* or *) +(* ----------------------- *) + +(*val || [or] : bool -> bool -> bool*) +(*let || b1 b2= match (b1, b2) with + | (false, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* implication *) +(* ----------------------- *) + +(*val --> [imp] : bool -> bool -> bool*) +(*let --> b1 b2= match (b1, b2) with + | (true, false) -> false + | _ -> true +end*) + + +(* ----------------------- *) +(* equivalence *) +(* ----------------------- *) + +(*val <-> [equiv] : bool -> bool -> bool*) +(*let <-> b1 b2= match (b1, b2) with + | (true, true) -> true + | (false, false) -> true + | _ -> false +end*) + + +(* ----------------------- *) +(* xor *) +(* ----------------------- *) + +(*val xor : bool -> bool -> bool*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_either.thy b/snapshots/isabelle/lib/lem/Lem_either.thy new file mode 100644 index 00000000..e181f823 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_either.thy @@ -0,0 +1,85 @@ +chapter \<open>Generated by Lem from either.lem.\<close> + +theory "Lem_either" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_list" + "Lem_tuple" + +begin + + + +(*open import Bool Basic_classes List Tuple*) +(*open import {hol} `sumTheory`*) +(*open import {ocaml} `Either`*) + +(*type either 'a 'b + = Left of 'a + | Right of 'b*) + + +(* -------------------------------------------------------------------------- *) +(* Equality. *) +(* -------------------------------------------------------------------------- *) + +(*val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool*) +(*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*) + +definition eitherEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('b \<Rightarrow> 'b \<Rightarrow> bool)\<Rightarrow>('a,'b)sum \<Rightarrow>('a,'b)sum \<Rightarrow> bool " where + " eitherEqualBy eql eqr (left:: ('a, 'b) sum) (right:: ('a, 'b) sum) = ( + (case (left, right) of + (Inl l, Inl l') => eql l l' + | (Inr r, Inr r') => eqr r r' + | _ => False + ))" + +(*let eitherEqual= eitherEqualBy (=) (=)*) + +fun either_setElemCompare :: "('d \<Rightarrow> 'b \<Rightarrow> ordering)\<Rightarrow>('c \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow>('d,'c)sum \<Rightarrow>('b,'a)sum \<Rightarrow> ordering " where + " either_setElemCompare cmpa cmpb (Inl x') (Inl y') = ( cmpa x' y' )" +|" either_setElemCompare cmpa cmpb (Inr x') (Inr y') = ( cmpb x' y' )" +|" either_setElemCompare cmpa cmpb (Inl _) (Inr _) = ( LT )" +|" either_setElemCompare cmpa cmpb (Inr _) (Inl _) = ( GT )" + + + +(* -------------------------------------------------------------------------- *) +(* Utility functions. *) +(* -------------------------------------------------------------------------- *) + +(*val isLeft : forall 'a 'b. either 'a 'b -> bool*) + +(*val isRight : forall 'a 'b. either 'a 'b -> bool*) + + +(*val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c*) +(*let either fa fb x= match x with + | Left a -> fa a + | Right b -> fb b +end*) + + +(*val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)*) +(*let rec partitionEither l= match l with + | [] -> ([], []) + | x :: xs -> begin + let (ll, rl) = partitionEither xs in + match x with + | Left l -> (l::ll, rl) + | Right r -> (ll, r::rl) + end + end +end*) + + +(*val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a*) + + +(*val rights : forall 'a 'b. list (either 'a 'b) -> list 'b*) + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_function.thy b/snapshots/isabelle/lib/lem/Lem_function.thy new file mode 100644 index 00000000..29c1fb04 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_function.thy @@ -0,0 +1,72 @@ +chapter \<open>Generated by Lem from function.lem.\<close> + +theory "Lem_function" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + +begin + +(******************************************************************************) +(* A library for common operations on functions *) +(******************************************************************************) + +(*open import Bool Basic_classes*) + +(*open import {coq} `Program.Basics`*) + +(* ----------------------- *) +(* identity function *) +(* ----------------------- *) + +(*val id : forall 'a. 'a -> 'a*) +(*let id x= x*) + + +(* ----------------------- *) +(* constant function *) +(* ----------------------- *) + +(*val const : forall 'a 'b. 'a -> 'b -> 'a*) + + +(* ----------------------- *) +(* function composition *) +(* ----------------------- *) + +(*val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)*) +(*let comb f g= (fun x -> f (g x))*) + + +(* ----------------------- *) +(* function application *) +(* ----------------------- *) + +(*val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)*) +(*let $ f= (fun x -> f x)*) + +(*val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b*) +(*let $> x f= f x*) + +(* ----------------------- *) +(* flipping argument order *) +(* ----------------------- *) + +(*val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)*) +(*let flip f= (fun x y -> f y x)*) + + +(* currying / uncurrying *) + +(*val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c*) +definition curry :: "('a*'b \<Rightarrow> 'c)\<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow> 'c " where + " curry f = ( (\<lambda> a b . f (a, b)))" + + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) +fun uncurry :: "('a \<Rightarrow> 'b \<Rightarrow> 'c)\<Rightarrow> 'a*'b \<Rightarrow> 'c " where + " uncurry f (a,b) = ( f a b )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_function_extra.thy b/snapshots/isabelle/lib/lem/Lem_function_extra.thy new file mode 100644 index 00000000..f742e1e6 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_function_extra.thy @@ -0,0 +1,29 @@ +chapter \<open>Generated by Lem from function_extra.lem.\<close> + +theory "Lem_function_extra" + +imports + Main + "Lem_maybe" + "Lem_bool" + "Lem_basic_classes" + "Lem_num" + "Lem_function" + "Lem" + +begin + + + +(*open import Maybe Bool Basic_classes Num Function*) + +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* getting a unique value *) +(* ----------------------- *) + +(*val THE : forall 'a. ('a -> bool) -> maybe 'a*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_list.thy b/snapshots/isabelle/lib/lem/Lem_list.thy new file mode 100644 index 00000000..3bdef057 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_list.thy @@ -0,0 +1,776 @@ +chapter \<open>Generated by Lem from list.lem.\<close> + +theory "Lem_list" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_basic_classes" + "Lem_function" + "Lem_tuple" + "Lem_num" + "Lem" + +begin + + + +(*open import Bool Maybe Basic_classes Function Tuple Num*) + +(*open import {coq} `Coq.Lists.List`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) +(*open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`*) + +(* ========================================================================== *) +(* Basic list functions *) +(* ========================================================================== *) + +(* The type of lists as well as list literals like [], [1;2], ... are hardcoded. + Thus, we can directly dive into derived definitions. *) + + +(* ----------------------- *) +(* cons *) +(* ----------------------- *) + +(*val :: : forall 'a. 'a -> list 'a -> list 'a*) + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. list 'a -> bool*) +(*let null l= match l with [] -> true | _ -> false end*) + +(* ----------------------- *) +(* Length *) +(* ----------------------- *) + +(*val length : forall 'a. list 'a -> nat*) +(*let rec length l= + match l with + | [] -> 0 + | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1 + end*) + +(* ----------------------- *) +(* Equality *) +(* ----------------------- *) + +(*val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + +fun listEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where + " listEqualBy eq ([]) ([]) = ( True )" +|" listEqualBy eq ([]) (_ # _) = ( False )" +|" listEqualBy eq (_ # _) ([]) = ( False )" +|" listEqualBy eq (x # xs) (y # ys) = ( (eq x y \<and> listEqualBy eq xs ys))" + + + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> ordering*) +(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a -> ordering*) + +fun lexicographicCompareBy :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> ordering " where + " lexicographicCompareBy cmp ([]) ([]) = ( EQ )" +|" lexicographicCompareBy cmp ([]) (_ # _) = ( LT )" +|" lexicographicCompareBy cmp (_ # _) ([]) = ( GT )" +|" lexicographicCompareBy cmp (x # xs) (y # ys) = ( ( + (case cmp x y of + LT => LT + | GT => GT + | EQ => lexicographicCompareBy cmp xs ys + ) + ))" + + +(*val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) +fun lexicographicLessBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where + " lexicographicLessBy less1 less_eq1 ([]) ([]) = ( False )" +|" lexicographicLessBy less1 less_eq1 ([]) (_ # _) = ( True )" +|" lexicographicLessBy less1 less_eq1 (_ # _) ([]) = ( False )" +|" lexicographicLessBy less1 less_eq1 (x # xs) (y # ys) = ( ((less1 x y) \<or> ((less_eq1 x y) \<and> (lexicographicLessBy less1 less_eq1 xs ys))))" + + +(*val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool*) +(*val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) +fun lexicographicLessEqBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where + " lexicographicLessEqBy less1 less_eq1 ([]) ([]) = ( True )" +|" lexicographicLessEqBy less1 less_eq1 ([]) (_ # _) = ( True )" +|" lexicographicLessEqBy less1 less_eq1 (_ # _) ([]) = ( False )" +|" lexicographicLessEqBy less1 less_eq1 (x # xs) (y # ys) = ( (less1 x y \<or> (less_eq1 x y \<and> lexicographicLessEqBy less1 less_eq1 xs ys)))" + + + +definition instance_Basic_classes_Ord_list_dict :: " 'a Ord_class \<Rightarrow>('a list)Ord_class " where + " instance_Basic_classes_Ord_list_dict dict_Basic_classes_Ord_a = ((| + + compare_method = (lexicographicCompareBy + (compare_method dict_Basic_classes_Ord_a)), + + isLess_method = (lexicographicLessBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)), + + isLessEqual_method = (lexicographicLessEqBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a)), + + isGreater_method = (\<lambda> x y. (lexicographicLessBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x)), + + isGreaterEqual_method = (\<lambda> x y. (lexicographicLessEqBy + (isLess_method dict_Basic_classes_Ord_a) (isLessEqual_method dict_Basic_classes_Ord_a) y x))|) )" + + + +(* ----------------------- *) +(* Append *) +(* ----------------------- *) + +(*val ++ : forall 'a. list 'a -> list 'a -> list 'a*) (* originally append *) +(*let rec ++ xs ys= match xs with + | [] -> ys + | x :: xs' -> x :: (xs' ++ ys) + end*) + +(* ----------------------- *) +(* snoc *) +(* ----------------------- *) + +(*val snoc : forall 'a. 'a -> list 'a -> list 'a*) +(*let snoc e l= l ++ [e]*) + + +(* ----------------------- *) +(* Reverse *) +(* ----------------------- *) + +(* First lets define the function [reverse_append], which is + closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1]. + This can be implemented more efficienctly than appending and is + used to implement reverse. *) + +(*val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a*) (* originally named rev_append *) +(*let rec reverseAppend l1 l2= match l1 with + | [] -> l2 + | x :: xs -> reverseAppend xs (x :: l2) + end*) + +(* Reversing a list *) +(*val reverse : forall 'a. list 'a -> list 'a*) (* originally named rev *) +(*let reverse l= reverseAppend l []*) + +(* ----------------------- *) +(* Map *) +(* ----------------------- *) + +(*val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b*) +function (sequential,domintros) map_tr :: " 'b list \<Rightarrow>('a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> 'b list " where + " map_tr rev_acc f ([]) = ( List.rev rev_acc )" +|" map_tr rev_acc f (x # xs) = ( map_tr ((f x) # rev_acc) f xs )" +by pat_completeness auto + + +(* taken from: https://blogs.janestreet.com/optimizing-list-map/ *) +(*val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b*) +function (sequential,domintros) count_map :: "('a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> nat \<Rightarrow> 'b list " where + " count_map f ([]) ctr = ( [])" +|" count_map f (hd1 # tl1) ctr = ( f hd1 # + (if ctr <( 5000 :: nat) then count_map f tl1 (ctr +( 1 :: nat)) + else map_tr [] f tl1))" +by pat_completeness auto + + +(*val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) +(*let map f l= count_map f l 0*) + +(* ----------------------- *) +(* Reverse Map *) +(* ----------------------- *) + +(*val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*) + + +(* ========================================================================== *) +(* Folding *) +(* ========================================================================== *) + +(* ----------------------- *) +(* fold left *) +(* ----------------------- *) + +(*val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a*) (* originally foldl *) + +(*let rec foldl f b l= match l with + | [] -> b + | x :: xs -> foldl f (f b x) xs +end*) + + +(* ----------------------- *) +(* fold right *) +(* ----------------------- *) + +(*val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b*) (* originally foldr with different argument order *) +(*let rec foldr f b l= match l with + | [] -> b + | x :: xs -> f x (foldr f b xs) +end*) + + +(* ----------------------- *) +(* concatenating lists *) +(* ----------------------- *) + +(*val concat : forall 'a. list (list 'a) -> list 'a*) (* before also called flatten *) +(*let concat= foldr (++) []*) + + +(* -------------------------- *) +(* concatenating with mapping *) +(* -------------------------- *) + +(*val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b*) + + +(* ------------------------- *) +(* universal qualification *) +(* ------------------------- *) + +(*val all : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally for_all *) +(*let all P l= foldl (fun r e -> P e && r) true l*) + + + +(* ------------------------- *) +(* existential qualification *) +(* ------------------------- *) + +(*val any : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally exist *) +(*let any P l= foldl (fun r e -> P e || r) false l*) + + +(* ------------------------- *) +(* dest_init *) +(* ------------------------- *) + +(* get the initial part and the last element of the list in a safe way *) + +(*val dest_init : forall 'a. list 'a -> maybe (list 'a * 'a)*) + +fun dest_init_aux :: " 'a list \<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list*'a " where + " dest_init_aux rev_init last_elem_seen ([]) = ( (List.rev rev_init, last_elem_seen))" +|" dest_init_aux rev_init last_elem_seen (x # xs) = ( dest_init_aux (last_elem_seen # rev_init) x xs )" + + +fun dest_init :: " 'a list \<Rightarrow>('a list*'a)option " where + " dest_init ([]) = ( None )" +|" dest_init (x # xs) = ( Some (dest_init_aux [] x xs))" + + + +(* ========================================================================== *) +(* Indexing lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* index / nth with maybe *) +(* ------------------------- *) + +(*val index : forall 'a. list 'a -> nat -> maybe 'a*) + +(*let rec index l n= match l with + | [] -> Nothing + | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then Just x else index xs ((Instance_Num_NumMinus_nat.-)n 1) +end*) + +(* ------------------------- *) +(* findIndices *) +(* ------------------------- *) + +(* [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P]. + Counting starts with 0, the result list is sorted ascendingly *) +(*val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat*) + +fun findIndices_aux :: " nat \<Rightarrow>('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow>(nat)list " where + " findIndices_aux (i::nat) P ([]) = ( [])" +|" findIndices_aux (i::nat) P (x # xs) = ( if P x then i # findIndices_aux (i +( 1 :: nat)) P xs else findIndices_aux (i +( 1 :: nat)) P xs )" + +(*let findIndices P l= findIndices_aux 0 P l*) + + + +(* ------------------------- *) +(* findIndex *) +(* ------------------------- *) + +(* findIndex returns the first index of a list that satisfies a given predicate. *) +(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> maybe nat*) +(*let findIndex P l= match findIndices P l with + | [] -> Nothing + | x :: _ -> Just x +end*) + +(* ------------------------- *) +(* elemIndices *) +(* ------------------------- *) + +(*val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat*) + +(* ------------------------- *) +(* elemIndex *) +(* ------------------------- *) + +(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> maybe nat*) + + +(* ========================================================================== *) +(* Creating lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* genlist *) +(* ------------------------- *) + +(* [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] *) +(*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*) + + +(*let rec genlist f n= + match n with + | 0 -> [] + | n' + 1 -> snoc (f n') (genlist f n') + end*) + + +(* ------------------------- *) +(* replicate *) +(* ------------------------- *) + +(*val replicate : forall 'a. nat -> 'a -> list 'a*) +(*let rec replicate n x= + match n with + | 0 -> [] + | n' + 1 -> x :: replicate n' x + end*) + + +(* ========================================================================== *) +(* Sublists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* splitAt *) +(* ------------------------- *) + +(* [splitAt n xs] returns a tuple (xs1, xs2), with append xs1 xs2 = xs and + length xs1 = n. If there are not enough elements + in [xs], the original list and the empty one are returned. *) +(*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*) +function (sequential,domintros) splitAtAcc :: " 'a list \<Rightarrow> nat \<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where + " splitAtAcc revAcc n l = ( + (case l of + [] => (List.rev revAcc, []) + | x # xs => if n \<le>( 0 :: nat) then (List.rev revAcc, l) else splitAtAcc (x # revAcc) (n-( 1 :: nat)) xs + ))" +by pat_completeness auto + + +(*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*) +(*let rec splitAt n l= + splitAtAcc [] n l*) + + +(* ------------------------- *) +(* take *) +(* ------------------------- *) + +(* take n xs returns the prefix of xs of length n, or xs itself if n > length xs *) +(*val take : forall 'a. nat -> list 'a -> list 'a*) +(*let take n l= fst (splitAt n l)*) + +(* ------------------------- *) +(* drop *) +(* ------------------------- *) + +(* [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. *) +(*val drop : forall 'a. nat -> list 'a -> list 'a*) +(*let drop n l= snd (splitAt n l)*) + +(* ------------------------------------ *) +(* splitWhile, takeWhile, and dropWhile *) +(* ------------------------------------ *) + +(*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*) +fun splitWhile_tr :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where + " splitWhile_tr p ([]) acc1 = ( + (List.rev acc1, []))" +|" splitWhile_tr p (x # xs) acc1 = ( + if p x then + splitWhile_tr p xs (x # acc1) + else + (List.rev acc1, (x # xs)))" + + +(*val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)*) +definition splitWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where + " splitWhile p xs = ( splitWhile_tr p xs [])" + + +(* [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. *) +(*val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +definition takeWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list " where + " takeWhile p l = ( fst (splitWhile p l))" + + +(* [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. *) +(*val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +definition dropWhile :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list " where + " dropWhile p l = ( snd (splitWhile p l))" + + +(* ------------------------- *) +(* isPrefixOf *) +(* ------------------------- *) + +(*val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +fun isPrefixOf :: " 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where + " isPrefixOf ([]) _ = ( True )" +|" isPrefixOf (_ # _) ([]) = ( False )" +|" isPrefixOf (x # xs) (y # ys) = ( (x = y) \<and> isPrefixOf xs ys )" + + +(* ------------------------- *) +(* update *) +(* ------------------------- *) +(*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*) +(*let rec update l n e= + match l with + | [] -> [] + | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e) +end*) + + + +(* ========================================================================== *) +(* Searching lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* Membership test *) +(* ------------------------- *) + +(* The membership test, one of the basic list functions, is actually tricky for + Lem, because it is tricky, which equality to use. From Lem`s point of + perspective, we want to use the equality provided by the equality type - class. + This allows for example to check whether a set is in a list of sets. + + However, in order to use the equality type class, elem essentially becomes + existential quantification over lists. For types, which implement semantic + equality (=) with syntactic equality, this is overly complicated. In + our theorem prover backend, we would end up with overly complicated, harder + to read definitions and some of the automation would be harder to apply. + Moreover, nearly all the old Lem generated code would change and require + (hopefully minor) adaptions of proofs. + + For now, we ignore this problem and just demand, that all instances of + the equality type class do the right thing for the theorem prover backends. +*) + +(*val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool*) +(*val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool*) + +definition elemBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> bool " where + " elemBy eq e l = ( ((\<exists> x \<in> (set l). (eq e) x)))" + +(*let elem= elemBy (=)*) + +(* ------------------------- *) +(* Find *) +(* ------------------------- *) +(*val find : forall 'a. ('a -> bool) -> list 'a -> maybe 'a*) (* previously not of maybe type *) +(*let rec find P l= match l with + | [] -> Nothing + | x :: xs -> if P x then Just x else find P xs +end*) + + +(* ----------------------------- *) +(* Lookup in an associative list *) +(* ----------------------------- *) +(*val lookup : forall 'a 'b. Eq 'a => 'a -> list ('a * 'b) -> maybe 'b*) +(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> maybe 'b*) + +(* DPM: eta-expansion for Coq backend type-inference. *) +definition lookupBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow>('a*'b)list \<Rightarrow> 'b option " where + " lookupBy eq k m = ( map_option (\<lambda> x . snd x) (List.find ( \<lambda>x . + (case x of (k', _) => eq k k' )) m))" + + +(* ------------------------- *) +(* filter *) +(* ------------------------- *) +(*val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a*) +(*let rec filter P l= match l with + | [] -> [] + | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs + end*) + + +(* ------------------------- *) +(* partition *) +(* ------------------------- *) +(*val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +(*let partition P l= (filter P l, filter (fun x -> not (P x)) l)*) + +(*val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*) +definition reversePartition :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list*'a list " where + " reversePartition P l = ( List.partition P (List.rev l))" + + + +(* ------------------------- *) +(* delete first element *) +(* with certain property *) +(* ------------------------- *) + +(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> maybe (list 'a)*) +(*let rec deleteFirst P l= match l with + | [] -> Nothing + | x :: xs -> if (P x) then Just xs else Maybe.map (fun xs' -> x :: xs') (deleteFirst P xs) + end*) + + +(*val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a*) +(*val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +definition deleteBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " deleteBy eq x l = ( case_option l id (delete_first (eq x) l))" + + + +(* ========================================================================== *) +(* Zipping and unzipping lists *) +(* ========================================================================== *) + +(* ------------------------- *) +(* zip *) +(* ------------------------- *) + +(* zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. *) +(*val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) (* before combine *) +(*let rec zip l1 l2= match (l1, l2) with + | (x :: xs, y :: ys) -> (x, y) :: zip xs ys + | _ -> [] +end*) + +(* ------------------------- *) +(* unzip *) +(* ------------------------- *) + +(*val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)*) +(*let rec unzip l= match l with + | [] -> ([], []) + | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys) +end*) + +(* ------------------------- *) +(* distinct elements *) +(* ------------------------- *) + +(*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*) +fun allDistinct :: " 'a list \<Rightarrow> bool " where + " allDistinct ([]) = ( True )" +|" allDistinct (x # l') = ( \<not> (Set.member x (set l')) \<and> allDistinct l' )" + + +(* some more useful functions *) +(*val mapMaybe : forall 'a 'b. ('a -> maybe 'b) -> list 'a -> list 'b*) +function (sequential,domintros) mapMaybe :: "('a \<Rightarrow> 'b option)\<Rightarrow> 'a list \<Rightarrow> 'b list " where + " mapMaybe f ([]) = ( [])" +|" mapMaybe f (x # xs) = ( + (case f x of + None => mapMaybe f xs + | Some y => y # (mapMaybe f xs) + ))" +by pat_completeness auto + + +(*val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b*) +function (sequential,domintros) mapiAux :: "(nat \<Rightarrow> 'b \<Rightarrow> 'a)\<Rightarrow> nat \<Rightarrow> 'b list \<Rightarrow> 'a list " where + " mapiAux f (n :: nat) ([]) = ( [])" +|" mapiAux f (n :: nat) (x # xs) = ( (f n x) # mapiAux f (n +( 1 :: nat)) xs )" +by pat_completeness auto + +definition mapi :: "(nat \<Rightarrow> 'a \<Rightarrow> 'b)\<Rightarrow> 'a list \<Rightarrow> 'b list " where + " mapi f l = ( mapiAux f(( 0 :: nat)) l )" + + +(*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*) +definition deletes :: " 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " deletes xs ys = ( + List.foldl ((\<lambda> x y. remove1 y x)) xs ys )" + + +(* ========================================================================== *) +(* Comments (not clean yet, please ignore the rest of the file) *) +(* ========================================================================== *) + +(* ----------------------- *) +(* skipped from Haskell Lib*) +(* ----------------------- + +intersperse :: a -> [a] -> [a] +intercalate :: [a] -> [[a]] -> [a] +transpose :: [[a]] -> [[a]] +subsequences :: [a] -> [[a]] +permutations :: [a] -> [[a]] +foldl` :: (a -> b -> a) -> a -> [b] -> aSource +foldl1` :: (a -> a -> a) -> [a] -> aSource + +and +or +sum +product +maximum +minimum +scanl +scanr +scanl1 +scanr1 +Accumulating maps + +mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source +mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source + +iterate :: (a -> a) -> a -> [a] +repeat :: a -> [a] +cycle :: [a] -> [a] +unfoldr + + +takeWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhile :: (a -> Bool) -> [a] -> [a]Source +dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source +span :: (a -> Bool) -> [a] -> ([a], [a])Source +break :: (a -> Bool) -> [a] -> ([a], [a])Source +break p is equivalent to span (not . p). +stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source +group :: Eq a => [a] -> [[a]]Source +inits :: [a] -> [[a]]Source +tails :: [a] -> [[a]]Source + + +isPrefixOf :: Eq a => [a] -> [a] -> BoolSource +isSuffixOf :: Eq a => [a] -> [a] -> BoolSource +isInfixOf :: Eq a => [a] -> [a] -> BoolSource + + + +notElem :: Eq a => a -> [a] -> BoolSource + +zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source +zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source +zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source +zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source +zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source + +zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source +zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source +zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source +zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source +zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source +zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source + + +unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source +unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source +unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source +unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source +unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source + + +lines :: String -> [String]Source +words :: String -> [String]Source +unlines :: [String] -> StringSource +unwords :: [String] -> StringSource +nub :: Eq a => [a] -> [a]Source +delete :: Eq a => a -> [a] -> [a]Source + +() :: Eq a => [a] -> [a] -> [a]Source +union :: Eq a => [a] -> [a] -> [a]Source +intersect :: Eq a => [a] -> [a] -> [a]Source +sort :: Ord a => [a] -> [a]Source +insert :: Ord a => a -> [a] -> [a]Source + + +nubBy :: (a -> a -> Bool) -> [a] -> [a]Source +deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source +deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source +groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source +sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source +insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source +maximumBy :: (a -> a -> Ordering) -> [a] -> aSource +minimumBy :: (a -> a -> Ordering) -> [a] -> aSource +genericLength :: Num i => [b] -> iSource +genericTake :: Integral i => i -> [a] -> [a]Source +genericDrop :: Integral i => i -> [a] -> [a]Source +genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source +genericIndex :: Integral a => [b] -> a -> bSource +genericReplicate :: Integral i => i -> a -> [a]Source + + +*) + + +(* ----------------------- *) +(* skipped from Lem Lib *) +(* ----------------------- + + +val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool +val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c +val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a +val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c + + +(* now maybe result and called lookup *) +val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b +let inline {ocaml} assoc = Ocaml.List.assoc + + +val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool +val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b) + + + +val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a +val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a + +val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a +val intersect : forall 'a. list 'a -> list 'a -> list 'a + + +*) + +(*val catMaybes : forall 'a. list (maybe 'a) -> list 'a*) +function (sequential,domintros) catMaybes :: "('a option)list \<Rightarrow> 'a list " where + " catMaybes ([]) = ( + [])" +|" catMaybes (None # xs') = ( + catMaybes xs' )" +|" catMaybes (Some x # xs') = ( + x # catMaybes xs' )" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/lem/Lem_list_extra.thy b/snapshots/isabelle/lib/lem/Lem_list_extra.thy new file mode 100644 index 00000000..9caf32fc --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_list_extra.thy @@ -0,0 +1,117 @@ +chapter \<open>Generated by Lem from list_extra.lem.\<close> + +theory "Lem_list_extra" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_basic_classes" + "Lem_tuple" + "Lem_num" + "Lem_list" + "Lem_assert_extra" + +begin + + + +(*open import Bool Maybe Basic_classes Tuple Num List Assert_extra*) + +(* ------------------------- *) +(* head of non-empty list *) +(* ------------------------- *) +(*val head : forall 'a. list 'a -> 'a*) +(*let head l= match l with | x::xs -> x | [] -> failwith List_extra.head of empty list end*) + + +(* ------------------------- *) +(* tail of non-empty list *) +(* ------------------------- *) +(*val tail : forall 'a. list 'a -> list 'a*) +(*let tail l= match l with | x::xs -> xs | [] -> failwith List_extra.tail of empty list end*) + + +(* ------------------------- *) +(* last *) +(* ------------------------- *) +(*val last : forall 'a. list 'a -> 'a*) +(*let rec last l= match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith List_extra.last of empty list end*) + + +(* ------------------------- *) +(* init *) +(* ------------------------- *) + +(* All elements of a non-empty list except the last one. *) +(*val init : forall 'a. list 'a -> list 'a*) +(*let rec init l= match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith List_extra.init of empty list end*) + + +(* ------------------------- *) +(* foldl1 / foldr1 *) +(* ------------------------- *) + +(* folding functions for non-empty lists, + which don`t take the base case *) +(*val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +fun foldl1 :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a " where + " foldl1 f (x # xs) = ( List.foldl f x xs )" +|" foldl1 f ([]) = ( failwith (''List_extra.foldl1 of empty list''))" + + +(*val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*) +fun foldr1 :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a " where + " foldr1 f (x # xs) = ( List.foldr f xs x )" +|" foldr1 f ([]) = ( failwith (''List_extra.foldr1 of empty list''))" + + + +(* ------------------------- *) +(* nth element *) +(* ------------------------- *) + +(* get the nth element of a list *) +(*val nth : forall 'a. list 'a -> nat -> 'a*) +(*let nth l n= match index l n with Just e -> e | Nothing -> failwith List_extra.nth end*) + + +(* ------------------------- *) +(* Find_non_pure *) +(* ------------------------- *) +(*val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a*) +definition findNonPure :: "('a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a " where + " findNonPure P l = ( (case (List.find P l) of + Some e => e + | None => failwith (''List_extra.findNonPure'') +))" + + + +(* ------------------------- *) +(* zip same length *) +(* ------------------------- *) + +(*val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) +fun zipSameLength :: " 'a list \<Rightarrow> 'b list \<Rightarrow>('a*'b)list " where + " zipSameLength l1 l2 = ( (case (l1, l2) of + (x # xs, y # ys) => (x, y) # zipSameLength xs ys + | ([], []) => [] + | _ => failwith (''List_extra.zipSameLength of different length lists'') + +))" + + +(*val unfoldr: forall 'a 'b. ('a -> maybe ('b * 'a)) -> 'a -> list 'b*) +function (sequential,domintros) unfoldr :: "('a \<Rightarrow>('b*'a)option)\<Rightarrow> 'a \<Rightarrow> 'b list " where + " unfoldr f x = ( + (case f x of + Some (y, x') => + y # unfoldr f x' + | None => + [] + ))" +by pat_completeness auto + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_machine_word.thy b/snapshots/isabelle/lib/lem/Lem_machine_word.thy new file mode 100644 index 00000000..3f83789c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_machine_word.thy @@ -0,0 +1,450 @@ +chapter \<open>Generated by Lem from machine_word.lem.\<close> + +theory "Lem_machine_word" + +imports + Main + "Lem_bool" + "Lem_num" + "Lem_basic_classes" + "Lem_show" + "~~/src/HOL/Word/Word" + +begin + + + +(*open import Bool Num Basic_classes Show*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*) + +(*type mword 'a*) + +(*class (Size 'a) + val size : nat +end*) + +(*val native_size : forall 'a. nat*) + +(*val ocaml_inject : forall 'a. nat * natural -> mword 'a*) + +(* A singleton type family that can be used to carry a size as the type parameter *) + +(*type itself 'a*) + +(*val the_value : forall 'a. itself 'a*) + +(*val size_itself : forall 'a. Size 'a => itself 'a -> nat*) +definition size_itself :: "('a::len)itself \<Rightarrow> nat " where + " size_itself x = ( (len_of (TYPE(_) :: 'a itself)))" + + +(*******************************************************************) +(* Fixed bitwidths extracted from Anthony's models. *) +(* *) +(* If you need a size N that is not included here, put the lines *) +(* *) +(* type tyN *) +(* instance (Size tyN) let size = N end *) +(* declare isabelle target_rep type tyN = `N` *) +(* declare hol target_rep type tyN = `N` *) +(* *) +(* in your project, replacing N in each line. *) +(*******************************************************************) + +(*type ty1*) +(*type ty2*) +(*type ty3*) +(*type ty4*) +(*type ty5*) +(*type ty6*) +(*type ty7*) +(*type ty8*) +(*type ty9*) +(*type ty10*) +(*type ty11*) +(*type ty12*) +(*type ty13*) +(*type ty14*) +(*type ty15*) +(*type ty16*) +(*type ty17*) +(*type ty18*) +(*type ty19*) +(*type ty20*) +(*type ty21*) +(*type ty22*) +(*type ty23*) +(*type ty24*) +(*type ty25*) +(*type ty26*) +(*type ty27*) +(*type ty28*) +(*type ty29*) +(*type ty30*) +(*type ty31*) +(*type ty32*) +(*type ty33*) +(*type ty34*) +(*type ty35*) +(*type ty36*) +(*type ty37*) +(*type ty38*) +(*type ty39*) +(*type ty40*) +(*type ty41*) +(*type ty42*) +(*type ty43*) +(*type ty44*) +(*type ty45*) +(*type ty46*) +(*type ty47*) +(*type ty48*) +(*type ty49*) +(*type ty50*) +(*type ty51*) +(*type ty52*) +(*type ty53*) +(*type ty54*) +(*type ty55*) +(*type ty56*) +(*type ty57*) +(*type ty58*) +(*type ty59*) +(*type ty60*) +(*type ty61*) +(*type ty62*) +(*type ty63*) +(*type ty64*) +(*type ty65*) +(*type ty66*) +(*type ty67*) +(*type ty68*) +(*type ty69*) +(*type ty70*) +(*type ty71*) +(*type ty72*) +(*type ty73*) +(*type ty74*) +(*type ty75*) +(*type ty76*) +(*type ty77*) +(*type ty78*) +(*type ty79*) +(*type ty80*) +(*type ty81*) +(*type ty82*) +(*type ty83*) +(*type ty84*) +(*type ty85*) +(*type ty86*) +(*type ty87*) +(*type ty88*) +(*type ty89*) +(*type ty90*) +(*type ty91*) +(*type ty92*) +(*type ty93*) +(*type ty94*) +(*type ty95*) +(*type ty96*) +(*type ty97*) +(*type ty98*) +(*type ty99*) +(*type ty100*) +(*type ty101*) +(*type ty102*) +(*type ty103*) +(*type ty104*) +(*type ty105*) +(*type ty106*) +(*type ty107*) +(*type ty108*) +(*type ty109*) +(*type ty110*) +(*type ty111*) +(*type ty112*) +(*type ty113*) +(*type ty114*) +(*type ty115*) +(*type ty116*) +(*type ty117*) +(*type ty118*) +(*type ty119*) +(*type ty120*) +(*type ty121*) +(*type ty122*) +(*type ty123*) +(*type ty124*) +(*type ty125*) +(*type ty126*) +(*type ty127*) +(*type ty128*) +(*type ty129*) +(*type ty130*) +(*type ty131*) +(*type ty132*) +(*type ty133*) +(*type ty134*) +(*type ty135*) +(*type ty136*) +(*type ty137*) +(*type ty138*) +(*type ty139*) +(*type ty140*) +(*type ty141*) +(*type ty142*) +(*type ty143*) +(*type ty144*) +(*type ty145*) +(*type ty146*) +(*type ty147*) +(*type ty148*) +(*type ty149*) +(*type ty150*) +(*type ty151*) +(*type ty152*) +(*type ty153*) +(*type ty154*) +(*type ty155*) +(*type ty156*) +(*type ty157*) +(*type ty158*) +(*type ty159*) +(*type ty160*) +(*type ty161*) +(*type ty162*) +(*type ty163*) +(*type ty164*) +(*type ty165*) +(*type ty166*) +(*type ty167*) +(*type ty168*) +(*type ty169*) +(*type ty170*) +(*type ty171*) +(*type ty172*) +(*type ty173*) +(*type ty174*) +(*type ty175*) +(*type ty176*) +(*type ty177*) +(*type ty178*) +(*type ty179*) +(*type ty180*) +(*type ty181*) +(*type ty182*) +(*type ty183*) +(*type ty184*) +(*type ty185*) +(*type ty186*) +(*type ty187*) +(*type ty188*) +(*type ty189*) +(*type ty190*) +(*type ty191*) +(*type ty192*) +(*type ty193*) +(*type ty194*) +(*type ty195*) +(*type ty196*) +(*type ty197*) +(*type ty198*) +(*type ty199*) +(*type ty200*) +(*type ty201*) +(*type ty202*) +(*type ty203*) +(*type ty204*) +(*type ty205*) +(*type ty206*) +(*type ty207*) +(*type ty208*) +(*type ty209*) +(*type ty210*) +(*type ty211*) +(*type ty212*) +(*type ty213*) +(*type ty214*) +(*type ty215*) +(*type ty216*) +(*type ty217*) +(*type ty218*) +(*type ty219*) +(*type ty220*) +(*type ty221*) +(*type ty222*) +(*type ty223*) +(*type ty224*) +(*type ty225*) +(*type ty226*) +(*type ty227*) +(*type ty228*) +(*type ty229*) +(*type ty230*) +(*type ty231*) +(*type ty232*) +(*type ty233*) +(*type ty234*) +(*type ty235*) +(*type ty236*) +(*type ty237*) +(*type ty238*) +(*type ty239*) +(*type ty240*) +(*type ty241*) +(*type ty242*) +(*type ty243*) +(*type ty244*) +(*type ty245*) +(*type ty246*) +(*type ty247*) +(*type ty248*) +(*type ty249*) +(*type ty250*) +(*type ty251*) +(*type ty252*) +(*type ty253*) +(*type ty254*) +(*type ty255*) +(*type ty256*) +(*type ty257*) + +(*val word_length : forall 'a. mword 'a -> nat*) + +(******************************************************************) +(* Conversions *) +(******************************************************************) + +(*val signedIntegerFromWord : forall 'a. mword 'a -> integer*) + +(*val unsignedIntegerFromWord : forall 'a. mword 'a -> integer*) + +(* Version without typeclass constraint so that we can derive operations + in Lem for one of the theorem provers without requiring it. *) +(*val proverWordFromInteger : forall 'a. integer -> mword 'a*) + +(*val wordFromInteger : forall 'a. Size 'a => integer -> mword 'a*) +(* The OCaml version is defined after the arithmetic operations, below. *) + +(*val naturalFromWord : forall 'a. mword 'a -> natural*) + +(*val wordFromNatural : forall 'a. Size 'a => natural -> mword 'a*) + +(*val wordToHex : forall 'a. mword 'a -> string*) +(* Building libraries fails if we don't provide implementations for the + type class. *) +definition wordToHex :: "('a::len)Word.word \<Rightarrow> string " where + " wordToHex w = ( (''wordToHex not yet implemented''))" + + +definition instance_Show_Show_Machine_word_mword_dict :: "(('a::len)Word.word)Show_class " where + " instance_Show_Show_Machine_word_mword_dict = ((| + + show_method = wordToHex |) )" + + +(*val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a*) + +(*val bitlistFromWord : forall 'a. mword 'a -> list bool*) + + +(*val size_test_fn : forall 'a. Size 'a => mword 'a -> nat*) +definition size_test_fn :: "('a::len)Word.word \<Rightarrow> nat " where + " size_test_fn _ = ( (len_of (TYPE(_) :: 'a itself)))" + + +(******************************************************************) +(* Comparisons *) +(******************************************************************) + +(*val mwordEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool*) + +(*val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool*) + +(* Comparison tests are below, after the definition of wordFromInteger *) + +(******************************************************************) +(* Appending, splitting and probing words *) +(******************************************************************) + +(*val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c*) + +(* Note that we assume the result type has the correct size, especially + for Isabelle. *) +(*val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b*) + +(* Needs to be in the prover because we'd end up with unknown sizes in the + types in Lem. +*) +(*val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a*) + +(*val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a*) + +(*val getBit : forall 'a. mword 'a -> nat -> bool*) + +(*val msb : forall 'a. mword 'a -> bool*) + +(*val lsb : forall 'a. mword 'a -> bool*) + +(******************************************************************) +(* Bitwise operations, shifts, etc. *) +(******************************************************************) + +(*val shiftLeft : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val shiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a*) + +(*val lAnd : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lOr : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lXor : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val lNot : forall 'a. mword 'a -> mword 'a*) + +(*val rotateRight : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a*) + +(*val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(*val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*) + +(* Sign extension tests are below, after the definition of wordFromInteger *) + +(*****************************************************************) +(* Arithmetic *) +(*****************************************************************) + +(*val plus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val minus : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val uminus : forall 'a. mword 'a -> mword 'a*) + +(*val times : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +(*val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) +(*val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*) + +definition signedDivide :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " signedDivide x y = ( + if Bits.msb x then + if Bits.msb y then (- x) div (- y) + else - ((- x) div y) + else if Bits.msb y then - (x div (- y)) + else x div y )" + + +(*val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_map.thy b/snapshots/isabelle/lib/lem/Lem_map.thy new file mode 100644 index 00000000..fbaed71a --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_map.thy @@ -0,0 +1,159 @@ +chapter \<open>Generated by Lem from map.lem.\<close> + +theory "Lem_map" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + "Lem_maybe" + "Lem_list" + "Lem_tuple" + "Lem_set" + "Lem_num" + +begin + + + +(*open import Bool Basic_classes Function Maybe List Tuple Set Num*) +(*open import {hol} `finite_mapTheory` `finite_mapLib`*) + +(*type map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Map equality. *) +(* -------------------------------------------------------------------------- *) + +(*val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool*) +(*val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* Map type class *) +(* -------------------------------------------------------------------------- *) + +(*class ( MapKeyType 'a ) + val {ocaml;coq} mapKeyCompare : 'a -> 'a -> ordering +end*) + +(* -------------------------------------------------------------------------- *) +(* Empty maps *) +(* -------------------------------------------------------------------------- *) + +(*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*) +(*val emptyBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Insertion *) +(* -------------------------------------------------------------------------- *) + +(*val insert : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Singleton *) +(* -------------------------------------------------------------------------- *) + +(*val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v*) + + + +(* -------------------------------------------------------------------------- *) +(* Emptyness check *) +(* -------------------------------------------------------------------------- *) + +(*val null : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool*) + + +(* -------------------------------------------------------------------------- *) +(* lookup *) +(* -------------------------------------------------------------------------- *) + +(*val lookupBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> maybe 'v*) + +(*val lookup : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> maybe 'v*) + +(* -------------------------------------------------------------------------- *) +(* findWithDefault *) +(* -------------------------------------------------------------------------- *) + +(*val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v*) + +(* -------------------------------------------------------------------------- *) +(* from lists *) +(* -------------------------------------------------------------------------- *) + +(*val fromList : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v*) +(*let fromList l= foldl (fun m (k,v) -> insert k v m) empty l*) + + +(* -------------------------------------------------------------------------- *) +(* to sets / domain / range *) +(* -------------------------------------------------------------------------- *) + +(*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*) +(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> ordering) -> map 'k 'v -> set ('k * 'v)*) + + +(*val domainBy : forall 'k 'v. ('k -> 'k -> ordering) -> map 'k 'v -> set 'k*) +(*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*) + + +(*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*) +(*val rangeBy : forall 'k 'v. ('v -> 'v -> ordering) -> map 'k 'v -> set 'v*) + + +(* -------------------------------------------------------------------------- *) +(* member *) +(* -------------------------------------------------------------------------- *) + +(*val member : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(*val notMember : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*) + +(* -------------------------------------------------------------------------- *) +(* Quantification *) +(* -------------------------------------------------------------------------- *) + +(*val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) +(*val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) + +(*let all P m= (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))*) + + +(* -------------------------------------------------------------------------- *) +(* Set-like operations. *) +(* -------------------------------------------------------------------------- *) +(*val deleteBy : forall 'k 'v. ('k -> 'k -> ordering) -> 'k -> map 'k 'v -> map 'k 'v*) +(*val delete : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*) +(*val deleteSwap : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*) + +(*val union : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v*) + +(*val unions : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v*) + + +(* -------------------------------------------------------------------------- *) +(* Maps (in the functor sense). *) +(* -------------------------------------------------------------------------- *) + +(*val map : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(*val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w*) + +(* -------------------------------------------------------------------------- *) +(* Cardinality *) +(* -------------------------------------------------------------------------- *) +(*val size : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat*) + +(* instance of SetType *) +definition map_setElemCompare :: "(('d*'c)set \<Rightarrow>('b*'a)set \<Rightarrow> 'e)\<Rightarrow>('d,'c)Map.map \<Rightarrow>('b,'a)Map.map \<Rightarrow> 'e " where + " map_setElemCompare cmp x y = ( + cmp (map_to_set x) (map_to_set y))" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_map_extra.thy b/snapshots/isabelle/lib/lem/Lem_map_extra.thy new file mode 100644 index 00000000..4117fe81 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_map_extra.thy @@ -0,0 +1,82 @@ +chapter \<open>Generated by Lem from map_extra.lem.\<close> + +theory "Lem_map_extra" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + "Lem_assert_extra" + "Lem_maybe" + "Lem_list" + "Lem_num" + "Lem_set" + "Lem_map" + +begin + + + +(*open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map*) + +(* -------------------------------------------------------------------------- *) +(* find *) +(* -------------------------------------------------------------------------- *) + +(*val find : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> 'v*) +(*let find k m= match (lookup k m) with Just x -> x | Nothing -> failwith Map_extra.find end*) + + + +(* -------------------------------------------------------------------------- *) +(* from sets / domain / range *) +(* -------------------------------------------------------------------------- *) + + +(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> map 'k 'v*) +definition fromSet :: "('k \<Rightarrow> 'v)\<Rightarrow> 'k set \<Rightarrow>('k,'v)Map.map " where + " fromSet f s = ( Finite_Set.fold (\<lambda> k m . map_update k (f k) m) Map.empty s )" + + +(* +assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty) +assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)] +*) + +(* -------------------------------------------------------------------------- *) +(* fold *) +(* -------------------------------------------------------------------------- *) + +(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> map 'k 'v -> 'r -> 'r*) +definition fold :: "('k \<Rightarrow> 'v \<Rightarrow> 'r \<Rightarrow> 'r)\<Rightarrow>('k,'v)Map.map \<Rightarrow> 'r \<Rightarrow> 'r " where + " fold f m v = ( Finite_Set.fold ( \<lambda>x . + (case x of (k, v) => \<lambda> r . f k v r )) v (map_to_set m))" + + +(* +assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9) +assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12) +*) + +(*val toList: forall 'k 'v. MapKeyType 'k => map 'k 'v -> list ('k * 'v)*) +(* declare compile_message toList = Map_extra.toList is only defined for the ocaml, isabelle and coq backend *) + +(* more 'map' functions *) + +(* TODO: this function is in map_extra rather than map just for implementation reasons *) +(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> maybe 'c) -> map 'a 'b -> map 'a 'c*) +(* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *) +definition option_map :: "('a \<Rightarrow> 'b \<Rightarrow> 'c option)\<Rightarrow>('a,'b)Map.map \<Rightarrow>('a,'c)Map.map " where + " option_map f m = ( + List.foldl + (\<lambda> m' . \<lambda>x . + (case x of + (k, v) => + (case f k v of None => m' | Some v' => map_update k v' m' ) + )) + Map.empty + (list_of_set (LemExtraDefs.map_to_set m)))" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_maybe.thy b/snapshots/isabelle/lib/lem/Lem_maybe.thy new file mode 100644 index 00000000..da0bde92 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_maybe.thy @@ -0,0 +1,113 @@ +chapter \<open>Generated by Lem from maybe.lem.\<close> + +theory "Lem_maybe" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_function" + +begin + + + +(*open import Bool Basic_classes Function*) + +(* ========================================================================== *) +(* Basic stuff *) +(* ========================================================================== *) + +(*type maybe 'a = + | Nothing + | Just of 'a*) + + +(*val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool*) +(*val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool*) + +fun maybeEqualBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a option \<Rightarrow> 'a option \<Rightarrow> bool " where + " maybeEqualBy eq None None = ( True )" +|" maybeEqualBy eq None (Some _) = ( False )" +|" maybeEqualBy eq (Some _) None = ( False )" +|" maybeEqualBy eq (Some x') (Some y') = ( (eq x' y'))" + + + +fun maybeCompare :: "('b \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'b option \<Rightarrow> 'a option \<Rightarrow> ordering " where + " maybeCompare cmp None None = ( EQ )" +|" maybeCompare cmp None (Some _) = ( LT )" +|" maybeCompare cmp (Some _) None = ( GT )" +|" maybeCompare cmp (Some x') (Some y') = ( cmp x' y' )" + + +definition instance_Basic_classes_Ord_Maybe_maybe_dict :: " 'a Ord_class \<Rightarrow>('a option)Ord_class " where + " instance_Basic_classes_Ord_Maybe_maybe_dict dict_Basic_classes_Ord_a = ((| + + compare_method = (maybeCompare + (compare_method dict_Basic_classes_Ord_a)), + + isLess_method = (\<lambda> m1 . (\<lambda> m2 . maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2 = LT)), + + isLessEqual_method = (\<lambda> m1 . (\<lambda> m2 . ((let r = (maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = LT) \<or> (r = EQ))))), + + isGreater_method = (\<lambda> m1 . (\<lambda> m2 . maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2 = GT)), + + isGreaterEqual_method = (\<lambda> m1 . (\<lambda> m2 . ((let r = (maybeCompare + (compare_method dict_Basic_classes_Ord_a) m1 m2) in (r = GT) \<or> (r = EQ)))))|) )" + + +(* ----------------------- *) +(* maybe *) +(* ----------------------- *) + +(*val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b*) +(*let maybe d f mb= match mb with + | Just a -> f a + | Nothing -> d +end*) + +(* ----------------------- *) +(* isJust / isNothing *) +(* ----------------------- *) + +(*val isJust : forall 'a. maybe 'a -> bool*) +(*let isJust mb= match mb with + | Just _ -> true + | Nothing -> false +end*) + +(*val isNothing : forall 'a. maybe 'a -> bool*) +(*let isNothing mb= match mb with + | Just _ -> false + | Nothing -> true +end*) + +(* ----------------------- *) +(* fromMaybe *) +(* ----------------------- *) + +(*val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a*) +(*let fromMaybe d mb= match mb with + | Just v -> v + | Nothing -> d +end*) + +(* ----------------------- *) +(* map *) +(* ----------------------- *) + +(*val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b*) +(*let map f= maybe Nothing (fun v -> Just (f v))*) + + +(* ----------------------- *) +(* bind *) +(* ----------------------- *) + +(*val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b*) +(*let bind mb f= maybe Nothing f mb*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy b/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy new file mode 100644 index 00000000..0a57814c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_maybe_extra.thy @@ -0,0 +1,24 @@ +chapter \<open>Generated by Lem from maybe_extra.lem.\<close> + +theory "Lem_maybe_extra" + +imports + Main + "Lem_basic_classes" + "Lem_maybe" + "Lem_assert_extra" + +begin + + + +(*open import Basic_classes Maybe Assert_extra*) + +(* ----------------------- *) +(* fromJust *) +(* ----------------------- *) + +(*val fromJust : forall 'a. maybe 'a -> 'a*) +(*let fromJust op= match op with | Just v -> v | Nothing -> failwith fromJust of Nothing end*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_num.thy b/snapshots/isabelle/lib/lem/Lem_num.thy new file mode 100644 index 00000000..0d7a72ea --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_num.thy @@ -0,0 +1,1302 @@ +chapter \<open>Generated by Lem from num.lem.\<close> + +theory "Lem_num" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "~~/src/HOL/Word/Word" + "Real" + "~~/src/HOL/NthRoot" + +begin + + + +(*open import Bool Basic_classes*) +(*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*) +(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*) +(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) + +(*class inline ( Numeral 'a ) + val fromNumeral : numeral -> 'a +end*) + +(* ========================================================================== *) +(* Syntactic type-classes for common operations *) +(* ========================================================================== *) + +(* Typeclasses can be used as a mean to overload constants like +, -, etc *) + +record 'a NumNegate_class= + + numNegate_method ::" 'a \<Rightarrow> 'a " + + + +record 'a NumAbs_class= + + abs_method ::" 'a \<Rightarrow> 'a " + + + +record 'a NumAdd_class= + + numAdd_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a NumMinus_class= + + numMinus_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a NumMult_class= + + numMult_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a NumPow_class= + + numPow_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a " + + + +record 'a NumDivision_class= + + numDivision_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a NumIntegerDivision_class= + + div_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + + +record 'a NumRemainder_class= + + mod_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a NumSucc_class= + + succ_method ::" 'a \<Rightarrow> 'a " + + + +record 'a NumPred_class= + + pred_method ::" 'a \<Rightarrow> 'a " + + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* unbounded size natural numbers *) +(*type natural*) + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* bounded size integers with uncertain length *) + +(*type int*) + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(* unbounded size integers *) + +(*type integer*) + +(* ----------------------- *) +(* bint *) +(* ----------------------- *) + +(* TODO the bounded ints are only partially implemented, use with care. *) + +(* 32 bit integers *) +(*type int32*) + +(* 64 bit integers *) +(*type int64*) + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(* unbounded size and precision rational numbers *) + +(*type rational*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(* real numbers *) +(* Note that for OCaml, this is mapped to floats with 64 bits. *) + +(*type real*) (* ???: better type for this in HOL? *) + + +(* ----------------------- *) +(* double *) +(* ----------------------- *) + +(* double precision floating point (64 bits) *) + +(*type float64*) (* ???: better type for this in HOL? *) + +(*type float32*) (* ???: better type for this in HOL? *) + + +(* ========================================================================== *) +(* Binding the standard operations for the number types *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(*val natFromNumeral : numeral -> nat*) + +(*val natEq : nat -> nat -> bool*) + +(*val natLess : nat -> nat -> bool*) +(*val natLessEqual : nat -> nat -> bool*) +(*val natGreater : nat -> nat -> bool*) +(*val natGreaterEqual : nat -> nat -> bool*) + +(*val natCompare : nat -> nat -> ordering*) + +definition instance_Basic_classes_Ord_nat_dict :: "(nat)Ord_class " where + " instance_Basic_classes_Ord_nat_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val natAdd : nat -> nat -> nat*) + +definition instance_Num_NumAdd_nat_dict :: "(nat)NumAdd_class " where + " instance_Num_NumAdd_nat_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val natMinus : nat -> nat -> nat*) + +definition instance_Num_NumMinus_nat_dict :: "(nat)NumMinus_class " where + " instance_Num_NumMinus_nat_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val natSucc : nat -> nat*) +(*let natSucc n= (Instance_Num_NumAdd_nat.+) n 1*) +definition instance_Num_NumSucc_nat_dict :: "(nat)NumSucc_class " where + " instance_Num_NumSucc_nat_dict = ((| + + succ_method = Suc |) )" + + +(*val natPred : nat -> nat*) +definition instance_Num_NumPred_nat_dict :: "(nat)NumPred_class " where + " instance_Num_NumPred_nat_dict = ((| + + pred_method = (\<lambda> n. n -( 1 :: nat))|) )" + + +(*val natMult : nat -> nat -> nat*) + +definition instance_Num_NumMult_nat_dict :: "(nat)NumMult_class " where + " instance_Num_NumMult_nat_dict = ((| + + numMult_method = (op*)|) )" + + +(*val natDiv : nat -> nat -> nat*) + +definition instance_Num_NumIntegerDivision_nat_dict :: "(nat)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_nat_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_nat_dict :: "(nat)NumDivision_class " where + " instance_Num_NumDivision_nat_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val natMod : nat -> nat -> nat*) + +definition instance_Num_NumRemainder_nat_dict :: "(nat)NumRemainder_class " where + " instance_Num_NumRemainder_nat_dict = ((| + + mod_method = (op mod)|) )" + + + +(*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*) +fun gen_pow_aux :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where + " gen_pow_aux (mul :: 'a \<Rightarrow> 'a \<Rightarrow> 'a) (a :: 'a) (b :: 'a) (e :: nat) = ( + (case e of + 0 => a (* cannot happen, call discipline guarentees e >= 1 *) + | (Suc 0) => mul a b + | ( (Suc(Suc e'))) => (let e'' = (e div( 2 :: nat)) in + (let a' = (if (e mod( 2 :: nat)) =( 0 :: nat) then a else mul a b) in + gen_pow_aux mul a' (mul b b) e'')) + ))" + + +definition gen_pow :: " 'a \<Rightarrow>('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where + " gen_pow (one :: 'a) (mul :: 'a \<Rightarrow> 'a \<Rightarrow> 'a) (b :: 'a) (e :: nat) = ( + if e <( 0 :: nat) then one else + if (e =( 0 :: nat)) then one else gen_pow_aux mul one b e )" + + +(*val natPow : nat -> nat -> nat*) + +definition instance_Num_NumPow_nat_dict :: "(nat)NumPow_class " where + " instance_Num_NumPow_nat_dict = ((| + + numPow_method = (op^)|) )" + + +(*val natMin : nat -> nat -> nat*) + +(*val natMax : nat -> nat -> nat*) + +definition instance_Basic_classes_OrdMaxMin_nat_dict :: "(nat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_nat_dict = ((| + + max_method = max, + + min_method = min |) )" + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(*val naturalFromNumeral : numeral -> natural*) + +(*val naturalEq : natural -> natural -> bool*) + +(*val naturalLess : natural -> natural -> bool*) +(*val naturalLessEqual : natural -> natural -> bool*) +(*val naturalGreater : natural -> natural -> bool*) +(*val naturalGreaterEqual : natural -> natural -> bool*) + +(*val naturalCompare : natural -> natural -> ordering*) + +definition instance_Basic_classes_Ord_Num_natural_dict :: "(nat)Ord_class " where + " instance_Basic_classes_Ord_Num_natural_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val naturalAdd : natural -> natural -> natural*) + +definition instance_Num_NumAdd_Num_natural_dict :: "(nat)NumAdd_class " where + " instance_Num_NumAdd_Num_natural_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val naturalMinus : natural -> natural -> natural*) + +definition instance_Num_NumMinus_Num_natural_dict :: "(nat)NumMinus_class " where + " instance_Num_NumMinus_Num_natural_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val naturalSucc : natural -> natural*) +(*let naturalSucc n= (Instance_Num_NumAdd_Num_natural.+) n 1*) +definition instance_Num_NumSucc_Num_natural_dict :: "(nat)NumSucc_class " where + " instance_Num_NumSucc_Num_natural_dict = ((| + + succ_method = Suc |) )" + + +(*val naturalPred : natural -> natural*) +definition instance_Num_NumPred_Num_natural_dict :: "(nat)NumPred_class " where + " instance_Num_NumPred_Num_natural_dict = ((| + + pred_method = (\<lambda> n. n -( 1 :: nat))|) )" + + +(*val naturalMult : natural -> natural -> natural*) + +definition instance_Num_NumMult_Num_natural_dict :: "(nat)NumMult_class " where + " instance_Num_NumMult_Num_natural_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val naturalPow : natural -> nat -> natural*) + +definition instance_Num_NumPow_Num_natural_dict :: "(nat)NumPow_class " where + " instance_Num_NumPow_Num_natural_dict = ((| + + numPow_method = (op^)|) )" + + +(*val naturalDiv : natural -> natural -> natural*) + +definition instance_Num_NumIntegerDivision_Num_natural_dict :: "(nat)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_natural_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_natural_dict :: "(nat)NumDivision_class " where + " instance_Num_NumDivision_Num_natural_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val naturalMod : natural -> natural -> natural*) + +definition instance_Num_NumRemainder_Num_natural_dict :: "(nat)NumRemainder_class " where + " instance_Num_NumRemainder_Num_natural_dict = ((| + + mod_method = (op mod)|) )" + + +(*val naturalMin : natural -> natural -> natural*) + +(*val naturalMax : natural -> natural -> natural*) + +definition instance_Basic_classes_OrdMaxMin_Num_natural_dict :: "(nat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_natural_dict = ((| + + max_method = max, + + min_method = min |) )" + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(*val intFromNumeral : numeral -> int*) + +(*val intEq : int -> int -> bool*) + +(*val intLess : int -> int -> bool*) +(*val intLessEqual : int -> int -> bool*) +(*val intGreater : int -> int -> bool*) +(*val intGreaterEqual : int -> int -> bool*) + +(*val intCompare : int -> int -> ordering*) + +definition instance_Basic_classes_Ord_Num_int_dict :: "(int)Ord_class " where + " instance_Basic_classes_Ord_Num_int_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val intNegate : int -> int*) + +definition instance_Num_NumNegate_Num_int_dict :: "(int)NumNegate_class " where + " instance_Num_NumNegate_Num_int_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val intAbs : int -> int*) (* TODO: check *) + +definition instance_Num_NumAbs_Num_int_dict :: "(int)NumAbs_class " where + " instance_Num_NumAbs_Num_int_dict = ((| + + abs_method = abs |) )" + + +(*val intAdd : int -> int -> int*) + +definition instance_Num_NumAdd_Num_int_dict :: "(int)NumAdd_class " where + " instance_Num_NumAdd_Num_int_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val intMinus : int -> int -> int*) + +definition instance_Num_NumMinus_Num_int_dict :: "(int)NumMinus_class " where + " instance_Num_NumMinus_Num_int_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val intSucc : int -> int*) +definition instance_Num_NumSucc_Num_int_dict :: "(int)NumSucc_class " where + " instance_Num_NumSucc_Num_int_dict = ((| + + succ_method = (\<lambda> n. n +( 1 :: int))|) )" + + +(*val intPred : int -> int*) +definition instance_Num_NumPred_Num_int_dict :: "(int)NumPred_class " where + " instance_Num_NumPred_Num_int_dict = ((| + + pred_method = (\<lambda> n. n -( 1 :: int))|) )" + + +(*val intMult : int -> int -> int*) + +definition instance_Num_NumMult_Num_int_dict :: "(int)NumMult_class " where + " instance_Num_NumMult_Num_int_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val intPow : int -> nat -> int*) + +definition instance_Num_NumPow_Num_int_dict :: "(int)NumPow_class " where + " instance_Num_NumPow_Num_int_dict = ((| + + numPow_method = (op^)|) )" + + +(*val intDiv : int -> int -> int*) + +definition instance_Num_NumIntegerDivision_Num_int_dict :: "(int)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int_dict :: "(int)NumDivision_class " where + " instance_Num_NumDivision_Num_int_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val intMod : int -> int -> int*) + +definition instance_Num_NumRemainder_Num_int_dict :: "(int)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int_dict = ((| + + mod_method = (op mod)|) )" + + +(*val intMin : int -> int -> int*) + +(*val intMax : int -> int -> int*) + +definition instance_Basic_classes_OrdMaxMin_Num_int_dict :: "(int)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int_dict = ((| + + max_method = max, + + min_method = min |) )" + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) +(*val int32FromNumeral : numeral -> int32*) + +(*val int32Eq : int32 -> int32 -> bool*) + +(*val int32Less : int32 -> int32 -> bool*) +(*val int32LessEqual : int32 -> int32 -> bool*) +(*val int32Greater : int32 -> int32 -> bool*) +(*val int32GreaterEqual : int32 -> int32 -> bool*) + +(*val int32Compare : int32 -> int32 -> ordering*) + +definition instance_Basic_classes_Ord_Num_int32_dict :: "( 32 word)Ord_class " where + " instance_Basic_classes_Ord_Num_int32_dict = ((| + + compare_method = (genericCompare word_sless (op=)), + + isLess_method = word_sless, + + isLessEqual_method = word_sle, + + isGreater_method = (\<lambda> x y. word_sless y x), + + isGreaterEqual_method = (\<lambda> x y. word_sle y x)|) )" + + +(*val int32Negate : int32 -> int32*) + +definition instance_Num_NumNegate_Num_int32_dict :: "( 32 word)NumNegate_class " where + " instance_Num_NumNegate_Num_int32_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val int32Abs : int32 -> int32*) +definition int32Abs :: " 32 word \<Rightarrow> 32 word " where + " int32Abs i = ( (if word_sle(((word_of_int 0) :: 32 word)) i then i else - i))" + + +definition instance_Num_NumAbs_Num_int32_dict :: "( 32 word)NumAbs_class " where + " instance_Num_NumAbs_Num_int32_dict = ((| + + abs_method = int32Abs |) )" + + + +(*val int32Add : int32 -> int32 -> int32*) + +definition instance_Num_NumAdd_Num_int32_dict :: "( 32 word)NumAdd_class " where + " instance_Num_NumAdd_Num_int32_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val int32Minus : int32 -> int32 -> int32*) + +definition instance_Num_NumMinus_Num_int32_dict :: "( 32 word)NumMinus_class " where + " instance_Num_NumMinus_Num_int32_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val int32Succ : int32 -> int32*) + +definition instance_Num_NumSucc_Num_int32_dict :: "( 32 word)NumSucc_class " where + " instance_Num_NumSucc_Num_int32_dict = ((| + + succ_method = (\<lambda> n. n +((word_of_int 1) :: 32 word))|) )" + + +(*val int32Pred : int32 -> int32*) +definition instance_Num_NumPred_Num_int32_dict :: "( 32 word)NumPred_class " where + " instance_Num_NumPred_Num_int32_dict = ((| + + pred_method = (\<lambda> n. n -((word_of_int 1) :: 32 word))|) )" + + +(*val int32Mult : int32 -> int32 -> int32*) + +definition instance_Num_NumMult_Num_int32_dict :: "( 32 word)NumMult_class " where + " instance_Num_NumMult_Num_int32_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val int32Pow : int32 -> nat -> int32*) + +definition instance_Num_NumPow_Num_int32_dict :: "( 32 word)NumPow_class " where + " instance_Num_NumPow_Num_int32_dict = ((| + + numPow_method = (op^)|) )" + + +(*val int32Div : int32 -> int32 -> int32*) + +definition instance_Num_NumIntegerDivision_Num_int32_dict :: "( 32 word)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int32_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int32_dict :: "( 32 word)NumDivision_class " where + " instance_Num_NumDivision_Num_int32_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val int32Mod : int32 -> int32 -> int32*) + +definition instance_Num_NumRemainder_Num_int32_dict :: "( 32 word)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int32_dict = ((| + + mod_method = (op mod)|) )" + + +(*val int32Min : int32 -> int32 -> int32*) + +(*val int32Max : int32 -> int32 -> int32*) + +definition instance_Basic_classes_OrdMaxMin_Num_int32_dict :: "( 32 word)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int32_dict = ((| + + max_method = ((\<lambda> x y. if (word_sle y x) then x else y)), + + min_method = ((\<lambda> x y. if (word_sle x y) then x else y))|) )" + + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) +(*val int64FromNumeral : numeral -> int64*) + +(*val int64Eq : int64 -> int64 -> bool*) + +(*val int64Less : int64 -> int64 -> bool*) +(*val int64LessEqual : int64 -> int64 -> bool*) +(*val int64Greater : int64 -> int64 -> bool*) +(*val int64GreaterEqual : int64 -> int64 -> bool*) + +(*val int64Compare : int64 -> int64 -> ordering*) + +definition instance_Basic_classes_Ord_Num_int64_dict :: "( 64 word)Ord_class " where + " instance_Basic_classes_Ord_Num_int64_dict = ((| + + compare_method = (genericCompare word_sless (op=)), + + isLess_method = word_sless, + + isLessEqual_method = word_sle, + + isGreater_method = (\<lambda> x y. word_sless y x), + + isGreaterEqual_method = (\<lambda> x y. word_sle y x)|) )" + + +(*val int64Negate : int64 -> int64*) + +definition instance_Num_NumNegate_Num_int64_dict :: "( 64 word)NumNegate_class " where + " instance_Num_NumNegate_Num_int64_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val int64Abs : int64 -> int64*) +definition int64Abs :: " 64 word \<Rightarrow> 64 word " where + " int64Abs i = ( (if word_sle(((word_of_int 0) :: 64 word)) i then i else - i))" + + +definition instance_Num_NumAbs_Num_int64_dict :: "( 64 word)NumAbs_class " where + " instance_Num_NumAbs_Num_int64_dict = ((| + + abs_method = int64Abs |) )" + + + +(*val int64Add : int64 -> int64 -> int64*) + +definition instance_Num_NumAdd_Num_int64_dict :: "( 64 word)NumAdd_class " where + " instance_Num_NumAdd_Num_int64_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val int64Minus : int64 -> int64 -> int64*) + +definition instance_Num_NumMinus_Num_int64_dict :: "( 64 word)NumMinus_class " where + " instance_Num_NumMinus_Num_int64_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val int64Succ : int64 -> int64*) + +definition instance_Num_NumSucc_Num_int64_dict :: "( 64 word)NumSucc_class " where + " instance_Num_NumSucc_Num_int64_dict = ((| + + succ_method = (\<lambda> n. n +((word_of_int 1) :: 64 word))|) )" + + +(*val int64Pred : int64 -> int64*) +definition instance_Num_NumPred_Num_int64_dict :: "( 64 word)NumPred_class " where + " instance_Num_NumPred_Num_int64_dict = ((| + + pred_method = (\<lambda> n. n -((word_of_int 1) :: 64 word))|) )" + + +(*val int64Mult : int64 -> int64 -> int64*) + +definition instance_Num_NumMult_Num_int64_dict :: "( 64 word)NumMult_class " where + " instance_Num_NumMult_Num_int64_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val int64Pow : int64 -> nat -> int64*) + +definition instance_Num_NumPow_Num_int64_dict :: "( 64 word)NumPow_class " where + " instance_Num_NumPow_Num_int64_dict = ((| + + numPow_method = (op^)|) )" + + +(*val int64Div : int64 -> int64 -> int64*) + +definition instance_Num_NumIntegerDivision_Num_int64_dict :: "( 64 word)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_int64_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_int64_dict :: "( 64 word)NumDivision_class " where + " instance_Num_NumDivision_Num_int64_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val int64Mod : int64 -> int64 -> int64*) + +definition instance_Num_NumRemainder_Num_int64_dict :: "( 64 word)NumRemainder_class " where + " instance_Num_NumRemainder_Num_int64_dict = ((| + + mod_method = (op mod)|) )" + + +(*val int64Min : int64 -> int64 -> int64*) + +(*val int64Max : int64 -> int64 -> int64*) + +definition instance_Basic_classes_OrdMaxMin_Num_int64_dict :: "( 64 word)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_int64_dict = ((| + + max_method = ((\<lambda> x y. if (word_sle y x) then x else y)), + + min_method = ((\<lambda> x y. if (word_sle x y) then x else y))|) )" + + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerFromNumeral : numeral -> integer*) + +(*val integerFromNat : nat -> integer*) (* TODO: check *) + +(*val integerEq : integer -> integer -> bool*) + +(*val integerLess : integer -> integer -> bool*) +(*val integerLessEqual : integer -> integer -> bool*) +(*val integerGreater : integer -> integer -> bool*) +(*val integerGreaterEqual : integer -> integer -> bool*) + +(*val integerCompare : integer -> integer -> ordering*) + +definition instance_Basic_classes_Ord_Num_integer_dict :: "(int)Ord_class " where + " instance_Basic_classes_Ord_Num_integer_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val integerNegate : integer -> integer*) + +definition instance_Num_NumNegate_Num_integer_dict :: "(int)NumNegate_class " where + " instance_Num_NumNegate_Num_integer_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val integerAbs : integer -> integer*) (* TODO: check *) + +definition instance_Num_NumAbs_Num_integer_dict :: "(int)NumAbs_class " where + " instance_Num_NumAbs_Num_integer_dict = ((| + + abs_method = abs |) )" + + +(*val integerAdd : integer -> integer -> integer*) + +definition instance_Num_NumAdd_Num_integer_dict :: "(int)NumAdd_class " where + " instance_Num_NumAdd_Num_integer_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val integerMinus : integer -> integer -> integer*) + +definition instance_Num_NumMinus_Num_integer_dict :: "(int)NumMinus_class " where + " instance_Num_NumMinus_Num_integer_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val integerSucc : integer -> integer*) +definition instance_Num_NumSucc_Num_integer_dict :: "(int)NumSucc_class " where + " instance_Num_NumSucc_Num_integer_dict = ((| + + succ_method = (\<lambda> n. n +( 1 :: int))|) )" + + +(*val integerPred : integer -> integer*) +definition instance_Num_NumPred_Num_integer_dict :: "(int)NumPred_class " where + " instance_Num_NumPred_Num_integer_dict = ((| + + pred_method = (\<lambda> n. n -( 1 :: int))|) )" + + +(*val integerMult : integer -> integer -> integer*) + +definition instance_Num_NumMult_Num_integer_dict :: "(int)NumMult_class " where + " instance_Num_NumMult_Num_integer_dict = ((| + + numMult_method = (op*)|) )" + + + +(*val integerPow : integer -> nat -> integer*) + +definition instance_Num_NumPow_Num_integer_dict :: "(int)NumPow_class " where + " instance_Num_NumPow_Num_integer_dict = ((| + + numPow_method = (op^)|) )" + + +(*val integerDiv : integer -> integer -> integer*) + +definition instance_Num_NumIntegerDivision_Num_integer_dict :: "(int)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Num_integer_dict = ((| + + div_method = (op div)|) )" + + +definition instance_Num_NumDivision_Num_integer_dict :: "(int)NumDivision_class " where + " instance_Num_NumDivision_Num_integer_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val integerMod : integer -> integer -> integer*) + +definition instance_Num_NumRemainder_Num_integer_dict :: "(int)NumRemainder_class " where + " instance_Num_NumRemainder_Num_integer_dict = ((| + + mod_method = (op mod)|) )" + + +(*val integerMin : integer -> integer -> integer*) + +(*val integerMax : integer -> integer -> integer*) + +definition instance_Basic_classes_OrdMaxMin_Num_integer_dict :: "(int)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_integer_dict = ((| + + max_method = max, + + min_method = min |) )" + + + + +(* ----------------------- *) +(* rational *) +(* ----------------------- *) + +(*val rationalFromNumeral : numeral -> rational*) + +(*val rationalFromInt : int -> rational*) + +(*val rationalEq : rational -> rational -> bool*) + +(*val rationalLess : rational -> rational -> bool*) +(*val rationalLessEqual : rational -> rational -> bool*) +(*val rationalGreater : rational -> rational -> bool*) +(*val rationalGreaterEqual : rational -> rational -> bool*) + +(*val rationalCompare : rational -> rational -> ordering*) + +definition instance_Basic_classes_Ord_Num_rational_dict :: "(rat)Ord_class " where + " instance_Basic_classes_Ord_Num_rational_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val rationalAdd : rational -> rational -> rational*) + +definition instance_Num_NumAdd_Num_rational_dict :: "(rat)NumAdd_class " where + " instance_Num_NumAdd_Num_rational_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val rationalMinus : rational -> rational -> rational*) + +definition instance_Num_NumMinus_Num_rational_dict :: "(rat)NumMinus_class " where + " instance_Num_NumMinus_Num_rational_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val rationalNegate : rational -> rational*) + +definition instance_Num_NumNegate_Num_rational_dict :: "(rat)NumNegate_class " where + " instance_Num_NumNegate_Num_rational_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val rationalAbs : rational -> rational*) + +definition instance_Num_NumAbs_Num_rational_dict :: "(rat)NumAbs_class " where + " instance_Num_NumAbs_Num_rational_dict = ((| + + abs_method = abs |) )" + + +(*val rationalSucc : rational -> rational*) +definition instance_Num_NumSucc_Num_rational_dict :: "(rat)NumSucc_class " where + " instance_Num_NumSucc_Num_rational_dict = ((| + + succ_method = (\<lambda> n. n +(Fract ( 1 :: int) (1 :: int)))|) )" + + +(*val rationalPred : rational -> rational*) +definition instance_Num_NumPred_Num_rational_dict :: "(rat)NumPred_class " where + " instance_Num_NumPred_Num_rational_dict = ((| + + pred_method = (\<lambda> n. n -(Fract ( 1 :: int) (1 :: int)))|) )" + + +(*val rationalMult : rational -> rational -> rational*) + +definition instance_Num_NumMult_Num_rational_dict :: "(rat)NumMult_class " where + " instance_Num_NumMult_Num_rational_dict = ((| + + numMult_method = (op*)|) )" + + +(*val rationalDiv : rational -> rational -> rational*) + +definition instance_Num_NumDivision_Num_rational_dict :: "(rat)NumDivision_class " where + " instance_Num_NumDivision_Num_rational_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val rationalFromFrac : int -> int -> rational*) +(*let rationalFromFrac n d= (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)*) + +(*val rationalPowInteger : rational -> integer -> rational*) +fun rationalPowInteger :: " rat \<Rightarrow> int \<Rightarrow> rat " where + " rationalPowInteger b e = ( + if e =( 0 :: int) then(Fract ( 1 :: int) (1 :: int)) else + if e >( 0 :: int) then rationalPowInteger b (e -( 1 :: int)) * b else + rationalPowInteger b (e +( 1 :: int)) div b )" + + +(*val rationalPowNat : rational -> nat -> rational*) +(*let rationalPowNat r e= rationalPowInteger r (integerFromNat e)*) + +definition instance_Num_NumPow_Num_rational_dict :: "(rat)NumPow_class " where + " instance_Num_NumPow_Num_rational_dict = ((| + + numPow_method = power |) )" + + +(*val rationalMin : rational -> rational -> rational*) + +(*val rationalMax : rational -> rational -> rational*) + +definition instance_Basic_classes_OrdMaxMin_Num_rational_dict :: "(rat)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_rational_dict = ((| + + max_method = max, + + min_method = min |) )" + + + + +(* ----------------------- *) +(* real *) +(* ----------------------- *) + +(*val realFromNumeral : numeral -> real*) + +(*val realFromInteger : integer -> real*) + +(*val realEq : real -> real -> bool*) + +(*val realLess : real -> real -> bool*) +(*val realLessEqual : real -> real -> bool*) +(*val realGreater : real -> real -> bool*) +(*val realGreaterEqual : real -> real -> bool*) + +(*val realCompare : real -> real -> ordering*) + +definition instance_Basic_classes_Ord_Num_real_dict :: "(real)Ord_class " where + " instance_Basic_classes_Ord_Num_real_dict = ((| + + compare_method = (genericCompare (op<) (op=)), + + isLess_method = (op<), + + isLessEqual_method = (op \<le>), + + isGreater_method = (op>), + + isGreaterEqual_method = (op \<ge>)|) )" + + +(*val realAdd : real -> real -> real*) + +definition instance_Num_NumAdd_Num_real_dict :: "(real)NumAdd_class " where + " instance_Num_NumAdd_Num_real_dict = ((| + + numAdd_method = (op+)|) )" + + +(*val realMinus : real -> real -> real*) + +definition instance_Num_NumMinus_Num_real_dict :: "(real)NumMinus_class " where + " instance_Num_NumMinus_Num_real_dict = ((| + + numMinus_method = (op-)|) )" + + +(*val realNegate : real -> real*) + +definition instance_Num_NumNegate_Num_real_dict :: "(real)NumNegate_class " where + " instance_Num_NumNegate_Num_real_dict = ((| + + numNegate_method = (\<lambda> i. - i)|) )" + + +(*val realAbs : real -> real*) + +definition instance_Num_NumAbs_Num_real_dict :: "(real)NumAbs_class " where + " instance_Num_NumAbs_Num_real_dict = ((| + + abs_method = abs |) )" + + +(*val realSucc : real -> real*) +definition instance_Num_NumSucc_Num_real_dict :: "(real)NumSucc_class " where + " instance_Num_NumSucc_Num_real_dict = ((| + + succ_method = (\<lambda> n. n +( 1 :: real))|) )" + + +(*val realPred : real -> real*) +definition instance_Num_NumPred_Num_real_dict :: "(real)NumPred_class " where + " instance_Num_NumPred_Num_real_dict = ((| + + pred_method = (\<lambda> n. n -( 1 :: real))|) )" + + +(*val realMult : real -> real -> real*) + +definition instance_Num_NumMult_Num_real_dict :: "(real)NumMult_class " where + " instance_Num_NumMult_Num_real_dict = ((| + + numMult_method = (op*)|) )" + + +(*val realDiv : real -> real -> real*) + +definition instance_Num_NumDivision_Num_real_dict :: "(real)NumDivision_class " where + " instance_Num_NumDivision_Num_real_dict = ((| + + numDivision_method = (op div)|) )" + + +(*val realFromFrac : integer -> integer -> real*) +definition realFromFrac :: " int \<Rightarrow> int \<Rightarrow> real " where + " realFromFrac n d = ( ((real_of_int n)) div ((real_of_int d)))" + + +(*val realPowInteger : real -> integer -> real*) +fun realPowInteger :: " real \<Rightarrow> int \<Rightarrow> real " where + " realPowInteger b e = ( + if e =( 0 :: int) then( 1 :: real) else + if e >( 0 :: int) then realPowInteger b (e -( 1 :: int)) * b else + realPowInteger b (e +( 1 :: int)) div b )" + + +(*val realPowNat : real -> nat -> real*) +(*let realPowNat r e= realPowInteger r (integerFromNat e)*) + +definition instance_Num_NumPow_Num_real_dict :: "(real)NumPow_class " where + " instance_Num_NumPow_Num_real_dict = ((| + + numPow_method = power |) )" + + +(*val realSqrt : real -> real*) + +(*val realMin : real -> real -> real*) + +(*val realMax : real -> real -> real*) + +definition instance_Basic_classes_OrdMaxMin_Num_real_dict :: "(real)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Num_real_dict = ((| + + max_method = max, + + min_method = min |) )" + + +(*val realCeiling : real -> integer*) + +(*val realFloor : real -> integer*) + +(* ========================================================================== *) +(* Translation between number types *) +(* ========================================================================== *) + +(******************) +(* integerFrom... *) +(******************) + +(*val integerFromInt : int -> integer*) + +(*val integerFromNatural : natural -> integer*) + + +(*val integerFromInt32 : int32 -> integer*) + + +(*val integerFromInt64 : int64 -> integer*) + + +(******************) +(* naturalFrom... *) +(******************) + +(*val naturalFromNat : nat -> natural*) + +(*val naturalFromInteger : integer -> natural*) + + +(******************) +(* intFrom ... *) +(******************) + +(*val intFromInteger : integer -> int*) + +(*val intFromNat : nat -> int*) + + +(******************) +(* natFrom ... *) +(******************) + +(*val natFromNatural : natural -> nat*) + +(*val natFromInt : int -> nat*) + + +(******************) +(* int32From ... *) +(******************) + +(*val int32FromNat : nat -> int32*) + +(*val int32FromNatural : natural -> int32*) + +(*val int32FromInteger : integer -> int32*) +(*let int32FromInteger i= ( + let abs_int32 = int32FromNatural (naturalFromInteger i) in + if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int32.~ abs_int32) else abs_int32 +)*) + +(*val int32FromInt : int -> int32*) +(*let int32FromInt i= int32FromInteger (integerFromInt i)*) + + +(*val int32FromInt64 : int64 -> int32*) +(*let int32FromInt64 i= int32FromInteger (integerFromInt64 i)*) + + + + +(******************) +(* int64From ... *) +(******************) + +(*val int64FromNat : nat -> int64*) + +(*val int64FromNatural : natural -> int64*) + +(*val int64FromInteger : integer -> int64*) +(*let int64FromInteger i= ( + let abs_int64 = int64FromNatural (naturalFromInteger i) in + if ((Instance_Basic_classes_Ord_Num_integer.<) i 0) then (Instance_Num_NumNegate_Num_int64.~ abs_int64) else abs_int64 +)*) + +(*val int64FromInt : int -> int64*) +(*let int64FromInt i= int64FromInteger (integerFromInt i)*) + + +(*val int64FromInt32 : int32 -> int64*) +(*let int64FromInt32 i= int64FromInteger (integerFromInt32 i)*) + + +(******************) +(* what's missing *) +(******************) + +(*val naturalFromInt : int -> natural*) +(*val naturalFromInt32 : int32 -> natural*) +(*val naturalFromInt64 : int64 -> natural*) + + +(*val intFromNatural : natural -> int*) +(*val intFromInt32 : int32 -> int*) +(*val intFromInt64 : int64 -> int*) + +(*val natFromInteger : integer -> nat*) +(*val natFromInt32 : int32 -> nat*) +(*val natFromInt64 : int64 -> nat*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_num_extra.thy b/snapshots/isabelle/lib/lem/Lem_num_extra.thy new file mode 100644 index 00000000..0611862e --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_num_extra.thy @@ -0,0 +1,34 @@ +chapter \<open>Generated by Lem from num_extra.lem.\<close> + +theory "Lem_num_extra" + +imports + Main + "Lem_num" + "Lem_string" + +begin + +(* **************************************************** *) +(* *) +(* A library of additional functions on numbers *) +(* *) +(* **************************************************** *) + +(*open import Num*) +(*open import String*) + +(*val naturalOfString : string -> natural*) + +(*val integerOfString : string -> integer*) + + +(* Truncation integer division (round toward zero) *) +(*val integerDiv_t: integer -> integer -> integer*) + +(* Truncation modulo *) +(*val integerRem_t: integer -> integer -> integer*) + +(* Flooring modulo *) +(*val integerRem_f: integer -> integer -> integer*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_pervasives.thy b/snapshots/isabelle/lib/lem/Lem_pervasives.thy new file mode 100644 index 00000000..37da1224 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_pervasives.thy @@ -0,0 +1,31 @@ +chapter \<open>Generated by Lem from pervasives.lem.\<close> + +theory "Lem_pervasives" + +imports + Main + "Lem_basic_classes" + "Lem_bool" + "Lem_tuple" + "Lem_maybe" + "Lem_either" + "Lem_function" + "Lem_num" + "Lem_map" + "Lem_set" + "Lem_list" + "Lem_string" + "Lem_word" + "Lem_show" + "Lem_sorting" + "Lem_relation" + +begin + + + +(*include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show*) + +(*import Sorting Relation*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy b/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy new file mode 100644 index 00000000..0e3e5a88 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_pervasives_extra.thy @@ -0,0 +1,26 @@ +chapter \<open>Generated by Lem from pervasives_extra.lem.\<close> + +theory "Lem_pervasives_extra" + +imports + Main + "Lem_pervasives" + "Lem_function_extra" + "Lem_maybe_extra" + "Lem_map_extra" + "Lem_num_extra" + "Lem_set_extra" + "Lem_set_helpers" + "Lem_list_extra" + "Lem_string_extra" + "Lem_assert_extra" + "Lem_show_extra" + "Lem_machine_word" + +begin + + + +(*include import Pervasives*) +(*include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_relation.thy b/snapshots/isabelle/lib/lem/Lem_relation.thy new file mode 100644 index 00000000..23e7d707 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_relation.thy @@ -0,0 +1,449 @@ +chapter \<open>Generated by Lem from relation.lem.\<close> + +theory "Lem_relation" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_tuple" + "Lem_set" + "Lem_num" + +begin + + + +(*open import Bool Basic_classes Tuple Set Num*) +(*open import {hol} `set_relationTheory`*) + +(* ========================================================================== *) +(* The type of relations *) +(* ========================================================================== *) + +type_synonym( 'a, 'b) rel_pred =" 'a \<Rightarrow> 'b \<Rightarrow> bool " +type_synonym( 'a, 'b) rel_set =" ('a * 'b) set " + +(* Binary relations are usually represented as either + sets of pairs (rel_set) or as curried functions (rel_pred). + + The choice depends on taste and the backend. Lem should not take a + decision, but supports both representations. There is an abstract type + pred, which can be converted to both representations. The representation + of pred itself then depends on the backend. However, for the time beeing, + let's implement relations as sets to get them working more quickly. *) + +type_synonym( 'a, 'b) rel =" ('a, 'b) rel_set " + +(*val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b*) +(*val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b*) + +(*val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool*) +definition relEq :: "('a*'b)set \<Rightarrow>('a*'b)set \<Rightarrow> bool " where + " relEq r1 r2 = ( (r1 = r2))" + + +(*val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b*) +(*val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b*) + +definition relToPred :: "('a*'b)set \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow> bool " where + " relToPred r = ( (\<lambda> x y . (x, y) \<in> r))" + +definition relFromPred :: " 'a set \<Rightarrow> 'b set \<Rightarrow>('a \<Rightarrow> 'b \<Rightarrow> bool)\<Rightarrow>('a*'b)set " where + " relFromPred xs ys p = ( set_filter ( \<lambda>x . + (case x of (x,y) => p x y )) (xs \<times> ys))" + + + +(* ========================================================================== *) +(* Basic Operations *) +(* ========================================================================== *) + +(* ----------------------- *) +(* membership test *) +(* ----------------------- *) + +(*val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool*) + + +(* ----------------------- *) +(* empty relation *) +(* ----------------------- *) + +(*val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b*) + +(* ----------------------- *) +(* Insertion *) +(* ----------------------- *) + +(*val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b*) + + +(* ----------------------- *) +(* Identity relation *) +(* ----------------------- *) + +(*val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a*) +definition relIdOn :: " 'a set \<Rightarrow>('a*'a)set " where + " relIdOn s = ( relFromPred s s (op=))" + + +(*val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a*) + +(* ----------------------- *) +(* relation union *) +(* ----------------------- *) + +(*val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* relation intersection *) +(* ----------------------- *) + +(*val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) + +(* ----------------------- *) +(* Relation Composition *) +(* ----------------------- *) + +(*val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c*) +(*let relComp r1 r2= relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}*) + +(* ----------------------- *) +(* restrict *) +(* ----------------------- *) + +(*val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +definition relRestrict :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow>('a*'a)set " where + " relRestrict r s = ( ((let x2 = + ({}) in Finite_Set.fold + (\<lambda>a x2 . Finite_Set.fold + (\<lambda>b x2 . + if (a, b) \<in> r then Set.insert (a, b) x2 else x2) + x2 s) x2 s)))" + + + +(* ----------------------- *) +(* Converse *) +(* ----------------------- *) + +(*val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a*) +(*let relConverse r= relFromSet (Set.map swap (relToSet r))*) + + +(* ----------------------- *) +(* domain *) +(* ----------------------- *) + +(*val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a*) +(*let relDomain r= Set.map (fun x -> fst x) (relToSet r)*) + +(* ----------------------- *) +(* range *) +(* ----------------------- *) + +(*val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b*) +(*let relRange r= Set.map (fun x -> snd x) (relToSet r)*) + + +(* ----------------------- *) +(* field / definedOn *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a*) + +(* ----------------------- *) +(* relOver *) +(* *) +(* avoid the keyword field *) +(* ----------------------- *) + +(*val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool*) +definition relOver :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " relOver r s = ( ((((Domain r) \<union> (Range r))) \<subseteq> s))" + + + +(* ----------------------- *) +(* apply a relation *) +(* ----------------------- *) + +(* Given a relation r and a set s, relApply r s applies s to r, i.e. + it returns the set of all value reachable via r from a value in s. + This operation can be seen as a generalisation of function application. *) + +(*val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b*) +(*let relApply r s= { y | forall ((x, y) IN (relToSet r)) | x IN s }*) + + +(* ========================================================================== *) +(* Properties *) +(* ========================================================================== *) + +(* ----------------------- *) +(* subrel *) +(* ----------------------- *) + +(*val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool*) + +(* ----------------------- *) +(* reflexivity *) +(* ----------------------- *) + +(*val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isReflexiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isReflexiveOn r s = ( ((\<forall> e \<in> s. (e, e) \<in> r)))" + + +(*val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let ~{ocaml;coq} isReflexive r= (forall e. inRel e e r)*) + + +(* ----------------------- *) +(* irreflexivity *) +(* ----------------------- *) + +(*val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isIrreflexiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isIrreflexiveOn r s = ( ((\<forall> e \<in> s. \<not> ((e, e) \<in> r))))" + + +(*val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isIrreflexive r= (forall ((e1, e2) IN (relToSet r)). not (e1 = e2))*) + + +(* ----------------------- *) +(* symmetry *) +(* ----------------------- *) + +(*val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isSymmetricOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isSymmetricOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> ((e2, e1) \<in> r))))" + + +(*val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isSymmetric r= (forall ((e1, e2) IN relToSet r). inRel e2 e1 r)*) + + +(* ----------------------- *) +(* antisymmetry *) +(* ----------------------- *) + +(*val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isAntisymmetricOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isAntisymmetricOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> (((e2, e1) \<in> r) \<longrightarrow> (e1 = e2)))))" + + +(*val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isAntisymmetric r= (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))*) + + +(* ----------------------- *) +(* transitivity *) +(* ----------------------- *) + +(*val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTransitiveOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isTransitiveOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. \<forall> e3 \<in> s. ((e1, e2) \<in> r) \<longrightarrow> (((e2, e3) \<in> r) \<longrightarrow> ((e1, e3) \<in> r)))))" + + +(*val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let isTransitive r= (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)*) + +(* ----------------------- *) +(* total *) +(* ----------------------- *) + +(*val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTotalOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isTotalOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<or> ((e2, e1) \<in> r))))" + + + +(*val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +(*let ~{ocaml;coq} isTotal r= (forall e1 e2. (inRel e1 e2 r) || (inRel e2 e1 r))*) + +(*val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTrichotomousOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isTrichotomousOn r s = ( ((\<forall> e1 \<in> s. \<forall> e2 \<in> s. ((e1, e2) \<in> r) \<or> ((e1 = e2) \<or> ((e2, e1) \<in> r)))))" + + +(*val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isTrichotomous :: "('a*'a)set \<Rightarrow> bool " where + " isTrichotomous r = ( ((\<forall> e1. \<forall> e2. ((e1, e2) \<in> r) \<or> ((e1 = e2) \<or> ((e2, e1) \<in> r)))))" + + + +(* ----------------------- *) +(* is_single_valued *) +(* ----------------------- *) + +(*val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool*) +definition isSingleValued :: "('a*'b)set \<Rightarrow> bool " where + " isSingleValued r = ( ((\<forall> (e1, e2a) \<in> r. \<forall> e2b \<in> Image r {e1}. e2a = e2b)))" + + + +(* ----------------------- *) +(* equivalence relation *) +(* ----------------------- *) + +(*val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isEquivalenceOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isEquivalenceOn r s = ( isReflexiveOn r s \<and> (isSymmetricOn r s \<and> isTransitiveOn r s))" + + + +(*val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isEquivalence :: "('a*'a)set \<Rightarrow> bool " where + " isEquivalence r = ( refl r \<and> (sym r \<and> trans r))" + + + +(* ----------------------- *) +(* well founded *) +(* ----------------------- *) + +(*val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isWellFounded :: "('a*'a)set \<Rightarrow> bool " where + " isWellFounded r = ( ((\<forall> P. ((\<forall> x. ((\<forall> y. ((y, x) \<in> r) \<longrightarrow> P x)) \<longrightarrow> P x)) \<longrightarrow> ((\<forall> x. P x)))))" + + + +(* ========================================================================== *) +(* Orders *) +(* ========================================================================== *) + + +(* ----------------------- *) +(* pre- or quasiorders *) +(* ----------------------- *) + +(*val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isPreorderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isPreorderOn r s = ( isReflexiveOn r s \<and> isTransitiveOn r s )" + + +(*val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isPreorder :: "('a*'a)set \<Rightarrow> bool " where + " isPreorder r = ( refl r \<and> trans r )" + + + +(* ----------------------- *) +(* partial orders *) +(* ----------------------- *) + +(*val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isPartialOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isPartialOrderOn r s = ( isReflexiveOn r s \<and> (isTransitiveOn r s \<and> isAntisymmetricOn r s))" + + + +(*val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isStrictPartialOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isStrictPartialOrderOn r s = ( isIrreflexiveOn r s \<and> isTransitiveOn r s )" + + + +(*val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isStrictPartialOrder :: "('a*'a)set \<Rightarrow> bool " where + " isStrictPartialOrder r = ( irrefl r \<and> trans r )" + + +(*val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isPartialOrder :: "('a*'a)set \<Rightarrow> bool " where + " isPartialOrder r = ( refl r \<and> (trans r \<and> antisym r))" + + +(* ----------------------- *) +(* total / linear orders *) +(* ----------------------- *) + +(*val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isTotalOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isTotalOrderOn r s = ( isPartialOrderOn r s \<and> isTotalOn r s )" + + +(*val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*) +definition isStrictTotalOrderOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow> bool " where + " isStrictTotalOrderOn r s = ( isStrictPartialOrderOn r s \<and> isTrichotomousOn r s )" + + +(*val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isTotalOrder :: "('a*'a)set \<Rightarrow> bool " where + " isTotalOrder r = ( isPartialOrder r \<and> total r )" + + +(*val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*) +definition isStrictTotalOrder :: "('a*'a)set \<Rightarrow> bool " where + " isStrictTotalOrder r = ( isStrictPartialOrder r \<and> isTrichotomous r )" + + + + +(* ========================================================================== *) +(* closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* transitive closure *) +(* ----------------------- *) + +(*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByEq : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*) +(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> ordering) -> rel 'a 'a -> rel 'a 'a*) + + +(* ----------------------- *) +(* transitive closure step *) +(* ----------------------- *) + +(*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*) + +definition transitiveClosureAdd :: " 'a \<Rightarrow> 'a \<Rightarrow>('a*'a)set \<Rightarrow>('a*'a)set " where + " transitiveClosureAdd x y r = ( + (((((Set.insert (x,y) (r)))) \<union> ((((((let x2 = + ({}) in Finite_Set.fold + (\<lambda>z x2 . if (y, z) \<in> r then Set.insert (x, z) x2 else x2) + x2 (Range r)))) \<union> (((let x2 = + ({}) in Finite_Set.fold + (\<lambda>z x2 . if (z, x) \<in> r then Set.insert (z, y) x2 else x2) + x2 (Domain r))))))))))" + + + +(* ========================================================================== *) +(* reflexive closure *) +(* ========================================================================== *) + +(*val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*) +definition reflexiveTransitiveClosureOn :: "('a*'a)set \<Rightarrow> 'a set \<Rightarrow>('a*'a)set " where + " reflexiveTransitiveClosureOn r s = ( trancl (((r) \<union> ((relIdOn s)))))" + + + +(*val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +definition reflexiveTransitiveClosure :: "('a*'a)set \<Rightarrow>('a*'a)set " where + " reflexiveTransitiveClosure r = ( trancl (((r) \<union> (Id))))" + + + + +(* ========================================================================== *) +(* inverse of closures *) +(* ========================================================================== *) + +(* ----------------------- *) +(* without transitve edges *) +(* ----------------------- *) + +(*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*) +(*let withoutTransitiveEdges r= + let tc = transitiveClosure r in + {(a, c) | forall ((a, c) IN r) + | forall (b IN relRange r). a <> b && b <> c --> not ((a, b) IN tc && (b, c) IN tc)}*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_set.thy b/snapshots/isabelle/lib/lem/Lem_set.thy new file mode 100644 index 00000000..f77d4d98 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set.thy @@ -0,0 +1,325 @@ +chapter \<open>Generated by Lem from set.lem.\<close> + +theory "Lem_set" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + "Lem_list" + "Lem_set_helpers" + "Lem" + +begin + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets. + OCaml and Haskell both represent sets by some kind of balancing trees. This means + that sets are finite and an order on the element type is required. + Such sets are constructed by simple, executable operations like inserting or + deleting elements, union, intersection, filtering etc. + + On the other hand, we want to use sets for specifications. This leads often + infinite sets, which are specificied in complicated, perhaps even undecidable + ways. + + The set library in this file, chooses the first approach. It describes + *finite* sets with an underlying order. Infinite sets should in the medium + run be represented by a separate type. Since this would require some significant + changes to Lem, for the moment also infinite sets are represented using this + class. However, a run-time exception might occour when using these sets. + This problem needs adressing in the future. *) + + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Set_helpers*) + +(* DPM: sets currently implemented as lists due to mismatch between Coq type + * class hierarchy and the hierarchy implemented in Lem. + *) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `lemTheory`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ----------------------- *) +(* Equality check *) +(* ----------------------- *) + +(*val setEqualBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) + +(*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* Empty set *) +(* ----------------------- *) + +(*val empty : forall 'a. SetType 'a => set 'a*) +(*val emptyBy : forall 'a. ('a -> 'a -> ordering) -> set 'a*) + +(* ----------------------- *) +(* any / all *) +(* ----------------------- *) + +(*val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + +(*val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*) + + +(* ----------------------- *) +(* (IN) *) +(* ----------------------- *) + +(*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) +(*val memberBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a -> bool*) + +(* ----------------------- *) +(* not (IN) *) +(* ----------------------- *) + +(*val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) + + + +(* ----------------------- *) +(* Emptyness check *) +(* ----------------------- *) + +(*val null : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ------------------------ *) +(* singleton *) +(* ------------------------ *) + +(*val singletonBy : forall 'a. ('a -> 'a -> ordering) -> 'a -> set 'a*) +(*val singleton : forall 'a. SetType 'a => 'a -> set 'a*) + + +(* ----------------------- *) +(* size *) +(* ----------------------- *) + +(*val size : forall 'a. SetType 'a => set 'a -> nat*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b*) + + +(* ------------------------ *) +(* union *) +(* ------------------------ *) + +(*val unionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) +(*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* insert *) +(* ----------------------- *) + +(*val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a*) + +(* ----------------------- *) +(* filter *) +(* ----------------------- *) + +(*val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a*) +(*let filter P s= {e | forall (e IN s) | P e}*) + + +(* ----------------------- *) +(* partition *) +(* ----------------------- *) + +(*val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a*) +definition partition :: "('a \<Rightarrow> bool)\<Rightarrow> 'a set \<Rightarrow> 'a set*'a set " where + " partition P s = ( (set_filter P s, set_filter (\<lambda> e . \<not> (P e)) s))" + + + +(* ----------------------- *) +(* split *) +(* ----------------------- *) + +(*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*) +definition split :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a set \<Rightarrow> 'a set*'a set " where + " split dict_Basic_classes_Ord_a p s = ( (set_filter ( + (isGreater_method dict_Basic_classes_Ord_a) p) s, set_filter ((isLess_method dict_Basic_classes_Ord_a) p) s))" + + +(*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*) +definition splitMember :: " 'a Ord_class \<Rightarrow> 'a \<Rightarrow> 'a set \<Rightarrow> 'a set*bool*'a set " where + " splitMember dict_Basic_classes_Ord_a p s = ( (set_filter ( + (isLess_method dict_Basic_classes_Ord_a) p) s, (p \<in> s), set_filter ( + (isGreater_method dict_Basic_classes_Ord_a) p) s))" + + +(* ------------------------ *) +(* subset and proper subset *) +(* ------------------------ *) + +(*val isSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) +(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> bool*) + +(*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) +(*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*) + + +(* ------------------------ *) +(* delete *) +(* ------------------------ *) + +(*val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a*) +(*val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* bigunion *) +(* ------------------------ *) + +(*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +(*val bigunionBy : forall 'a. ('a -> 'a -> ordering) -> set (set 'a) -> set 'a*) + +(*let bigunion bs= {x | forall (s IN bs) (x IN s) | true}*) + +(* ------------------------ *) +(* big intersection *) +(* ------------------------ *) + +(* Shaked's addition, for which he is now forever responsible as a de facto + * Lem maintainer... + *) +(*val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a*) +definition bigintersection :: "('a set)set \<Rightarrow> 'a set " where + " bigintersection bs = ( (let x2 = + ({}) in Finite_Set.fold + (\<lambda>x x2 . + if( \<forall> s \<in> bs. x \<in> s) then Set.insert x x2 else x2) + x2 (\<Union> bs)))" + + +(* ------------------------ *) +(* difference *) +(* ------------------------ *) + +(*val differenceBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) +(*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) + +(* ------------------------ *) +(* intersection *) +(* ------------------------ *) + +(*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*) +(*val intersectionBy : forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> set 'a*) + + +(* ------------------------ *) +(* map *) +(* ------------------------ *) + +(*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *) +(*let map f s= { f e | forall (e IN s) | true }*) + +(*val mapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> 'b) -> set 'a -> set 'b*) + + +(* ------------------------ *) +(* bigunionMap *) +(* ------------------------ *) + +(* In order to avoid providing an comparison function for sets of sets, + it might be better to combine bigunion and map sometimes into a single operation. *) + +(*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*) +(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> ordering) -> ('a -> set 'b) -> set 'a -> set 'b*) + +(* ------------------------ *) +(* mapMaybe and fromMaybe *) +(* ------------------------ *) + +(* If the mapping function returns Just x, x is added to the result + set. If it returns Nothing, no element is added. *) + +(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> maybe 'b) -> set 'a -> set 'b*) +definition setMapMaybe :: "('a \<Rightarrow> 'b option)\<Rightarrow> 'a set \<Rightarrow> 'b set " where + " setMapMaybe f s = ( + \<Union> (Set.image (\<lambda> x . (case f x of + Some y => {y} + | None => {} + )) s))" + + +(*val removeMaybe : forall 'a. SetType 'a => set (maybe 'a) -> set 'a*) +definition removeMaybe :: "('a option)set \<Rightarrow> 'a set " where + " removeMaybe s = ( setMapMaybe (\<lambda> x . x) s )" + + +(* ------------------------ *) +(* min and max *) +(* ------------------------ *) + +(*val findMin : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) +(*val findMax : forall 'a. SetType 'a, Eq 'a => set 'a -> maybe 'a*) + +(* ------------------------ *) +(* fromList *) +(* ------------------------ *) + +(*val fromList : forall 'a. SetType 'a => list 'a -> set 'a*) (* before from_list *) +(*val fromListBy : forall 'a. ('a -> 'a -> ordering) -> list 'a -> set 'a*) + + +(* ------------------------ *) +(* Sigma *) +(* ------------------------ *) + +(*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*) +(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*) + +(*let sigma sa sb= { (a, b) | forall (a IN sa) (b IN sb a) | true }*) + + +(* ------------------------ *) +(* cross product *) +(* ------------------------ *) + +(*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*) +(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> ordering) -> set 'a -> set 'b -> set ('a * 'b)*) + +(*let cross s1 s2= { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*) + + +(* ------------------------ *) +(* finite *) +(* ------------------------ *) + +(*val finite : forall 'a. SetType 'a => set 'a -> bool*) + + +(* ----------------------------*) +(* fixed point *) +(* --------------------------- *) + +(*val leastFixedPoint : forall 'a. SetType 'a + => nat -> (set 'a -> set 'a) -> set 'a -> set 'a*) +fun leastFixedPoint :: " nat \<Rightarrow>('a set \<Rightarrow> 'a set)\<Rightarrow> 'a set \<Rightarrow> 'a set " where + " leastFixedPoint 0 f x = ( x )" +|" leastFixedPoint ((Suc bound')) f x = ( (let fx = (f x) in + if fx \<subseteq> x then x + else leastFixedPoint bound' f (fx \<union> x)))" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_set_extra.thy b/snapshots/isabelle/lib/lem/Lem_set_extra.thy new file mode 100644 index 00000000..33516be7 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set_extra.thy @@ -0,0 +1,121 @@ +chapter \<open>Generated by Lem from set_extra.lem.\<close> + +theory "Lem_set_extra" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + "Lem_list" + "Lem_sorting" + "Lem_set" + +begin + +(******************************************************************************) +(* A library for sets *) +(* *) +(* It mainly follows the Haskell Set-library *) +(******************************************************************************) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num List Sorting Set*) + + +(* ----------------------------*) +(* set choose (be careful !) *) +(* --------------------------- *) + +(*val choose : forall 'a. SetType 'a => set 'a -> 'a*) + +(* ------------------------ *) +(* chooseAndSplit *) +(* ------------------------ *) +(* The idea here is to provide a simple primitive that Lem code can use + * to perform its own custom searches within the set -- likely using a + * search criterion related to the element ordering, but not necessarily). + * For example, sometimes we don't necessarily want to search for a specific + * element, but want to search for elements greater than or less than some other. + * Someties we'd like to use split but don't know a good value to split at. + * This function lets the set implementation decide that value. + * + * The contract of chooseAndSplit is simply to select an element nondeterministically + * and return that element, together with the subsets of elements less than and + * greater than it. In this way, we can recursively traverse the set with any + * search criterion, and we avoid baking in the tree representation (although that + * is the obvious choice). + *) +(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> maybe (set 'a * 'a * set 'a)*) +definition chooseAndSplit :: " 'a Ord_class \<Rightarrow> 'a set \<Rightarrow>('a set*'a*'a set)option " where + " chooseAndSplit dict_Basic_classes_Ord_a s = ( + if s = {} then + None + else + (let element = (set_choose s) in + (let (lt, gt) = (Lem_set.split + dict_Basic_classes_Ord_a element s) in + Some (lt, element, gt))))" + + +(* ----------------------------*) +(* universal set *) +(* --------------------------- *) + +(*val universal : forall 'a. SetType 'a => set 'a*) + + +(* ----------------------------*) +(* toList *) +(* --------------------------- *) + +(*val toList : forall 'a. SetType 'a => set 'a -> list 'a*) + + +(* ----------------------------*) +(* toOrderedList *) +(* --------------------------- *) + +(* toOrderedList returns a sorted list. Therefore the result is (given a suitable order) deterministic. + Therefore, it is much preferred to toList. However, it still is only defined for finite sets. So, please + use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations + and then transforming back to sets. *) + +(*val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a*) + +(*val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a*) + +(* ----------------------- *) +(* compare *) +(* ----------------------- *) + +(*val setCompareBy: forall 'a. ('a -> 'a -> ordering) -> set 'a -> set 'a -> ordering*) +definition setCompareBy :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a set \<Rightarrow> 'a set \<Rightarrow> ordering " where + " setCompareBy cmp ss ts = ( + (let ss' = (ordered_list_of_set (\<lambda> x y . cmp x y = LT) ss) in + (let ts' = (ordered_list_of_set (\<lambda> x y . cmp x y = LT) ts) in + lexicographicCompareBy cmp ss' ts')))" + + +(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> ordering*) +definition setCompare :: " 'a Ord_class \<Rightarrow> 'a set \<Rightarrow> 'a set \<Rightarrow> ordering " where + " setCompare dict_Basic_classes_Ord_a = ( setCompareBy + (compare_method dict_Basic_classes_Ord_a) )" + + +(* ----------------------------*) +(* unbounded fixed point *) +(* --------------------------- *) + +(* Is NOT supported by the coq backend! *) +(*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*) +(*let rec leastFixedPointUnbounded f x= + let fx = f x in + if fx subset x then x + else leastFixedPointUnbounded f (fx union x)*) +end diff --git a/snapshots/isabelle/lib/lem/Lem_set_helpers.thy b/snapshots/isabelle/lib/lem/Lem_set_helpers.thy new file mode 100644 index 00000000..1a2f5f50 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_set_helpers.thy @@ -0,0 +1,50 @@ +chapter \<open>Generated by Lem from set_helpers.lem.\<close> + +theory "Lem_set_helpers" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_function" + "Lem_num" + +begin + +(******************************************************************************) +(* Helper functions for sets *) +(******************************************************************************) + +(* Usually there is a something.lem file containing the main definitions and a + something_extra.lem one containing functions that might cause problems for + some backends or are just seldomly used. + + For sets the situation is different. folding is not well defined, since it + is only sensibly defined for finite sets and the traversal + order is underspecified. *) + +(* ========================================================================== *) +(* Header *) +(* ========================================================================== *) + +(*open import Bool Basic_classes Maybe Function Num*) + +(*open import {coq} `Coq.Lists.List`*) + +(* ------------------------ *) +(* fold *) +(* ------------------------ *) + +(* fold is suspicious, because if given a function, for which + the order, in which the arguments are given, matters, its + results are undefined. On the other hand, it is very handy to + define other - non suspicious functions. + + Moreover, fold is central for OCaml, since it is used to + compile set comprehensions *) + +(*val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b*) + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_show.thy b/snapshots/isabelle/lib/lem/Lem_show.thy new file mode 100644 index 00000000..fced534d --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_show.thy @@ -0,0 +1,87 @@ +chapter \<open>Generated by Lem from show.lem.\<close> + +theory "Lem_show" + +imports + Main + "Lem_string" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + +begin + + + +(*open import String Maybe Num Basic_classes*) + +(*open import {hol} `lemTheory`*) + +record 'a Show_class= + + show_method::" 'a \<Rightarrow> string " + + + +definition instance_Show_Show_string_dict :: "(string)Show_class " where + " instance_Show_Show_string_dict = ((| + + show_method = (\<lambda> s. ([(char_of_nat 34)]) @ (s @ ([(char_of_nat 34)])))|) )" + + +(*val stringFromMaybe : forall 'a. ('a -> string) -> maybe 'a -> string*) +fun stringFromMaybe :: "('a \<Rightarrow> string)\<Rightarrow> 'a option \<Rightarrow> string " where + " stringFromMaybe showX (Some x) = ( (''Just ('') @ (showX x @ ('')'')))" +|" stringFromMaybe showX None = ( (''Nothing''))" + + +definition instance_Show_Show_Maybe_maybe_dict :: " 'a Show_class \<Rightarrow>('a option)Show_class " where + " instance_Show_Show_Maybe_maybe_dict dict_Show_Show_a = ((| + + show_method = (\<lambda> x_opt. stringFromMaybe + (show_method dict_Show_Show_a) x_opt)|) )" + + +(*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*) +function (sequential,domintros) stringFromListAux :: "('a \<Rightarrow> string)\<Rightarrow> 'a list \<Rightarrow> string " where + " stringFromListAux showX ([]) = ( (''''))" +|" stringFromListAux showX (x # xs') = ( + (case xs' of + [] => showX x + | _ => showX x @ ((''; '') @ stringFromListAux showX xs') + ))" +by pat_completeness auto + + +(*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*) +definition stringFromList :: "('a \<Rightarrow> string)\<Rightarrow> 'a list \<Rightarrow> string " where + " stringFromList showX xs = ( + (''['') @ (stringFromListAux showX xs @ ('']'')))" + + +definition instance_Show_Show_list_dict :: " 'a Show_class \<Rightarrow>('a list)Show_class " where + " instance_Show_Show_list_dict dict_Show_Show_a = ((| + + show_method = (\<lambda> xs. stringFromList + (show_method dict_Show_Show_a) xs)|) )" + + +(*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*) +fun stringFromPair :: "('a \<Rightarrow> string)\<Rightarrow>('b \<Rightarrow> string)\<Rightarrow> 'a*'b \<Rightarrow> string " where + " stringFromPair showX showY (x,y) = ( + (''('') @ (showX x @ (('', '') @ (showY y @ ('')'')))))" + + +definition instance_Show_Show_tup2_dict :: " 'a Show_class \<Rightarrow> 'b Show_class \<Rightarrow>('a*'b)Show_class " where + " instance_Show_Show_tup2_dict dict_Show_Show_a dict_Show_Show_b = ((| + + show_method = (stringFromPair + (show_method dict_Show_Show_a) (show_method dict_Show_Show_b))|) )" + + +definition instance_Show_Show_bool_dict :: "(bool)Show_class " where + " instance_Show_Show_bool_dict = ((| + + show_method = (\<lambda> b. if b then (''true'') else (''false''))|) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_show_extra.thy b/snapshots/isabelle/lib/lem/Lem_show_extra.thy new file mode 100644 index 00000000..25ab2570 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_show_extra.thy @@ -0,0 +1,74 @@ +chapter \<open>Generated by Lem from show_extra.lem.\<close> + +theory "Lem_show_extra" + +imports + Main + "Lem_string" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + "Lem_set" + "Lem_relation" + "Lem_show" + "Lem_set_extra" + "Lem_string_extra" + +begin + + + +(*open import String Maybe Num Basic_classes Set Relation Show*) +(*import Set_extra String_extra*) + +definition instance_Show_Show_nat_dict :: "(nat)Show_class " where + " instance_Show_Show_nat_dict = ((| + + show_method = Lem_string_extra.stringFromNat |) )" + + +definition instance_Show_Show_Num_natural_dict :: "(nat)Show_class " where + " instance_Show_Show_Num_natural_dict = ((| + + show_method = Lem_string_extra.stringFromNatural |) )" + + +definition instance_Show_Show_Num_int_dict :: "(int)Show_class " where + " instance_Show_Show_Num_int_dict = ((| + + show_method = Lem_string_extra.stringFromInt |) )" + + +definition instance_Show_Show_Num_integer_dict :: "(int)Show_class " where + " instance_Show_Show_Num_integer_dict = ((| + + show_method = Lem_string_extra.stringFromInteger |) )" + + +definition stringFromSet :: "('a \<Rightarrow> string)\<Rightarrow> 'a set \<Rightarrow> string " where + " stringFromSet showX xs = ( + (''{'') @ (Lem_show.stringFromListAux showX (list_of_set xs) @ (''}'')))" + + +(* Abbreviates the representation if the relation is transitive. *) +definition stringFromRelation :: "('a*'a \<Rightarrow> string)\<Rightarrow>('a*'a)set \<Rightarrow> string " where + " stringFromRelation showX rel = ( + if trans rel then + (let pruned_rel = (LemExtraDefs.without_trans_edges rel) in + if ((\<forall> e \<in> rel. (e \<in> pruned_rel))) then + (* The relations are the same (there are no transitive edges), + so we can just as well print the original one. *) + stringFromSet showX rel + else + (''trancl of '') @ stringFromSet showX pruned_rel) + else + stringFromSet showX rel )" + + +definition instance_Show_Show_set_dict :: " 'a Show_class \<Rightarrow>('a set)Show_class " where + " instance_Show_Show_set_dict dict_Show_Show_a = ((| + + show_method = (\<lambda> xs. stringFromSet + (show_method dict_Show_Show_a) xs)|) )" + +end diff --git a/snapshots/isabelle/lib/lem/Lem_sorting.thy b/snapshots/isabelle/lib/lem/Lem_sorting.thy new file mode 100644 index 00000000..d42425a2 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_sorting.thy @@ -0,0 +1,110 @@ +chapter \<open>Generated by Lem from sorting.lem.\<close> + +theory "Lem_sorting" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_maybe" + "Lem_list" + "Lem_num" + "Lem" + "~~/src/HOL/Library/Permutation" + +begin + + + +(*open import Bool Basic_classes Maybe List Num*) + +(*open import {isabelle} `~~/src/HOL/Library/Permutation`*) +(*open import {coq} `Coq.Lists.List`*) +(*open import {hol} `sortingTheory` `permLib`*) +(*open import {isabelle} `$LIB_DIR/Lem`*) + +(* ------------------------- *) +(* permutations *) +(* ------------------------- *) + +(*val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool*) +(*val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*) + +fun isPermutationBy :: "('a \<Rightarrow> 'a \<Rightarrow> bool)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> bool " where + " isPermutationBy eq ([]) l2 = ( (l2 = []))" +|" isPermutationBy eq (x # xs) l2 = ( ( + (case delete_first (eq x) l2 of + None => False + | Some ys => isPermutationBy eq xs ys + ) + ))" + + + + +(* ------------------------- *) +(* isSorted *) +(* ------------------------- *) + +(* isSortedBy R l + checks, whether the list l is sorted by ordering R. + R should represent an order, i.e. it should be transitive. + Different backends defined isSorted slightly differently. However, + the definitions coincide for transitive R. Therefore there is the + following restriction: + + WARNING: Use isSorted and isSortedBy only with transitive relations! +*) + +(*val isSorted : forall 'a. Ord 'a => list 'a -> bool*) +(*val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool*) + +(* DPM: rejigged the definition with a nested match to get past Coq's termination checker. *) +(*let rec isSortedBy cmp l= match l with + | [] -> true + | x1 :: xs -> + match xs with + | [] -> true + | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs) + end +end*) + + +(* ----------------------- *) +(* insertion sort *) +(* ----------------------- *) + +(*val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a*) +(*val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*) + +(*val insertSort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) + +(*let rec insertBy cmp e l= match l with + | [] -> [e] + | x :: xs -> if cmp x e then x :: (insertBy cmp e xs) else (e :: x :: xs) +end*) + +(*let insertSortBy cmp l= List.foldl (fun l e -> insertBy cmp e l) [] l*) + + +(* ----------------------- *) +(* general sorting *) +(* ----------------------- *) + +(*val sort: forall 'a. Ord 'a => list 'a -> list 'a*) +(*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*) +(*val sortByOrd: forall 'a. ('a -> 'a -> ordering) -> list 'a -> list 'a*) + +(*val predicate_of_ord : forall 'a. ('a -> 'a -> ordering) -> 'a -> 'a -> bool*) +definition predicate_of_ord :: "('a \<Rightarrow> 'a \<Rightarrow> ordering)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where + " predicate_of_ord f x y = ( + (case f x y of + LT => True + | EQ => True + | GT => False + ))" + + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_string.thy b/snapshots/isabelle/lib/lem/Lem_string.thy new file mode 100644 index 00000000..9df246c4 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_string.thy @@ -0,0 +1,75 @@ +chapter \<open>Generated by Lem from string.lem.\<close> + +theory "Lem_string" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + "Lem_list" + +begin + + + +(*open import Bool Basic_classes List*) +(*open import {ocaml} `Xstring`*) +(*open import {hol} `lemTheory` `stringTheory`*) +(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*) + +(* ------------------------------------------- *) +(* translations between strings and char lists *) +(* ------------------------------------------- *) + +(*val toCharList : string -> list char*) + +(*val toString : list char -> string*) + + +(* ----------------------- *) +(* generating strings *) +(* ----------------------- *) + +(*val makeString : nat -> char -> string*) +(*let makeString len c= toString (replicate len c)*) + +(* ----------------------- *) +(* length *) +(* ----------------------- *) + +(*val stringLength : string -> nat*) + +(* ----------------------- *) +(* string concatenation *) +(* ----------------------- *) + +(*val ^ [stringAppend] : string -> string -> string*) + + +(* ----------------------------*) +(* setting up pattern matching *) +(* --------------------------- *) + +(*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*) + +(*let string_case s c_empty c_cons= + match (toCharList s) with + | [] -> c_empty + | c :: cs -> c_cons c (toString cs) + end*) + +(*val empty_string : string*) + +(*val cons_string : char -> string -> string*) + +(*val concat : string -> list string -> string*) +function (sequential,domintros) concat :: " string \<Rightarrow>(string)list \<Rightarrow> string " where + " concat sep ([]) = ( (''''))" +|" concat sep (s # ss') = ( + (case ss' of + [] => s + | _ => s @ (sep @ concat sep ss') + ))" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/lem/Lem_string_extra.thy b/snapshots/isabelle/lib/lem/Lem_string_extra.thy new file mode 100644 index 00000000..bd8317ba --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_string_extra.thy @@ -0,0 +1,137 @@ +chapter \<open>Generated by Lem from string_extra.lem.\<close> + +theory "Lem_string_extra" + +imports + Main + "Lem_num" + "Lem_list" + "Lem_basic_classes" + "Lem_string" + "Lem_list_extra" + +begin + +(******************************************************************************) +(* String functions *) +(******************************************************************************) + +(*open import Basic_classes*) +(*open import Num*) +(*open import List*) +(*open import String*) +(*open import List_extra*) +(*open import {hol} `stringLib`*) +(*open import {hol} `ASCIInumbersTheory`*) + + +(******************************************************************************) +(* Character's to numbers *) +(******************************************************************************) + +(*val ord : char -> nat*) + +(*val chr : nat -> char*) + +(******************************************************************************) +(* Converting to strings *) +(******************************************************************************) + +(*val stringFromNatHelper : nat -> list char -> list char*) +fun stringFromNatHelper :: " nat \<Rightarrow>(char)list \<Rightarrow>(char)list " where + " stringFromNatHelper n acc1 = ( + if n =( 0 :: nat) then + acc1 + else + stringFromNatHelper (n div( 10 :: nat)) (char_of_nat ((n mod( 10 :: nat)) +( 48 :: nat)) # acc1))" + + +(*val stringFromNat : nat -> string*) +definition stringFromNat :: " nat \<Rightarrow> string " where + " stringFromNat n = ( + if n =( 0 :: nat) then (''0'') else (stringFromNatHelper n []))" + + +(*val stringFromNaturalHelper : natural -> list char -> list char*) +fun stringFromNaturalHelper :: " nat \<Rightarrow>(char)list \<Rightarrow>(char)list " where + " stringFromNaturalHelper n acc1 = ( + if n =( 0 :: nat) then + acc1 + else + stringFromNaturalHelper (n div( 10 :: nat)) (char_of_nat ( ((n mod( 10 :: nat)) +( 48 :: nat))) # acc1))" + + +(*val stringFromNatural : natural -> string*) +definition stringFromNatural :: " nat \<Rightarrow> string " where + " stringFromNatural n = ( + if n =( 0 :: nat) then (''0'') else (stringFromNaturalHelper n []))" + + +(*val stringFromInt : int -> string*) +definition stringFromInt :: " int \<Rightarrow> string " where + " stringFromInt i = ( + if i <( 0 :: int) then + (''-'') @ stringFromNat (nat (abs i)) + else + stringFromNat (nat (abs i)))" + + +(*val stringFromInteger : integer -> string*) +definition stringFromInteger :: " int \<Rightarrow> string " where + " stringFromInteger i = ( + if i <( 0 :: int) then + (''-'') @ stringFromNatural (nat (abs i)) + else + stringFromNatural (nat (abs i)))" + + + +(******************************************************************************) +(* List-like operations *) +(******************************************************************************) + +(*val nth : string -> nat -> char*) +definition nth :: " string \<Rightarrow> nat \<Rightarrow> char " where + " nth s n = ( List.nth ( s) n )" + + +(*val stringConcat : list string -> string*) +definition stringConcat :: "(string)list \<Rightarrow> string " where + " stringConcat s = ( + List.foldr (op@) s (''''))" + + +(******************************************************************************) +(* String comparison *) +(******************************************************************************) + +(*val stringCompare : string -> string -> ordering*) + +definition stringLess :: " string \<Rightarrow> string \<Rightarrow> bool " where + " stringLess x y = ( orderingIsLess (EQ))" + +definition stringLessEq :: " string \<Rightarrow> string \<Rightarrow> bool " where + " stringLessEq x y = ( \<not> (orderingIsGreater (EQ)))" + +definition stringGreater :: " string \<Rightarrow> string \<Rightarrow> bool " where + " stringGreater x y = ( stringLess y x )" + +definition stringGreaterEq :: " string \<Rightarrow> string \<Rightarrow> bool " where + " stringGreaterEq x y = ( stringLessEq y x )" + + +definition instance_Basic_classes_Ord_string_dict :: "(string)Ord_class " where + " instance_Basic_classes_Ord_string_dict = ((| + + compare_method = (\<lambda> x y. EQ), + + isLess_method = stringLess, + + isLessEqual_method = stringLessEq, + + isGreater_method = stringGreater, + + isGreaterEqual_method = stringGreaterEq |) )" + + +end diff --git a/snapshots/isabelle/lib/lem/Lem_tuple.thy b/snapshots/isabelle/lib/lem/Lem_tuple.thy new file mode 100644 index 00000000..66f1a209 --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_tuple.thy @@ -0,0 +1,51 @@ +chapter \<open>Generated by Lem from tuple.lem.\<close> + +theory "Lem_tuple" + +imports + Main + "Lem_bool" + "Lem_basic_classes" + +begin + + + +(*open import Bool Basic_classes*) + +(* ----------------------- *) +(* fst *) +(* ----------------------- *) + +(*val fst : forall 'a 'b. 'a * 'b -> 'a*) +(*let fst (v1, v2)= v1*) + +(* ----------------------- *) +(* snd *) +(* ----------------------- *) + +(*val snd : forall 'a 'b. 'a * 'b -> 'b*) +(*let snd (v1, v2)= v2*) + + +(* ----------------------- *) +(* curry *) +(* ----------------------- *) + +(*val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)*) + +(* ----------------------- *) +(* uncurry *) +(* ----------------------- *) + +(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*) + + +(* ----------------------- *) +(* swap *) +(* ----------------------- *) + +(*val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)*) +(*let swap (v1, v2)= (v2, v1)*) + +end diff --git a/snapshots/isabelle/lib/lem/Lem_word.thy b/snapshots/isabelle/lib/lem/Lem_word.thy new file mode 100644 index 00000000..bc56da3c --- /dev/null +++ b/snapshots/isabelle/lib/lem/Lem_word.thy @@ -0,0 +1,1024 @@ +chapter \<open>Generated by Lem from word.lem.\<close> + +theory "Lem_word" + +imports + Main + "Lem_bool" + "Lem_maybe" + "Lem_num" + "Lem_basic_classes" + "Lem_list" + "~~/src/HOL/Word/Word" + +begin + + + +(*open import Bool Maybe Num Basic_classes List*) + +(*open import {isabelle} `~~/src/HOL/Word/Word`*) +(*open import {hol} `wordsTheory` `wordsLib`*) + + +(* ========================================================================== *) +(* Define general purpose word, i.e. sequences of bits of arbitrary length *) +(* ========================================================================== *) + +datatype bitSequence = BitSeq " + nat option " " (* length of the sequence, Nothing means infinite length *) + bool " " bool (* sign of the word, used to fill up after concrete value is exhausted *) + list " (* the initial part of the sequence, least significant bit first *) + +(*val bitSeqEq : bitSequence -> bitSequence -> bool*) + +(*val boolListFrombitSeq : nat -> bitSequence -> list bool*) + +fun boolListFrombitSeqAux :: " nat \<Rightarrow> 'a \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " boolListFrombitSeqAux n s bl = ( + if n =( 0 :: nat) then [] else + (case bl of + [] => List.replicate n s + | b # bl' => b # (boolListFrombitSeqAux (n-( 1 :: nat)) s bl') + ))" + + +fun boolListFrombitSeq :: " nat \<Rightarrow> bitSequence \<Rightarrow>(bool)list " where + " boolListFrombitSeq n (BitSeq _ s bl) = ( boolListFrombitSeqAux n s bl )" + + + +(*val bitSeqFromBoolList : list bool -> maybe bitSequence*) +definition bitSeqFromBoolList :: "(bool)list \<Rightarrow>(bitSequence)option " where + " bitSeqFromBoolList bl = ( + (case dest_init bl of + None => None + | Some (bl', s) => Some (BitSeq (Some (List.length bl)) s bl') + ))" + + + +(* cleans up the representation of a bitSequence without changing its semantics *) +(*val cleanBitSeq : bitSequence -> bitSequence*) +fun cleanBitSeq :: " bitSequence \<Rightarrow> bitSequence " where + " cleanBitSeq (BitSeq len s bl) = ( (case len of + None => (BitSeq len s (List.rev (dropWhile ((op \<longleftrightarrow>) s) (List.rev bl)))) + | Some n => (BitSeq len s (List.rev (dropWhile ((op \<longleftrightarrow>) s) (List.rev (List.take (n-( 1 :: nat)) bl))))) +))" + + + +(*val bitSeqTestBit : bitSequence -> nat -> maybe bool*) +fun bitSeqTestBit :: " bitSequence \<Rightarrow> nat \<Rightarrow>(bool)option " where + " bitSeqTestBit (BitSeq None s bl) pos = ( if pos < List.length bl then index bl pos else Some s )" +|" bitSeqTestBit (BitSeq(Some l) s bl) pos = ( if (pos \<ge> l) then None else + if ((pos = (l -( 1 :: nat))) \<or> (pos \<ge> List.length bl)) then Some s else + index bl pos )" + + +(*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*) +fun bitSeqSetBit :: " bitSequence \<Rightarrow> nat \<Rightarrow> bool \<Rightarrow> bitSequence " where + " bitSeqSetBit (BitSeq len s bl) pos v = ( + (let bl' = (if (pos < List.length bl) then bl else bl @ List.replicate pos s) in + (let bl'' = (List.list_update bl' pos v) in + (let bs' = (BitSeq len s bl'') in + cleanBitSeq bs'))))" + + + +(*val resizeBitSeq : maybe nat -> bitSequence -> bitSequence*) +definition resizeBitSeq :: "(nat)option \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " resizeBitSeq new_len bs = ( + (case cleanBitSeq bs of + (BitSeq len s bl) => + (let shorten_opt = ((case (new_len, len) of + (None, _) => None + | (Some l1, None) => Some l1 + | (Some l1, Some l2) => + if (l1 < l2) then Some l1 else None + )) in + (case shorten_opt of + None => BitSeq new_len s bl + | Some l1 => ( + (let bl' = (List.take l1 (bl @ [s])) in + (case dest_init bl' of + None => (BitSeq len s bl) (* do nothing if size 0 is requested *) + | Some (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'') + ))) + )) + ) )" + + +(*val bitSeqNot : bitSequence -> bitSequence*) +fun bitSeqNot :: " bitSequence \<Rightarrow> bitSequence " where + " bitSeqNot (BitSeq len s bl) = ( BitSeq len (\<not> s) (List.map (\<lambda> x. \<not> x) bl))" + + +(*val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence*) + +(*val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool*) +fun bitSeqBinopAux :: "(bool \<Rightarrow> bool \<Rightarrow> bool)\<Rightarrow> bool \<Rightarrow>(bool)list \<Rightarrow> bool \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where + " bitSeqBinopAux binop s1 ([]) s2 ([]) = ( [])" +|" bitSeqBinopAux binop s1 (b1 # bl1') s2 ([]) = ( (binop b1 s2) # bitSeqBinopAux binop s1 bl1' s2 [])" +|" bitSeqBinopAux binop s1 ([]) s2 (b2 # bl2') = ( (binop s1 b2) # bitSeqBinopAux binop s1 [] s2 bl2' )" +|" bitSeqBinopAux binop s1 (b1 # bl1') s2 (b2 # bl2') = ( (binop b1 b2) # bitSeqBinopAux binop s1 bl1' s2 bl2' )" + + +definition bitSeqBinop :: "(bool \<Rightarrow> bool \<Rightarrow> bool)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqBinop binop bs1 bs2 = ( ( + (case cleanBitSeq bs1 of + (BitSeq len1 s1 bl1) => + (case cleanBitSeq bs2 of + (BitSeq len2 s2 bl2) => + (let len = ((case (len1, len2) of + (Some l1, Some l2) => Some (max l1 l2) + | _ => None + )) in + (let s = (binop s1 s2) in + (let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in + cleanBitSeq (BitSeq len s bl)))) + ) + ) +))" + + +definition bitSeqAnd :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqAnd = ( bitSeqBinop (op \<and>))" + +definition bitSeqOr :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqOr = ( bitSeqBinop (op \<or>))" + +definition bitSeqXor :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqXor = ( bitSeqBinop (\<lambda> b1 b2. \<not> (b1 \<longleftrightarrow> b2)))" + + +(*val bitSeqShiftLeft : bitSequence -> nat -> bitSequence*) +fun bitSeqShiftLeft :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where + " bitSeqShiftLeft (BitSeq len s bl) n = ( cleanBitSeq (BitSeq len s (List.replicate n False @ bl)))" + + +(*val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence*) +definition bitSeqArithmeticShiftRight :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where + " bitSeqArithmeticShiftRight bs n = ( + (case cleanBitSeq bs of + (BitSeq len s bl) => + cleanBitSeq (BitSeq len s (List.drop n bl)) + ) )" + + +(*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*) +definition bitSeqLogicalShiftRight :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where + " bitSeqLogicalShiftRight bs n = ( + if (n =( 0 :: nat)) then cleanBitSeq bs else + (case cleanBitSeq bs of + (BitSeq len s bl) => + (case len of + None => cleanBitSeq (BitSeq len s (List.drop n bl)) + | Some l => cleanBitSeq + (BitSeq len False ((List.drop n bl) @ List.replicate l s)) + ) + ) )" + + + +(* integerFromBoolList sign bl creates an integer from a list of bits + (least significant bit first) and an explicitly given sign bit. + It uses two's complement encoding. *) +(*val integerFromBoolList : (bool * list bool) -> integer*) + +fun integerFromBoolListAux :: " int \<Rightarrow>(bool)list \<Rightarrow> int " where + " integerFromBoolListAux (acc1 :: int) (([]) :: bool list) = ( acc1 )" +|" integerFromBoolListAux (acc1 :: int) ((True # bl') :: bool list) = ( integerFromBoolListAux ((acc1 *( 2 :: int)) +( 1 :: int)) bl' )" +|" integerFromBoolListAux (acc1 :: int) ((False # bl') :: bool list) = ( integerFromBoolListAux (acc1 *( 2 :: int)) bl' )" + + +fun integerFromBoolList :: " bool*(bool)list \<Rightarrow> int " where + " integerFromBoolList (sign, bl) = ( + if sign then + - (integerFromBoolListAux(( 0 :: int)) (List.rev (List.map (\<lambda> x. \<not> x) bl)) +( 1 :: int)) + else integerFromBoolListAux(( 0 :: int)) (List.rev bl))" + + +(* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*) +(*val boolListFromInteger : integer -> bool * list bool*) + +fun boolListFromNatural :: "(bool)list \<Rightarrow> nat \<Rightarrow>(bool)list " where + " boolListFromNatural acc1 (remainder :: nat) = ( + if (remainder >( 0 :: nat)) then + (boolListFromNatural (((remainder mod( 2 :: nat)) =( 1 :: nat)) # acc1) + (remainder div( 2 :: nat))) + else + List.rev acc1 )" + + +definition boolListFromInteger :: " int \<Rightarrow> bool*(bool)list " where + " boolListFromInteger (i :: int) = ( + if (i <( 0 :: int)) then + (True, List.map (\<lambda> x. \<not> x) (boolListFromNatural [] (nat (abs (- (i +( 1 :: int))))))) + else + (False, boolListFromNatural [] (nat (abs i))))" + + + +(* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough + bits, truncation happens *) +(*val bitSeqFromInteger : maybe nat -> integer -> bitSequence*) +definition bitSeqFromInteger :: "(nat)option \<Rightarrow> int \<Rightarrow> bitSequence " where + " bitSeqFromInteger len_opt i = ( + (let (s, bl) = (boolListFromInteger i) in + resizeBitSeq len_opt (BitSeq None s bl)))" + + + +(*val integerFromBitSeq : bitSequence -> integer*) +definition integerFromBitSeq :: " bitSequence \<Rightarrow> int " where + " integerFromBitSeq bs = ( + (case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) ) )" + + + +(* Now we can via translation to integers map arithmetic operations to bitSequences *) + +(*val bitSeqArithUnaryOp : (integer -> integer) -> bitSequence -> bitSequence*) +definition bitSeqArithUnaryOp :: "(int \<Rightarrow> int)\<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqArithUnaryOp uop bs = ( + (case bs of + (BitSeq len _ _) => + bitSeqFromInteger len (uop (integerFromBitSeq bs)) + ) )" + + +(*val bitSeqArithBinOp : (integer -> integer -> integer) -> bitSequence -> bitSequence -> bitSequence*) +definition bitSeqArithBinOp :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqArithBinOp binop bs1 bs2 = ( + (case bs1 of + (BitSeq len1 _ _) => + (case bs2 of + (BitSeq len2 _ _) => + (let len = ((case (len1, len2) of + (Some l1, Some l2) => Some (max l1 l2) + | _ => None + )) in + bitSeqFromInteger len + (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))) + ) + ) )" + + +(*val bitSeqArithBinTest : forall 'a. (integer -> integer -> 'a) -> bitSequence -> bitSequence -> 'a*) +definition bitSeqArithBinTest :: "(int \<Rightarrow> int \<Rightarrow> 'a)\<Rightarrow> bitSequence \<Rightarrow> bitSequence \<Rightarrow> 'a " where + " bitSeqArithBinTest binop bs1 bs2 = ( binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))" + + + +(* now instantiate the number interface for bit-sequences *) + +(*val bitSeqFromNumeral : numeral -> bitSequence*) + +(*val bitSeqLess : bitSequence -> bitSequence -> bool*) +definition bitSeqLess :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where + " bitSeqLess bs1 bs2 = ( bitSeqArithBinTest (op<) bs1 bs2 )" + + +(*val bitSeqLessEqual : bitSequence -> bitSequence -> bool*) +definition bitSeqLessEqual :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where + " bitSeqLessEqual bs1 bs2 = ( bitSeqArithBinTest (op \<le>) bs1 bs2 )" + + +(*val bitSeqGreater : bitSequence -> bitSequence -> bool*) +definition bitSeqGreater :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where + " bitSeqGreater bs1 bs2 = ( bitSeqArithBinTest (op>) bs1 bs2 )" + + +(*val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool*) +definition bitSeqGreaterEqual :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bool " where + " bitSeqGreaterEqual bs1 bs2 = ( bitSeqArithBinTest (op \<ge>) bs1 bs2 )" + + +(*val bitSeqCompare : bitSequence -> bitSequence -> ordering*) +definition bitSeqCompare :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> ordering " where + " bitSeqCompare bs1 bs2 = ( bitSeqArithBinTest (genericCompare (op<) (op=)) bs1 bs2 )" + + +definition instance_Basic_classes_Ord_Word_bitSequence_dict :: "(bitSequence)Ord_class " where + " instance_Basic_classes_Ord_Word_bitSequence_dict = ((| + + compare_method = bitSeqCompare, + + isLess_method = bitSeqLess, + + isLessEqual_method = bitSeqLessEqual, + + isGreater_method = bitSeqGreater, + + isGreaterEqual_method = bitSeqGreaterEqual |) )" + + +(* arithmetic negation, don't mix up with bitwise negation *) +(*val bitSeqNegate : bitSequence -> bitSequence*) +definition bitSeqNegate :: " bitSequence \<Rightarrow> bitSequence " where + " bitSeqNegate bs = ( bitSeqArithUnaryOp (\<lambda> i. - i) bs )" + + +definition instance_Num_NumNegate_Word_bitSequence_dict :: "(bitSequence)NumNegate_class " where + " instance_Num_NumNegate_Word_bitSequence_dict = ((| + + numNegate_method = bitSeqNegate |) )" + + + +(*val bitSeqAdd : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqAdd :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqAdd bs1 bs2 = ( bitSeqArithBinOp (op+) bs1 bs2 )" + + +definition instance_Num_NumAdd_Word_bitSequence_dict :: "(bitSequence)NumAdd_class " where + " instance_Num_NumAdd_Word_bitSequence_dict = ((| + + numAdd_method = bitSeqAdd |) )" + + +(*val bitSeqMinus : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMinus :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqMinus bs1 bs2 = ( bitSeqArithBinOp (op-) bs1 bs2 )" + + +definition instance_Num_NumMinus_Word_bitSequence_dict :: "(bitSequence)NumMinus_class " where + " instance_Num_NumMinus_Word_bitSequence_dict = ((| + + numMinus_method = bitSeqMinus |) )" + + +(*val bitSeqSucc : bitSequence -> bitSequence*) +definition bitSeqSucc :: " bitSequence \<Rightarrow> bitSequence " where + " bitSeqSucc bs = ( bitSeqArithUnaryOp (\<lambda> n. n +( 1 :: int)) bs )" + + +definition instance_Num_NumSucc_Word_bitSequence_dict :: "(bitSequence)NumSucc_class " where + " instance_Num_NumSucc_Word_bitSequence_dict = ((| + + succ_method = bitSeqSucc |) )" + + +(*val bitSeqPred : bitSequence -> bitSequence*) +definition bitSeqPred :: " bitSequence \<Rightarrow> bitSequence " where + " bitSeqPred bs = ( bitSeqArithUnaryOp (\<lambda> n. n -( 1 :: int)) bs )" + + +definition instance_Num_NumPred_Word_bitSequence_dict :: "(bitSequence)NumPred_class " where + " instance_Num_NumPred_Word_bitSequence_dict = ((| + + pred_method = bitSeqPred |) )" + + +(*val bitSeqMult : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMult :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqMult bs1 bs2 = ( bitSeqArithBinOp (op*) bs1 bs2 )" + + +definition instance_Num_NumMult_Word_bitSequence_dict :: "(bitSequence)NumMult_class " where + " instance_Num_NumMult_Word_bitSequence_dict = ((| + + numMult_method = bitSeqMult |) )" + + + +(*val bitSeqPow : bitSequence -> nat -> bitSequence*) +definition bitSeqPow :: " bitSequence \<Rightarrow> nat \<Rightarrow> bitSequence " where + " bitSeqPow bs n = ( bitSeqArithUnaryOp (\<lambda> i . i ^ n) bs )" + + +definition instance_Num_NumPow_Word_bitSequence_dict :: "(bitSequence)NumPow_class " where + " instance_Num_NumPow_Word_bitSequence_dict = ((| + + numPow_method = bitSeqPow |) )" + + +(*val bitSeqDiv : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqDiv :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqDiv bs1 bs2 = ( bitSeqArithBinOp (op div) bs1 bs2 )" + + +definition instance_Num_NumIntegerDivision_Word_bitSequence_dict :: "(bitSequence)NumIntegerDivision_class " where + " instance_Num_NumIntegerDivision_Word_bitSequence_dict = ((| + + div_method = bitSeqDiv |) )" + + +definition instance_Num_NumDivision_Word_bitSequence_dict :: "(bitSequence)NumDivision_class " where + " instance_Num_NumDivision_Word_bitSequence_dict = ((| + + numDivision_method = bitSeqDiv |) )" + + +(*val bitSeqMod : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMod :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqMod bs1 bs2 = ( bitSeqArithBinOp (op mod) bs1 bs2 )" + + +definition instance_Num_NumRemainder_Word_bitSequence_dict :: "(bitSequence)NumRemainder_class " where + " instance_Num_NumRemainder_Word_bitSequence_dict = ((| + + mod_method = bitSeqMod |) )" + + +(*val bitSeqMin : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMin :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqMin bs1 bs2 = ( bitSeqArithBinOp min bs1 bs2 )" + + +(*val bitSeqMax : bitSequence -> bitSequence -> bitSequence*) +definition bitSeqMax :: " bitSequence \<Rightarrow> bitSequence \<Rightarrow> bitSequence " where + " bitSeqMax bs1 bs2 = ( bitSeqArithBinOp max bs1 bs2 )" + + +definition instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict :: "(bitSequence)OrdMaxMin_class " where + " instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict = ((| + + max_method = bitSeqMax, + + min_method = bitSeqMin |) )" + + + + + +(* ========================================================================== *) +(* Interface for bitoperations *) +(* ========================================================================== *) + +record 'a WordNot_class= + + lnot_method ::" 'a \<Rightarrow> 'a " + + + +record 'a WordAnd_class= + + land_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a WordOr_class= + + lor_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + + +record 'a WordXor_class= + + lxor_method ::" 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +record 'a WordLsl_class= + + lsl_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a " + + + +record 'a WordLsr_class= + + lsr_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a " + + + +record 'a WordAsr_class= + + asr_method ::" 'a \<Rightarrow> nat \<Rightarrow> 'a " + + + +(* ----------------------- *) +(* bitSequence *) +(* ----------------------- *) + +definition instance_Word_WordNot_Word_bitSequence_dict :: "(bitSequence)WordNot_class " where + " instance_Word_WordNot_Word_bitSequence_dict = ((| + + lnot_method = bitSeqNot |) )" + + +definition instance_Word_WordAnd_Word_bitSequence_dict :: "(bitSequence)WordAnd_class " where + " instance_Word_WordAnd_Word_bitSequence_dict = ((| + + land_method = bitSeqAnd |) )" + + +definition instance_Word_WordOr_Word_bitSequence_dict :: "(bitSequence)WordOr_class " where + " instance_Word_WordOr_Word_bitSequence_dict = ((| + + lor_method = bitSeqOr |) )" + + +definition instance_Word_WordXor_Word_bitSequence_dict :: "(bitSequence)WordXor_class " where + " instance_Word_WordXor_Word_bitSequence_dict = ((| + + lxor_method = bitSeqXor |) )" + + +definition instance_Word_WordLsl_Word_bitSequence_dict :: "(bitSequence)WordLsl_class " where + " instance_Word_WordLsl_Word_bitSequence_dict = ((| + + lsl_method = bitSeqShiftLeft |) )" + + +definition instance_Word_WordLsr_Word_bitSequence_dict :: "(bitSequence)WordLsr_class " where + " instance_Word_WordLsr_Word_bitSequence_dict = ((| + + lsr_method = bitSeqLogicalShiftRight |) )" + + +definition instance_Word_WordAsr_Word_bitSequence_dict :: "(bitSequence)WordAsr_class " where + " instance_Word_WordAsr_Word_bitSequence_dict = ((| + + asr_method = bitSeqArithmeticShiftRight |) )" + + + +(* ----------------------- *) +(* int32 *) +(* ----------------------- *) + +(*val int32Lnot : int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordNot_Num_int32_dict :: "( 32 word)WordNot_class " where + " instance_Word_WordNot_Num_int32_dict = ((| + + lnot_method = (\<lambda> w. (NOT w))|) )" + + + +(*val int32Lor : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordOr_Num_int32_dict :: "( 32 word)WordOr_class " where + " instance_Word_WordOr_Num_int32_dict = ((| + + lor_method = (op OR)|) )" + + +(*val int32Lxor : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordXor_Num_int32_dict :: "( 32 word)WordXor_class " where + " instance_Word_WordXor_Num_int32_dict = ((| + + lxor_method = (op XOR)|) )" + + +(*val int32Land : int32 -> int32 -> int32*) (* XXX: fix *) + +definition instance_Word_WordAnd_Num_int32_dict :: "( 32 word)WordAnd_class " where + " instance_Word_WordAnd_Num_int32_dict = ((| + + land_method = (op AND)|) )" + + +(*val int32Lsl : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordLsl_Num_int32_dict :: "( 32 word)WordLsl_class " where + " instance_Word_WordLsl_Num_int32_dict = ((| + + lsl_method = (op<<)|) )" + + +(*val int32Lsr : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordLsr_Num_int32_dict :: "( 32 word)WordLsr_class " where + " instance_Word_WordLsr_Num_int32_dict = ((| + + lsr_method = (op>>)|) )" + + + +(*val int32Asr : int32 -> nat -> int32*) (* XXX: fix *) + +definition instance_Word_WordAsr_Num_int32_dict :: "( 32 word)WordAsr_class " where + " instance_Word_WordAsr_Num_int32_dict = ((| + + asr_method = (op>>>)|) )" + + + +(* ----------------------- *) +(* int64 *) +(* ----------------------- *) + +(*val int64Lnot : int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordNot_Num_int64_dict :: "( 64 word)WordNot_class " where + " instance_Word_WordNot_Num_int64_dict = ((| + + lnot_method = (\<lambda> w. (NOT w))|) )" + + +(*val int64Lor : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordOr_Num_int64_dict :: "( 64 word)WordOr_class " where + " instance_Word_WordOr_Num_int64_dict = ((| + + lor_method = (op OR)|) )" + + +(*val int64Lxor : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordXor_Num_int64_dict :: "( 64 word)WordXor_class " where + " instance_Word_WordXor_Num_int64_dict = ((| + + lxor_method = (op XOR)|) )" + + +(*val int64Land : int64 -> int64 -> int64*) (* XXX: fix *) + +definition instance_Word_WordAnd_Num_int64_dict :: "( 64 word)WordAnd_class " where + " instance_Word_WordAnd_Num_int64_dict = ((| + + land_method = (op AND)|) )" + + +(*val int64Lsl : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordLsl_Num_int64_dict :: "( 64 word)WordLsl_class " where + " instance_Word_WordLsl_Num_int64_dict = ((| + + lsl_method = (op<<)|) )" + + +(*val int64Lsr : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordLsr_Num_int64_dict :: "( 64 word)WordLsr_class " where + " instance_Word_WordLsr_Num_int64_dict = ((| + + lsr_method = (op>>)|) )" + + +(*val int64Asr : int64 -> nat -> int64*) (* XXX: fix *) + +definition instance_Word_WordAsr_Num_int64_dict :: "( 64 word)WordAsr_class " where + " instance_Word_WordAsr_Num_int64_dict = ((| + + asr_method = (op>>>)|) )" + + + +(* ----------------------- *) +(* Words via bit sequences *) +(* ----------------------- *) + +(*val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a*) +definition defaultLnot :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a " where + " defaultLnot fromBitSeq toBitSeq x = ( fromBitSeq (bitSeqNegate (toBitSeq x)))" + + +(*val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLand :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where + " defaultLand fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLor :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where + " defaultLor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*) +definition defaultLxor :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " where + " defaultLxor fromBitSeq toBitSeq x1 x2 = ( fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2)))" + + +(*val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultLsl :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where + " defaultLsl fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqShiftLeft (toBitSeq x) n))" + + +(*val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultLsr :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where + " defaultLsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n))" + + +(*val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*) +definition defaultAsr :: "(bitSequence \<Rightarrow> 'a)\<Rightarrow>('a \<Rightarrow> bitSequence)\<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow> 'a " where + " defaultAsr fromBitSeq toBitSeq x n = ( fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n))" + + +(* ----------------------- *) +(* integer *) +(* ----------------------- *) + +(*val integerLnot : integer -> integer*) +definition integerLnot :: " int \<Rightarrow> int " where + " integerLnot i = ( - (i +( 1 :: int)))" + + +definition instance_Word_WordNot_Num_integer_dict :: "(int)WordNot_class " where + " instance_Word_WordNot_Num_integer_dict = ((| + + lnot_method = integerLnot |) )" + + + +(*val integerLor : integer -> integer -> integer*) +definition integerLor :: " int \<Rightarrow> int \<Rightarrow> int " where + " integerLor i1 i2 = ( defaultLor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordOr_Num_integer_dict :: "(int)WordOr_class " where + " instance_Word_WordOr_Num_integer_dict = ((| + + lor_method = integerLor |) )" + + +(*val integerLxor : integer -> integer -> integer*) +definition integerLxor :: " int \<Rightarrow> int \<Rightarrow> int " where + " integerLxor i1 i2 = ( defaultLxor integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordXor_Num_integer_dict :: "(int)WordXor_class " where + " instance_Word_WordXor_Num_integer_dict = ((| + + lxor_method = integerLxor |) )" + + +(*val integerLand : integer -> integer -> integer*) +definition integerLand :: " int \<Rightarrow> int \<Rightarrow> int " where + " integerLand i1 i2 = ( defaultLand integerFromBitSeq (bitSeqFromInteger None) i1 i2 )" + + +definition instance_Word_WordAnd_Num_integer_dict :: "(int)WordAnd_class " where + " instance_Word_WordAnd_Num_integer_dict = ((| + + land_method = integerLand |) )" + + +(*val integerLsl : integer -> nat -> integer*) +definition integerLsl :: " int \<Rightarrow> nat \<Rightarrow> int " where + " integerLsl i n = ( defaultLsl integerFromBitSeq (bitSeqFromInteger None) i n )" + + +definition instance_Word_WordLsl_Num_integer_dict :: "(int)WordLsl_class " where + " instance_Word_WordLsl_Num_integer_dict = ((| + + lsl_method = integerLsl |) )" + + +(*val integerAsr : integer -> nat -> integer*) +definition integerAsr :: " int \<Rightarrow> nat \<Rightarrow> int " where + " integerAsr i n = ( defaultAsr integerFromBitSeq (bitSeqFromInteger None) i n )" + + +definition instance_Word_WordLsr_Num_integer_dict :: "(int)WordLsr_class " where + " instance_Word_WordLsr_Num_integer_dict = ((| + + lsr_method = integerAsr |) )" + + +definition instance_Word_WordAsr_Num_integer_dict :: "(int)WordAsr_class " where + " instance_Word_WordAsr_Num_integer_dict = ((| + + asr_method = integerAsr |) )" + + + +(* ----------------------- *) +(* int *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on ints. + However, since int is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of int *) + +(*val intFromBitSeq : bitSequence -> int*) +definition intFromBitSeq :: " bitSequence \<Rightarrow> int " where + " intFromBitSeq bs = ( (integerFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))" + + + +(*val bitSeqFromInt : int -> bitSequence*) +definition bitSeqFromInt :: " int \<Rightarrow> bitSequence " where + " bitSeqFromInt i = ( bitSeqFromInteger (Some(( 31 :: nat))) ( i))" + + + +(*val intLnot : int -> int*) +definition intLnot :: " int \<Rightarrow> int " where + " intLnot i = ( - (i +( 1 :: int)))" + + +definition instance_Word_WordNot_Num_int_dict :: "(int)WordNot_class " where + " instance_Word_WordNot_Num_int_dict = ((| + + lnot_method = intLnot |) )" + + +(*val intLor : int -> int -> int*) +definition intLor :: " int \<Rightarrow> int \<Rightarrow> int " where + " intLor i1 i2 = ( defaultLor intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordOr_Num_int_dict :: "(int)WordOr_class " where + " instance_Word_WordOr_Num_int_dict = ((| + + lor_method = intLor |) )" + + +(*val intLxor : int -> int -> int*) +definition intLxor :: " int \<Rightarrow> int \<Rightarrow> int " where + " intLxor i1 i2 = ( defaultLxor intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordXor_Num_int_dict :: "(int)WordXor_class " where + " instance_Word_WordXor_Num_int_dict = ((| + + lxor_method = intLxor |) )" + + +(*val intLand : int -> int -> int*) +definition intLand :: " int \<Rightarrow> int \<Rightarrow> int " where + " intLand i1 i2 = ( defaultLand intFromBitSeq bitSeqFromInt i1 i2 )" + + +definition instance_Word_WordAnd_Num_int_dict :: "(int)WordAnd_class " where + " instance_Word_WordAnd_Num_int_dict = ((| + + land_method = intLand |) )" + + +(*val intLsl : int -> nat -> int*) +definition intLsl :: " int \<Rightarrow> nat \<Rightarrow> int " where + " intLsl i n = ( defaultLsl intFromBitSeq bitSeqFromInt i n )" + + +definition instance_Word_WordLsl_Num_int_dict :: "(int)WordLsl_class " where + " instance_Word_WordLsl_Num_int_dict = ((| + + lsl_method = intLsl |) )" + + +(*val intAsr : int -> nat -> int*) +definition intAsr :: " int \<Rightarrow> nat \<Rightarrow> int " where + " intAsr i n = ( defaultAsr intFromBitSeq bitSeqFromInt i n )" + + +definition instance_Word_WordAsr_Num_int_dict :: "(int)WordAsr_class " where + " instance_Word_WordAsr_Num_int_dict = ((| + + asr_method = intAsr |) )" + + + + +(* ----------------------- *) +(* natural *) +(* ----------------------- *) + +(* some operations work also on positive numbers *) + +(*val naturalFromBitSeq : bitSequence -> natural*) +definition naturalFromBitSeq :: " bitSequence \<Rightarrow> nat " where + " naturalFromBitSeq bs = ( nat (abs (integerFromBitSeq bs)))" + + +(*val bitSeqFromNatural : maybe nat -> natural -> bitSequence*) +definition bitSeqFromNatural :: "(nat)option \<Rightarrow> nat \<Rightarrow> bitSequence " where + " bitSeqFromNatural len n = ( bitSeqFromInteger len (int n))" + + +(*val naturalLor : natural -> natural -> natural*) +definition naturalLor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " naturalLor i1 i2 = ( defaultLor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordOr_Num_natural_dict :: "(nat)WordOr_class " where + " instance_Word_WordOr_Num_natural_dict = ((| + + lor_method = naturalLor |) )" + + +(*val naturalLxor : natural -> natural -> natural*) +definition naturalLxor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " naturalLxor i1 i2 = ( defaultLxor naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordXor_Num_natural_dict :: "(nat)WordXor_class " where + " instance_Word_WordXor_Num_natural_dict = ((| + + lxor_method = naturalLxor |) )" + + +(*val naturalLand : natural -> natural -> natural*) +definition naturalLand :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " naturalLand i1 i2 = ( defaultLand naturalFromBitSeq (bitSeqFromNatural None) i1 i2 )" + + +definition instance_Word_WordAnd_Num_natural_dict :: "(nat)WordAnd_class " where + " instance_Word_WordAnd_Num_natural_dict = ((| + + land_method = naturalLand |) )" + + +(*val naturalLsl : natural -> nat -> natural*) +definition naturalLsl :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " naturalLsl i n = ( defaultLsl naturalFromBitSeq (bitSeqFromNatural None) i n )" + + +definition instance_Word_WordLsl_Num_natural_dict :: "(nat)WordLsl_class " where + " instance_Word_WordLsl_Num_natural_dict = ((| + + lsl_method = naturalLsl |) )" + + +(*val naturalAsr : natural -> nat -> natural*) +definition naturalAsr :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " naturalAsr i n = ( defaultAsr naturalFromBitSeq (bitSeqFromNatural None) i n )" + + +definition instance_Word_WordLsr_Num_natural_dict :: "(nat)WordLsr_class " where + " instance_Word_WordLsr_Num_natural_dict = ((| + + lsr_method = naturalAsr |) )" + + +definition instance_Word_WordAsr_Num_natural_dict :: "(nat)WordAsr_class " where + " instance_Word_WordAsr_Num_natural_dict = ((| + + asr_method = naturalAsr |) )" + + + +(* ----------------------- *) +(* nat *) +(* ----------------------- *) + +(* sometimes it is convenient to be able to perform bit-operations on nats. + However, since nat is not well-defined (it has different size on different systems), + it should be used very carefully and only for operations that don't depend on the + bitwidth of nat *) + +(*val natFromBitSeq : bitSequence -> nat*) +definition natFromBitSeq :: " bitSequence \<Rightarrow> nat " where + " natFromBitSeq bs = ( (naturalFromBitSeq (resizeBitSeq (Some(( 31 :: nat))) bs)))" + + + +(*val bitSeqFromNat : nat -> bitSequence*) +definition bitSeqFromNat :: " nat \<Rightarrow> bitSequence " where + " bitSeqFromNat i = ( bitSeqFromNatural (Some(( 31 :: nat))) ( i))" + + + +(*val natLor : nat -> nat -> nat*) +definition natLor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " natLor i1 i2 = ( defaultLor natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordOr_nat_dict :: "(nat)WordOr_class " where + " instance_Word_WordOr_nat_dict = ((| + + lor_method = natLor |) )" + + +(*val natLxor : nat -> nat -> nat*) +definition natLxor :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " natLxor i1 i2 = ( defaultLxor natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordXor_nat_dict :: "(nat)WordXor_class " where + " instance_Word_WordXor_nat_dict = ((| + + lxor_method = natLxor |) )" + + +(*val natLand : nat -> nat -> nat*) +definition natLand :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " natLand i1 i2 = ( defaultLand natFromBitSeq bitSeqFromNat i1 i2 )" + + +definition instance_Word_WordAnd_nat_dict :: "(nat)WordAnd_class " where + " instance_Word_WordAnd_nat_dict = ((| + + land_method = natLand |) )" + + +(*val natLsl : nat -> nat -> nat*) +definition natLsl :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " natLsl i n = ( defaultLsl natFromBitSeq bitSeqFromNat i n )" + + +definition instance_Word_WordLsl_nat_dict :: "(nat)WordLsl_class " where + " instance_Word_WordLsl_nat_dict = ((| + + lsl_method = natLsl |) )" + + +(*val natAsr : nat -> nat -> nat*) +definition natAsr :: " nat \<Rightarrow> nat \<Rightarrow> nat " where + " natAsr i n = ( defaultAsr natFromBitSeq bitSeqFromNat i n )" + + +definition instance_Word_WordAsr_nat_dict :: "(nat)WordAsr_class " where + " instance_Word_WordAsr_nat_dict = ((| + + asr_method = natAsr |) )" + + +end diff --git a/snapshots/isabelle/lib/lem/ROOT b/snapshots/isabelle/lib/lem/ROOT new file mode 100644 index 00000000..443687f9 --- /dev/null +++ b/snapshots/isabelle/lib/lem/ROOT @@ -0,0 +1,7 @@ +session LEM = "HOL-Word" + + description {* + HOL + LEM specific theories + *} + theories Lem_pervasives Lem_pervasives_extra + + diff --git a/snapshots/isabelle/lib/sail/Hoare.thy b/snapshots/isabelle/lib/sail/Hoare.thy new file mode 100644 index 00000000..ee7a5fa6 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Hoare.thy @@ -0,0 +1,320 @@ +theory Hoare + imports + State_lemmas + "HOL-Eisbach.Eisbach_Tools" +begin + +(*adhoc_overloading + Monad_Syntax.bind State_monad.bindS*) + +section \<open>Hoare logic for the state, exception and nondeterminism monad\<close> + +subsection \<open>Hoare triples\<close> + +type_synonym 'regs predS = "'regs sequential_state \<Rightarrow> bool" + +definition PrePost :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> (('a, 'e) result \<Rightarrow> 'regs predS) \<Rightarrow> bool" + where "PrePost P f Q \<equiv> (\<forall>s. P s \<longrightarrow> (\<forall>(r, s') \<in> f s. Q r s'))" + +lemma PrePostI: + assumes "\<And>s r s'. P s \<Longrightarrow> (r, s') \<in> f s \<Longrightarrow> Q r s'" + shows "PrePost P f Q" + using assms unfolding PrePost_def by auto + +lemma PrePost_elim: + assumes "PrePost P f Q" and "P s" and "(r, s') \<in> f s" + obtains "Q r s'" + using assms by (fastforce simp: PrePost_def) + +lemma PrePost_consequence: + assumes "PrePost A f B" + and "\<And>s. P s \<Longrightarrow> A s" and "\<And>v s. B v s \<Longrightarrow> Q v s" + shows "PrePost P f Q" + using assms unfolding PrePost_def by (blast intro: list.pred_mono_strong) + +lemma PrePost_strengthen_pre: + assumes "PrePost A f C" and "\<And>s. B s \<Longrightarrow> A s" + shows "PrePost B f C" + using assms by (rule PrePost_consequence) + +lemma PrePost_weaken_post: + assumes "PrePost A f B" and "\<And>v s. B v s \<Longrightarrow> C v s" + shows "PrePost A f C" + using assms by (blast intro: PrePost_consequence) + +named_theorems PrePost_intro + +lemma PrePost_True_post[PrePost_intro, intro, simp]: + "PrePost P m (\<lambda>_ _. True)" + unfolding PrePost_def by auto + +lemma PrePost_any: "PrePost (\<lambda>s. \<forall>(r, s') \<in> m s. Q r s') m Q" + unfolding PrePost_def by auto + +lemma PrePost_returnS[intro, PrePost_intro]: "PrePost (P (Value x)) (returnS x) P" + unfolding PrePost_def returnS_def by auto + +lemma PrePost_bindS[intro, PrePost_intro]: + assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePost (R a) (f a) Q" + and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R a | Ex e \<Rightarrow> Q (Ex e))" + shows "PrePost P (bindS m f) Q" +proof (intro PrePostI) + fix s r s' + assume P: "P s" and bind: "(r, s') \<in> bindS m f s" + from bind show "Q r s'" + proof (cases r s' m f s rule: bindS_cases) + case (Value a a' s'') + then have "R a' s''" using P m by (auto elim: PrePost_elim) + then show ?thesis using Value f by (auto elim: PrePost_elim) + next + case (Ex_Left e) + then show ?thesis using P m by (auto elim: PrePost_elim) + next + case (Ex_Right e a s'') + then have "R a s''" using P m by (auto elim: PrePost_elim) + then show ?thesis using Ex_Right f by (auto elim: PrePost_elim) + qed +qed + +lemma PrePost_bindS_ignore: + assumes f: "PrePost R f Q" + and m : "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R | Ex e \<Rightarrow> Q (Ex e))" + shows "PrePost P (bindS m (\<lambda>_. f)) Q" + using assms by auto + +lemma PrePost_bindS_unit: + fixes m :: "('regs, unit, 'e) monadS" + assumes f: "PrePost R (f ()) Q" + and m: "PrePost P m (\<lambda>r. case r of Value a \<Rightarrow> R | Ex e \<Rightarrow> Q (Ex e))" + shows "PrePost P (bindS m f) Q" + using assms by auto + +lemma PrePost_readS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value (f s)) s) (readS f) P" + unfolding PrePost_def readS_def returnS_def by auto + +lemma PrePost_updateS[intro, PrePost_intro]: "PrePost (\<lambda>s. P (Value ()) (f s)) (updateS f) P" + unfolding PrePost_def updateS_def returnS_def by auto + +lemma PrePost_if: + assumes "b \<Longrightarrow> PrePost P f Q" and "\<not>b \<Longrightarrow> PrePost P g Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_branch[PrePost_intro]: + assumes "b \<Longrightarrow> PrePost Pf f Q" and "\<not>b \<Longrightarrow> PrePost Pg g Q" + shows "PrePost (if b then Pf else Pg) (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_then: + assumes "b" and "PrePost P f Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_if_else: + assumes "\<not>b" and "PrePost P g Q" + shows "PrePost P (if b then f else g) Q" + using assms by auto + +lemma PrePost_prod_cases[PrePost_intro]: + assumes "PrePost P (f (fst x) (snd x)) Q" + shows "PrePost P (case x of (a, b) \<Rightarrow> f a b) Q" + using assms by (auto split: prod.splits) + +lemma PrePost_option_cases[PrePost_intro]: + assumes "\<And>a. PrePost (PS a) (s a) Q" and "PrePost PN n Q" + shows "PrePost (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q" + using assms by (auto split: option.splits) + +lemma PrePost_let[intro, PrePost_intro]: + assumes "PrePost P (m y) Q" + shows "PrePost P (let x = y in m x) Q" + using assms by auto + +lemma PrePost_assert_expS[intro, PrePost_intro]: "PrePost (if c then P (Value ()) else P (Ex (Failure m))) (assert_expS c m) P" + unfolding PrePost_def assert_expS_def by (auto simp: returnS_def failS_def) + +lemma PrePost_chooseS[intro, PrePost_intro]: "PrePost (\<lambda>s. \<forall>x \<in> xs. Q (Value x) s) (chooseS xs) Q" + by (auto simp: PrePost_def chooseS_def) + +lemma PrePost_failS[intro, PrePost_intro]: "PrePost (Q (Ex (Failure msg))) (failS msg) Q" + by (auto simp: PrePost_def failS_def) + +lemma case_result_combine[simp]: + "(case r of Value a \<Rightarrow> Q (Value a) | Ex e \<Rightarrow> Q (Ex e)) = Q r" + by (auto split: result.splits) + +lemma PrePost_foreachS_Nil[intro, simp, PrePost_intro]: + "PrePost (Q (Value vars)) (foreachS [] vars body) Q" + by auto + +lemma PrePost_foreachS_Cons: + assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePost (Q (Value vars')) (foreachS xs vars' body) Q" + and "PrePost (Q (Value vars)) (body x vars) Q" + shows "PrePost (Q (Value vars)) (foreachS (x # xs) vars body) Q" + using assms by fastforce + +lemma PrePost_foreachS_invariant: + assumes "\<And>x vars. x \<in> set xs \<Longrightarrow> PrePost (Q (Value vars)) (body x vars) Q" + shows "PrePost (Q (Value vars)) (foreachS xs vars body) Q" +proof (use assms in \<open>induction xs arbitrary: vars\<close>) + case (Cons x xs) + have "PrePost (Q (Value vars)) (bindS (body x vars) (\<lambda>vars. foreachS xs vars body)) Q" + proof (rule PrePost_bindS) + fix vars' + show "PrePost (Q (Value vars')) (foreachS xs vars' body) Q" + using Cons by auto + show "PrePost (Q (Value vars)) (body x vars) (\<lambda>r. case r of Value a \<Rightarrow> Q (Value a) | result.Ex e \<Rightarrow> Q (result.Ex e))" + unfolding case_result_combine + using Cons by auto + qed + then show ?case by auto +qed auto + +subsection \<open>Hoare quadruples\<close> + +text \<open>It is often convenient to treat the exception case separately. For this purpose, we use +a Hoare logic similar to the one used in [1]. It features not only Hoare triples, but also quadruples +with two postconditions: one for the case where the computation succeeds, and one for the case where +there is an exception. + +[1] D. Cock, G. Klein, and T. Sewell, ‘Secure Microkernels, State Monads and Scalable Refinement’, +in Theorem Proving in Higher Order Logics, 2008, pp. 167–182.\<close> + +definition PrePostE :: "'regs predS \<Rightarrow> ('regs, 'a, 'e) monadS \<Rightarrow> ('a \<Rightarrow> 'regs predS) \<Rightarrow> ('e ex \<Rightarrow> 'regs predS) \<Rightarrow> bool" + where "PrePostE P f Q E \<equiv> PrePost P f (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)" + +lemmas PrePost_defs = PrePost_def PrePostE_def + +lemma PrePostE_I[case_names Val Err]: + assumes "\<And>s a s'. P s \<Longrightarrow> (Value a, s') \<in> f s \<Longrightarrow> Q a s'" + and "\<And>s e s'. P s \<Longrightarrow> (Ex e, s') \<in> f s \<Longrightarrow> E e s'" + shows "PrePostE P f Q E" + using assms unfolding PrePostE_def by (intro PrePostI) (auto split: result.splits) + +lemma PrePostE_PrePost: + assumes "PrePost P m (\<lambda>v. case v of Value a \<Rightarrow> Q a | Ex e \<Rightarrow> E e)" + shows "PrePostE P m Q E" + using assms unfolding PrePostE_def by auto + +lemma PrePostE_elim: + assumes "PrePostE P f Q E" and "P s" and "(r, s') \<in> f s" + obtains + (Val) v where "r = Value v" "Q v s'" + | (Ex) e where "r = Ex e" "E e s'" + using assms by (cases r; fastforce simp: PrePost_defs) + +lemma PrePostE_consequence: + assumes "PrePostE A f B C" + and "\<And>s. P s \<Longrightarrow> A s" and "\<And>v s. B v s \<Longrightarrow> Q v s" and "\<And>e s. C e s \<Longrightarrow> E e s" + shows "PrePostE P f Q E" + using assms unfolding PrePostE_def by (auto elim: PrePost_consequence split: result.splits) + +lemma PrePostE_strengthen_pre: + assumes "PrePostE R f Q E" and "\<And>s. P s \<Longrightarrow> R s" + shows "PrePostE P f Q E" + using assms PrePostE_consequence by blast + +lemma PrePostE_weaken_post: + assumes "PrePostE A f B E" and "\<And>v s. B v s \<Longrightarrow> C v s" + shows "PrePostE A f C E" + using assms by (blast intro: PrePostE_consequence) + +named_theorems PrePostE_intro + +lemma PrePostE_True_post[PrePost_intro, intro, simp]: + "PrePostE P m (\<lambda>_ _. True) (\<lambda>_ _. True)" + unfolding PrePost_defs by (auto split: result.splits) + +lemma PrePostE_any: "PrePostE (\<lambda>s. \<forall>(r, s') \<in> m s. case r of Value a \<Rightarrow> Q a s' | Ex e \<Rightarrow> E e s') m Q E" + by (intro PrePostE_I) auto + +lemma PrePostE_returnS[PrePostE_intro, intro, simp]: + "PrePostE (P x) (returnS x) P Q" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_bindS[intro, PrePostE_intro]: + assumes f: "\<And>s a s'. (Value a, s') \<in> m s \<Longrightarrow> PrePostE (R a) (f a) Q E" + and m: "PrePostE P m R E" + shows "PrePostE P (bindS m f) Q E" + using assms + by (fastforce simp: PrePostE_def cong: result.case_cong) + +lemma PrePostE_bindS_ignore: + assumes f: "PrePostE R f Q E" + and m : "PrePostE P m (\<lambda>_. R) E" + shows "PrePostE P (bindS m (\<lambda>_. f)) Q E" + using assms by auto + +lemma PrePostE_bindS_unit: + fixes m :: "('regs, unit, 'e) monadS" + assumes f: "PrePostE R (f ()) Q E" + and m: "PrePostE P m (\<lambda>_. R) E" + shows "PrePostE P (bindS m f) Q E" + using assms by auto + +lemma PrePostE_readS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q (f s) s) (readS f) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_updateS[PrePostE_intro, intro]: "PrePostE (\<lambda>s. Q () (f s)) (updateS f) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_if_branch[PrePostE_intro]: + assumes "b \<Longrightarrow> PrePostE Pf f Q E" and "\<not>b \<Longrightarrow> PrePostE Pg g Q E" + shows "PrePostE (if b then Pf else Pg) (if b then f else g) Q E" + using assms by (auto) + +lemma PrePostE_if: + assumes "b \<Longrightarrow> PrePostE P f Q E" and "\<not>b \<Longrightarrow> PrePostE P g Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_if_then: + assumes "b" and "PrePostE P f Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_if_else: + assumes "\<not> b" and "PrePostE P g Q E" + shows "PrePostE P (if b then f else g) Q E" + using assms by auto + +lemma PrePostE_prod_cases[PrePostE_intro]: + assumes "PrePostE P (f (fst x) (snd x)) Q E" + shows "PrePostE P (case x of (a, b) \<Rightarrow> f a b) Q E" + using assms by (auto split: prod.splits) + +lemma PrePostE_option_cases[PrePostE_intro]: + assumes "\<And>a. PrePostE (PS a) (s a) Q E" and "PrePostE PN n Q E" + shows "PrePostE (case x of Some a \<Rightarrow> PS a | None \<Rightarrow> PN) (case x of Some a \<Rightarrow> s a | None \<Rightarrow> n) Q E" + using assms by (auto split: option.splits) + +lemma PrePostE_let[PrePostE_intro]: + assumes "PrePostE P (m y) Q E" + shows "PrePostE P (let x = y in m x) Q E" + using assms by auto + +lemma PrePostE_assert_expS[PrePostE_intro, intro]: + "PrePostE (if c then P () else Q (Failure m)) (assert_expS c m) P Q" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_failS[PrePost_intro, intro]: + "PrePostE (E (Failure msg)) (failS msg) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_chooseS[intro, PrePostE_intro]: + "PrePostE (\<lambda>s. \<forall>x \<in> xs. Q x s) (chooseS xs) Q E" + unfolding PrePostE_def by (auto intro: PrePost_strengthen_pre) + +lemma PrePostE_foreachS_Cons: + assumes "\<And>s vars' s'. (Value vars', s') \<in> body x vars s \<Longrightarrow> PrePostE (Q vars') (foreachS xs vars' body) Q E" + and "PrePostE (Q vars) (body x vars) Q E" + shows "PrePostE (Q vars) (foreachS (x # xs) vars body) Q E" + using assms by fastforce + +lemma PrePostE_foreachS_invariant: + assumes "\<And>x vars. x \<in> set xs \<Longrightarrow> PrePostE (Q vars) (body x vars) Q E" + shows "PrePostE (Q vars) (foreachS xs vars body) Q E" + using assms unfolding PrePostE_def + by (intro PrePost_foreachS_invariant[THEN PrePost_strengthen_pre]) auto + +end diff --git a/snapshots/isabelle/lib/sail/Prompt.thy b/snapshots/isabelle/lib/sail/Prompt.thy new file mode 100644 index 00000000..5792e575 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt.thy @@ -0,0 +1,150 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/prompt.lem.\<close> + +theory "Prompt" + +imports + Main + "Lem_pervasives_extra" + "Sail_values" + "Prompt_monad" + "Prompt_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_values*) +(*open import Prompt_monad*) +(*open import {isabelle} `Prompt_monad_lemmas`*) + +(*val >>= : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*) + +(*val >> : forall 'rv 'b 'e. monad 'rv unit 'e -> monad 'rv 'b 'e -> monad 'rv 'b 'e*) + +(*val iter_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +fun iter_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where + " iter_aux i f (x # xs) = ( f i x \<then> iter_aux (i +( 1 :: int)) f xs )" +|" iter_aux i f ([]) = ( return () )" + + +(*val iteri : forall 'rv 'a 'e. (integer -> 'a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +definition iteri :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where + " iteri f xs = ( iter_aux(( 0 :: int)) f xs )" + + +(*val iter : forall 'rv 'a 'e. ('a -> monad 'rv unit 'e) -> list 'a -> monad 'rv unit 'e*) +definition iter :: "('a \<Rightarrow>('rv,(unit),'e)monad)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monad " where + " iter f xs = ( iteri ( \<lambda>x . + (case x of _ => \<lambda> x . f x )) xs )" + + +(*val foreachM : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +fun foreachM :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where + " foreachM ([]) vars body = ( return vars )" +|" foreachM (x # xs) vars body = ( + body x vars \<bind> (\<lambda> vars . + foreachM xs vars body))" + + +(*val and_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) +definition and_boolM :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad " where + " and_boolM l r = ( l \<bind> (\<lambda> l . if l then r else return False))" + + +(*val or_boolM : forall 'rv 'e. monad 'rv bool 'e -> monad 'rv bool 'e -> monad 'rv bool 'e*) +definition or_boolM :: "('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad \<Rightarrow>('rv,(bool),'e)monad " where + " or_boolM l r = ( l \<bind> (\<lambda> l . if l then return True else r))" + + +(*val bool_of_bitU_fail : forall 'rv 'e. bitU -> monad 'rv bool 'e*) +definition bool_of_bitU_fail :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where + " bool_of_bitU_fail = ( \<lambda>x . + (case x of + B0 => return False + | B1 => return True + | BU => Fail (''bool_of_bitU'') + ) )" + + +(*val bool_of_bitU_oracle : forall 'rv 'e. bitU -> monad 'rv bool 'e*) +definition bool_of_bitU_oracle :: " bitU \<Rightarrow>('rv,(bool),'e)monad " where + " bool_of_bitU_oracle = ( \<lambda>x . + (case x of + B0 => return False + | B1 => return True + | BU => undefined_bool () + ) )" + + +(*val bools_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bool) 'e*) +definition bools_of_bits_oracle :: "(bitU)list \<Rightarrow>('rv,((bool)list),'e)monad " where + " bools_of_bits_oracle bits = ( + foreachM bits [] + (\<lambda> b bools . + bool_of_bitU_oracle b \<bind> (\<lambda> b . + return (bools @ [b]))))" + + +(*val of_bits_oracle : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) +definition of_bits_oracle :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where + " of_bits_oracle dict_Sail_values_Bitvector_a bits = ( + bools_of_bits_oracle bits \<bind> (\<lambda> bs . + return ((of_bools_method dict_Sail_values_Bitvector_a) bs)))" + + +(*val of_bits_fail : forall 'rv 'a 'e. Bitvector 'a => list bitU -> monad 'rv 'a 'e*) +definition of_bits_fail :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow>('rv,'a,'e)monad " where + " of_bits_fail dict_Sail_values_Bitvector_a bits = ( maybe_fail (''of_bits'') ( + (of_bits_method dict_Sail_values_Bitvector_a) bits))" + + +(*val mword_oracle : forall 'rv 'a 'e. Size 'a => unit -> monad 'rv (mword 'a) 'e*) +definition mword_oracle :: " unit \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mword_oracle _ = ( + bools_of_bits_oracle (repeat [BU] (int (len_of (TYPE(_) :: 'a itself)))) \<bind> (\<lambda> bs . + return (Word.of_bl bs)))" + + +(*val whileM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> + ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +function (sequential,domintros) whileM :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where + " whileM vars cond body = ( + cond vars \<bind> (\<lambda> cond_val . + if cond_val then + body vars \<bind> (\<lambda> vars . whileM vars cond body) + else return vars))" +by pat_completeness auto + + +(*val untilM : forall 'rv 'vars 'e. 'vars -> ('vars -> monad 'rv bool 'e) -> + ('vars -> monad 'rv 'vars 'e) -> monad 'rv 'vars 'e*) +function (sequential,domintros) untilM :: " 'vars \<Rightarrow>('vars \<Rightarrow>('rv,(bool),'e)monad)\<Rightarrow>('vars \<Rightarrow>('rv,'vars,'e)monad)\<Rightarrow>('rv,'vars,'e)monad " where + " untilM vars cond body = ( + body vars \<bind> (\<lambda> vars . + cond vars \<bind> (\<lambda> cond_val . + if cond_val then return vars else untilM vars cond body)))" +by pat_completeness auto + + +(*let write_two_regs r1 r2 vec = + let is_inc = + let is_inc_r1 = is_inc_of_reg r1 in + let is_inc_r2 = is_inc_of_reg r2 in + let () = ensure (is_inc_r1 = is_inc_r2) + write_two_regs called with vectors of different direction in + is_inc_r1 in + + let (size_r1 : integer) = size_of_reg r1 in + let (start_vec : integer) = get_start vec in + let size_vec = length vec in + let r1_v = + if is_inc + then slice vec start_vec (size_r1 - start_vec - 1) + else slice vec start_vec (start_vec - size_r1 - 1) in + let r2_v = + if is_inc + then slice vec (size_r1 - start_vec) (size_vec - start_vec) + else slice vec (start_vec - size_r1) (start_vec - size_vec) in + write_reg r1 r1_v >> write_reg r2 r2_v*) +end diff --git a/snapshots/isabelle/lib/sail/Prompt_monad.thy b/snapshots/isabelle/lib/sail/Prompt_monad.thy new file mode 100644 index 00000000..e4aecfba --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt_monad.thy @@ -0,0 +1,267 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/prompt_monad.lem.\<close> + +theory "Prompt_monad" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) + +type_synonym register_name =" string " +type_synonym address =" bitU list " + +datatype( 'regval, 'a, 'e) monad = + Done " 'a " + (* Read a number of bytes from memory, returned in little endian order *) + | Read_mem " read_kind " " address " " nat " " ( memory_byte list \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Read the tag of a memory address *) + | Read_tag " address " " (bitU \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Tell the system a write is imminent, at address lifted, of size nat *) + | Write_ea " write_kind " " address " " nat " " ('regval, 'a, 'e) monad " + (* Request the result of store-exclusive *) + | Excl_res " (bool \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Request to write memory at last signalled address. Memory value should be 8 + times the size given in ea signal, given in little endian order *) + | Write_memv " memory_byte list " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Request to write the tag at given address. *) + | Write_tag " address " " bitU " " (bool \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Tell the system to dynamically recalculate dependency footprint *) + | Footprint " ('regval, 'a, 'e) monad " + (* Request a memory barrier *) + | Barrier " barrier_kind " " ('regval, 'a, 'e) monad " + (* Request to read register, will track dependency when mode.track_values *) + | Read_reg " register_name " " ('regval \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Request to write register *) + | Write_reg " register_name " " 'regval " " ('regval, 'a, 'e) monad " + | Undefined " (bool \<Rightarrow> ('regval, 'a, 'e) monad)" + (* Print debugging or tracing information *) + | Print " string " " ('regval, 'a, 'e) monad " + (*Result of a failed assert with possible error message to report*) + | Fail " string " + (* Exception of type 'e *) + | Exception " 'e " + +(*val return : forall 'rv 'a 'e. 'a -> monad 'rv 'a 'e*) +definition return :: " 'a \<Rightarrow>('rv,'a,'e)monad " where + " return a = ( Done a )" + + +(*val bind : forall 'rv 'a 'b 'e. monad 'rv 'a 'e -> ('a -> monad 'rv 'b 'e) -> monad 'rv 'b 'e*) +function (sequential,domintros) bind :: "('rv,'a,'e)monad \<Rightarrow>('a \<Rightarrow>('rv,'b,'e)monad)\<Rightarrow>('rv,'b,'e)monad " where + " bind (Done a) f = ( f a )" +|" bind (Read_mem rk a sz k) f = ( Read_mem rk a sz (\<lambda> v . bind (k v) f))" +|" bind (Read_tag a k) f = ( Read_tag a (\<lambda> v . bind (k v) f))" +|" bind (Write_memv descr k) f = ( Write_memv descr (\<lambda> v . bind (k v) f))" +|" bind (Write_tag a t k) f = ( Write_tag a t (\<lambda> v . bind (k v) f))" +|" bind (Read_reg descr k) f = ( Read_reg descr (\<lambda> v . bind (k v) f))" +|" bind (Excl_res k) f = ( Excl_res (\<lambda> v . bind (k v) f))" +|" bind (Undefined k) f = ( Undefined (\<lambda> v . bind (k v) f))" +|" bind (Write_ea wk a sz k) f = ( Write_ea wk a sz (bind k f))" +|" bind (Footprint k) f = ( Footprint (bind k f))" +|" bind (Barrier bk k) f = ( Barrier bk (bind k f))" +|" bind (Write_reg r v k) f = ( Write_reg r v (bind k f))" +|" bind (Print msg k) f = ( Print msg (bind k f))" +|" bind (Fail descr) f = ( Fail descr )" +|" bind (Exception e) f = ( Exception e )" +by pat_completeness auto + + +(*val exit : forall 'rv 'a 'e. unit -> monad 'rv 'a 'e*) +definition exit0 :: " unit \<Rightarrow>('rv,'a,'e)monad " where + " exit0 _ = ( Fail (''exit''))" + + +(*val undefined_bool : forall 'rv 'e. unit -> monad 'rv bool 'e*) +definition undefined_bool :: " unit \<Rightarrow>('rv,(bool),'e)monad " where + " undefined_bool _ = ( Undefined return )" + + +(*val assert_exp : forall 'rv 'e. bool -> string -> monad 'rv unit 'e*) +definition assert_exp :: " bool \<Rightarrow> string \<Rightarrow>('rv,(unit),'e)monad " where + " assert_exp exp msg = ( if exp then Done () else Fail msg )" + + +(*val throw : forall 'rv 'a 'e. 'e -> monad 'rv 'a 'e*) +definition throw :: " 'e \<Rightarrow>('rv,'a,'e)monad " where + " throw e = ( Exception e )" + + +(*val try_catch : forall 'rv 'a 'e1 'e2. monad 'rv 'a 'e1 -> ('e1 -> monad 'rv 'a 'e2) -> monad 'rv 'a 'e2*) +function (sequential,domintros) try_catch :: "('rv,'a,'e1)monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,'e2)monad)\<Rightarrow>('rv,'a,'e2)monad " where + " try_catch (Done a) h = ( Done a )" +|" try_catch (Read_mem rk a sz k) h = ( Read_mem rk a sz (\<lambda> v . try_catch (k v) h))" +|" try_catch (Read_tag a k) h = ( Read_tag a (\<lambda> v . try_catch (k v) h))" +|" try_catch (Write_memv descr k) h = ( Write_memv descr (\<lambda> v . try_catch (k v) h))" +|" try_catch (Write_tag a t k) h = ( Write_tag a t (\<lambda> v . try_catch (k v) h))" +|" try_catch (Read_reg descr k) h = ( Read_reg descr (\<lambda> v . try_catch (k v) h))" +|" try_catch (Excl_res k) h = ( Excl_res (\<lambda> v . try_catch (k v) h))" +|" try_catch (Undefined k) h = ( Undefined (\<lambda> v . try_catch (k v) h))" +|" try_catch (Write_ea wk a sz k) h = ( Write_ea wk a sz (try_catch k h))" +|" try_catch (Footprint k) h = ( Footprint (try_catch k h))" +|" try_catch (Barrier bk k) h = ( Barrier bk (try_catch k h))" +|" try_catch (Write_reg r v k) h = ( Write_reg r v (try_catch k h))" +|" try_catch (Print msg k) h = ( Print msg (try_catch k h))" +|" try_catch (Fail descr) h = ( Fail descr )" +|" try_catch (Exception e) h = ( h e )" +by pat_completeness auto + + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is either 'r 'e, where Right e + represents a proper exception and Left r an early return of value r. *) +type_synonym( 'rv, 'a, 'r, 'e) monadR =" ('rv, 'a, ( ('r, 'e)sum)) monad " + +(*val early_return : forall 'rv 'a 'r 'e. 'r -> monadR 'rv 'a 'r 'e*) +definition early_return :: " 'r \<Rightarrow>('rv,'a,(('r,'e)sum))monad " where + " early_return r = ( throw (Inl r))" + + +(*val catch_early_return : forall 'rv 'a 'e. monadR 'rv 'a 'a 'e -> monad 'rv 'a 'e*) +definition catch_early_return :: "('rv,'a,(('a,'e)sum))monad \<Rightarrow>('rv,'a,'e)monad " where + " catch_early_return m = ( + try_catch m + (\<lambda>x . (case x of Inl a => return a | Inr e => throw e )))" + + +(* Lift to monad with early return by wrapping exceptions *) +(*val liftR : forall 'rv 'a 'r 'e. monad 'rv 'a 'e -> monadR 'rv 'a 'r 'e*) +definition liftR :: "('rv,'a,'e)monad \<Rightarrow>('rv,'a,(('r,'e)sum))monad " where + " liftR m = ( try_catch m (\<lambda> e . throw (Inr e)))" + + +(* Catch exceptions in the presence of early returns *) +(*val try_catchR : forall 'rv 'a 'r 'e1 'e2. monadR 'rv 'a 'r 'e1 -> ('e1 -> monadR 'rv 'a 'r 'e2) -> monadR 'rv 'a 'r 'e2*) +definition try_catchR :: "('rv,'a,(('r,'e1)sum))monad \<Rightarrow>('e1 \<Rightarrow>('rv,'a,(('r,'e2)sum))monad)\<Rightarrow>('rv,'a,(('r,'e2)sum))monad " where + " try_catchR m h = ( + try_catch m + (\<lambda>x . (case x of Inl r => throw (Inl r) | Inr e => h e )))" + + +(*val maybe_fail : forall 'rv 'a 'e. string -> maybe 'a -> monad 'rv 'a 'e*) +definition maybe_fail :: " string \<Rightarrow> 'a option \<Rightarrow>('rv,'a,'e)monad " where + " maybe_fail msg = ( \<lambda>x . + (case x of Some a => return a | None => Fail msg ) )" + + +(*val read_mem_bytes : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv (list memory_byte) 'e*) +definition read_mem_bytes :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,((memory_byte)list),'e)monad " where + " read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( + Read_mem rk ((bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) return )" + + +(*val read_mem : forall 'rv 'a 'b 'e. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monad 'rv 'b 'e*) +definition read_mem :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,'b,'e)monad " where + " read_mem dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk addr sz = ( + bind + (read_mem_bytes dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_a rk addr sz) + (\<lambda> bytes . + maybe_fail (''bits_of_mem_bytes'') ( + (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + + +(*val read_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bitU 'e*) +definition read_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bitU),'e)monad " where + " read_tag dict_Sail_values_Bitvector_a addr = ( Read_tag ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) return )" + + +(*val excl_result : forall 'rv 'e. unit -> monad 'rv bool 'e*) +definition excl_result :: " unit \<Rightarrow>('rv,(bool),'e)monad " where + " excl_result _ = ( + (let k = (\<lambda> successful . (return successful)) in Excl_res k) )" + + +(*val write_mem_ea : forall 'rv 'a 'e. Bitvector 'a => write_kind -> 'a -> integer -> monad 'rv unit 'e*) +definition write_mem_ea :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " write_mem_ea dict_Sail_values_Bitvector_a wk addr sz = ( Write_ea wk ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) (nat_of_int sz) (Done () ))" + + +(*val write_mem_val : forall 'rv 'a 'e. Bitvector 'a => 'a -> monad 'rv bool 'e*) +definition write_mem_val :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('rv,(bool),'e)monad " where + " write_mem_val dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail_values_Bitvector_a v of + Some v => Write_memv v return + | None => Fail (''write_mem_val'') +))" + + +(*val write_tag : forall 'rv 'a 'e. Bitvector 'a => 'a -> bitU -> monad 'rv bool 'e*) +definition write_tag :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('rv,(bool),'e)monad " where + " write_tag dict_Sail_values_Bitvector_a addr b = ( Write_tag ( + (bits_of_method dict_Sail_values_Bitvector_a) addr) b return )" + + +(*val read_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> monad 'rv 'a 'e*) +definition read_reg :: "('s,'rv,'a)register_ref \<Rightarrow>('rv,'a,'e)monad " where + " read_reg reg = ( + (let k = (\<lambda> v . + (case (of_regval reg) v of + Some v => Done v + | None => Fail (''read_reg: unrecognised value'') + )) in Read_reg (name reg) k) )" + + +(* TODO +val read_reg_range : forall 's 'r 'rv 'a 'e. Bitvector 'a => register_ref 's 'rv 'r -> integer -> integer -> monad 'rv 'a 'e +let read_reg_range reg i j = + read_reg_aux of_bits (external_reg_slice reg (nat_of_int i,nat_of_int j)) + +let read_reg_bit reg i = + read_reg_aux (fun v -> v) (external_reg_slice reg (nat_of_int i,nat_of_int i)) >>= fun v -> + return (extract_only_element v) + +let read_reg_field reg regfield = + read_reg_aux (external_reg_field_whole reg regfield) + +let read_reg_bitfield reg regfield = + read_reg_aux (external_reg_field_whole reg regfield) >>= fun v -> + return (extract_only_element v)*) + +definition reg_deref :: "('d,'c,'b)register_ref \<Rightarrow>('c,'b,'a)monad " where + " reg_deref = ( read_reg )" + + +(*val write_reg : forall 's 'rv 'a 'e. register_ref 's 'rv 'a -> 'a -> monad 'rv unit 'e*) +definition write_reg :: "('s,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monad " where + " write_reg reg v = ( Write_reg(name reg) ((regval_of reg) v) (Done () ))" + + +(* TODO +let write_reg reg v = + write_reg_aux (external_reg_whole reg) v +let write_reg_range reg i j v = + write_reg_aux (external_reg_slice reg (nat_of_int i,nat_of_int j)) v +let write_reg_pos reg i v = + let iN = nat_of_int i in + write_reg_aux (external_reg_slice reg (iN,iN)) [v] +let write_reg_bit = write_reg_pos +let write_reg_field reg regfield v = + write_reg_aux (external_reg_field_whole reg regfield.field_name) v +let write_reg_field_bit reg regfield bit = + write_reg_aux (external_reg_field_whole reg regfield.field_name) + (Vector [bit] 0 (is_inc_of_reg reg)) +let write_reg_field_range reg regfield i j v = + write_reg_aux (external_reg_field_slice reg regfield.field_name (nat_of_int i,nat_of_int j)) v +let write_reg_field_pos reg regfield i v = + write_reg_field_range reg regfield i i [v] +let write_reg_field_bit = write_reg_field_pos*) + +(*val barrier : forall 'rv 'e. barrier_kind -> monad 'rv unit 'e*) +definition barrier :: " barrier_kind \<Rightarrow>('rv,(unit),'e)monad " where + " barrier bk = ( Barrier bk (Done () ))" + + +(*val footprint : forall 'rv 'e. unit -> monad 'rv unit 'e*) +definition footprint :: " unit \<Rightarrow>('rv,(unit),'e)monad " where + " footprint _ = ( Footprint (Done () ))" + +end diff --git a/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy b/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy new file mode 100644 index 00000000..e883c2a0 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Prompt_monad_lemmas.thy @@ -0,0 +1,170 @@ +theory Prompt_monad_lemmas + imports + Prompt_monad + Sail_values_lemmas +begin + +notation bind (infixr "\<bind>" 54) + +abbreviation seq :: "('rv,unit,'e)monad \<Rightarrow> ('rv,'b,'e)monad \<Rightarrow>('rv,'b,'e)monad" (infixr "\<then>" 54) where + "m \<then> n \<equiv> m \<bind> (\<lambda>_. n)" + +lemma All_bind_dom: "bind_dom (m, f)" + by (induction m) (auto intro: bind.domintros) + +termination bind using All_bind_dom by auto +lemmas bind_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = bind.induct + +lemma bind_return[simp]: "bind (return a) f = f a" + by (auto simp: return_def) + +lemma bind_assoc[simp]: "bind (bind m f) g = bind m (\<lambda>x. bind (f x) g)" + by (induction m f arbitrary: g rule: bind.induct) auto + +lemma bind_assert_True[simp]: "bind (assert_exp True msg) f = f ()" + by (auto simp: assert_exp_def) + +lemma All_try_catch_dom: "try_catch_dom (m, h)" + by (induction m) (auto intro: try_catch.domintros) +termination try_catch using All_try_catch_dom by auto +lemmas try_catch_induct[case_names Done Read_mem Write_memv Read_reg Excl_res Write_ea Barrier Write_reg Fail Exception] = try_catch.induct + +datatype 'regval event = + (* Request to read memory *) + e_read_mem read_kind "bitU list" nat "memory_byte list" + | e_read_tag "bitU list" bitU + (* Write is imminent, at address lifted, of size nat *) + | e_write_ea write_kind "bitU list" nat + (* Request the result of store-exclusive *) + | e_excl_res bool + (* Request to write memory at last signalled address. Memory value should be 8 + times the size given in ea signal *) + | e_write_memv "memory_byte list" bool + | e_write_tag "bitU list" bitU bool + (* Tell the system to dynamically recalculate dependency footprint *) + | e_footprint + (* Request a memory barrier *) + | e_barrier " barrier_kind " + (* Request to read register *) + | e_read_reg string 'regval + (* Request to write register *) + | e_write_reg string 'regval + | e_undefined bool + | e_print string + +inductive_set T :: "(('rv, 'a, 'e) monad \<times> 'rv event \<times> ('rv, 'a, 'e) monad) set" where + Read_mem: "((Read_mem rk addr sz k), e_read_mem rk addr sz v, k v) \<in> T" +| Read_tag: "((Read_tag addr k), e_read_tag addr v, k v) \<in> T" +| Write_ea: "((Write_ea wk addr sz k), e_write_ea wk addr sz, k) \<in> T" +| Excl_res: "((Excl_res k), e_excl_res r, k r) \<in> T" +| Write_memv: "((Write_memv v k), e_write_memv v r, k r) \<in> T" +| Write_tag: "((Write_tag a v k), e_write_tag a v r, k r) \<in> T" +| Footprint: "((Footprint k), e_footprint, k) \<in> T" +| Barrier: "((Barrier bk k), e_barrier bk, k) \<in> T" +| Read_reg: "((Read_reg r k), e_read_reg r v, k v) \<in> T" +| Write_reg: "((Write_reg r v k), e_write_reg r v, k) \<in> T" +| Undefined : "((Undefined k), e_undefined v, k v) \<in> T" +| Print: "((Print msg k), e_print msg, k) \<in> T" + +inductive_set Traces :: "(('rv, 'a, 'e) monad \<times> 'rv event list \<times> ('rv, 'a, 'e) monad) set" where + Nil: "(s, [], s) \<in> Traces" +| Step: "\<lbrakk>(s, e, s'') \<in> T; (s'', t, s') \<in> Traces\<rbrakk> \<Longrightarrow> (s, e # t, s') \<in> Traces" + +declare Traces.intros[intro] +declare T.intros[intro] + +declare prod.splits[split] + +lemmas Traces_ConsI = T.intros[THEN Step, rotated] + +inductive_cases Traces_NilE[elim]: "(s, [], s') \<in> Traces" +inductive_cases Traces_ConsE[elim]: "(s, e # t, s') \<in> Traces" + +lemma Traces_cases: + fixes m :: "('rv, 'a, 'e) monad" + assumes Run: "(m, t, m') \<in> Traces" + obtains (Nil) a where "m = m'" and "t = []" + | (Read_mem) rk addr s k t' v where "m = Read_mem rk addr s k" and "t = e_read_mem rk addr s v # t'" and "(k v, t', m') \<in> Traces" + | (Read_tag) addr k t' v where "m = Read_tag addr k" and "t = e_read_tag addr v # t'" and "(k v, t', m') \<in> Traces" + | (Write_memv) val k t' v where "m = Write_memv val k" and "t = e_write_memv val v # t'" and "(k v, t', m') \<in> Traces" + | (Write_tag) a val k t' v where "m = Write_tag a val k" and "t = e_write_tag a val v # t'" and "(k v, t', m') \<in> Traces" + | (Barrier) bk k t' v where "m = Barrier bk k" and "t = e_barrier bk # t'" and "(k, t', m') \<in> Traces" + | (Read_reg) reg k t' v where "m = Read_reg reg k" and "t = e_read_reg reg v # t'" and "(k v, t', m') \<in> Traces" + | (Excl_res) k t' v where "m = Excl_res k" and "t = e_excl_res v # t'" and "(k v, t', m') \<in> Traces" + | (Write_ea) wk addr s k t' where "m = Write_ea wk addr s k" and "t = e_write_ea wk addr s # t'" and "(k, t', m') \<in> Traces" + | (Footprint) k t' where "m = Footprint k" and "t = e_footprint # t'" and "(k, t', m') \<in> Traces" + | (Write_reg) reg v k t' where "m = Write_reg reg v k" and "t = e_write_reg reg v # t'" and "(k, t', m') \<in> Traces" + | (Undefined) v k t' where "m = Undefined k" and "t = e_undefined v # t'" and "(k v, t', m') \<in> Traces" + | (Print) msg k t' where "m = Print msg k" and "t = e_print msg # t'" and "(k, t', m') \<in> Traces" +proof (use Run in \<open>cases m t m' set: Traces\<close>) + case Nil + then show ?thesis by (auto intro: that(1)) +next + case (Step e m'' t') + from \<open>(m, e, m'') \<in> T\<close> and \<open>t = e # t'\<close> and \<open>(m'', t', m') \<in> Traces\<close> + show ?thesis by (cases m e m'' rule: T.cases; elim that; blast) +qed + +abbreviation Run :: "('rv, 'a, 'e) monad \<Rightarrow> 'rv event list \<Rightarrow> 'a \<Rightarrow> bool" + where "Run s t a \<equiv> (s, t, Done a) \<in> Traces" + +lemma Run_appendI: + assumes "(s, t1, s') \<in> Traces" + and "Run s' t2 a" + shows "Run s (t1 @ t2) a" +proof (use assms in \<open>induction t1 arbitrary: s\<close>) + case (Cons e t1) + then show ?case by (elim Traces_ConsE) auto +qed auto + +lemma bind_DoneE: + assumes "bind m f = Done a" + obtains a' where "m = Done a'" and "f a' = Done a" + using assms by (auto elim: bind.elims) + +lemma bind_T_cases: + assumes "(bind m f, e, s') \<in> T" + obtains (Done) a where "m = Done a" + | (Bind) m' where "s' = bind m' f" and "(m, e, m') \<in> T" + using assms by (cases; blast elim: bind.elims) + +lemma Run_bindE: + fixes m :: "('rv, 'b, 'e) monad" and a :: 'a + assumes "Run (bind m f) t a" + obtains tm am tf where "t = tm @ tf" and "Run m tm am" and "Run (f am) tf a" +proof (use assms in \<open>induction "bind m f" t "Done a :: ('rv, 'a, 'e) monad" arbitrary: m rule: Traces.induct\<close>) + case Nil + obtain am where "m = Done am" and "f am = Done a" using Nil(1) by (elim bind_DoneE) + then show ?case by (intro Nil(2)) auto +next + case (Step e s'' t m) + show thesis using Step(1) + proof (cases rule: bind_T_cases) + case (Done am) + then show ?thesis using Step(1,2) by (intro Step(4)[of "[]" "e # t" am]) auto + next + case (Bind m') + show ?thesis proof (rule Step(3)[OF Bind(1)]) + fix tm tf am + assume "t = tm @ tf" and "Run m' tm am" and "Run (f am) tf a" + then show thesis using Bind by (intro Step(4)[of "e # tm" tf am]) auto + qed + qed +qed + +lemma Run_DoneE: + assumes "Run (Done a) t a'" + obtains "t = []" and "a' = a" + using assms by (auto elim: Traces.cases T.cases) + +lemma Run_Done_iff_Nil[simp]: "Run (Done a) t a' \<longleftrightarrow> t = [] \<and> a' = a" + by (auto elim: Run_DoneE) + +lemma bind_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\<And>t a. Run m2 t a \<Longrightarrow> f1 a = f2 a" + shows "bind m1 f1 = bind m2 f2" + unfolding m using f + by (induction m2 f1 arbitrary: f2 rule: bind.induct; unfold bind.simps; blast) + +end diff --git a/snapshots/isabelle/lib/sail/ROOT b/snapshots/isabelle/lib/sail/ROOT new file mode 100644 index 00000000..3189f216 --- /dev/null +++ b/snapshots/isabelle/lib/sail/ROOT @@ -0,0 +1,11 @@ +session "Sail" = "LEM" + + options [document = false] + sessions + "HOL-Eisbach" + theories + Sail_values_lemmas + Prompt + State_lemmas + Sail_operators_mwords_lemmas + Sail_operators_bitlists + Hoare diff --git a/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy b/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy new file mode 100644 index 00000000..088ff4a8 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_instr_kinds.thy @@ -0,0 +1,494 @@ +chapter \<open>Generated by Lem from ../../src/lem_interp/sail_instr_kinds.lem.\<close> + +theory "Sail_instr_kinds" + +imports + Main + "Lem_pervasives_extra" + +begin + +(*========================================================================*) +(* Sail *) +(* *) +(* Copyright (c) 2013-2017 *) +(* Kathyrn Gray *) +(* Shaked Flur *) +(* Stephen Kell *) +(* Gabriel Kerneis *) +(* Robert Norton-Wright *) +(* Christopher Pulte *) +(* Peter Sewell *) +(* Alasdair Armstrong *) +(* Brian Campbell *) +(* Thomas Bauereiss *) +(* Anthony Fox *) +(* Jon French *) +(* Dominic Mulligan *) +(* Stephen Kell *) +(* Mark Wassell *) +(* *) +(* All rights reserved. *) +(* *) +(* This software was developed by the University of Cambridge Computer *) +(* Laboratory as part of the Rigorous Engineering of Mainstream Systems *) +(* (REMS) project, funded by EPSRC grant EP/K008528/1. *) +(* *) +(* Redistribution and use in source and binary forms, with or without *) +(* modification, are permitted provided that the following conditions *) +(* are met: *) +(* 1. Redistributions of source code must retain the above copyright *) +(* notice, this list of conditions and the following disclaimer. *) +(* 2. Redistributions in binary form must reproduce the above copyright *) +(* notice, this list of conditions and the following disclaimer in *) +(* the documentation and/or other materials provided with the *) +(* distribution. *) +(* *) +(* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' *) +(* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *) +(* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *) +(* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR *) +(* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *) +(* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *) +(* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF *) +(* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND *) +(* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, *) +(* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT *) +(* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF *) +(* SUCH DAMAGE. *) +(*========================================================================*) + +(*open import Pervasives_extra*) + + +record 'a EnumerationType_class= + + toNat_method ::" 'a \<Rightarrow> nat " + + + + +(*val enumeration_typeCompare : forall 'a. EnumerationType 'a => 'a -> 'a -> ordering*) +definition enumeration_typeCompare :: " 'a EnumerationType_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> ordering " where + " enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a e1 e2 = ( + (genericCompare (op<) (op=) ( + (toNat_method dict_Sail_instr_kinds_EnumerationType_a) e1) ((toNat_method dict_Sail_instr_kinds_EnumerationType_a) e2)))" + + + +definition instance_Basic_classes_Ord_var_dict :: " 'a EnumerationType_class \<Rightarrow> 'a Ord_class " where + " instance_Basic_classes_Ord_var_dict dict_Sail_instr_kinds_EnumerationType_a = ((| + + compare_method = + (enumeration_typeCompare dict_Sail_instr_kinds_EnumerationType_a), + + isLess_method = (\<lambda> r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = LT), + + isLessEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> GT), + + isGreater_method = (\<lambda> r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) = GT), + + isGreaterEqual_method = (\<lambda> r1 r2. (enumeration_typeCompare + dict_Sail_instr_kinds_EnumerationType_a r1 r2) \<noteq> LT)|) )" + + + +(* Data structures for building up instructions *) + +(* careful: changes in the read/write/barrier kinds have to be + reflected in deep_shallow_convert *) +datatype read_kind = + (* common reads *) + Read_plain + (* Power reads *) + | Read_reserve + (* AArch64 reads *) + | Read_acquire | Read_exclusive | Read_exclusive_acquire | Read_stream + (* RISC-V reads *) + | Read_RISCV_acquire | Read_RISCV_strong_acquire + | Read_RISCV_reserved | Read_RISCV_reserved_acquire + | Read_RISCV_reserved_strong_acquire + (* x86 reads *) + | Read_X86_locked (* the read part of a lock'd instruction (rmw) *) + +definition instance_Show_Show_Sail_instr_kinds_read_kind_dict :: "(read_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_read_kind_dict = ((| + + show_method = (\<lambda>x . + (case x of + Read_plain => (''Read_plain'') + | Read_reserve => (''Read_reserve'') + | Read_acquire => (''Read_acquire'') + | Read_exclusive => (''Read_exclusive'') + | Read_exclusive_acquire => (''Read_exclusive_acquire'') + | Read_stream => (''Read_stream'') + | Read_RISCV_acquire => (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => (''Read_X86_locked'') + ))|) )" + + +datatype write_kind = + (* common writes *) + Write_plain + (* Power writes *) + | Write_conditional + (* AArch64 writes *) + | Write_release | Write_exclusive | Write_exclusive_release + (* RISC-V *) + | Write_RISCV_release | Write_RISCV_strong_release + | Write_RISCV_conditional | Write_RISCV_conditional_release + | Write_RISCV_conditional_strong_release + (* x86 writes *) + | Write_X86_locked (* the write part of a lock'd instruction (rmw) *) + +definition instance_Show_Show_Sail_instr_kinds_write_kind_dict :: "(write_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_write_kind_dict = ((| + + show_method = (\<lambda>x . + (case x of + Write_plain => (''Write_plain'') + | Write_conditional => (''Write_conditional'') + | Write_release => (''Write_release'') + | Write_exclusive => (''Write_exclusive'') + | Write_exclusive_release => (''Write_exclusive_release'') + | Write_RISCV_release => (''Write_RISCV_release'') + | Write_RISCV_strong_release => (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => (''Write_X86_locked'') + ))|) )" + + +datatype barrier_kind = + (* Power barriers *) + Barrier_Sync | Barrier_LwSync | Barrier_Eieio | Barrier_Isync + (* AArch64 barriers *) + | Barrier_DMB | Barrier_DMB_ST | Barrier_DMB_LD | Barrier_DSB + | Barrier_DSB_ST | Barrier_DSB_LD | Barrier_ISB + | Barrier_TM_COMMIT + (* MIPS barriers *) + | Barrier_MIPS_SYNC + (* RISC-V barriers *) + | Barrier_RISCV_rw_rw + | Barrier_RISCV_r_rw + | Barrier_RISCV_r_r + | Barrier_RISCV_rw_w + | Barrier_RISCV_w_w + | Barrier_RISCV_i + (* X86 *) + | Barrier_x86_MFENCE + + +definition instance_Show_Show_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_barrier_kind_dict = ((| + + show_method = (\<lambda>x . + (case x of + Barrier_Sync => (''Barrier_Sync'') + | Barrier_LwSync => (''Barrier_LwSync'') + | Barrier_Eieio => (''Barrier_Eieio'') + | Barrier_Isync => (''Barrier_Isync'') + | Barrier_DMB => (''Barrier_DMB'') + | Barrier_DMB_ST => (''Barrier_DMB_ST'') + | Barrier_DMB_LD => (''Barrier_DMB_LD'') + | Barrier_DSB => (''Barrier_DSB'') + | Barrier_DSB_ST => (''Barrier_DSB_ST'') + | Barrier_DSB_LD => (''Barrier_DSB_LD'') + | Barrier_ISB => (''Barrier_ISB'') + | Barrier_TM_COMMIT => (''Barrier_TM_COMMIT'') + | Barrier_MIPS_SYNC => (''Barrier_MIPS_SYNC'') + | Barrier_RISCV_rw_rw => (''Barrier_RISCV_rw_rw'') + | Barrier_RISCV_r_rw => (''Barrier_RISCV_r_rw'') + | Barrier_RISCV_r_r => (''Barrier_RISCV_r_r'') + | Barrier_RISCV_rw_w => (''Barrier_RISCV_rw_w'') + | Barrier_RISCV_w_w => (''Barrier_RISCV_w_w'') + | Barrier_RISCV_i => (''Barrier_RISCV_i'') + | Barrier_x86_MFENCE => (''Barrier_x86_MFENCE'') + ))|) )" + + +datatype trans_kind = + (* AArch64 *) + Transaction_start | Transaction_commit | Transaction_abort + +definition instance_Show_Show_Sail_instr_kinds_trans_kind_dict :: "(trans_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_trans_kind_dict = ((| + + show_method = (\<lambda>x . + (case x of + Transaction_start => (''Transaction_start'') + | Transaction_commit => (''Transaction_commit'') + | Transaction_abort => (''Transaction_abort'') + ))|) )" + + +datatype instruction_kind = + IK_barrier " barrier_kind " + | IK_mem_read " read_kind " + | IK_mem_write " write_kind " + | IK_mem_rmw " (read_kind * write_kind)" + | IK_branch (* this includes conditional-branch (multiple nias, none of which is NIA_indirect_address), + indirect/computed-branch (single nia of kind NIA_indirect_address) + and branch/jump (single nia of kind NIA_concrete_address) *) + | IK_trans " trans_kind " + | IK_simple + + +definition instance_Show_Show_Sail_instr_kinds_instruction_kind_dict :: "(instruction_kind)Show_class " where + " instance_Show_Show_Sail_instr_kinds_instruction_kind_dict = ((| + + show_method = (\<lambda>x . + (case x of + IK_barrier barrier_kind => (''IK_barrier '') @ + (((\<lambda>x . (case x of + Barrier_Sync => + (''Barrier_Sync'') + | Barrier_LwSync => + (''Barrier_LwSync'') + | Barrier_Eieio => + (''Barrier_Eieio'') + | Barrier_Isync => + (''Barrier_Isync'') + | Barrier_DMB => + (''Barrier_DMB'') + | Barrier_DMB_ST => + (''Barrier_DMB_ST'') + | Barrier_DMB_LD => + (''Barrier_DMB_LD'') + | Barrier_DSB => + (''Barrier_DSB'') + | Barrier_DSB_ST => + (''Barrier_DSB_ST'') + | Barrier_DSB_LD => + (''Barrier_DSB_LD'') + | Barrier_ISB => + (''Barrier_ISB'') + | Barrier_TM_COMMIT => + (''Barrier_TM_COMMIT'') + | Barrier_MIPS_SYNC => + (''Barrier_MIPS_SYNC'') + | Barrier_RISCV_rw_rw => + (''Barrier_RISCV_rw_rw'') + | Barrier_RISCV_r_rw => + (''Barrier_RISCV_r_rw'') + | Barrier_RISCV_r_r => + (''Barrier_RISCV_r_r'') + | Barrier_RISCV_rw_w => + (''Barrier_RISCV_rw_w'') + | Barrier_RISCV_w_w => + (''Barrier_RISCV_w_w'') + | Barrier_RISCV_i => + (''Barrier_RISCV_i'') + | Barrier_x86_MFENCE => + (''Barrier_x86_MFENCE'') + )) barrier_kind)) + | IK_mem_read read_kind => (''IK_mem_read '') @ + (((\<lambda>x . (case x of + Read_plain => + (''Read_plain'') + | Read_reserve => + (''Read_reserve'') + | Read_acquire => + (''Read_acquire'') + | Read_exclusive => + (''Read_exclusive'') + | Read_exclusive_acquire => + (''Read_exclusive_acquire'') + | Read_stream => + (''Read_stream'') + | Read_RISCV_acquire => + (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => + (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => + (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => + (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => + (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => + (''Read_X86_locked'') + )) read_kind)) + | IK_mem_write write_kind => (''IK_mem_write '') @ + (((\<lambda>x . (case x of + Write_plain => + (''Write_plain'') + | Write_conditional => + (''Write_conditional'') + | Write_release => + (''Write_release'') + | Write_exclusive => + (''Write_exclusive'') + | Write_exclusive_release => + (''Write_exclusive_release'') + | Write_RISCV_release => + (''Write_RISCV_release'') + | Write_RISCV_strong_release => + (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => + (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => + (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => + (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => + (''Write_X86_locked'') + )) write_kind)) + | IK_mem_rmw (r, w) => (''IK_mem_rmw '') @ + ((((\<lambda>x . (case x of + Read_plain => (''Read_plain'') + | Read_reserve => (''Read_reserve'') + | Read_acquire => (''Read_acquire'') + | Read_exclusive => + (''Read_exclusive'') + | Read_exclusive_acquire => + (''Read_exclusive_acquire'') + | Read_stream => (''Read_stream'') + | Read_RISCV_acquire => + (''Read_RISCV_acquire'') + | Read_RISCV_strong_acquire => + (''Read_RISCV_strong_acquire'') + | Read_RISCV_reserved => + (''Read_RISCV_reserved'') + | Read_RISCV_reserved_acquire => + (''Read_RISCV_reserved_acquire'') + | Read_RISCV_reserved_strong_acquire => + (''Read_RISCV_reserved_strong_acquire'') + | Read_X86_locked => + (''Read_X86_locked'') + )) r)) @ + (('' '') @ + (((\<lambda>x . (case x of + Write_plain => + (''Write_plain'') + | Write_conditional => + (''Write_conditional'') + | Write_release => + (''Write_release'') + | Write_exclusive => + (''Write_exclusive'') + | Write_exclusive_release => + (''Write_exclusive_release'') + | Write_RISCV_release => + (''Write_RISCV_release'') + | Write_RISCV_strong_release => + (''Write_RISCV_strong_release'') + | Write_RISCV_conditional => + (''Write_RISCV_conditional'') + | Write_RISCV_conditional_release => + (''Write_RISCV_conditional_release'') + | Write_RISCV_conditional_strong_release => + (''Write_RISCV_conditional_strong_release'') + | Write_X86_locked => + (''Write_X86_locked'') + )) w)))) + | IK_branch => (''IK_branch'') + | IK_trans trans_kind => (''IK_trans '') @ + (((\<lambda>x . (case x of + Transaction_start => + (''Transaction_start'') + | Transaction_commit => + (''Transaction_commit'') + | Transaction_abort => + (''Transaction_abort'') + )) trans_kind)) + | IK_simple => (''IK_simple'') + ))|) )" + + + +definition read_is_exclusive :: " read_kind \<Rightarrow> bool " where + " read_is_exclusive = ( \<lambda>x . + (case x of + Read_plain => False + | Read_reserve => True + | Read_acquire => False + | Read_exclusive => True + | Read_exclusive_acquire => True + | Read_stream => False + | Read_RISCV_acquire => False + | Read_RISCV_strong_acquire => False + | Read_RISCV_reserved => True + | Read_RISCV_reserved_acquire => True + | Read_RISCV_reserved_strong_acquire => True + | Read_X86_locked => True + ) )" + + + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict :: "(read_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_read_kind_dict = ((| + + toNat_method = (\<lambda>x . + (case x of + Read_plain =>( 0 :: nat) + | Read_reserve =>( 1 :: nat) + | Read_acquire =>( 2 :: nat) + | Read_exclusive =>( 3 :: nat) + | Read_exclusive_acquire =>( 4 :: nat) + | Read_stream =>( 5 :: nat) + | Read_RISCV_acquire =>( 6 :: nat) + | Read_RISCV_strong_acquire =>( 7 :: nat) + | Read_RISCV_reserved =>( 8 :: nat) + | Read_RISCV_reserved_acquire =>( 9 :: nat) + | Read_RISCV_reserved_strong_acquire =>( 10 :: nat) + | Read_X86_locked =>( 11 :: nat) + ))|) )" + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict :: "(write_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_write_kind_dict = ((| + + toNat_method = (\<lambda>x . + (case x of + Write_plain =>( 0 :: nat) + | Write_conditional =>( 1 :: nat) + | Write_release =>( 2 :: nat) + | Write_exclusive =>( 3 :: nat) + | Write_exclusive_release =>( 4 :: nat) + | Write_RISCV_release =>( 5 :: nat) + | Write_RISCV_strong_release =>( 6 :: nat) + | Write_RISCV_conditional =>( 7 :: nat) + | Write_RISCV_conditional_release =>( 8 :: nat) + | Write_RISCV_conditional_strong_release =>( 9 :: nat) + | Write_X86_locked =>( 10 :: nat) + ))|) )" + + +definition instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict :: "(barrier_kind)EnumerationType_class " where + " instance_Sail_instr_kinds_EnumerationType_Sail_instr_kinds_barrier_kind_dict = ((| + + toNat_method = (\<lambda>x . + (case x of + Barrier_Sync =>( 0 :: nat) + | Barrier_LwSync =>( 1 :: nat) + | Barrier_Eieio =>( 2 :: nat) + | Barrier_Isync =>( 3 :: nat) + | Barrier_DMB =>( 4 :: nat) + | Barrier_DMB_ST =>( 5 :: nat) + | Barrier_DMB_LD =>( 6 :: nat) + | Barrier_DSB =>( 7 :: nat) + | Barrier_DSB_ST =>( 8 :: nat) + | Barrier_DSB_LD =>( 9 :: nat) + | Barrier_ISB =>( 10 :: nat) + | Barrier_TM_COMMIT =>( 11 :: nat) + | Barrier_MIPS_SYNC =>( 12 :: nat) + | Barrier_RISCV_rw_rw =>( 13 :: nat) + | Barrier_RISCV_r_rw =>( 14 :: nat) + | Barrier_RISCV_r_r =>( 15 :: nat) + | Barrier_RISCV_rw_w =>( 16 :: nat) + | Barrier_RISCV_w_w =>( 17 :: nat) + | Barrier_RISCV_i =>( 18 :: nat) + | Barrier_x86_MFENCE =>( 19 :: nat) + ))|) )" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators.thy b/snapshots/isabelle/lib/sail/Sail_operators.thy new file mode 100644 index 00000000..00b32a85 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators.thy @@ -0,0 +1,326 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators.lem.\<close> + +theory "Sail_operators" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) + +(*** Bit vector operations *) + +(*val concat_bv : forall 'a 'b. Bitvector 'a, Bitvector 'b => 'a -> 'b -> list bitU*) +definition concat_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'b \<Rightarrow>(bitU)list " where + " concat_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b l r = ( ( + (bits_of_method dict_Sail_values_Bitvector_a) l @(bits_of_method dict_Sail_values_Bitvector_b) r))" + + +(*val cons_bv : forall 'a. Bitvector 'a => bitU -> 'a -> list bitU*) +definition cons_bv :: " 'a Bitvector_class \<Rightarrow> bitU \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " cons_bv dict_Sail_values_Bitvector_a b v = ( b # + (bits_of_method dict_Sail_values_Bitvector_a) v )" + + +(*val cast_unit_bv : bitU -> list bitU*) +definition cast_unit_bv :: " bitU \<Rightarrow>(bitU)list " where + " cast_unit_bv b = ( [b])" + + +(*val bv_of_bit : integer -> bitU -> list bitU*) +definition bv_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " bv_of_bit len b = ( extz_bits len [b])" + + +definition most_significant :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU " where + " most_significant dict_Sail_values_Bitvector_a v = ( (case + (bits_of_method dict_Sail_values_Bitvector_a) v of + b # _ => b + | _ => B0 (* Treat empty bitvector as all zeros *) + ))" + + +definition get_max_representable_in :: " bool \<Rightarrow> int \<Rightarrow> int " where + " get_max_representable_in sign (n :: int) = ( + if (n =( 64 :: int)) then (case sign of True => max_64 | False => max_64u ) + else if (n=( 32 :: int)) then (case sign of True => max_32 | False => max_32u ) + else if (n=( 8 :: int)) then max_8 + else if (n=( 5 :: int)) then max_5 + else (case sign of True => (( 2 :: int))^ ((nat (abs ( n))) -( 1 :: nat)) + | False => (( 2 :: int))^ (nat (abs ( n))) + ))" + + +definition get_min_representable_in :: " 'a \<Rightarrow> int \<Rightarrow> int " where + " get_min_representable_in _ (n :: int) = ( + if n =( 64 :: int) then min_64 + else if n =( 32 :: int) then min_32 + else if n =( 8 :: int) then min_8 + else if n =( 5 :: int) then min_5 + else( 0 :: int) - ((( 2 :: int))^ (nat (abs ( n)))))" + + +(*val arith_op_bv_int : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> 'a -> integer -> 'a*) +definition arith_op_bv_int :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'a " where + " arith_op_bv_int dict_Sail_values_Bitvector_a op1 sign l r = ( + (let r' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l r'))" + + +(*val arith_op_int_bv : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a*) +definition arith_op_int_bv :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a " where + " arith_op_int_bv dict_Sail_values_Bitvector_a op1 sign l r = ( + (let l' = ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) r) l) in (arith_op_bv_method dict_Sail_values_Bitvector_a) op1 sign l' r))" + + +definition arith_op_bv_bool :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where + " arith_op_bv_bool dict_Sail_values_Bitvector_a op1 sign l r = ( arith_op_bv_int + dict_Sail_values_Bitvector_a op1 sign l (if r then( 1 :: int) else( 0 :: int)))" + +definition arith_op_bv_bit :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where + " arith_op_bv_bit dict_Sail_values_Bitvector_a op1 sign l r = ( map_option (arith_op_bv_bool + dict_Sail_values_Bitvector_a op1 sign l) (bool_of_bitU r))" + + +(* TODO (or just omit and define it per spec if needed) +val arith_op_overflow_bv : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> (list bitU * bitU * bitU) +let arith_op_overflow_bv op sign size l r = + let len = length l in + let act_size = len * size in + match (int_of_bv sign l, int_of_bv sign r, int_of_bv false l, int_of_bv false r) with + | (Just l_sign, Just r_sign, Just l_unsign, Just r_unsign) -> + let n = op l_sign r_sign in + let n_unsign = op l_unsign r_unsign in + let correct_size = of_int act_size n in + let one_more_size_u = bits_of_int (act_size + 1) n_unsign in + let overflow = + if n <= get_max_representable_in sign len && + n >= get_min_representable_in sign len + then B0 else B1 in + let c_out = most_significant one_more_size_u in + (correct_size,overflow,c_out) + | (_, _, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv = arith_op_overflow_bv integerAdd false 1 +let adds_overflow_bv = arith_op_overflow_bv integerAdd true 1 +let sub_overflow_bv = arith_op_overflow_bv integerMinus false 1 +let subs_overflow_bv = arith_op_overflow_bv integerMinus true 1 +let mult_overflow_bv = arith_op_overflow_bv integerMult false 2 +let mults_overflow_bv = arith_op_overflow_bv integerMult true 2 + +val arith_op_overflow_bv_bit : forall 'a. Bitvector 'a => + (integer -> integer -> integer) -> bool -> integer -> 'a -> bitU -> (list bitU * bitU * bitU) +let arith_op_overflow_bv_bit op sign size l r_bit = + let act_size = length l * size in + match (int_of_bv sign l, int_of_bv false l, r_bit = BU) with + | (Just l', Just l_u, false) -> + let (n, nu, changed) = match r_bit with + | B1 -> (op l' 1, op l_u 1, true) + | B0 -> (l', l_u, false) + | BU -> (* unreachable due to check above *) + failwith arith_op_overflow_bv_bit applied to undefined bit + end in + let correct_size = of_int act_size n in + let one_larger = bits_of_int (act_size + 1) nu in + let overflow = + if changed + then + if n <= get_max_representable_in sign act_size && n >= get_min_representable_in sign act_size + then B0 else B1 + else B0 in + (correct_size, overflow, most_significant one_larger) + | (_, _, _) -> + (repeat [BU] act_size, BU, BU) + end + +let add_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd false 1 +let adds_overflow_bv_bit = arith_op_overflow_bv_bit integerAdd true 1 +let sub_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus false 1 +let subs_overflow_bv_bit = arith_op_overflow_bv_bit integerMinus true 1*) + +datatype shift = LL_shift | RR_shift | RR_shift_arith | LL_rot | RR_rot + +definition invert_shift :: " shift \<Rightarrow> shift " where + " invert_shift = ( \<lambda>x . + (case x of + LL_shift => RR_shift + | RR_shift => LL_shift + | RR_shift_arith => LL_shift + | LL_rot => RR_rot + | RR_rot => LL_rot + ) )" + + +(*val shift_op_bv : forall 'a. Bitvector 'a => shift -> 'a -> integer -> list bitU*) +definition shift_op_bv :: " 'a Bitvector_class \<Rightarrow> shift \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " shift_op_bv dict_Sail_values_Bitvector_a op1 v n = ( + (let v = ((bits_of_method dict_Sail_values_Bitvector_a) v) in + if n =( 0 :: int) then v else + (let (op1, n) = (if n >( 0 :: int) then (op1, n) else (invert_shift op1, - n)) in + (case op1 of + LL_shift => + subrange_list True v n (int (List.length v) -( 1 :: int)) @ repeat [B0] n + | RR_shift => + repeat [B0] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) + | RR_shift_arith => + repeat [most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) v] n @ subrange_list True v(( 0 :: int)) ((int (List.length v) - n) -( 1 :: int)) + | LL_rot => + subrange_list True v n (int (List.length v) -( 1 :: int)) @ subrange_list True v(( 0 :: int)) (n -( 1 :: int)) + | RR_rot => + subrange_list False v(( 0 :: int)) (n -( 1 :: int)) @ subrange_list False v n (int (List.length v) -( 1 :: int)) + ))))" + + +definition shiftl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " shiftl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_shift )" + (*<<*) +definition shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a RR_shift )" + (*>>*) +definition arith_shiftr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " arith_shiftr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a RR_shift_arith )" + +definition rotl_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " rotl_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_rot )" + (*<<<*) +definition rotr_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " rotr_bv dict_Sail_values_Bitvector_a = ( shift_op_bv + dict_Sail_values_Bitvector_a LL_rot )" + (*>>>*) + +definition shiftl_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " shiftl_mword w n = ( w << (nat_of_int n))" + +definition shiftr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " shiftr_mword w n = ( w >> (nat_of_int n))" + +definition arith_shiftr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " arith_shiftr_mword w n = ( w >>> (nat_of_int n))" + +definition rotl_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " rotl_mword w n = ( Word.word_rotl (nat_of_int n) w )" + +definition rotr_mword :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " rotr_mword w n = ( Word.word_rotr (nat_of_int n) w )" + + +fun arith_op_no0 :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)option " where + " arith_op_no0 (op1 :: int \<Rightarrow> int \<Rightarrow> int) l r = ( + if r =( 0 :: int) + then None + else Some (op1 l r))" + + +(*val arith_op_bv_no0 : forall 'a 'b. Bitvector 'a, Bitvector 'b => + (integer -> integer -> integer) -> bool -> integer -> 'a -> 'a -> maybe 'b*) +definition arith_op_bv_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'b option " where + " arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( + Option.bind (int_of_bv + dict_Sail_values_Bitvector_a sign l) (\<lambda> l' . + Option.bind (int_of_bv + dict_Sail_values_Bitvector_a sign r) (\<lambda> r' . + if r' =( 0 :: int) then None else Some ( + (of_int_method dict_Sail_values_Bitvector_b) ((length_method dict_Sail_values_Bitvector_a) l * size1) (op1 l' r')))))" + + +definition mod_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where + " mod_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + +definition quot_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where + " quot_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + +definition quots_bv :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> 'b \<Rightarrow> 'a option " where + " quots_bv dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot True(( 1 :: int)))" + + +definition mod_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " mod_mword = ( (op mod))" + +definition quot_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " quot_mword = ( (op div))" + +definition quots_mword :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " quots_mword = ( Lem_machine_word.signedDivide )" + + +definition arith_op_bv_int_no0 :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> 'b option " where + " arith_op_bv_int_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l r = ( + arith_op_bv_no0 dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b op1 sign size1 l ((of_int_method dict_Sail_values_Bitvector_a) ((length_method dict_Sail_values_Bitvector_a) l) r))" + + +definition quot_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where + " quot_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_quot False(( 1 :: int)))" + +definition mod_bv_int :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> 'a option " where + " mod_bv_int dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b = ( arith_op_bv_int_no0 + dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a hardware_mod False(( 1 :: int)))" + + +definition mod_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " mod_mword_int l r = ( l mod (Word.word_of_int r))" + +definition quot_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " quot_mword_int l r = ( l div (Word.word_of_int r))" + +definition quots_mword_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " quots_mword_int l r = ( Lem_machine_word.signedDivide l (Word.word_of_int r))" + + +definition replicate_bits_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " replicate_bits_bv dict_Sail_values_Bitvector_a v count1 = ( repeat ( + (bits_of_method dict_Sail_values_Bitvector_a) v) count1 )" + +definition duplicate_bit_bv :: " 'a BitU_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>(bitU)list " where + " duplicate_bit_bv dict_Sail_values_BitU_a bit len = ( replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a) [bit] len )" + + +(*val eq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +definition eq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where + " eq_bv dict_Sail_values_Bitvector_a l r = ( ( + (bits_of_method dict_Sail_values_Bitvector_a) l =(bits_of_method dict_Sail_values_Bitvector_a) r))" + + +(*val neq_bv : forall 'a. Bitvector 'a => 'a -> 'a -> bool*) +definition neq_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> bool " where + " neq_bv dict_Sail_values_Bitvector_a l r = ( \<not> (eq_bv + dict_Sail_values_Bitvector_a l r))" + + +(*val get_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a*) +definition get_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a " where + " get_slice_int_bv dict_Sail_values_Bitvector_a len n lo = ( + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bools_of_int (hi +( 1 :: int)) n) in + (of_bools_method dict_Sail_values_Bitvector_a) (subrange_list False bs hi lo))))" + + +(*val set_slice_int_bv : forall 'a. Bitvector 'a => integer -> integer -> integer -> 'a -> integer*) +definition set_slice_int_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> int " where + " set_slice_int_bv dict_Sail_values_Bitvector_a len n lo v = ( + (let hi = ((lo + len) -( 1 :: int)) in + (let bs = (bits_of_int (hi +( 1 :: int)) n) in + maybe_failwith (signed_of_bits (update_subrange_list False bs hi lo ( + (bits_of_method dict_Sail_values_Bitvector_a) v))))))" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy b/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy new file mode 100644 index 00000000..d3d886ed --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_bitlists.thy @@ -0,0 +1,773 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_bitlists.lem.\<close> + +theory "Sail_operators_bitlists" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + "Sail_operators" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) + +(* Specialisation of operators to bit lists *) + +(*val uint_maybe : list bitU -> maybe integer*) +definition uint_maybe :: "(bitU)list \<Rightarrow>(int)option " where + " uint_maybe v = ( unsigned_of_bits (List.map (\<lambda> b. b) v))" + +definition uint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where + " uint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''uint'') ( + (unsigned_method dict_Sail_values_Bitvector_a) v))" + +definition uint_oracle :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " uint_oracle v = ( + bools_of_bits_oracle v \<bind> (\<lambda> bs . + return (int_of_bools False bs)))" + +definition uint :: "(bitU)list \<Rightarrow> int " where + " uint v = ( maybe_failwith (uint_maybe v))" + + +(*val sint_maybe : list bitU -> maybe integer*) +definition sint_maybe :: "(bitU)list \<Rightarrow>(int)option " where + " sint_maybe v = ( signed_of_bits (List.map (\<lambda> b. b) v))" + +definition sint_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('c,(int),'b)monad " where + " sint_fail dict_Sail_values_Bitvector_a v = ( maybe_fail (''sint'') ( + (signed_method dict_Sail_values_Bitvector_a) v))" + +definition sint_oracle :: "(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " sint_oracle v = ( + bools_of_bits_oracle v \<bind> (\<lambda> bs . + return (int_of_bools True bs)))" + +definition sint :: "(bitU)list \<Rightarrow> int " where + " sint v = ( maybe_failwith (sint_maybe v))" + + +(*val extz_vec : integer -> list bitU -> list bitU*) +definition extz_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " extz_vec = ( + extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val exts_vec : integer -> list bitU -> list bitU*) +definition exts_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " exts_vec = ( + exts_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val zero_extend : list bitU -> integer -> list bitU*) +definition zero_extend :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " zero_extend bits len = ( extz_bits len bits )" + + +(*val sign_extend : list bitU -> integer -> list bitU*) +definition sign_extend :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " sign_extend bits len = ( exts_bits len bits )" + + +(*val zeros : integer -> list bitU*) +definition zeros :: " int \<Rightarrow>(bitU)list " where + " zeros len = ( repeat [B0] len )" + + +(*val vector_truncate : list bitU -> integer -> list bitU*) +definition vector_truncate :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " vector_truncate bs len = ( extz_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) len bs )" + + +(*val vec_of_bits_maybe : list bitU -> maybe (list bitU)*) +(*val vec_of_bits_fail : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'e. list bitU -> monad 'rv (list bitU) 'e*) +(*val vec_of_bits_failwith : list bitU -> list bitU*) +(*val vec_of_bits : list bitU -> list bitU*) + +(*val access_vec_inc : list bitU -> integer -> bitU*) +definition access_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where + " access_vec_inc = ( + access_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val access_vec_dec : list bitU -> integer -> bitU*) +definition access_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU " where + " access_vec_dec = ( + access_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_vec_inc : list bitU -> integer -> bitU -> list bitU*) +definition update_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " update_vec_inc = ( + update_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition update_vec_inc_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where + " update_vec_inc_maybe v i b = ( Some (update_vec_inc v i b))" + +definition update_vec_inc_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_inc_fail v i b = ( return (update_vec_inc v i b))" + +definition update_vec_inc_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_inc_oracle v i b = ( return (update_vec_inc v i b))" + + +(*val update_vec_dec : list bitU -> integer -> bitU -> list bitU*) +definition update_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " update_vec_dec = ( + update_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition update_vec_dec_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where + " update_vec_dec_maybe v i b = ( Some (update_vec_dec v i b))" + +definition update_vec_dec_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_dec_fail v i b = ( return (update_vec_dec v i b))" + +definition update_vec_dec_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " update_vec_dec_oracle v i b = ( return (update_vec_dec v i b))" + + +(*val subrange_vec_inc : list bitU -> integer -> integer -> list bitU*) +definition subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " subrange_vec_inc = ( + subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val subrange_vec_dec : list bitU -> integer -> integer -> list bitU*) +definition subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " subrange_vec_dec = ( + subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_subrange_vec_inc : list bitU -> integer -> integer -> list bitU -> list bitU*) +definition update_subrange_vec_inc :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " update_subrange_vec_inc = ( + update_subrange_bv_inc + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val update_subrange_vec_dec : list bitU -> integer -> integer -> list bitU -> list bitU*) +definition update_subrange_vec_dec :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " update_subrange_vec_dec = ( + update_subrange_bv_dec + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val concat_vec : list bitU -> list bitU -> list bitU*) +definition concat_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " concat_vec = ( + concat_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val cons_vec : bitU -> list bitU -> list bitU*) +definition cons_vec :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " cons_vec = ( + cons_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition cons_vec_maybe :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where + " cons_vec_maybe b v = ( Some (cons_vec b v))" + +definition cons_vec_fail :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where + " cons_vec_fail b v = ( return (cons_vec b v))" + +definition cons_vec_oracle :: " bitU \<Rightarrow>(bitU)list \<Rightarrow>('b,((bitU)list),'a)monad " where + " cons_vec_oracle b v = ( return (cons_vec b v))" + + +(*val cast_unit_vec : bitU -> list bitU*) +definition cast_unit_vec :: " bitU \<Rightarrow>(bitU)list " where + " cast_unit_vec = ( cast_unit_bv )" + +definition cast_unit_vec_maybe :: " bitU \<Rightarrow>((bitU)list)option " where + " cast_unit_vec_maybe b = ( Some (cast_unit_vec b))" + +definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " cast_unit_vec_fail b = ( return (cast_unit_vec b))" + +definition cast_unit_vec_oracle :: " bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " cast_unit_vec_oracle b = ( return (cast_unit_vec b))" + + +(*val vec_of_bit : integer -> bitU -> list bitU*) +definition vec_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " vec_of_bit = ( bv_of_bit )" + +definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>((bitU)list)option " where + " vec_of_bit_maybe len b = ( Some (vec_of_bit len b))" + +definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " vec_of_bit_fail len b = ( return (vec_of_bit len b))" + +definition vec_of_bit_oracle :: " int \<Rightarrow> bitU \<Rightarrow>('b,((bitU)list),'a)monad " where + " vec_of_bit_oracle len b = ( return (vec_of_bit len b))" + + +(*val msb : list bitU -> bitU*) +definition msb :: "(bitU)list \<Rightarrow> bitU " where + " msb = ( + most_significant + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val int_of_vec_maybe : bool -> list bitU -> maybe integer*) +definition int_of_vec_maybe :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option " where + " int_of_vec_maybe = ( + int_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition int_of_vec_fail :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " int_of_vec_fail sign v = ( maybe_fail (''int_of_vec'') (int_of_vec_maybe sign v))" + +definition int_of_vec_oracle :: " bool \<Rightarrow>(bitU)list \<Rightarrow>('b,(int),'a)monad " where + " int_of_vec_oracle sign v = ( bools_of_bits_oracle v \<bind> (\<lambda> v . return (int_of_bools sign v)))" + +definition int_of_vec :: " bool \<Rightarrow>(bitU)list \<Rightarrow> int " where + " int_of_vec sign v = ( maybe_failwith (int_of_vec_maybe sign v))" + + +(*val string_of_vec : list bitU -> string*) +definition string_of_vec :: "(bitU)list \<Rightarrow> string " where + " string_of_vec = ( + string_of_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val and_vec : list bitU -> list bitU -> list bitU*) +(*val or_vec : list bitU -> list bitU -> list bitU*) +(*val xor_vec : list bitU -> list bitU -> list bitU*) +(*val not_vec : list bitU -> list bitU*) +definition and_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " and_vec = ( binop_list and_bit )" + +definition or_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " or_vec = ( binop_list or_bit )" + +definition xor_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " xor_vec = ( binop_list xor_bit )" + +definition not_vec :: "(bitU)list \<Rightarrow>(bitU)list " where + " not_vec = ( List.map not_bit )" + + +(*val arith_op_double_bl : forall 'a 'b. Bitvector 'a => + (integer -> integer -> integer) -> bool -> 'a -> 'a -> list bitU*) +definition arith_op_double_bl :: " 'a Bitvector_class \<Rightarrow>(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " arith_op_double_bl dict_Sail_values_Bitvector_a op1 sign l r = ( + (let len =(( 2 :: int) * + (length_method dict_Sail_values_Bitvector_a) l) in + (let l' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len l else extz_bv dict_Sail_values_Bitvector_a len l) in + (let r' = (if sign then exts_bv + dict_Sail_values_Bitvector_a len r else extz_bv dict_Sail_values_Bitvector_a len r) in + List.map (\<lambda> b. b) (arith_op_bits op1 sign (List.map (\<lambda> b. b) l') (List.map (\<lambda> b. b) r'))))))" + + +(*val add_vec : list bitU -> list bitU -> list bitU*) +(*val adds_vec : list bitU -> list bitU -> list bitU*) +(*val sub_vec : list bitU -> list bitU -> list bitU*) +(*val subs_vec : list bitU -> list bitU -> list bitU*) +(*val mult_vec : list bitU -> list bitU -> list bitU*) +(*val mults_vec : list bitU -> list bitU -> list bitU*) +definition add_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " add_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))" + +definition adds_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " adds_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op+) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))" + +definition sub_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " sub_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) False (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))" + +definition subs_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " subs_vec = ( (\<lambda> l r. List.map (\<lambda> b. b) (arith_op_bits (op-) True (List.map (\<lambda> b. b) l) (List.map (\<lambda> b. b) r))))" + +definition mult_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " mult_vec = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False )" + +definition mults_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " mults_vec = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True )" + + +(*val add_vec_int : list bitU -> integer -> list bitU*) +(*val adds_vec_int : list bitU -> integer -> list bitU*) +(*val sub_vec_int : list bitU -> integer -> list bitU*) +(*val subs_vec_int : list bitU -> integer -> list bitU*) +(*val mult_vec_int : list bitU -> integer -> list bitU*) +(*val mults_vec_int : list bitU -> integer -> list bitU*) +definition add_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " add_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" + +definition adds_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " adds_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" + +definition sub_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " sub_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" + +definition subs_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " subs_vec_int l r = ( arith_op_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" + +definition mult_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " mult_vec_int l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))" + +definition mults_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " mults_vec_int l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True l (List.map (\<lambda> b. b) (bits_of_int (int (List.length l)) r)))" + + +(*val add_int_vec : integer -> list bitU -> list bitU*) +(*val adds_int_vec : integer -> list bitU -> list bitU*) +(*val sub_int_vec : integer -> list bitU -> list bitU*) +(*val subs_int_vec : integer -> list bitU -> list bitU*) +(*val mult_int_vec : integer -> list bitU -> list bitU*) +(*val mults_int_vec : integer -> list bitU -> list bitU*) +definition add_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " add_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) False l r )" + +definition adds_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " adds_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op+) True l r )" + +definition sub_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " sub_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) False l r )" + +definition subs_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " subs_int_vec l r = ( arith_op_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op-) True l r )" + +definition mult_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " mult_int_vec l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) False (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )" + +definition mults_int_vec :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " mults_int_vec l r = ( arith_op_double_bl + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (op*) True (List.map (\<lambda> b. b) (bits_of_int (int (List.length r)) l)) r )" + + +(*val add_vec_bit : list bitU -> bitU -> list bitU*) +(*val adds_vec_bit : list bitU -> bitU -> list bitU*) +(*val sub_vec_bit : list bitU -> bitU -> list bitU*) +(*val subs_vec_bit : list bitU -> bitU -> list bitU*) + +definition add_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where + " add_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op+) False l r )" + +definition add_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where + " add_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op+) False l r )" + +definition add_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " add_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''add_vec_bit'') (add_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition add_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " add_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (add_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition add_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " add_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (add_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition adds_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where + " adds_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op+) True l r )" + +definition adds_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where + " adds_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op+) True l r )" + +definition adds_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " adds_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''adds_vec_bit'') (adds_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition adds_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " adds_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (adds_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition adds_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " adds_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (adds_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition sub_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where + " sub_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op-) False l r )" + +definition sub_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where + " sub_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op-) False l r )" + +definition sub_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " sub_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (sub_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition sub_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " sub_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (sub_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition sub_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " sub_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (sub_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +definition subs_vec_bool :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bool \<Rightarrow> 'a " where + " subs_vec_bool dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bool + dict_Sail_values_Bitvector_a (op-) True l r )" + +definition subs_vec_bit_maybe :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow> 'a option " where + " subs_vec_bit_maybe dict_Sail_values_Bitvector_a l r = ( arith_op_bv_bit + dict_Sail_values_Bitvector_a (op-) True l r )" + +definition subs_vec_bit_fail :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " subs_vec_bit_fail dict_Sail_values_Bitvector_a l r = ( maybe_fail (''sub_vec_bit'') (subs_vec_bit_maybe + dict_Sail_values_Bitvector_a l r))" + +definition subs_vec_bit_oracle :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('d,'a,'c)monad " where + " subs_vec_bit_oracle dict_Sail_values_Bitvector_a l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (subs_vec_bool + dict_Sail_values_Bitvector_a l r)))" + +definition subs_vec_bit :: "(bitU)list \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " subs_vec_bit l r = ( case_option (repeat [BU] (int (List.length l))) id (subs_vec_bit_maybe + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + + +(*val add_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec : list bitU -> list bitU -> (list bitU * bitU * bitU) +val mult_overflow_vec_signed : list bitU -> list bitU -> (list bitU * bitU * bitU) +let add_overflow_vec = add_overflow_bv +let add_overflow_vec_signed = add_overflow_bv_signed +let sub_overflow_vec = sub_overflow_bv +let sub_overflow_vec_signed = sub_overflow_bv_signed +let mult_overflow_vec = mult_overflow_bv +let mult_overflow_vec_signed = mult_overflow_bv_signed + +val add_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val add_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit : list bitU -> bitU -> (list bitU * bitU * bitU) +val sub_overflow_vec_bit_signed : list bitU -> bitU -> (list bitU * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : list bitU -> integer -> list bitU*) +(*val shiftr : list bitU -> integer -> list bitU*) +(*val arith_shiftr : list bitU -> integer -> list bitU*) +(*val rotl : list bitU -> integer -> list bitU*) +(*val rotr : list bitU -> integer -> list bitU*) +definition shiftl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " shiftl = ( + shiftl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " shiftr = ( + shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition arith_shiftr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " arith_shiftr = ( + arith_shiftr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition rotl :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " rotl = ( + rotl_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition rotr :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " rotr = ( + rotr_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val mod_vec : list bitU -> list bitU -> list bitU*) +(*val mod_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val mod_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val mod_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition mod_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " mod_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where + " mod_vec_maybe l r = ( mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition mod_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec l r))" + + +(*val quot_vec : list bitU -> list bitU -> list bitU*) +(*val quot_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quot_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quot_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition quot_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " quot_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where + " quot_vec_maybe l r = ( quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quot_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec l r))" + + +(*val quots_vec : list bitU -> list bitU -> list bitU*) +(*val quots_vec_maybe : list bitU -> list bitU -> maybe (list bitU)*) +(*val quots_vec_fail : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +(*val quots_vec_oracle : forall 'rv 'e. list bitU -> list bitU -> monad 'rv (list bitU) 'e*) +definition quots_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " quots_vec l r = ( case_option (repeat [BU] (int (List.length l))) id (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quots_vec_maybe :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>((bitU)list)option " where + " quots_vec_maybe l r = ( quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quots_vec_fail :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quots_vec_oracle :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quots_vec_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quots_vec l r))" + + +(*val mod_vec_int : list bitU -> integer -> list bitU*) +(*val mod_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val mod_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +definition mod_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " mod_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where + " mod_vec_int_maybe l r = ( mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition mod_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition mod_vec_int_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " mod_vec_int_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (mod_vec_int l r))" + + +(*val quot_vec_int : list bitU -> integer -> list bitU*) +(*val quot_vec_int_maybe : list bitU -> integer -> maybe (list bitU)*) +(*val quot_vec_int_fail : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'e. list bitU -> integer -> monad 'rv (list bitU) 'e*) +definition quot_vec_int :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " quot_vec_int l r = ( case_option (repeat [BU] (int (List.length l))) id (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_int_maybe :: "(bitU)list \<Rightarrow> int \<Rightarrow>((bitU)list)option " where + " quot_vec_int_maybe l r = ( quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r )" + +definition quot_vec_int_fail :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) l r))" + +definition quot_vec_int_oracle :: "(bitU)list \<Rightarrow> int \<Rightarrow>('rv,((bitU)list),'e)monad " where + " quot_vec_int_oracle l r = ( of_bits_oracle + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) (quot_vec_int l r))" + + +(*val replicate_bits : list bitU -> integer -> list bitU*) +definition replicate_bits :: "(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list " where + " replicate_bits = ( + replicate_bits_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val duplicate : bitU -> integer -> list bitU*) +definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>(bitU)list " where + " duplicate = ( + duplicate_bit_bv instance_Sail_values_BitU_Sail_values_bitU_dict )" + +definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>((bitU)list)option " where + " duplicate_maybe b n = ( Some (duplicate b n))" + +definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where + " duplicate_fail b n = ( return (duplicate b n))" + +definition duplicate_oracle :: " bitU \<Rightarrow> int \<Rightarrow>('b,((bitU)list),'a)monad " where + " duplicate_oracle b n = ( + bool_of_bitU_oracle b \<bind> (\<lambda> b . + return (duplicate (bitU_of_bool b) n)))" + + +(*val reverse_endianness : list bitU -> list bitU*) +definition reverse_endianness :: "(bitU)list \<Rightarrow>(bitU)list " where + " reverse_endianness v = ( reverse_endianness_list v )" + + +(*val get_slice_int : integer -> integer -> integer -> list bitU*) +definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " get_slice_int = ( + get_slice_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val set_slice_int : integer -> integer -> integer -> list bitU -> integer*) +definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int " where + " set_slice_int = ( + set_slice_int_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + + +(*val slice : list bitU -> integer -> integer -> list bitU*) +definition slice :: "(bitU)list \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " slice v lo len = ( + subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )" + + +(*val set_slice : integer -> integer -> list bitU -> integer -> list bitU -> list bitU*) +definition set_slice :: " int \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow> int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = ( + update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )" + + +(*val eq_vec : list bitU -> list bitU -> bool*) +(*val neq_vec : list bitU -> list bitU -> bool*) +definition eq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where + " eq_vec = ( + eq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +definition neq_vec :: "(bitU)list \<Rightarrow>(bitU)list \<Rightarrow> bool " where + " neq_vec = ( + neq_bv + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) )" + +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy new file mode 100644 index 00000000..edaec4e3 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_mwords.thy @@ -0,0 +1,638 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail_operators_mwords.lem.\<close> + +theory "Sail_operators_mwords" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + "Sail_values" + "Sail_operators" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_values*) +(*open import Sail_operators*) +(*open import Prompt_monad*) +(*open import Prompt*) +definition uint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where + " uint_maybe v = ( Some (Word.uint v))" + +definition uint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " uint_fail v = ( return (Word.uint v))" + +definition uint_oracle :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " uint_oracle v = ( return (Word.uint v))" + +definition sint_maybe :: "('a::len)Word.word \<Rightarrow>(int)option " where + " sint_maybe v = ( Some (Word.sint v))" + +definition sint_fail :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " sint_fail v = ( return (Word.sint v))" + +definition sint_oracle :: "('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " sint_oracle v = ( return (Word.sint v))" + + +(*val vec_of_bits_maybe : forall 'a. Size 'a => list bitU -> maybe (mword 'a)*) +(*val vec_of_bits_fail : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_oracle : forall 'rv 'a 'e. Size 'a => list bitU -> monad 'rv (mword 'a) 'e*) +(*val vec_of_bits_failwith : forall 'a. Size 'a => list bitU -> mword 'a*) +(*val vec_of_bits : forall 'a. Size 'a => list bitU -> mword 'a*) +definition vec_of_bits_maybe :: "(bitU)list \<Rightarrow>(('a::len)Word.word)option " where + " vec_of_bits_maybe bits = ( map_option Word.of_bl (just_list (List.map bool_of_bitU bits)))" + +definition vec_of_bits_fail :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " vec_of_bits_fail bits = ( of_bits_fail + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits_oracle :: "(bitU)list \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " vec_of_bits_oracle bits = ( of_bits_oracle + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits_failwith :: "(bitU)list \<Rightarrow>('a::len)Word.word " where + " vec_of_bits_failwith bits = ( of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + +definition vec_of_bits :: "(bitU)list \<Rightarrow>('a::len)Word.word " where + " vec_of_bits bits = ( of_bits_failwith + instance_Sail_values_Bitvector_Machine_word_mword_dict bits )" + + +(*val access_vec_inc : forall 'a. Size 'a => mword 'a -> integer -> bitU*) +definition access_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where + " access_vec_inc = ( + access_bv_inc instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val access_vec_dec : forall 'a. Size 'a => mword 'a -> integer -> bitU*) +definition access_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where + " access_vec_dec = ( + access_bv_dec instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +definition update_vec_dec_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " update_vec_dec_maybe w i b = ( update_mword_dec w i b )" + +definition update_vec_dec_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_dec_fail w i b = ( + bool_of_bitU_fail b \<bind> (\<lambda> b . + return (update_mword_bool_dec w i b)))" + +definition update_vec_dec_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_dec_oracle w i b = ( + bool_of_bitU_oracle b \<bind> (\<lambda> b . + return (update_mword_bool_dec w i b)))" + +definition update_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " update_vec_dec w i b = ( maybe_failwith (update_vec_dec_maybe w i b))" + + +definition update_vec_inc_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " update_vec_inc_maybe w i b = ( update_mword_inc w i b )" + +definition update_vec_inc_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_inc_fail w i b = ( + bool_of_bitU_fail b \<bind> (\<lambda> b . + return (update_mword_bool_inc w i b)))" + +definition update_vec_inc_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " update_vec_inc_oracle w i b = ( + bool_of_bitU_oracle b \<bind> (\<lambda> b . + return (update_mword_bool_inc w i b)))" + +definition update_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " update_vec_inc w i b = ( maybe_failwith (update_vec_inc_maybe w i b))" + + +(*val subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition subrange_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " subrange_vec_dec w i j = ( Word.slice (nat_of_int j) w )" + + +(*val subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition subrange_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " subrange_vec_inc w i j = ( subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j))" + + +(*val update_subrange_vec_dec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_subrange_vec_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " update_subrange_vec_dec w i j w' = ( Lem.word_update w (nat_of_int j) (nat_of_int i) w' )" + + +(*val update_subrange_vec_inc : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_subrange_vec_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " update_subrange_vec_inc w i j w' = ( update_subrange_vec_dec w ((int (size w) -( 1 :: int)) - i) ((int (size w) -( 1 :: int)) - j) w' )" + + +(*val extz_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition extz_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " extz_vec _ w = ( Word.ucast w )" + + +(*val exts_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition exts_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " exts_vec _ w = ( Word.scast w )" + + +(*val zero_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition zero_extend :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " zero_extend w _ = ( Word.ucast w )" + + +(*val sign_extend : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition sign_extend :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " sign_extend w _ = ( Word.scast w )" + + +(*val zeros : forall 'a. Size 'a => integer -> mword 'a*) +definition zeros :: " int \<Rightarrow>('a::len)Word.word " where + " zeros _ = ( Word.word_of_int (int(( 0 :: nat))))" + + +(*val vector_truncate : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition vector_truncate :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " vector_truncate w _ = ( Word.ucast w )" + + +(*val concat_vec : forall 'a 'b 'c. Size 'a, Size 'b, Size 'c => mword 'a -> mword 'b -> mword 'c*) +definition concat_vec :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('c::len)Word.word " where + " concat_vec = ( Word.word_cat )" + + +(*val cons_vec_bool : forall 'a 'b 'c. Size 'a, Size 'b => bool -> mword 'a -> mword 'b*) +definition cons_vec_bool :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " cons_vec_bool b w = ( Word.of_bl (b # Word.to_bl w))" + +definition cons_vec_maybe :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>(('b::len)Word.word)option " where + " cons_vec_maybe b w = ( map_option (\<lambda> b . cons_vec_bool b w) (bool_of_bitU b))" + +definition cons_vec_fail :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where + " cons_vec_fail b w = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cons_vec_bool b w)))" + +definition cons_vec_oracle :: " bitU \<Rightarrow>('c::len)Word.word \<Rightarrow>('e,(('b::len)Word.word),'d)monad " where + " cons_vec_oracle b w = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (cons_vec_bool b w)))" + +definition cons_vec :: " bitU \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " cons_vec b w = ( maybe_failwith (cons_vec_maybe b w))" + + +(*val vec_of_bool : forall 'a. Size 'a => integer -> bool -> mword 'a*) +definition vec_of_bool :: " int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " vec_of_bool _ b = ( Word.of_bl [b])" + +definition vec_of_bit_maybe :: " int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " vec_of_bit_maybe len b = ( map_option (vec_of_bool len) (bool_of_bitU b))" + +definition vec_of_bit_fail :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " vec_of_bit_fail len b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (vec_of_bool len b)))" + +definition vec_of_bit_oracle :: " int \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " vec_of_bit_oracle len b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (vec_of_bool len b)))" + +definition vec_of_bit :: " int \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " vec_of_bit len b = ( maybe_failwith (vec_of_bit_maybe len b))" + + +(*val cast_bool_vec : bool -> mword ty1*) +definition cast_bool_vec :: " bool \<Rightarrow>(1)Word.word " where + " cast_bool_vec b = ( vec_of_bool(( 1 :: int)) b )" + +definition cast_unit_vec_maybe :: " bitU \<Rightarrow>(('a::len)Word.word)option " where + " cast_unit_vec_maybe b = ( vec_of_bit_maybe(( 1 :: int)) b )" + +definition cast_unit_vec_fail :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where + " cast_unit_vec_fail b = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (cast_bool_vec b)))" + +definition cast_unit_vec_oracle :: " bitU \<Rightarrow>('b,((1)Word.word),'a)monad " where + " cast_unit_vec_oracle b = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (cast_bool_vec b)))" + +definition cast_unit_vec :: " bitU \<Rightarrow>('a::len)Word.word " where + " cast_unit_vec b = ( maybe_failwith (cast_unit_vec_maybe b))" + + +(*val msb : forall 'a. Size 'a => mword 'a -> bitU*) +definition msb :: "('a::len)Word.word \<Rightarrow> bitU " where + " msb = ( + most_significant instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val int_of_vec : forall 'a. Size 'a => bool -> mword 'a -> integer*) +definition int_of_vec :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where + " int_of_vec sign w = ( + if sign + then Word.sint w + else Word.uint w )" + +definition int_of_vec_maybe :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>(int)option " where + " int_of_vec_maybe sign w = ( Some (int_of_vec sign w))" + +definition int_of_vec_fail :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow>('c,(int),'b)monad " where + " int_of_vec_fail sign w = ( return (int_of_vec sign w))" + + +(*val string_of_vec : forall 'a. Size 'a => mword 'a -> string*) +definition string_of_vec :: "('a::len)Word.word \<Rightarrow> string " where + " string_of_vec = ( + string_of_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val and_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val or_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val xor_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val not_vec : forall 'a. Size 'a => mword 'a -> mword 'a*) +definition and_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " and_vec = ( Bits.bitAND )" + +definition or_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " or_vec = ( Bits.bitOR )" + +definition xor_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " xor_vec = ( Bits.bitXOR )" + +definition not_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " not_vec = ( Bits.bitNOT )" + + +(*val add_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val adds_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val sub_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val subs_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mult_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) +(*val mults_vec : forall 'a 'b. Size 'a, Size 'b => mword 'a -> mword 'a -> mword 'b*) +definition add_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " add_vec l r = ( Word.word_of_int ((int_of_mword False l) + (int_of_mword False r)))" + +definition adds_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " adds_vec l r = ( Word.word_of_int ((int_of_mword True l) + (int_of_mword True r)))" + +definition sub_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " sub_vec l r = ( Word.word_of_int ((int_of_mword False l) - (int_of_mword False r)))" + +definition subs_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " subs_vec l r = ( Word.word_of_int ((int_of_mword True l) - (int_of_mword True r)))" + +definition mult_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " mult_vec l r = ( Word.word_of_int ((int_of_mword False (Word.ucast l :: ( 'b::len)Word.word)) * (int_of_mword False (Word.ucast r :: ( 'b::len)Word.word))))" + +definition mults_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " mults_vec l r = ( Word.word_of_int ((int_of_mword True (Word.scast l :: ( 'b::len)Word.word)) * (int_of_mword True (Word.scast r :: ( 'b::len)Word.word))))" + + +(*val add_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val adds_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val sub_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val subs_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mult_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +(*val mults_vec_int : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition add_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " add_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition adds_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " adds_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition sub_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " sub_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition subs_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " subs_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition mult_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " mult_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False (Word.ucast l :: ( 'b::len)Word.word) r )" + +definition mults_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " mults_vec_int l r = ( arith_op_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True (Word.scast l :: ( 'b::len)Word.word) r )" + + +(*val add_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val adds_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val sub_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val subs_int_vec : forall 'a. Size 'a => integer -> mword 'a -> mword 'a*) +(*val mult_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +(*val mults_int_vec : forall 'a 'b. Size 'a, Size 'b => integer -> mword 'a -> mword 'b*) +definition add_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " add_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition adds_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " adds_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition sub_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " sub_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition subs_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " subs_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition mult_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " mult_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) False l (Word.ucast r :: ( 'b::len)Word.word))" + +definition mults_int_vec :: " int \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word " where + " mults_int_vec l r = ( arith_op_int_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict (op*) True l (Word.scast r :: ( 'b::len)Word.word))" + + +(*val add_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val adds_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val sub_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) +(*val subs_vec_bool : forall 'a. Size 'a => mword 'a -> bool -> mword 'a*) + +definition add_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " add_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) False l r )" + +definition add_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " add_vec_bit_maybe l r = ( map_option (add_vec_bool l) (bool_of_bitU r))" + +definition add_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " add_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (add_vec_bool l r)))" + +definition add_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " add_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (add_vec_bool l r)))" + +definition add_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " add_vec_bit l r = ( maybe_failwith (add_vec_bit_maybe l r))" + + +definition adds_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " adds_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op+) True l r )" + +definition adds_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " adds_vec_bit_maybe l r = ( map_option (adds_vec_bool l) (bool_of_bitU r))" + +definition adds_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " adds_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (adds_vec_bool l r)))" + +definition adds_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " adds_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (adds_vec_bool l r)))" + +definition adds_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " adds_vec_bit l r = ( maybe_failwith (adds_vec_bit_maybe l r))" + + +definition sub_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " sub_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) False l r )" + +definition sub_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " sub_vec_bit_maybe l r = ( map_option (sub_vec_bool l) (bool_of_bitU r))" + +definition sub_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " sub_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (sub_vec_bool l r)))" + +definition sub_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " sub_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (sub_vec_bool l r)))" + +definition sub_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " sub_vec_bit l r = ( maybe_failwith (sub_vec_bit_maybe l r))" + + +definition subs_vec_bool :: "('a::len)Word.word \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " subs_vec_bool l r = ( arith_op_bv_bool + instance_Sail_values_Bitvector_Machine_word_mword_dict (op-) True l r )" + +definition subs_vec_bit_maybe :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " subs_vec_bit_maybe l r = ( map_option (subs_vec_bool l) (bool_of_bitU r))" + +definition subs_vec_bit_fail :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " subs_vec_bit_fail l r = ( bool_of_bitU_fail r \<bind> (\<lambda> r . return (subs_vec_bool l r)))" + +definition subs_vec_bit_oracle :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " subs_vec_bit_oracle l r = ( bool_of_bitU_oracle r \<bind> (\<lambda> r . return (subs_vec_bool l r)))" + +definition subs_vec_bit :: "('a::len)Word.word \<Rightarrow> bitU \<Rightarrow>('a::len)Word.word " where + " subs_vec_bit l r = ( maybe_failwith (subs_vec_bit_maybe l r))" + + +(* TODO +val maybe_mword_of_bits_overflow : forall 'a. Size 'a => (list bitU * bitU * bitU) -> maybe (mword 'a * bitU * bitU) +let maybe_mword_of_bits_overflow (bits, overflow, carry) = + Maybe.map (fun w -> (w, overflow, carry)) (of_bits bits) + +val add_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val adds_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val sub_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val subs_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mult_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +val mults_overflow_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a * bitU * bitU) +let add_overflow_vec l r = maybe_mword_of_bits_overflow (add_overflow_bv l r) +let adds_overflow_vec l r = maybe_mword_of_bits_overflow (adds_overflow_bv l r) +let sub_overflow_vec l r = maybe_mword_of_bits_overflow (sub_overflow_bv l r) +let subs_overflow_vec l r = maybe_mword_of_bits_overflow (subs_overflow_bv l r) +let mult_overflow_vec l r = maybe_mword_of_bits_overflow (mult_overflow_bv l r) +let mults_overflow_vec l r = maybe_mword_of_bits_overflow (mults_overflow_bv l r) + +val add_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val add_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +val sub_overflow_vec_bit_signed : forall 'a. Size 'a => mword 'a -> bitU -> (mword 'a * bitU * bitU) +let add_overflow_vec_bit = add_overflow_bv_bit +let add_overflow_vec_bit_signed = add_overflow_bv_bit_signed +let sub_overflow_vec_bit = sub_overflow_bv_bit +let sub_overflow_vec_bit_signed = sub_overflow_bv_bit_signed*) + +(*val shiftl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val arith_shiftr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotl : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val rotr : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +definition shiftl :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " shiftl = ( shiftl_mword )" + +definition shiftr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " shiftr = ( shiftr_mword )" + +definition arith_shiftr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " arith_shiftr = ( arith_shiftr_mword )" + +definition rotl :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " rotl = ( rotl_mword )" + +definition rotr :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " rotr = ( rotr_mword )" + + +(*val mod_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val mod_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val mod_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition mod_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " mod_vec l r = ( mod_mword l r )" + +definition mod_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where + " mod_vec_maybe l r = ( mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition mod_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_fail l r = ( maybe_fail (''mod_vec'') (mod_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition mod_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_oracle l r = ( + (case (mod_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quot_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quot_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quot_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition quot_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " quot_vec l r = ( quot_mword l r )" + +definition quot_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where + " quot_vec_maybe l r = ( quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quot_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_fail l r = ( maybe_fail (''quot_vec'') (quot_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quot_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_oracle l r = ( + (case (quot_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quots_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> mword 'a*) +(*val quots_vec_maybe : forall 'a. Size 'a => mword 'a -> mword 'a -> maybe (mword 'a)*) +(*val quots_vec_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +(*val quots_vec_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> mword 'a -> monad 'rv (mword 'a) 'e*) +definition quots_vec :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " quots_vec l r = ( quots_mword l r )" + +definition quots_vec_maybe :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>(('a::len)Word.word)option " where + " quots_vec_maybe l r = ( quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quots_vec_fail :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quots_vec_fail l r = ( maybe_fail (''quots_vec'') (quots_bv + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quots_vec_oracle :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quots_vec_oracle l r = ( + (case (quots_bv instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val mod_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val mod_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val mod_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val mod_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +definition mod_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " mod_vec_int l r = ( mod_mword_int l r )" + +definition mod_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where + " mod_vec_int_maybe l r = ( mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition mod_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_int_fail l r = ( maybe_fail (''mod_vec_int'') (mod_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition mod_vec_int_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " mod_vec_int_oracle l r = ( + (case (mod_bv_int instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val quot_vec_int : forall 'a. Size 'a => mword 'a -> integer -> mword 'a*) +(*val quot_vec_int_maybe : forall 'a. Size 'a => mword 'a -> integer -> maybe (mword 'a)*) +(*val quot_vec_int_fail : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +(*val quot_vec_int_oracle : forall 'rv 'a 'e. Size 'a => mword 'a -> integer -> monad 'rv (mword 'a) 'e*) +definition quot_vec_int :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " quot_vec_int l r = ( quot_mword_int l r )" + +definition quot_vec_int_maybe :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where + " quot_vec_int_maybe l r = ( quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r )" + +definition quot_vec_int_fail :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_int_fail l r = ( maybe_fail (''quot_vec_int'') (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r))" + +definition quot_vec_int_oracle :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(('a::len)Word.word),'e)monad " where + " quot_vec_int_oracle l r = ( + (case (quot_bv_int + instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict l r) of + Some w => return w + | None => mword_oracle () + ))" + + +(*val replicate_bits : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> mword 'b*) +definition replicate_bits :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " replicate_bits v count1 = ( Word.of_bl (repeat (Word.to_bl v) count1))" + + +(*val duplicate_bool : forall 'a. Size 'a => bool -> integer -> mword 'a*) +definition duplicate_bool :: " bool \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " duplicate_bool b n = ( Word.of_bl (repeat [b] n))" + +definition duplicate_maybe :: " bitU \<Rightarrow> int \<Rightarrow>(('a::len)Word.word)option " where + " duplicate_maybe b n = ( map_option (\<lambda> b . duplicate_bool b n) (bool_of_bitU b))" + +definition duplicate_fail :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " duplicate_fail b n = ( bool_of_bitU_fail b \<bind> (\<lambda> b . return (duplicate_bool b n)))" + +definition duplicate_oracle :: " bitU \<Rightarrow> int \<Rightarrow>('c,(('a::len)Word.word),'b)monad " where + " duplicate_oracle b n = ( bool_of_bitU_oracle b \<bind> (\<lambda> b . return (duplicate_bool b n)))" + +definition duplicate :: " bitU \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " duplicate b n = ( maybe_failwith (duplicate_maybe b n))" + + +(*val reverse_endianness : forall 'a. Size 'a => mword 'a -> mword 'a*) +definition reverse_endianness :: "('a::len)Word.word \<Rightarrow>('a::len)Word.word " where + " reverse_endianness v = ( Word.of_bl (reverse_endianness_list (Word.to_bl v)))" + + +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a*) +definition get_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " get_slice_int = ( + get_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val set_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> mword 'a -> integer*) +definition set_slice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where + " set_slice_int = ( + set_slice_int_bv instance_Sail_values_Bitvector_Machine_word_mword_dict )" + + +(*val slice : forall 'a 'b. Size 'a, Size 'b => mword 'a -> integer -> integer -> mword 'b*) +definition slice :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " slice v lo len = ( + subrange_vec_dec v ((lo + len) -( 1 :: int)) lo )" + + +(*val set_slice : forall 'a 'b. Size 'a, Size 'b => integer -> integer -> mword 'a -> integer -> mword 'b -> mword 'a*) +definition set_slice :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " set_slice (out_len::ii) (slice_len::ii) out (n::ii) v = ( + update_subrange_vec_dec out ((n + slice_len) -( 1 :: int)) n v )" + + +(*val eq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) +(*val neq_vec : forall 'a. Size 'a => mword 'a -> mword 'a -> bool*) +end diff --git a/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy new file mode 100644 index 00000000..22c35e1f --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_operators_mwords_lemmas.thy @@ -0,0 +1,112 @@ +theory "Sail_operators_mwords_lemmas" + imports Sail_operators_mwords +begin + +lemmas uint_simps[simp] = uint_maybe_def uint_fail_def uint_oracle_def +lemmas sint_simps[simp] = sint_maybe_def sint_fail_def sint_oracle_def + +lemma bools_of_bits_oracle_just_list[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "bools_of_bits_oracle bus = return bs" +proof - + have f: "foreachM bus bools (\<lambda>b bools. bool_of_bitU_oracle b \<bind> (\<lambda>b. return (bools @ [b]))) = return (bools @ bs)" + if "just_list (map bool_of_bitU bus) = Some bs" for bus bs bools + proof (use that in \<open>induction bus arbitrary: bs bools\<close>) + case (Cons bu bus bs) + obtain b bs' where bs: "bs = b # bs'" and bu: "bool_of_bitU bu = Some b" + using Cons.prems by (cases bu) (auto split: option.splits) + then show ?case + using Cons.prems Cons.IH[where bs = bs' and bools = "bools @ [b]"] + by (cases bu) (auto simp: bool_of_bitU_oracle_def split: option.splits) + qed auto + then show ?thesis using f[OF assms, of "[]"] unfolding bools_of_bits_oracle_def + by auto +qed + +lemma of_bits_mword_return_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "of_bits_oracle BC_mword bus = return (of_bl bs)" + and "of_bits_fail BC_mword bus = return (of_bl bs)" + by (auto simp: of_bits_oracle_def of_bits_fail_def maybe_fail_def assms BC_mword_defs) + +lemma vec_of_bits_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "vec_of_bits_maybe bus = Some (of_bl bs)" + and "vec_of_bits_fail bus = return (of_bl bs)" + and "vec_of_bits_oracle bus = return (of_bl bs)" + and "vec_of_bits_failwith bus = of_bl bs" + and "vec_of_bits bus = of_bl bs" + unfolding vec_of_bits_maybe_def vec_of_bits_fail_def vec_of_bits_oracle_def + vec_of_bits_failwith_def vec_of_bits_def + by (auto simp: assms) + +lemmas access_vec_dec_test_bit[simp] = access_bv_dec_mword[folded access_vec_dec_def] + +lemma access_vec_inc_test_bit[simp]: + fixes w :: "('a::len) word" + assumes "n \<ge> 0" and "nat n < LENGTH('a)" + shows "access_vec_inc w n = bitU_of_bool (w !! (LENGTH('a) - 1 - nat n))" + using assms + by (auto simp: access_vec_inc_def access_bv_inc_def access_list_def BC_mword_defs rev_nth test_bit_bl) + +lemma bool_of_bitU_monadic_simps[simp]: + "bool_of_bitU_fail B0 = return False" + "bool_of_bitU_fail B1 = return True" + "bool_of_bitU_fail BU = Fail ''bool_of_bitU''" + "bool_of_bitU_oracle B0 = return False" + "bool_of_bitU_oracle B1 = return True" + "bool_of_bitU_oracle BU = undefined_bool ()" + unfolding bool_of_bitU_fail_def bool_of_bitU_oracle_def + by auto + +lemma update_vec_dec_simps[simp]: + "update_vec_dec_maybe w i B0 = Some (set_bit w (nat i) False)" + "update_vec_dec_maybe w i B1 = Some (set_bit w (nat i) True)" + "update_vec_dec_maybe w i BU = None" + "update_vec_dec_fail w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_fail w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_fail w i BU = Fail ''bool_of_bitU''" + "update_vec_dec_oracle w i B0 = return (set_bit w (nat i) False)" + "update_vec_dec_oracle w i B1 = return (set_bit w (nat i) True)" + "update_vec_dec_oracle w i BU = undefined_bool () \<bind> (\<lambda>b. return (set_bit w (nat i) b))" + "update_vec_dec w i B0 = set_bit w (nat i) False" + "update_vec_dec w i B1 = set_bit w (nat i) True" + unfolding update_vec_dec_maybe_def update_vec_dec_fail_def update_vec_dec_oracle_def update_vec_dec_def + by (auto simp: update_mword_dec_def update_mword_bool_dec_def maybe_failwith_def) + +lemma len_of_minus_One_minus_nonneg_lt_len_of[simp]: + "n \<ge> 0 \<Longrightarrow> nat (int LENGTH('a::len) - 1 - n) < LENGTH('a)" + by (metis diff_mono diff_zero len_gt_0 nat_eq_iff2 nat_less_iff order_refl zle_diff1_eq) + +declare extz_vec_def[simp] +declare exts_vec_def[simp] +declare concat_vec_def[simp] + +lemma msb_Bits_msb[simp]: + "msb w = bitU_of_bool (Bits.msb w)" + by (auto simp: msb_def most_significant_def BC_mword_defs word_msb_alt split: list.splits) + +declare and_vec_def[simp] +declare or_vec_def[simp] +declare xor_vec_def[simp] +declare not_vec_def[simp] + +lemma arith_vec_simps[simp]: + "add_vec l r = l + r" + "sub_vec l r = l - r" + "mult_vec l r = (ucast l) * (ucast r)" + unfolding add_vec_def sub_vec_def mult_vec_def + by (auto simp: int_of_mword_def word_add_def word_sub_wi word_mult_def) + +declare adds_vec_def[simp] +declare subs_vec_def[simp] +declare mults_vec_def[simp] + +lemma arith_vec_int_simps[simp]: + "add_vec_int l r = l + (word_of_int r)" + "sub_vec_int l r = l - (word_of_int r)" + "mult_vec_int l r = (ucast l) * (word_of_int r)" + unfolding add_vec_int_def sub_vec_int_def mult_vec_int_def + by (auto simp: arith_op_bv_int_def BC_mword_defs word_add_def word_sub_wi word_mult_def) + +end diff --git a/snapshots/isabelle/lib/sail/Sail_values.thy b/snapshots/isabelle/lib/sail/Sail_values.thy new file mode 100644 index 00000000..7338ac40 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_values.thy @@ -0,0 +1,1215 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/sail_values.lem.\<close> + +theory "Sail_values" + +imports + Main + "Lem_pervasives_extra" + "Lem_machine_word" + +begin + +(*open import Pervasives_extra*) +(*open import Machine_word*) +(*open import Sail_impl_base*) + + +type_synonym ii =" int " +type_synonym nn =" nat " + +(*val nat_of_int : integer -> nat*) +definition nat_of_int :: " int \<Rightarrow> nat " where + " nat_of_int i = ( if i <( 0 :: int) then( 0 :: nat) else nat (abs ( i)))" + + +(*val pow : integer -> integer -> integer*) +definition pow :: " int \<Rightarrow> int \<Rightarrow> int " where + " pow m n = ( m ^ (nat_of_int n))" + + +definition pow2 :: " int \<Rightarrow> int " where + " pow2 n = ( pow(( 2 :: int)) n )" + + +(*val eq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*val neq : forall 'a. Eq 'a => 'a -> 'a -> bool*) + +(*let add_int l r = integerAdd l r +let add_signed l r = integerAdd l r +let sub_int l r = integerMinus l r +let mult_int l r = integerMult l r +let div_int l r = integerDiv l r +let div_nat l r = natDiv l r +let power_int_nat l r = integerPow l r +let power_int_int l r = integerPow l (nat_of_int r) +let negate_int i = integerNegate i +let min_int l r = integerMin l r +let max_int l r = integerMax l r + +let add_real l r = realAdd l r +let sub_real l r = realMinus l r +let mult_real l r = realMult l r +let div_real l r = realDiv l r +let negate_real r = realNegate r +let abs_real r = realAbs r +let power_real b e = realPowInteger b e*) + +(*val prerr_endline : string -> unit*) +definition prerr_endline :: " string \<Rightarrow> unit " where + " prerr_endline _ = ( () )" + + +(*val print_int : string -> integer -> unit*) +definition print_int :: " string \<Rightarrow> int \<Rightarrow> unit " where + " print_int msg i = ( prerr_endline (msg @ (stringFromInteger i)))" + + +(*val putchar : integer -> unit*) +definition putchar :: " int \<Rightarrow> unit " where + " putchar _ = ( () )" + + +(*val shr_int : ii -> ii -> ii*) +function (sequential,domintros) shr_int :: " int \<Rightarrow> int \<Rightarrow> int " where + " shr_int x s = ( if s >( 0 :: int) then shr_int (x div( 2 :: int)) (s -( 1 :: int)) else x )" +by pat_completeness auto + + +(*val shl_int : integer -> integer -> integer*) +function (sequential,domintros) shl_int :: " int \<Rightarrow> int \<Rightarrow> int " where + " shl_int i shift = ( if shift >( 0 :: int) then( 2 :: int) * shl_int i (shift -( 1 :: int)) else i )" +by pat_completeness auto + +definition take_list :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " take_list n xs = ( List.take (nat_of_int n) xs )" + +definition drop_list :: " int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " drop_list n xs = ( List.drop (nat_of_int n) xs )" + + +(*val repeat : forall 'a. list 'a -> integer -> list 'a*) +fun repeat :: " 'a list \<Rightarrow> int \<Rightarrow> 'a list " where + " repeat xs n = ( + if n \<le>( 0 :: int) then [] + else xs @ repeat xs (n-( 1 :: int)))" + + +definition duplicate_to_list :: " 'a \<Rightarrow> int \<Rightarrow> 'a list " where + " duplicate_to_list bit length1 = ( repeat [bit] length1 )" + + +fun replace :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where + " replace ([]) (n :: int) b' = ( [])" +|" replace (b # bs) (n :: int) b' = ( + if n =( 0 :: int) then b' # bs + else b # replace bs (n -( 1 :: int)) b' )" + + +definition upper :: " 'a \<Rightarrow> 'a " where + " upper n = ( n )" + + +(* Modulus operation corresponding to quot below -- result + has sign of dividend. *) +definition hardware_mod :: " int \<Rightarrow> int \<Rightarrow> int " where + " hardware_mod (a:: int) (b::int) = ( + (let m = ((abs a) mod (abs b)) in + if a <( 0 :: int) then - m else m))" + + +(* There are different possible answers for integer divide regarding +rounding behaviour on negative operands. Positive operands always +round down so derive the one we want (trucation towards zero) from +that *) +definition hardware_quot :: " int \<Rightarrow> int \<Rightarrow> int " where + " hardware_quot (a::int) (b::int) = ( + (let q = ((abs a) div (abs b)) in + if ((a<( 0 :: int)) \<longleftrightarrow> (b<( 0 :: int))) then + q (* same sign -- result positive *) + else + - q))" + (* different sign -- result negative *) + +definition max_64u :: " int " where + " max_64u = ( ((( 2 :: int))^(( 64 :: nat))) -( 1 :: int))" + +definition max_64 :: " int " where + " max_64 = ( ((( 2 :: int))^(( 63 :: nat))) -( 1 :: int))" + +definition min_64 :: " int " where + " min_64 = (( 0 :: int) - ((( 2 :: int))^(( 63 :: nat))))" + +definition max_32u :: " int " where + " max_32u = ( (( 4294967295 :: int) :: int))" + +definition max_32 :: " int " where + " max_32 = ( (( 2147483647 :: int) :: int))" + +definition min_32 :: " int " where + " min_32 = ( (( 0 :: int) -( 2147483648 :: int) :: int))" + +definition max_8 :: " int " where + " max_8 = ( (( 127 :: int) :: int))" + +definition min_8 :: " int " where + " min_8 = ( (( 0 :: int) -( 128 :: int) :: int))" + +definition max_5 :: " int " where + " max_5 = ( (( 31 :: int) :: int))" + +definition min_5 :: " int " where + " min_5 = ( (( 0 :: int) -( 32 :: int) :: int))" + + +(* just_list takes a list of maybes and returns Just xs if all elements have + a value, and Nothing if one of the elements is Nothing. *) +(*val just_list : forall 'a. list (maybe 'a) -> maybe (list 'a)*) +fun just_list :: "('a option)list \<Rightarrow>('a list)option " where + " just_list ([]) = ( Some [])" +|" just_list (x # xs) = ( + (case (x, just_list xs) of + (Some x, Some xs) => Some (x # xs) + | (_, _) => None + ))" + + +(*val maybe_failwith : forall 'a. maybe 'a -> 'a*) +definition maybe_failwith :: " 'a option \<Rightarrow> 'a " where + " maybe_failwith = ( \<lambda>x . + (case x of Some a => a | None => failwith (''maybe_failwith'') ) )" + + +(*** Bits *) +datatype bitU = B0 | B1 | BU + +definition showBitU :: " bitU \<Rightarrow> string " where + " showBitU = ( \<lambda>x . + (case x of B0 => (''O'') | B1 => (''I'') | BU => (''U'') ) )" + + +definition bitU_char :: " bitU \<Rightarrow> char " where + " bitU_char = ( \<lambda>x . + (case x of B0 => (CHR ''0'') | B1 => (CHR ''1'') | BU => (CHR ''?'') ) )" + + +definition instance_Show_Show_Sail_values_bitU_dict :: "(bitU)Show_class " where + " instance_Show_Show_Sail_values_bitU_dict = ((| + + show_method = showBitU |) )" + + +(*val compare_bitU : bitU -> bitU -> ordering*) +fun compare_bitU :: " bitU \<Rightarrow> bitU \<Rightarrow> ordering " where + " compare_bitU BU BU = ( EQ )" +|" compare_bitU B0 B0 = ( EQ )" +|" compare_bitU B1 B1 = ( EQ )" +|" compare_bitU BU _ = ( LT )" +|" compare_bitU _ BU = ( GT )" +|" compare_bitU B0 _ = ( LT )" +|" compare_bitU _ _ = ( GT )" + + +definition instance_Basic_classes_Ord_Sail_values_bitU_dict :: "(bitU)Ord_class " where + " instance_Basic_classes_Ord_Sail_values_bitU_dict = ((| + + compare_method = compare_bitU, + + isLess_method = (\<lambda> l r. (compare_bitU l r) = LT), + + isLessEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> GT), + + isGreater_method = (\<lambda> l r. (compare_bitU l r) = GT), + + isGreaterEqual_method = (\<lambda> l r. (compare_bitU l r) \<noteq> LT)|) )" + + +record 'a BitU_class= + + to_bitU_method ::" 'a \<Rightarrow> bitU " + + of_bitU_method ::" bitU \<Rightarrow> 'a " + + + +definition instance_Sail_values_BitU_Sail_values_bitU_dict :: "(bitU)BitU_class " where + " instance_Sail_values_BitU_Sail_values_bitU_dict = ((| + + to_bitU_method = (\<lambda> b. b), + + of_bitU_method = (\<lambda> b. b)|) )" + + +definition bool_of_bitU :: " bitU \<Rightarrow>(bool)option " where + " bool_of_bitU = ( \<lambda>x . + (case x of B0 => Some False | B1 => Some True | BU => None ) )" + + +definition bitU_of_bool :: " bool \<Rightarrow> bitU " where + " bitU_of_bool b = ( if b then B1 else B0 )" + + +(*instance (BitU bool) + let to_bitU = bitU_of_bool + let of_bitU = bool_of_bitU +end*) + +definition cast_bit_bool :: " bitU \<Rightarrow>(bool)option " where + " cast_bit_bool = ( bool_of_bitU )" + + +definition not_bit :: " bitU \<Rightarrow> bitU " where + " not_bit = ( \<lambda>x . + (case x of B1 => B0 | B0 => B1 | BU => BU ) )" + + +(*val is_one : integer -> bitU*) +definition is_one :: " int \<Rightarrow> bitU " where + " is_one i = ( + if i =( 1 :: int) then B1 else B0 )" + + +(*val and_bit : bitU -> bitU -> bitU*) +fun and_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where + " and_bit B0 _ = ( B0 )" +|" and_bit _ B0 = ( B0 )" +|" and_bit B1 B1 = ( B1 )" +|" and_bit _ _ = ( BU )" + + +(*val or_bit : bitU -> bitU -> bitU*) +fun or_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where + " or_bit B1 _ = ( B1 )" +|" or_bit _ B1 = ( B1 )" +|" or_bit B0 B0 = ( B0 )" +|" or_bit _ _ = ( BU )" + + +(*val xor_bit : bitU -> bitU -> bitU*) +fun xor_bit :: " bitU \<Rightarrow> bitU \<Rightarrow> bitU " where + " xor_bit B0 B0 = ( B0 )" +|" xor_bit B0 B1 = ( B1 )" +|" xor_bit B1 B0 = ( B1 )" +|" xor_bit B1 B1 = ( B0 )" +|" xor_bit _ _ = ( BU )" + + +(*val &. : bitU -> bitU -> bitU*) + +(*val |. : bitU -> bitU -> bitU*) + +(*val +. : bitU -> bitU -> bitU*) + + +(*** Bool lists ***) + +(*val bools_of_nat_aux : integer -> natural -> list bool -> list bool*) +fun bools_of_nat_aux :: " int \<Rightarrow> nat \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where + " bools_of_nat_aux len x acc1 = ( + if len \<le>( 0 :: int) then acc1 + else bools_of_nat_aux (len -( 1 :: int)) (x div( 2 :: nat)) ((if (x mod( 2 :: nat)) =( 1 :: nat) then True else False) # acc1))" + +definition bools_of_nat :: " int \<Rightarrow> nat \<Rightarrow>(bool)list " where + " bools_of_nat len n = ( bools_of_nat_aux len n [])" + (*List.reverse (bools_of_nat_aux n)*) + +(*val nat_of_bools_aux : natural -> list bool -> natural*) +fun nat_of_bools_aux :: " nat \<Rightarrow>(bool)list \<Rightarrow> nat " where + " nat_of_bools_aux acc1 ([]) = ( acc1 )" +|" nat_of_bools_aux acc1 (True # bs) = ( nat_of_bools_aux ((( 2 :: nat) * acc1) +( 1 :: nat)) bs )" +|" nat_of_bools_aux acc1 (False # bs) = ( nat_of_bools_aux (( 2 :: nat) * acc1) bs )" + +definition nat_of_bools :: "(bool)list \<Rightarrow> nat " where + " nat_of_bools bs = ( nat_of_bools_aux(( 0 :: nat)) bs )" + + +(*val unsigned_of_bools : list bool -> integer*) +definition unsigned_of_bools :: "(bool)list \<Rightarrow> int " where + " unsigned_of_bools bs = ( int (nat_of_bools bs))" + + +(*val signed_of_bools : list bool -> integer*) +definition signed_of_bools :: "(bool)list \<Rightarrow> int " where + " signed_of_bools bs = ( + (case bs of + True # _ =>( 0 :: int) - (( 1 :: int) + (unsigned_of_bools (List.map (\<lambda> x. \<not> x) bs))) + | False # _ => unsigned_of_bools bs + | [] =>( 0 :: int) (* Treat empty list as all zeros *) + ))" + + +(*val int_of_bools : bool -> list bool -> integer*) +definition int_of_bools :: " bool \<Rightarrow>(bool)list \<Rightarrow> int " where + " int_of_bools sign bs = ( if sign then signed_of_bools bs else unsigned_of_bools bs )" + + +(*val pad_list : forall 'a. 'a -> list 'a -> integer -> list 'a*) +fun pad_list :: " 'a \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a list " where + " pad_list x xs n = ( + if n \<le>( 0 :: int) then xs else pad_list x (x # xs) (n -( 1 :: int)))" + + +definition ext_list :: " 'a \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " ext_list pad len xs = ( + (let longer = (len - (int (List.length xs))) in + if longer <( 0 :: int) then List.drop (nat_of_int (abs (longer))) xs + else pad_list pad xs longer))" + + +definition extz_bools :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where + " extz_bools len bs = ( ext_list False len bs )" + +definition exts_bools :: " int \<Rightarrow>(bool)list \<Rightarrow>(bool)list " where + " exts_bools len bs = ( + (case bs of + True # _ => ext_list True len bs + | _ => ext_list False len bs + ))" + + +fun add_one_bool_ignore_overflow_aux :: "(bool)list \<Rightarrow>(bool)list " where + " add_one_bool_ignore_overflow_aux ([]) = ( [])" +|" add_one_bool_ignore_overflow_aux (False # bits) = ( True # bits )" +|" add_one_bool_ignore_overflow_aux (True # bits) = ( False # add_one_bool_ignore_overflow_aux bits )" + + +definition add_one_bool_ignore_overflow :: "(bool)list \<Rightarrow>(bool)list " where + " add_one_bool_ignore_overflow bits = ( + List.rev (add_one_bool_ignore_overflow_aux (List.rev bits)))" + + +(*let bool_list_of_int n = + let bs_abs = false :: bools_of_nat (naturalFromInteger (abs n)) in + if n >= (0 : integer) then bs_abs + else add_one_bool_ignore_overflow (List.map not bs_abs) +let bools_of_int len n = exts_bools len (bool_list_of_int n)*) +definition bools_of_int :: " int \<Rightarrow> int \<Rightarrow>(bool)list " where + " bools_of_int len n = ( + (let bs_abs = (bools_of_nat len (nat (abs (abs n)))) in + if n \<ge> (( 0 :: int) :: int) then bs_abs + else add_one_bool_ignore_overflow (List.map (\<lambda> x. \<not> x) bs_abs)))" + + +(*** Bit lists ***) + +(*val has_undefined_bits : list bitU -> bool*) +definition has_undefined_bits :: "(bitU)list \<Rightarrow> bool " where + " has_undefined_bits bs = ( ((\<exists> x \<in> (set bs). (\<lambda>x . + (case x of BU => True | _ => False )) x)))" + + +definition bits_of_nat :: " int \<Rightarrow> nat \<Rightarrow>(bitU)list " where + " bits_of_nat len n = ( List.map bitU_of_bool (bools_of_nat len n))" + + +definition nat_of_bits :: "(bitU)list \<Rightarrow>(nat)option " where + " nat_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (nat_of_bools bs) + | None => None + ))" + + +definition not_bits :: "(bitU)list \<Rightarrow>(bitU)list " where + " not_bits = ( List.map not_bit )" + + +(*val binop_list : forall 'a. ('a -> 'a -> 'a) -> list 'a -> list 'a -> list 'a*) +definition binop_list :: "('a \<Rightarrow> 'a \<Rightarrow> 'a)\<Rightarrow> 'a list \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " binop_list op1 xs ys = ( + List.foldr ( \<lambda>x . + (case x of (x, y) => \<lambda> acc1 . op1 x y # acc1 )) (List.zip xs ys) [])" + + +definition unsigned_of_bits :: "(bitU)list \<Rightarrow>(int)option " where + " unsigned_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (unsigned_of_bools bs) + | None => None + ))" + + +definition signed_of_bits :: "(bitU)list \<Rightarrow>(int)option " where + " signed_of_bits bits = ( + (case (just_list (List.map bool_of_bitU bits)) of + Some bs => Some (signed_of_bools bs) + | None => None + ))" + + +(*val int_of_bits : bool -> list bitU -> maybe integer*) +definition int_of_bits :: " bool \<Rightarrow>(bitU)list \<Rightarrow>(int)option " where + " int_of_bits sign bs = ( if sign then signed_of_bits bs else unsigned_of_bits bs )" + + +definition extz_bits :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " extz_bits len bits = ( ext_list B0 len bits )" + +definition exts_bits :: " int \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " exts_bits len bits = ( + (case bits of + BU # _ => ext_list BU len bits + | B1 # _ => ext_list B1 len bits + | _ => ext_list B0 len bits + ))" + + +fun add_one_bit_ignore_overflow_aux :: "(bitU)list \<Rightarrow>(bitU)list " where + " add_one_bit_ignore_overflow_aux ([]) = ( [])" +|" add_one_bit_ignore_overflow_aux (B0 # bits) = ( B1 # bits )" +|" add_one_bit_ignore_overflow_aux (B1 # bits) = ( B0 # add_one_bit_ignore_overflow_aux bits )" +|" add_one_bit_ignore_overflow_aux (BU # bits) = ( BU # List.map ( \<lambda>x . + (case x of _ => BU )) bits )" + + +definition add_one_bit_ignore_overflow :: "(bitU)list \<Rightarrow>(bitU)list " where + " add_one_bit_ignore_overflow bits = ( + List.rev (add_one_bit_ignore_overflow_aux (List.rev bits)))" + + +(*let bit_list_of_int n = List.map bitU_of_bool (bool_list_of_int n) +let bits_of_int len n = exts_bits len (bit_list_of_int n)*) +definition bits_of_int :: " int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " bits_of_int len n = ( List.map bitU_of_bool (bools_of_int len n))" + + +(*val arith_op_bits : + (integer -> integer -> integer) -> bool -> list bitU -> list bitU -> list bitU*) +definition arith_op_bits :: "(int \<Rightarrow> int \<Rightarrow> int)\<Rightarrow> bool \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list \<Rightarrow>(bitU)list " where + " arith_op_bits op1 sign l r = ( + (case (int_of_bits sign l, int_of_bits sign r) of + (Some li, Some ri) => bits_of_int (int (List.length l)) (op1 li ri) + | (_, _) => repeat [BU] (int (List.length l)) + ))" + + +definition char_of_nibble :: " bitU*bitU*bitU*bitU \<Rightarrow>(char)option " where + " char_of_nibble = ( \<lambda>x . + (case x of + (B0, B0, B0, B0) => Some (CHR ''0'') + | (B0, B0, B0, B1) => Some (CHR ''1'') + | (B0, B0, B1, B0) => Some (CHR ''2'') + | (B0, B0, B1, B1) => Some (CHR ''3'') + | (B0, B1, B0, B0) => Some (CHR ''4'') + | (B0, B1, B0, B1) => Some (CHR ''5'') + | (B0, B1, B1, B0) => Some (CHR ''6'') + | (B0, B1, B1, B1) => Some (CHR ''7'') + | (B1, B0, B0, B0) => Some (CHR ''8'') + | (B1, B0, B0, B1) => Some (CHR ''9'') + | (B1, B0, B1, B0) => Some (CHR ''A'') + | (B1, B0, B1, B1) => Some (CHR ''B'') + | (B1, B1, B0, B0) => Some (CHR ''C'') + | (B1, B1, B0, B1) => Some (CHR ''D'') + | (B1, B1, B1, B0) => Some (CHR ''E'') + | (B1, B1, B1, B1) => Some (CHR ''F'') + | _ => None + ) )" + + +fun hexstring_of_bits :: "(bitU)list \<Rightarrow>((char)list)option " where + " hexstring_of_bits (b1 # b2 # b3 # b4 # bs) = ( + (let n = (char_of_nibble (b1, b2, b3, b4)) in + (let s = (hexstring_of_bits bs) in + (case (n, s) of + (Some n, Some s) => Some (n # s) + | _ => None + ))))" +|" hexstring_of_bits ([]) = ( Some [])" +|" hexstring_of_bits _ = ( None )" + + +definition show_bitlist :: "(bitU)list \<Rightarrow> string " where + " show_bitlist bs = ( + (case hexstring_of_bits bs of + Some s => ((CHR ''0'') # ((CHR ''x'') # s)) + | None => ((CHR ''0'') # ((CHR ''b'') # List.map bitU_char bs)) + ))" + + +(*val subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a*) +definition subrange_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where + " subrange_list_inc xs i j = ( + (let (toJ,suffix0) = (split_at (nat_of_int (j +( 1 :: int))) xs) in + (let (prefix0,fromItoJ) = (split_at (nat_of_int i) toJ) in + fromItoJ)))" + + +(*val subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a*) +definition subrange_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where + " subrange_list_dec xs i j = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + subrange_list_inc xs (top1 - i) (top1 - j)))" + + +(*val subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a*) +definition subrange_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list " where + " subrange_list is_inc xs i j = ( if is_inc then subrange_list_inc xs i j else subrange_list_dec xs i j )" + + +(*val update_subrange_list_inc : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " update_subrange_list_inc xs i j xs' = ( + (let (toJ,suffix) = (split_at (nat_of_int (j +( 1 :: int))) xs) in + (let (prefix,fromItoJ0) = (split_at (nat_of_int i) toJ) in + (prefix @ xs') @ suffix)))" + + +(*val update_subrange_list_dec : forall 'a. list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " update_subrange_list_dec xs i j xs' = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + update_subrange_list_inc xs (top1 - i) (top1 - j) xs'))" + + +(*val update_subrange_list : forall 'a. bool -> list 'a -> integer -> integer -> list 'a -> list 'a*) +definition update_subrange_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a list \<Rightarrow> 'a list " where + " update_subrange_list is_inc xs i j xs' = ( + if is_inc then update_subrange_list_inc xs i j xs' else update_subrange_list_dec xs i j xs' )" + + +(*val access_list_inc : forall 'a. list 'a -> integer -> 'a*) +definition access_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> 'a " where + " access_list_inc xs n = ( List.nth xs (nat_of_int n))" + + +(*val access_list_dec : forall 'a. list 'a -> integer -> 'a*) +definition access_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> 'a " where + " access_list_dec xs n = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + access_list_inc xs (top1 - n)))" + + +(*val access_list : forall 'a. bool -> list 'a -> integer -> 'a*) +definition access_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a " where + " access_list is_inc xs n = ( + if is_inc then access_list_inc xs n else access_list_dec xs n )" + + +(*val update_list_inc : forall 'a. list 'a -> integer -> 'a -> list 'a*) +definition update_list_inc :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where + " update_list_inc xs n x = ( List.list_update xs (nat_of_int n) x )" + + +(*val update_list_dec : forall 'a. list 'a -> integer -> 'a -> list 'a*) +definition update_list_dec :: " 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where + " update_list_dec xs n x = ( + (let top1 = ((int (List.length xs)) -( 1 :: int)) in + update_list_inc xs (top1 - n) x))" + + +(*val update_list : forall 'a. bool -> list 'a -> integer -> 'a -> list 'a*) +definition update_list :: " bool \<Rightarrow> 'a list \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow> 'a list " where + " update_list is_inc xs n x = ( + if is_inc then update_list_inc xs n x else update_list_dec xs n x )" + + +definition extract_only_bit :: "(bitU)list \<Rightarrow> bitU " where + " extract_only_bit = ( \<lambda>x . + (case x of [] => BU | [e] => e | _ => BU ) )" + + +(*** Machine words *) + +(*val length_mword : forall 'a. mword 'a -> integer*) + +(*val slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " slice_mword_dec w i j = ( Word.slice (nat_of_int i) w )" + + +(*val slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " slice_mword_inc w i j = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + slice_mword_dec w (top1 - i) (top1 - j)))" + + +(*val slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b*) +definition slice_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word " where + " slice_mword is_inc w i j = ( if is_inc then slice_mword_inc w i j else slice_mword_dec w i j )" + + +(*val update_slice_mword_dec : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " update_slice_mword_dec w i j w' = ( Lem.word_update w (nat_of_int i) (nat_of_int j) w' )" + + +(*val update_slice_mword_inc : forall 'a 'b. mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " update_slice_mword_inc w i j w' = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + update_slice_mword_dec w (top1 - i) (top1 - j) w'))" + + +(*val update_slice_mword : forall 'a 'b. bool -> mword 'a -> integer -> integer -> mword 'b -> mword 'a*) +definition update_slice_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " update_slice_mword is_inc w i j w' = ( + if is_inc then update_slice_mword_inc w i j w' else update_slice_mword_dec w i j w' )" + + +(*val access_mword_dec : forall 'a. mword 'a -> integer -> bitU*) +definition access_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where + " access_mword_dec w n = ( bitU_of_bool (Bits.test_bit w (nat_of_int n)))" + + +(*val access_mword_inc : forall 'a. mword 'a -> integer -> bitU*) +definition access_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where + " access_mword_inc w n = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + access_mword_dec w (top1 - n)))" + + +(*val access_mword : forall 'a. bool -> mword 'a -> integer -> bitU*) +definition access_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU " where + " access_mword is_inc w n = ( + if is_inc then access_mword_inc w n else access_mword_dec w n )" + + +(*val update_mword_bool_dec : forall 'a. mword 'a -> integer -> bool -> mword 'a*) +definition update_mword_bool_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " update_mword_bool_dec w n b = ( Bits.set_bit w (nat_of_int n) b )" + +definition update_mword_dec :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " update_mword_dec w n b = ( map_option (update_mword_bool_dec w n) (bool_of_bitU b))" + + +(*val update_mword_bool_inc : forall 'a. mword 'a -> integer -> bool -> mword 'a*) +definition update_mword_bool_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>('a::len)Word.word " where + " update_mword_bool_inc w n b = ( + (let top1 = ((int (size w)) -( 1 :: int)) in + update_mword_bool_dec w (top1 - n) b))" + +definition update_mword_inc :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(('a::len)Word.word)option " where + " update_mword_inc w n b = ( map_option (update_mword_bool_inc w n) (bool_of_bitU b))" + + +(*val int_of_mword : forall 'a. bool -> mword 'a -> integer*) +definition int_of_mword :: " bool \<Rightarrow>('a::len)Word.word \<Rightarrow> int " where + " int_of_mword sign w = ( + if sign then Word.sint w else Word.uint w )" + + +(* Translating between a type level number (itself 'n) and an integer *) + +definition size_itself_int :: "('a::len)itself \<Rightarrow> int " where + " size_itself_int x = ( int (size_itself x))" + + +(* NB: the corresponding sail type is forall 'n. atom('n) -> itself('n), + the actual integer is ignored. *) + +(*val make_the_value : forall 'n. integer -> itself 'n*) +definition make_the_value :: " int \<Rightarrow>('n::len)itself " where + " make_the_value _ = ( TYPE(_) )" + + +(*** Bitvectors *) + +record 'a Bitvector_class= + + bits_of_method ::" 'a \<Rightarrow> bitU list " + + (* We allow of_bits to be partial, as not all bitvector representations + support undefined bits *) + of_bits_method ::" bitU list \<Rightarrow> 'a option " + + of_bools_method ::" bool list \<Rightarrow> 'a " + + length_method ::" 'a \<Rightarrow> int " + + (* of_int: the first parameter specifies the desired length of the bitvector *) + of_int_method ::" int \<Rightarrow> int \<Rightarrow> 'a " + + (* Conversion to integers is undefined if any bit is undefined *) + unsigned_method ::" 'a \<Rightarrow> int option " + + signed_method ::" 'a \<Rightarrow> int option " + + (* Lifting of integer operations to bitvectors: The boolean flag indicates + whether to treat the bitvectors as signed (true) or not (false). *) + arith_op_bv_method ::" (int \<Rightarrow> int \<Rightarrow> int) \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow> 'a \<Rightarrow> 'a " + + + +(*val of_bits_failwith : forall 'a. Bitvector 'a => list bitU -> 'a*) +definition of_bits_failwith :: " 'a Bitvector_class \<Rightarrow>(bitU)list \<Rightarrow> 'a " where + " of_bits_failwith dict_Sail_values_Bitvector_a bits = ( maybe_failwith ( + (of_bits_method dict_Sail_values_Bitvector_a) bits))" + + +definition int_of_bv :: " 'a Bitvector_class \<Rightarrow> bool \<Rightarrow> 'a \<Rightarrow>(int)option " where + " int_of_bv dict_Sail_values_Bitvector_a sign = ( if sign then + (signed_method dict_Sail_values_Bitvector_a) else (unsigned_method dict_Sail_values_Bitvector_a) )" + + +definition instance_Sail_values_Bitvector_list_dict :: " 'a BitU_class \<Rightarrow>('a list)Bitvector_class " where + " instance_Sail_values_Bitvector_list_dict dict_Sail_values_BitU_a = ((| + + bits_of_method = (\<lambda> v. List.map + (to_bitU_method dict_Sail_values_BitU_a) v), + + of_bits_method = (\<lambda> v. Some (List.map + (of_bitU_method dict_Sail_values_BitU_a) v)), + + of_bools_method = (\<lambda> v. List.map + (of_bitU_method dict_Sail_values_BitU_a) (List.map bitU_of_bool v)), + + length_method = (\<lambda> xs. int (List.length xs)), + + of_int_method = (\<lambda> len n. List.map + (of_bitU_method dict_Sail_values_BitU_a) (bits_of_int len n)), + + unsigned_method = (\<lambda> v. unsigned_of_bits (List.map + (to_bitU_method dict_Sail_values_BitU_a) v)), + + signed_method = (\<lambda> v. signed_of_bits (List.map + (to_bitU_method dict_Sail_values_BitU_a) v)), + + arith_op_bv_method = (\<lambda> op1 sign l r. List.map + (of_bitU_method dict_Sail_values_BitU_a) (arith_op_bits op1 sign (List.map + (to_bitU_method dict_Sail_values_BitU_a) l) (List.map (to_bitU_method dict_Sail_values_BitU_a) r)))|) )" + + +definition instance_Sail_values_Bitvector_Machine_word_mword_dict :: "(('a::len)Word.word)Bitvector_class " where + " instance_Sail_values_Bitvector_Machine_word_mword_dict = ((| + + bits_of_method = (\<lambda> v. List.map bitU_of_bool (Word.to_bl v)), + + of_bits_method = (\<lambda> v. map_option Word.of_bl (just_list (List.map bool_of_bitU v))), + + of_bools_method = (\<lambda> v. Word.of_bl v), + + length_method = (\<lambda> v. int (size v)), + + of_int_method = ( \<lambda>x . + (case x of _ => \<lambda> n . Word.word_of_int n )), + + unsigned_method = (\<lambda> v. Some (Word.uint v)), + + signed_method = (\<lambda> v. Some (Word.sint v)), + + arith_op_bv_method = (\<lambda> op1 sign l r. Word.word_of_int (op1 (int_of_mword sign l) (int_of_mword sign r)))|) )" + + +definition access_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where + " access_bv_inc dict_Sail_values_Bitvector_a v n = ( access_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + +definition access_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU " where + " access_bv_dec dict_Sail_values_Bitvector_a v n = ( access_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n )" + + +definition update_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " update_bv_inc dict_Sail_values_Bitvector_a v n b = ( update_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + +definition update_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> bitU \<Rightarrow>(bitU)list " where + " update_bv_dec dict_Sail_values_Bitvector_a v n b = ( update_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) n b )" + + +definition subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " subrange_bv_inc dict_Sail_values_Bitvector_a v i j = ( subrange_list True ( + (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + +definition subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(bitU)list " where + " subrange_bv_dec dict_Sail_values_Bitvector_a v i j = ( subrange_list False ( + (bits_of_method dict_Sail_values_Bitvector_a) v) i j )" + + +definition update_subrange_bv_inc :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " update_subrange_bv_inc dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list True ( + (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + +definition update_subrange_bv_dec :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> 'b \<Rightarrow> int \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " update_subrange_bv_dec dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b v i j v' = ( update_subrange_list False ( + (bits_of_method dict_Sail_values_Bitvector_b) v) i j ((bits_of_method dict_Sail_values_Bitvector_a) v'))" + + +(*val extz_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) +definition extz_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " extz_bv dict_Sail_values_Bitvector_a n v = ( extz_bits n ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*val exts_bv : forall 'a. Bitvector 'a => integer -> 'a -> list bitU*) +definition exts_bv :: " 'a Bitvector_class \<Rightarrow> int \<Rightarrow> 'a \<Rightarrow>(bitU)list " where + " exts_bv dict_Sail_values_Bitvector_a n v = ( exts_bits n ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*val string_of_bv : forall 'a. Bitvector 'a => 'a -> string*) +definition string_of_bv :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> string " where + " string_of_bv dict_Sail_values_Bitvector_a v = ( show_bitlist ( + (bits_of_method dict_Sail_values_Bitvector_a) v))" + + +(*** Bytes and addresses *) + +type_synonym memory_byte =" bitU list " + +(*val byte_chunks : forall 'a. list 'a -> maybe (list (list 'a))*) +fun byte_chunks :: " 'a list \<Rightarrow>(('a list)list)option " where + " byte_chunks ([]) = ( Some [])" +|" byte_chunks (a # b # c # d # e # f # g # h # rest) = ( + Option.bind (byte_chunks rest) (\<lambda> rest . Some ([a,b,c,d,e,f,g,h] # rest)))" +|" byte_chunks _ = ( None )" + + +(*val bytes_of_bits : forall 'a. Bitvector 'a => 'a -> maybe (list memory_byte)*) +definition bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where + " bytes_of_bits dict_Sail_values_Bitvector_a bs = ( byte_chunks ( + (bits_of_method dict_Sail_values_Bitvector_a) bs))" + + +(*val bits_of_bytes : list memory_byte -> list bitU*) +definition bits_of_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where + " bits_of_bytes bs = ( List.concat (List.map (\<lambda> v. List.map (\<lambda> b. b) v) bs))" + + +definition mem_bytes_of_bits :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>(((bitU)list)list)option " where + " mem_bytes_of_bits dict_Sail_values_Bitvector_a bs = ( map_option List.rev (bytes_of_bits + dict_Sail_values_Bitvector_a bs))" + +definition bits_of_mem_bytes :: "((bitU)list)list \<Rightarrow>(bitU)list " where + " bits_of_mem_bytes bs = ( bits_of_bytes (List.rev bs))" + + +(*val bitv_of_byte_lifteds : list Sail_impl_base.byte_lifted -> list bitU +let bitv_of_byte_lifteds v = + foldl (fun x (Byte_lifted y) -> x ++ (List.map bitU_of_bit_lifted y)) [] v + +val bitv_of_bytes : list Sail_impl_base.byte -> list bitU +let bitv_of_bytes v = + foldl (fun x (Byte y) -> x ++ (List.map bitU_of_bit y)) [] v + +val byte_lifteds_of_bitv : list bitU -> list byte_lifted +let byte_lifteds_of_bitv bits = + let bits = List.map bit_lifted_of_bitU bits in + byte_lifteds_of_bit_lifteds bits + +val bytes_of_bitv : list bitU -> list byte +let bytes_of_bitv bits = + let bits = List.map bit_of_bitU bits in + bytes_of_bits bits + +val bit_lifteds_of_bitUs : list bitU -> list bit_lifted +let bit_lifteds_of_bitUs bits = List.map bit_lifted_of_bitU bits + +val bit_lifteds_of_bitv : list bitU -> list bit_lifted +let bit_lifteds_of_bitv v = bit_lifteds_of_bitUs v + + +val address_lifted_of_bitv : list bitU -> address_lifted +let address_lifted_of_bitv v = + let byte_lifteds = byte_lifteds_of_bitv v in + let maybe_address_integer = + match (maybe_all (List.map byte_of_byte_lifted byte_lifteds)) with + | Just bs -> Just (integer_of_byte_list bs) + | _ -> Nothing + end in + Address_lifted byte_lifteds maybe_address_integer + +val bitv_of_address_lifted : address_lifted -> list bitU +let bitv_of_address_lifted (Address_lifted bs _) = bitv_of_byte_lifteds bs + +val address_of_bitv : list bitU -> address +let address_of_bitv v = + let bytes = bytes_of_bitv v in + address_of_byte_list bytes*) + +function (sequential,domintros) reverse_endianness_list :: " 'a list \<Rightarrow> 'a list " where + " reverse_endianness_list bits = ( + if List.length bits \<le>( 8 :: nat) then bits else + reverse_endianness_list (drop_list(( 8 :: int)) bits) @ take_list(( 8 :: int)) bits )" +by pat_completeness auto + + + +(*** Registers *) + +(*type register_field = string +type register_field_index = string * (integer * integer) (* name, start and end *) + +type register = + | Register of string * (* name *) + integer * (* length *) + integer * (* start index *) + bool * (* is increasing *) + list register_field_index + | UndefinedRegister of integer (* length *) + | RegisterPair of register * register*) + +record( 'regstate, 'regval, 'a) register_ref = + + name ::" string " + + (*is_inc : bool;*) + read_from ::" 'regstate \<Rightarrow> 'a " + + write_to ::" 'a \<Rightarrow> 'regstate \<Rightarrow> 'regstate " + + of_regval ::" 'regval \<Rightarrow> 'a option " + + regval_of ::" 'a \<Rightarrow> 'regval " + + +(* Register accessors: pair of functions for reading and writing register values *) +type_synonym( 'regstate, 'regval) register_accessors =" + ((string \<Rightarrow> 'regstate \<Rightarrow> 'regval option) * + (string \<Rightarrow> 'regval \<Rightarrow> 'regstate \<Rightarrow> 'regstate option))" + +record( 'regtype, 'a) field_ref = + + field_name ::" string " + + field_start ::" int " + + field_is_inc ::" bool " + + get_field ::" 'regtype \<Rightarrow> 'a " + + set_field ::" 'regtype \<Rightarrow> 'a \<Rightarrow> 'regtype " + + +(*let name_of_reg = function + | Register name _ _ _ _ -> name + | UndefinedRegister _ -> failwith name_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith name_of_reg RegisterPair +end + +let size_of_reg = function + | Register _ size _ _ _ -> size + | UndefinedRegister size -> size + | RegisterPair _ _ -> failwith size_of_reg RegisterPair +end + +let start_of_reg = function + | Register _ _ start _ _ -> start + | UndefinedRegister _ -> failwith start_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith start_of_reg RegisterPair +end + +let is_inc_of_reg = function + | Register _ _ _ is_inc _ -> is_inc + | UndefinedRegister _ -> failwith is_inc_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith in_inc_of_reg RegisterPair +end + +let dir_of_reg = function + | Register _ _ _ is_inc _ -> dir_of_bool is_inc + | UndefinedRegister _ -> failwith dir_of_reg UndefinedRegister + | RegisterPair _ _ -> failwith dir_of_reg RegisterPair +end + +let size_of_reg_nat reg = natFromInteger (size_of_reg reg) +let start_of_reg_nat reg = natFromInteger (start_of_reg reg) + +val register_field_indices_aux : register -> register_field -> maybe (integer * integer) +let rec register_field_indices_aux register rfield = + match register with + | Register _ _ _ _ rfields -> List.lookup rfield rfields + | RegisterPair r1 r2 -> + let m_indices = register_field_indices_aux r1 rfield in + if isJust m_indices then m_indices else register_field_indices_aux r2 rfield + | UndefinedRegister _ -> Nothing + end + +val register_field_indices : register -> register_field -> integer * integer +let register_field_indices register rfield = + match register_field_indices_aux register rfield with + | Just indices -> indices + | Nothing -> failwith Invalid register/register-field combination + end + +let register_field_indices_nat reg regfield= + let (i,j) = register_field_indices reg regfield in + (natFromInteger i,natFromInteger j)*) + +(*let rec external_reg_value reg_name v = + let (internal_start, external_start, direction) = + match reg_name with + | Reg _ start size dir -> + (start, (if dir = D_increasing then start else (start - (size +1))), dir) + | Reg_slice _ reg_start dir (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_field _ reg_start dir _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + | Reg_f_slice _ reg_start dir _ _ (slice_start, _) -> + ((if dir = D_increasing then slice_start else (reg_start - slice_start)), + slice_start, dir) + end in + let bits = bit_lifteds_of_bitv v in + <| rv_bits = bits; + rv_dir = direction; + rv_start = external_start; + rv_start_internal = internal_start |> + +val internal_reg_value : register_value -> list bitU +let internal_reg_value v = + List.map bitU_of_bit_lifted v.rv_bits + (*(integerFromNat v.rv_start_internal) + (v.rv_dir = D_increasing)*) + + +let external_slice (d:direction) (start:nat) ((i,j):(nat*nat)) = + match d with + (*This is the case the thread/concurrecny model expects, so no change needed*) + | D_increasing -> (i,j) + | D_decreasing -> let slice_i = start - i in + let slice_j = (i - j) + slice_i in + (slice_i,slice_j) + end *) + +(* TODO +let external_reg_whole r = + Reg (r.name) (natFromInteger r.start) (natFromInteger r.size) (dir_of_bool r.is_inc) + +let external_reg_slice r (i,j) = + let start = natFromInteger r.start in + let dir = dir_of_bool r.is_inc in + Reg_slice (r.name) start dir (external_slice dir start (i,j)) + +let external_reg_field_whole reg rfield = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_field (name_of_reg reg) start dir rfield (external_slice dir start (m,n)) + +let external_reg_field_slice reg rfield (i,j) = + let (m,n) = register_field_indices_nat reg rfield in + let start = start_of_reg_nat reg in + let dir = dir_of_reg reg in + Reg_f_slice (name_of_reg reg) start dir rfield + (external_slice dir start (m,n)) + (external_slice dir start (i,j))*) + +(*val external_mem_value : list bitU -> memory_value +let external_mem_value v = + byte_lifteds_of_bitv v $> List.reverse + +val internal_mem_value : memory_value -> list bitU +let internal_mem_value bytes = + List.reverse bytes $> bitv_of_byte_lifteds*) + + +(*val foreach : forall 'a 'vars. + (list 'a) -> 'vars -> ('a -> 'vars -> 'vars) -> 'vars*) +fun foreach :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where + " foreach ([]) vars body = ( vars )" +|" foreach (x # xs) vars body = ( foreach xs (body x vars) body )" + + +(*val index_list : integer -> integer -> integer -> list integer*) +function (sequential,domintros) index_list :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>(int)list " where + " index_list from1 to1 step = ( + if ((step >( 0 :: int)) \<and> (from1 \<le> to1)) \<or> ((step <( 0 :: int)) \<and> (to1 \<le> from1)) then + from1 # index_list (from1 + step) to1 step + else [])" +by pat_completeness auto + + +(*val while : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) +function (sequential,domintros) while :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where + " while vars cond body = ( + if cond vars then while (body vars) cond body else vars )" +by pat_completeness auto + + +(*val until : forall 'vars. 'vars -> ('vars -> bool) -> ('vars -> 'vars) -> 'vars*) +function (sequential,domintros) until :: " 'vars \<Rightarrow>('vars \<Rightarrow> bool)\<Rightarrow>('vars \<Rightarrow> 'vars)\<Rightarrow> 'vars " where + " until vars cond body = ( + (let vars = (body vars) in + if cond vars then vars else until (body vars) cond body))" +by pat_completeness auto + + + +(* convert numbers unsafely to naturals *) + +record 'a ToNatural_class= + toNatural_method ::" 'a \<Rightarrow> nat " + +(* eta-expanded for Isabelle output, otherwise it breaks *) +definition instance_Sail_values_ToNatural_Num_integer_dict :: "(int)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_integer_dict = ((| + + toNatural_method = (\<lambda> n . nat (abs n))|) )" + +definition instance_Sail_values_ToNatural_Num_int_dict :: "(int)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_int_dict = ((| + + toNatural_method = (\<lambda> n . (nat (abs n)))|) )" + +definition instance_Sail_values_ToNatural_nat_dict :: "(nat)ToNatural_class " where + " instance_Sail_values_ToNatural_nat_dict = ((| + + toNatural_method = (\<lambda> n . n)|) )" + +definition instance_Sail_values_ToNatural_Num_natural_dict :: "(nat)ToNatural_class " where + " instance_Sail_values_ToNatural_Num_natural_dict = ((| + + toNatural_method = (\<lambda> n . n)|) )" + + +fun toNaturalFiveTup :: " 'a ToNatural_class \<Rightarrow> 'b ToNatural_class \<Rightarrow> 'c ToNatural_class \<Rightarrow> 'd ToNatural_class \<Rightarrow> 'e ToNatural_class \<Rightarrow> 'd*'c*'b*'a*'e \<Rightarrow> nat*nat*nat*nat*nat " where + " toNaturalFiveTup dict_Sail_values_ToNatural_a dict_Sail_values_ToNatural_b dict_Sail_values_ToNatural_c dict_Sail_values_ToNatural_d dict_Sail_values_ToNatural_e (n1,n2,n3,n4,n5) = ( + ((toNatural_method dict_Sail_values_ToNatural_d) n1,(toNatural_method dict_Sail_values_ToNatural_c) n2,(toNatural_method dict_Sail_values_ToNatural_b) n3,(toNatural_method dict_Sail_values_ToNatural_a) n4,(toNatural_method dict_Sail_values_ToNatural_e) n5))" + + +(* Let the following types be generated by Sail per spec, using either bitlists + or machine words as bitvector representation *) +(*type regfp = + | RFull of (string) + | RSlice of (string * integer * integer) + | RSliceBit of (string * integer) + | RField of (string * string) + +type niafp = + | NIAFP_successor + | NIAFP_concrete_address of vector bitU + | NIAFP_indirect_address + +(* only for MIPS *) +type diafp = + | DIAFP_none + | DIAFP_concrete of vector bitU + | DIAFP_reg of regfp + +let regfp_to_reg (reg_info : string -> maybe string -> (nat * nat * direction * (nat * nat))) = function + | RFull name -> + let (start,length,direction,_) = reg_info name Nothing in + Reg name start length direction + | RSlice (name,i,j) -> + let i = natFromInteger i in + let j = natFromInteger j in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,j) in + Reg_slice name start direction slice + | RSliceBit (name,i) -> + let i = natFromInteger i in + let (start,length,direction,_) = reg_info name Nothing in + let slice = external_slice direction start (i,i) in + Reg_slice name start direction slice + | RField (name,field_name) -> + let (start,length,direction,span) = reg_info name (Just field_name) in + let slice = external_slice direction start span in + Reg_field name start direction field_name slice +end + +let niafp_to_nia reginfo = function + | NIAFP_successor -> NIA_successor + | NIAFP_concrete_address v -> NIA_concrete_address (address_of_bitv v) + | NIAFP_indirect_address -> NIA_indirect_address +end + +let diafp_to_dia reginfo = function + | DIAFP_none -> DIA_none + | DIAFP_concrete v -> DIA_concrete_address (address_of_bitv v) + | DIAFP_reg r -> DIA_register (regfp_to_reg reginfo r) +end +*) +end diff --git a/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy b/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy new file mode 100644 index 00000000..dd008695 --- /dev/null +++ b/snapshots/isabelle/lib/sail/Sail_values_lemmas.thy @@ -0,0 +1,206 @@ +theory Sail_values_lemmas + imports Sail_values +begin + +lemma nat_of_int_nat_simps[simp]: "nat_of_int = nat" by (auto simp: nat_of_int_def) + +termination reverse_endianness_list by (lexicographic_order simp add: drop_list_def) + +termination index_list + by (relation "measure (\<lambda>(i, j, step). nat ((j - i + step) * sgn step))") auto + +lemma just_list_map_Some[simp]: "just_list (map Some v) = Some v" by (induction v) auto + +lemma just_list_None_iff[simp]: "just_list xs = None \<longleftrightarrow> None \<in> set xs" + by (induction xs) (auto split: option.splits) + +lemma just_list_Some_iff[simp]: "just_list xs = Some ys \<longleftrightarrow> xs = map Some ys" + by (induction xs arbitrary: ys) (auto split: option.splits) + +lemma just_list_cases: + assumes "just_list xs = y" + obtains (None) "None \<in> set xs" and "y = None" + | (Some) ys where "xs = map Some ys" and "y = Some ys" + using assms by (cases y) auto + +lemma repeat_singleton_replicate[simp]: + "repeat [x] n = replicate (nat n) x" +proof (induction n) + case (nonneg n) + have "nat (1 + int m) = Suc m" for m by auto + then show ?case by (induction n) auto +next + case (neg n) + then show ?case by auto +qed + +lemma bool_of_bitU_simps[simp]: + "bool_of_bitU B0 = Some False" + "bool_of_bitU B1 = Some True" + "bool_of_bitU BU = None" + by (auto simp: bool_of_bitU_def) + +lemma bitops_bitU_of_bool[simp]: + "and_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<and> y)" + "or_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool (x \<or> y)" + "xor_bit (bitU_of_bool x) (bitU_of_bool y) = bitU_of_bool ((x \<or> y) \<and> \<not>(x \<and> y))" + "not_bit (bitU_of_bool x) = bitU_of_bool (\<not>x)" + "not_bit \<circ> bitU_of_bool = bitU_of_bool \<circ> Not" + by (auto simp: bitU_of_bool_def not_bit_def) + +lemma image_bitU_of_bool_B0_B1: "bitU_of_bool ` bs \<subseteq> {B0, B1}" + by (auto simp: bitU_of_bool_def split: if_splits) + +lemma bool_of_bitU_bitU_of_bool[simp]: + "bool_of_bitU \<circ> bitU_of_bool = Some" + "bool_of_bitU \<circ> (bitU_of_bool \<circ> f) = Some \<circ> f" + "bool_of_bitU (bitU_of_bool x) = Some x" + by (intro ext, auto simp: bool_of_bitU_def bitU_of_bool_def)+ + +abbreviation "BC_bitU_list \<equiv> instance_Sail_values_Bitvector_list_dict instance_Sail_values_BitU_Sail_values_bitU_dict" +lemmas BC_bitU_list_def = instance_Sail_values_Bitvector_list_dict_def instance_Sail_values_BitU_Sail_values_bitU_dict_def +abbreviation "BC_mword \<equiv> instance_Sail_values_Bitvector_Machine_word_mword_dict" +lemmas BC_mword_defs = instance_Sail_values_Bitvector_Machine_word_mword_dict_def + access_mword_def access_mword_inc_def access_mword_dec_def + (*update_mword_def update_mword_inc_def update_mword_dec_def*) + subrange_list_def subrange_list_inc_def subrange_list_dec_def + update_subrange_list_def update_subrange_list_inc_def update_subrange_list_dec_def + +declare size_itself_int_def[simp] +declare size_itself_def[simp] +declare word_size[simp] + +lemma int_of_mword_simps[simp]: + "int_of_mword False w = uint w" + "int_of_mword True w = sint w" + "int_of_bv BC_mword False w = Some (uint w)" + "int_of_bv BC_mword True w = Some (sint w)" + by (auto simp: int_of_mword_def int_of_bv_def BC_mword_defs) + +lemma BC_mword_simps[simp]: + "unsigned_method BC_mword a = Some (uint a)" + "signed_method BC_mword a = Some (sint a)" + "length_method BC_mword (a :: ('a :: len) word) = int (LENGTH('a))" + by (auto simp: BC_mword_defs) + +lemma of_bits_mword_of_bl[simp]: + assumes "just_list (map bool_of_bitU bus) = Some bs" + shows "of_bits_method BC_mword bus = Some (of_bl bs)" + and "of_bits_failwith BC_mword bus = of_bl bs" + using assms by (auto simp: BC_mword_defs of_bits_failwith_def maybe_failwith_def) + +lemma nat_of_bits_aux_bl_to_bin_aux: + "nat_of_bools_aux acc bs = nat (bl_to_bin_aux bs (int acc))" + by (induction acc bs rule: nat_of_bools_aux.induct) + (auto simp: Bit_def intro!: arg_cong[where f = nat] arg_cong2[where f = bl_to_bin_aux] split: if_splits) + +lemma nat_of_bits_bl_to_bin[simp]: + "nat_of_bools bs = nat (bl_to_bin bs)" + by (auto simp: nat_of_bools_def bl_to_bin_def nat_of_bits_aux_bl_to_bin_aux) + +lemma unsigned_bits_of_mword[simp]: + "unsigned_method BC_bitU_list (bits_of_method BC_mword a) = Some (uint a)" + by (auto simp: BC_bitU_list_def BC_mword_defs unsigned_of_bits_def unsigned_of_bools_def) + +lemma bits_of_bitU_list[simp]: + "bits_of_method BC_bitU_list v = v" + "of_bits_method BC_bitU_list v = Some v" + by (auto simp: BC_bitU_list_def) + +lemma subrange_list_inc_drop_take: + "subrange_list_inc xs i j = drop (nat i) (take (nat (j + 1)) xs)" + by (auto simp: subrange_list_inc_def split_at_def) + +lemma subrange_list_dec_drop_take: + assumes "i \<ge> 0" and "j \<ge> 0" + shows "subrange_list_dec xs i j = drop (length xs - nat (i + 1)) (take (length xs - nat j) xs)" + using assms unfolding subrange_list_dec_def + by (auto simp: subrange_list_inc_drop_take add.commute diff_diff_add nat_minus_as_int) + +lemma update_subrange_list_inc_drop_take: + assumes "i \<ge> 0" and "j \<ge> i" + shows "update_subrange_list_inc xs i j xs' = take (nat i) xs @ xs' @ drop (nat (j + 1)) xs" + using assms unfolding update_subrange_list_inc_def + by (auto simp: split_at_def min_def) + +lemma update_subrange_list_dec_drop_take: + assumes "j \<ge> 0" and "i \<ge> j" + shows "update_subrange_list_dec xs i j xs' = take (length xs - nat (i + 1)) xs @ xs' @ drop (length xs - nat j) xs" + using assms unfolding update_subrange_list_dec_def update_subrange_list_inc_def + by (auto simp: split_at_def min_def Let_def add.commute diff_diff_add nat_minus_as_int) + +declare access_list_inc_def[simp] + +lemma access_list_dec_rev_nth: + assumes "0 \<le> i" and "nat i < length xs" + shows "access_list_dec xs i = rev xs ! (nat i)" + using assms + by (auto simp: access_list_dec_def rev_nth intro!: arg_cong2[where f = List.nth]) + +lemma access_bv_dec_mword[simp]: + fixes w :: "('a::len) word" + assumes "0 \<le> n" and "nat n < LENGTH('a)" + shows "access_bv_dec BC_mword w n = bitU_of_bool (w !! (nat n))" + using assms unfolding access_bv_dec_def access_list_def + by (auto simp: access_list_dec_rev_nth BC_mword_defs rev_map test_bit_bl) + +lemma access_list_dec_nth[simp]: + assumes "0 \<le> i" + shows "access_list_dec xs i = xs ! (length xs - nat (i + 1))" + using assms + by (auto simp: access_list_dec_def add.commute diff_diff_add nat_minus_as_int) + +lemma update_list_inc_update[simp]: + "update_list_inc xs n x = xs[nat n := x]" + by (auto simp: update_list_inc_def) + +lemma update_list_dec_update[simp]: + "update_list_dec xs n x = xs[length xs - nat (n + 1) := x]" + by (auto simp: update_list_dec_def add.commute diff_diff_add nat_minus_as_int) + +lemma bools_of_nat_aux_simps[simp]: + "\<And>len. len \<le> 0 \<Longrightarrow> bools_of_nat_aux len x acc = acc" + "\<And>len. bools_of_nat_aux (int (Suc len)) x acc = + bools_of_nat_aux (int len) (x div 2) ((if x mod 2 = 1 then True else False) # acc)" + by auto +declare bools_of_nat_aux.simps[simp del] + +lemma bools_of_nat_aux_bin_to_bl_aux: + "bools_of_nat_aux len n acc = bin_to_bl_aux (nat len) (int n) acc" +proof (cases len) + case (nonneg len') + show ?thesis unfolding nonneg + proof (induction len' arbitrary: n acc) + case (Suc len'' n acc) + then show ?case + using zmod_int[of n 2] + by (auto simp del: of_nat_simps simp add: bin_rest_def bin_last_def zdiv_int) + qed auto +qed auto + +lemma bools_of_nat_bin_to_bl[simp]: + "bools_of_nat len n = bin_to_bl (nat len) (int n)" + by (auto simp: bools_of_nat_def bools_of_nat_aux_bin_to_bl_aux) + +lemma add_one_bool_ignore_overflow_aux_rbl_succ[simp]: + "add_one_bool_ignore_overflow_aux xs = rbl_succ xs" + by (induction xs) auto + +lemma add_one_bool_ignore_overflow_rbl_succ[simp]: + "add_one_bool_ignore_overflow xs = rev (rbl_succ (rev xs))" + unfolding add_one_bool_ignore_overflow_def by auto + +lemma map_Not_bin_to_bl: + "map Not (bin_to_bl_aux len n acc) = bin_to_bl_aux len (-n - 1) (map Not acc)" +proof (induction len arbitrary: n acc) + case (Suc len n acc) + moreover have "(- (n div 2) - 1) = ((-n - 1) div 2)" by auto + moreover have "(n mod 2 = 0) = ((- n - 1) mod 2 = 1)" by presburger + ultimately show ?case by (auto simp: bin_rest_def bin_last_def) +qed auto + +lemma bools_of_int_bin_to_bl[simp]: + "bools_of_int (int len) n = bin_to_bl len n" + by (auto simp: bools_of_int_def Let_def map_Not_bin_to_bl rbl_succ[unfolded bin_to_bl_def]) + +end diff --git a/snapshots/isabelle/lib/sail/State.thy b/snapshots/isabelle/lib/sail/State.thy new file mode 100644 index 00000000..9d460e8e --- /dev/null +++ b/snapshots/isabelle/lib/sail/State.thy @@ -0,0 +1,102 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/state.lem.\<close> + +theory "State" + +imports + Main + "Lem_pervasives_extra" + "Sail_values" + "Prompt_monad" + "Prompt" + "State_monad" + "State_monad_lemmas" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_impl_base*) +(*open import Sail_values*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State_monad*) +(*open import {isabelle} `State_monad_lemmas`*) + +(* State monad wrapper around prompt monad *) + +(*val liftState : forall 'regval 'regs 'a 'e. register_accessors 'regs 'regval -> monad 'regval 'a 'e -> monadS 'regs 'a 'e*) +function (sequential,domintros) liftState :: "(string \<Rightarrow> 'regs \<Rightarrow> 'regval option)*(string \<Rightarrow> 'regval \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow>('regval,'a,'e)monad \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " liftState ra (Done a) = ( returnS a )" +|" liftState ra (Read_mem rk a sz k) = ( bindS (read_mem_bytesS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) rk a sz) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Read_tag t k) = ( bindS (read_tagS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) t) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_memv a k) = ( bindS (write_mem_bytesS a) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_tag a t k) = ( bindS (write_tagS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) a t) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Read_reg r k) = ( bindS (read_regvalS ra r) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Excl_res k) = ( bindS (excl_resultS () ) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Undefined k) = ( bindS (undefined_boolS () ) (\<lambda> v . liftState ra (k v)))" +|" liftState ra (Write_ea wk a sz k) = ( seqS (write_mem_eaS + (instance_Sail_values_Bitvector_list_dict + instance_Sail_values_BitU_Sail_values_bitU_dict) wk a sz) (liftState ra k))" +|" liftState ra (Write_reg r v k) = ( seqS (write_regvalS ra r v) (liftState ra k))" +|" liftState ra (Footprint k) = ( liftState ra k )" +|" liftState ra (Barrier _ k) = ( liftState ra k )" +|" liftState ra (Print _ k) = ( liftState ra k )" +|" liftState ra (Fail descr) = ( failS descr )" +|" liftState ra (Exception e) = ( throwS e )" +by pat_completeness auto + + + +(*val iterS_aux : forall 'rv 'a 'e. integer -> (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +fun iterS_aux :: " int \<Rightarrow>(int \<Rightarrow> 'a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow>('rv,(unit),'e)monadS " where + " iterS_aux i f (x # xs) = ( seqS (f i x) (iterS_aux (i +( 1 :: int)) f xs))" +|" iterS_aux i f ([]) = ( returnS () )" + + +(*val iteriS : forall 'rv 'a 'e. (integer -> 'a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iteriS :: "(int \<Rightarrow> 'a \<Rightarrow>('rv,(unit),'e)monadS)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where + " iteriS f xs = ( iterS_aux(( 0 :: int)) f xs )" + + +(*val iterS : forall 'rv 'a 'e. ('a -> monadS 'rv unit 'e) -> list 'a -> monadS 'rv unit 'e*) +definition iterS :: "('a \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set)\<Rightarrow> 'a list \<Rightarrow> 'rv sequential_state \<Rightarrow>(((unit),'e)result*'rv sequential_state)set " where + " iterS f xs = ( iteriS ( \<lambda>x . + (case x of _ => \<lambda> x . f x )) xs )" + + +(*val foreachS : forall 'a 'rv 'vars 'e. + list 'a -> 'vars -> ('a -> 'vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +fun foreachS :: " 'a list \<Rightarrow> 'vars \<Rightarrow>('a \<Rightarrow> 'vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " foreachS ([]) vars body = ( returnS vars )" +|" foreachS (x # xs) vars body = ( bindS + (body x vars) (\<lambda> vars . + foreachS xs vars body))" + + + +(*val whileS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) whileS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " whileS vars cond body s = ( + ( bindS(cond vars) (\<lambda> cond_val s' . + if cond_val then + ( bindS(body vars) (\<lambda> vars s'' . whileS vars cond body s'')) s' + else returnS vars s')) s )" +by pat_completeness auto + + +(*val untilS : forall 'rv 'vars 'e. 'vars -> ('vars -> monadS 'rv bool 'e) -> + ('vars -> monadS 'rv 'vars 'e) -> monadS 'rv 'vars 'e*) +function (sequential,domintros) untilS :: " 'vars \<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(((bool),'e)result*'rv sequential_state)set)\<Rightarrow>('vars \<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set)\<Rightarrow> 'rv sequential_state \<Rightarrow>(('vars,'e)result*'rv sequential_state)set " where + " untilS vars cond body s = ( + ( bindS(body vars) (\<lambda> vars s' . + ( bindS(cond vars) (\<lambda> cond_val s'' . + if cond_val then returnS vars s'' else untilS vars cond body s'')) s')) s )" +by pat_completeness auto + +end diff --git a/snapshots/isabelle/lib/sail/State_lemmas.thy b/snapshots/isabelle/lib/sail/State_lemmas.thy new file mode 100644 index 00000000..84b08e6c --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_lemmas.thy @@ -0,0 +1,202 @@ +theory State_lemmas + imports State +begin + +lemma All_liftState_dom: "liftState_dom (r, m)" + by (induction m) (auto intro: liftState.domintros) +termination liftState using All_liftState_dom by auto + +lemma liftState_bind[simp]: + "liftState r (bind m f) = bindS (liftState r m) (liftState r \<circ> f)" + by (induction m f rule: bind.induct) auto + +lemma liftState_return[simp]: "liftState r (return a) = returnS a" by (auto simp: return_def) + +lemma Value_liftState_Run: + assumes "(Value a, s') \<in> liftState r m s" + obtains t where "Run m t a" + by (use assms in \<open>induction r m arbitrary: s s' rule: liftState.induct\<close>; + auto simp add: failS_def throwS_def returnS_def simp del: read_regvalS.simps; + blast elim: Value_bindS_elim) + +lemmas liftState_if_distrib[simp] = if_distrib[where f = "liftState ra" for ra] + +lemma liftState_throw[simp]: "liftState r (throw e) = throwS e" by (auto simp: throw_def) +lemma liftState_assert[simp]: "liftState r (assert_exp c msg) = assert_expS c msg" by (auto simp: assert_exp_def assert_expS_def) +lemma liftState_exit[simp]: "liftState r (exit0 ()) = exitS ()" by (auto simp: exit0_def exitS_def) +lemma liftState_exclResult[simp]: "liftState r (excl_result ()) = excl_resultS ()" by (auto simp: excl_result_def) +lemma liftState_barrier[simp]: "liftState r (barrier bk) = returnS ()" by (auto simp: barrier_def) +lemma liftState_footprint[simp]: "liftState r (footprint ()) = returnS ()" by (auto simp: footprint_def) +lemma liftState_undefined[simp]: "liftState r (undefined_bool ()) = undefined_boolS ()" by (auto simp: undefined_bool_def) +lemma liftState_maybe_fail[simp]: "liftState r (maybe_fail msg x) = maybe_failS msg x" + by (auto simp: maybe_fail_def maybe_failS_def split: option.splits) + +lemma liftState_try_catch[simp]: + "liftState r (try_catch m h) = try_catchS (liftState r m) (liftState r \<circ> h)" + by (induction m h rule: try_catch_induct) (auto simp: try_catchS_bindS_no_throw) + +lemma liftState_early_return[simp]: + "liftState r (early_return r) = early_returnS r" + by (auto simp: early_return_def early_returnS_def) + +lemma liftState_catch_early_return[simp]: + "liftState r (catch_early_return m) = catch_early_returnS (liftState r m)" + by (auto simp: catch_early_return_def catch_early_returnS_def sum.case_distrib cong: sum.case_cong) + +lemma liftState_liftR[simp]: + "liftState r (liftR m) = liftSR (liftState r m)" + by (auto simp: liftR_def liftSR_def) + +lemma liftState_try_catchR[simp]: + "liftState r (try_catchR m h) = try_catchSR (liftState r m) (liftState r \<circ> h)" + by (auto simp: try_catchR_def try_catchSR_def sum.case_distrib cong: sum.case_cong) + +lemma liftState_read_mem_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (read_mem BCa BCb rk a sz) = read_memS BCa BCb rk a sz" + using assms + by (auto simp: read_mem_def read_mem_bytes_def read_memS_def read_mem_bytesS_def maybe_failS_def split: option.splits) + +lemma liftState_read_mem[simp]: + "\<And>a. liftState r (read_mem BC_mword BC_mword rk a sz) = read_memS BC_mword BC_mword rk a sz" + "\<And>a. liftState r (read_mem BC_bitU_list BC_bitU_list rk a sz) = read_memS BC_bitU_list BC_bitU_list rk a sz" + by (auto simp: liftState_read_mem_BC) + +lemma liftState_write_mem_ea_BC: + assumes "unsigned_method BC_bitU_list (bits_of_method BCa a) = unsigned_method BCa a" + shows "liftState r (write_mem_ea BCa rk a sz) = write_mem_eaS BCa rk a (nat sz)" + using assms by (auto simp: write_mem_ea_def write_mem_eaS_def) + +lemma liftState_write_mem_ea[simp]: + "\<And>a. liftState r (write_mem_ea BC_mword rk a sz) = write_mem_eaS BC_mword rk a (nat sz)" + "\<And>a. liftState r (write_mem_ea BC_bitU_list rk a sz) = write_mem_eaS BC_bitU_list rk a (nat sz)" + by (auto simp: liftState_write_mem_ea_BC) + +lemma liftState_write_mem_val: + "liftState r (write_mem_val BC v) = write_mem_valS BC v" + by (auto simp: write_mem_val_def write_mem_valS_def split: option.splits) + +lemma liftState_read_reg_readS: + assumes "\<And>s. Option.bind (get_regval' (name reg) s) (of_regval reg) = Some (read_from reg s)" + shows "liftState (get_regval', set_regval') (read_reg reg) = readS (read_from reg \<circ> regstate)" +proof + fix s :: "'a sequential_state" + obtain rv v where "get_regval' (name reg) (regstate s) = Some rv" + and "of_regval reg rv \<equiv> Some v" and "read_from reg (regstate s) = v" + using assms unfolding bind_eq_Some_conv by blast + then show "liftState (get_regval', set_regval') (read_reg reg) s = readS (read_from reg \<circ> regstate) s" + by (auto simp: read_reg_def bindS_def returnS_def read_regS_def readS_def) +qed + +lemma liftState_write_reg_updateS: + assumes "\<And>s. set_regval' (name reg) (regval_of reg v) s = Some (write_to reg v s)" + shows "liftState (get_regval', set_regval') (write_reg reg v) = updateS (regstate_update (write_to reg v))" + using assms by (auto simp: write_reg_def updateS_def returnS_def bindS_readS) + +lemma liftState_iter_aux[simp]: + shows "liftState r (iter_aux i f xs) = iterS_aux i (\<lambda>i x. liftState r (f i x)) xs" + by (induction i "\<lambda>i x. liftState r (f i x)" xs rule: iterS_aux.induct) (auto cong: bindS_cong) + +lemma liftState_iteri[simp]: + "liftState r (iteri f xs) = iteriS (\<lambda>i x. liftState r (f i x)) xs" + by (auto simp: iteri_def iteriS_def) + +lemma liftState_iter[simp]: + "liftState r (iter f xs) = iterS (liftState r \<circ> f) xs" + by (auto simp: iter_def iterS_def) + +lemma liftState_foreachM[simp]: + "liftState r (foreachM xs vars body) = foreachS xs vars (\<lambda>x vars. liftState r (body x vars))" + by (induction xs vars "\<lambda>x vars. liftState r (body x vars)" rule: foreachS.induct) + (auto cong: bindS_cong) + +lemma whileS_dom_step: + assumes "whileS_dom (vars, cond, body, s)" + and "(Value True, s') \<in> cond vars s" + and "(Value vars', s'') \<in> body vars s'" + shows "whileS_dom (vars', cond, body, s'')" + by (use assms in \<open>induction vars cond body s arbitrary: vars' s' s'' rule: whileS.pinduct\<close>) + (auto intro: whileS.domintros) + +lemma whileM_dom_step: + assumes "whileM_dom (vars, cond, body)" + and "Run (cond vars) t True" + and "Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: whileM.pinduct\<close>) + (auto intro: whileM.domintros) + +lemma whileM_dom_ex_step: + assumes "whileM_dom (vars, cond, body)" + and "\<exists>t. Run (cond vars) t True" + and "\<exists>t'. Run (body vars) t' vars'" + shows "whileM_dom (vars', cond, body)" + using assms by (blast intro: whileM_dom_step) + +lemmas whileS_pinduct = whileS.pinduct[case_names Step] + +lemma liftState_whileM: + assumes "whileS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" + and "whileM_dom (vars, cond, body)" + shows "liftState r (whileM vars cond body) s = whileS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" +proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: whileS.pinduct\<close>) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding whileS.psimps[OF domS] whileM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases cond while) + case (while a s') + have "bindS (liftState r (body vars)) (liftState r \<circ> (\<lambda>vars. whileM vars cond body)) s' = + bindS (liftState r (body vars)) (\<lambda>vars. whileS vars (liftState r \<circ> cond) (liftState r \<circ> body)) s'" + if "a" + proof (intro bindS_ext_cong, goal_cases body while') + case (while' vars' s'') + have "whileM_dom (vars', cond, body)" proof (rule whileM_dom_ex_step[OF domM]) + show "\<exists>t. Run (cond vars) t True" using while that by (auto elim: Value_liftState_Run) + show "\<exists>t'. Run (body vars) t' vars'" using while' that by (auto elim: Value_liftState_Run) + qed + then show ?case using while while' that IH by auto + qed auto + then show ?case by auto + qed auto +qed + + +lemma untilM_dom_step: + assumes "untilM_dom (vars, cond, body)" + and "Run (body vars) t vars'" + and "Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + by (use assms in \<open>induction vars cond body arbitrary: vars' t t' rule: untilM.pinduct\<close>) + (auto intro: untilM.domintros) + +lemma untilM_dom_ex_step: + assumes "untilM_dom (vars, cond, body)" + and "\<exists>t. Run (body vars) t vars'" + and "\<exists>t'. Run (cond vars') t' False" + shows "untilM_dom (vars', cond, body)" + using assms by (blast intro: untilM_dom_step) + +lemma liftState_untilM: + assumes "untilS_dom (vars, liftState r \<circ> cond, liftState r \<circ> body, s)" + and "untilM_dom (vars, cond, body)" + shows "liftState r (untilM vars cond body) s = untilS vars (liftState r \<circ> cond) (liftState r \<circ> body) s" +proof (use assms in \<open>induction vars "liftState r \<circ> cond" "liftState r \<circ> body" s rule: untilS.pinduct\<close>) + case Step: (1 vars s) + note domS = Step(1) and IH = Step(2) and domM = Step(3) + show ?case unfolding untilS.psimps[OF domS] untilM.psimps[OF domM] liftState_bind + proof (intro bindS_ext_cong, goal_cases body k) + case (k vars' s') + show ?case unfolding comp_def liftState_bind + proof (intro bindS_ext_cong, goal_cases cond until) + case (until a s'') + have "untilM_dom (vars', cond, body)" if "\<not>a" + proof (rule untilM_dom_ex_step[OF domM]) + show "\<exists>t. Run (body vars) t vars'" using k by (auto elim: Value_liftState_Run) + show "\<exists>t'. Run (cond vars') t' False" using until that by (auto elim: Value_liftState_Run) + qed + then show ?case using k until IH by (auto simp: comp_def) + qed auto + qed auto +qed + +end diff --git a/snapshots/isabelle/lib/sail/State_monad.thy b/snapshots/isabelle/lib/sail/State_monad.thy new file mode 100644 index 00000000..8e19f0b6 --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_monad.thy @@ -0,0 +1,375 @@ +chapter \<open>Generated by Lem from ../../src/gen_lib/state_monad.lem.\<close> + +theory "State_monad" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + +begin + +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) + +(* 'a is result type *) + +type_synonym memstate =" (int, memory_byte) Map.map " +type_synonym tagstate =" (int, bitU) Map.map " +(* type regstate = map string (vector bitU) *) + +record 'regs sequential_state = + + regstate ::" 'regs " + + memstate ::" memstate " + + tagstate ::" tagstate " + + write_ea ::" (write_kind * int * int)option " + + last_exclusive_operation_was_load ::" bool " + + (* Random bool generator for use as an undefined bit oracle *) + next_bool ::" nat \<Rightarrow> (bool * nat)" + + seed ::" nat " + + +(*val init_state : forall 'regs. 'regs -> (nat -> (bool* nat)) -> nat -> sequential_state 'regs*) +definition init_state :: " 'regs \<Rightarrow>(nat \<Rightarrow> bool*nat)\<Rightarrow> nat \<Rightarrow> 'regs sequential_state " where + " init_state regs o1 s = ( + (| regstate = regs, + memstate = Map.empty, + tagstate = Map.empty, + write_ea = None, + last_exclusive_operation_was_load = False, + next_bool = o1, + seed = s |) )" + + +datatype 'e ex = + Failure " string " + | Throw " 'e " + +datatype( 'a, 'e) result = + Value " 'a " + | Ex " ( 'e ex)" + +(* State, nondeterminism and exception monad with result value type 'a + and exception type 'e. *) +type_synonym( 'regs, 'a, 'e) monadS =" 'regs sequential_state \<Rightarrow> ( ('a, 'e)result * 'regs sequential_state) set " + +(*val returnS : forall 'regs 'a 'e. 'a -> monadS 'regs 'a 'e*) +definition returnS :: " 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " returnS a s = ( {(Value a,s)})" + + +(*val bindS : forall 'regs 'a 'b 'e. monadS 'regs 'a 'e -> ('a -> monadS 'regs 'b 'e) -> monadS 'regs 'b 'e*) +definition bindS :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow>('a \<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set " where + " bindS m f (s :: 'regs sequential_state) = ( + \<Union> (Set.image (\<lambda>x . + (case x of (Value a, s') => f a s' | (Ex e, s') => {(Ex e, s')} )) (m s)))" + + +(*val seqS: forall 'regs 'b 'e. monadS 'regs unit 'e -> monadS 'regs 'b 'e -> monadS 'regs 'b 'e*) +definition seqS :: "('regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set)\<Rightarrow>('regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('b,'e)result*'regs sequential_state)set " where + " seqS m n = ( bindS m ( \<lambda>x . + (case x of (_ :: unit) => n )))" + + +(*val chooseS : forall 'regs 'a 'e. SetType 'a => set 'a -> monadS 'regs 'a 'e*) +definition chooseS :: " 'a set \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " chooseS xs s = ( Set.image (\<lambda> x . (Value x, s)) xs )" + + +(*val readS : forall 'regs 'a 'e. (sequential_state 'regs -> 'a) -> monadS 'regs 'a 'e*) +definition readS :: "('regs sequential_state \<Rightarrow> 'a)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " readS f = ( (\<lambda> s . returnS (f s) s))" + + +(*val updateS : forall 'regs 'e. (sequential_state 'regs -> sequential_state 'regs) -> monadS 'regs unit 'e*) +definition updateS :: "('regs sequential_state \<Rightarrow> 'regs sequential_state)\<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where + " updateS f = ( (\<lambda> s . returnS () (f s)))" + + +(*val failS : forall 'regs 'a 'e. string -> monadS 'regs 'a 'e*) +definition failS :: " string \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " failS msg s = ( {(Ex (Failure msg), s)})" + + +(*val undefined_boolS : forall 'regval 'regs 'a 'e. unit -> monadS 'regs bool 'e*) +definition undefined_boolS :: " unit \<Rightarrow>('regs,(bool),'e)monadS " where + " undefined_boolS _ = ( bindS + (readS (\<lambda> s . (next_bool s) ((seed s)))) ( \<lambda>x . + (case x of + (b, seed1) => seqS (updateS (\<lambda> s . ( s (| seed := seed1 |)))) + (returnS b) + )))" + + +(*val exitS : forall 'regs 'e 'a. unit -> monadS 'regs 'a 'e*) +definition exitS :: " unit \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " exitS _ = ( failS (''exit''))" + + +(*val throwS : forall 'regs 'a 'e. 'e -> monadS 'regs 'a 'e*) +definition throwS :: " 'e \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " throwS e s = ( {(Ex (Throw e), s)})" + + +(*val try_catchS : forall 'regs 'a 'e1 'e2. monadS 'regs 'a 'e1 -> ('e1 -> monadS 'regs 'a 'e2) -> monadS 'regs 'a 'e2*) +definition try_catchS :: "('regs sequential_state \<Rightarrow>(('a,'e1)result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e2)result*'regs sequential_state)set " where + " try_catchS m h s = ( + \<Union> (Set.image (\<lambda>x . + (case x of + (Value a, s') => returnS a s' + | (Ex (Throw e), s') => h e s' + | (Ex (Failure msg), s') => {(Ex (Failure msg), s')} + )) (m s)))" + + +(*val assert_expS : forall 'regs 'e. bool -> string -> monadS 'regs unit 'e*) +definition assert_expS :: " bool \<Rightarrow> string \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where + " assert_expS exp msg = ( if exp then returnS () else failS msg )" + + +(* For early return, we abuse exceptions by throwing and catching + the return value. The exception type is either 'r 'e, where Right e + represents a proper exception and Left r an early return of value r. *) +type_synonym( 'regs, 'a, 'r, 'e) monadSR =" ('regs, 'a, ( ('r, 'e)sum)) monadS " + +(*val early_returnS : forall 'regs 'a 'r 'e. 'r -> monadSR 'regs 'a 'r 'e*) +definition early_returnS :: " 'r \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where + " early_returnS r = ( throwS (Inl r))" + + +(*val catch_early_returnS : forall 'regs 'a 'e. monadSR 'regs 'a 'a 'e -> monadS 'regs 'a 'e*) +definition catch_early_returnS :: "('regs sequential_state \<Rightarrow>(('a,(('a,'e)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " catch_early_returnS m = ( + try_catchS m + (\<lambda>x . (case x of Inl a => returnS a | Inr e => throwS e )))" + + +(* Lift to monad with early return by wrapping exceptions *) +(*val liftSR : forall 'a 'r 'regs 'e. monadS 'regs 'a 'e -> monadSR 'regs 'a 'r 'e*) +definition liftSR :: "('regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e)sum))result*'regs sequential_state)set " where + " liftSR m = ( try_catchS m (\<lambda> e . throwS (Inr e)))" + + +(* Catch exceptions in the presence of early returns *) +(*val try_catchSR : forall 'regs 'a 'r 'e1 'e2. monadSR 'regs 'a 'r 'e1 -> ('e1 -> monadSR 'regs 'a 'r 'e2) -> monadSR 'regs 'a 'r 'e2*) +definition try_catchSR :: "('regs sequential_state \<Rightarrow>(('a,(('r,'e1)sum))result*'regs sequential_state)set)\<Rightarrow>('e1 \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set)\<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,(('r,'e2)sum))result*'regs sequential_state)set " where + " try_catchSR m h = ( + try_catchS m + (\<lambda>x . (case x of Inl r => throwS (Inl r) | Inr e => h e )))" + + +(*val maybe_failS : forall 'regs 'a 'e. string -> maybe 'a -> monadS 'regs 'a 'e*) +definition maybe_failS :: " string \<Rightarrow> 'a option \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " maybe_failS msg = ( \<lambda>x . + (case x of Some a => returnS a | None => failS msg ) )" + + +(*val read_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> monadS 'regs bitU 'e*) +definition read_tagS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow>('regs,(bitU),'e)monadS " where + " read_tagS dict_Sail_values_Bitvector_a addr = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + readS (\<lambda> s . case_option B0 id ((tagstate s) addr))))" + + +(* Read bytes from memory and return in little endian order *) +(*val read_mem_bytesS : forall 'regs 'e 'a. Bitvector 'a => read_kind -> 'a -> nat -> monadS 'regs (list memory_byte) 'e*) +definition read_mem_bytesS :: " 'a Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(((bitU)list)list),'e)monadS " where + " read_mem_bytesS dict_Sail_values_Bitvector_a read_kind addr sz = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + (let sz = (int sz) in + (let addrs = (index_list addr ((addr+sz)-( 1 :: int))(( 1 :: int))) in + (let read_byte = (\<lambda> s addr . (memstate s) addr) in + bindS (readS (\<lambda> s . just_list (List.map (read_byte s) addrs))) + (\<lambda>x . (case x of + Some mem_val => seqS + (updateS + (\<lambda> s . + if read_is_exclusive read_kind + then + ( s (| last_exclusive_operation_was_load := True |)) + else s)) (returnS mem_val) + | None => failS (''read_memS'') + )))))))" + + +(*val read_memS : forall 'regs 'e 'a 'b. Bitvector 'a, Bitvector 'b => read_kind -> 'a -> integer -> monadS 'regs 'b 'e*) +definition read_memS :: " 'a Bitvector_class \<Rightarrow> 'b Bitvector_class \<Rightarrow> read_kind \<Rightarrow> 'a \<Rightarrow> int \<Rightarrow>('regs,'b,'e)monadS " where + " read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b rk a sz = ( bindS + (read_mem_bytesS dict_Sail_values_Bitvector_a rk a (nat_of_int sz)) (\<lambda> bytes . + maybe_failS (''bits_of_mem_bytes'') ( + (of_bits_method dict_Sail_values_Bitvector_b) (bits_of_mem_bytes bytes))))" + + +(*val excl_resultS : forall 'regs 'e. unit -> monadS 'regs bool 'e*) +definition excl_resultS :: " unit \<Rightarrow>('regs,(bool),'e)monadS " where + " excl_resultS _ = ( bindS + (readS (\<lambda> s . (last_exclusive_operation_was_load s))) (\<lambda> excl_load . seqS + (updateS (\<lambda> s . ( s (| last_exclusive_operation_was_load := False |)))) + (chooseS (if excl_load then {False, True} else {False}))))" + + +(*val write_mem_eaS : forall 'regs 'e 'a. Bitvector 'a => write_kind -> 'a -> nat -> monadS 'regs unit 'e*) +definition write_mem_eaS :: " 'a Bitvector_class \<Rightarrow> write_kind \<Rightarrow> 'a \<Rightarrow> nat \<Rightarrow>('regs,(unit),'e)monadS " where + " write_mem_eaS dict_Sail_values_Bitvector_a write_kind addr sz = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . + (let sz = (int sz) in + updateS (\<lambda> s . ( s (| write_ea := (Some (write_kind, addr, sz)) |))))))" + + +(* Write little-endian list of bytes to previously announced address *) +(*val write_mem_bytesS : forall 'regs 'e. list memory_byte -> monadS 'regs bool 'e*) +definition write_mem_bytesS :: "((bitU)list)list \<Rightarrow>('regs,(bool),'e)monadS " where + " write_mem_bytesS v = ( bindS + (readS (\<lambda> s . (write_ea s))) (\<lambda>x . + (case x of + None => failS (''write ea has not been announced yet'') + | Some (_, addr, sz) => + (let addrs = (index_list addr ((addr + sz) - ( 1 :: int)) (( 1 :: int))) in + (*let v = external_mem_value (bits_of v) in*) + (let a_v = (List.zip addrs v) in + (let write_byte = (\<lambda>mem p . (case (mem ,p ) of + ( mem , (addr, v) ) => map_update + addr + v mem + )) in + seqS + (updateS + (\<lambda> s . + ( s (| memstate := (List.foldl write_byte (memstate s) a_v) |)))) + (returnS True)))) + )))" + + +(*val write_mem_valS : forall 'regs 'e 'a. Bitvector 'a => 'a -> monadS 'regs bool 'e*) +definition write_mem_valS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((bool),'e)result*'regs sequential_state)set " where + " write_mem_valS dict_Sail_values_Bitvector_a v = ( (case mem_bytes_of_bits + dict_Sail_values_Bitvector_a v of + Some v => write_mem_bytesS v + | None => failS (''write_mem_val'') +))" + + +(*val write_tagS : forall 'regs 'a 'e. Bitvector 'a => 'a -> bitU -> monadS 'regs bool 'e*) +definition write_tagS :: " 'a Bitvector_class \<Rightarrow> 'a \<Rightarrow> bitU \<Rightarrow>('regs,(bool),'e)monadS " where + " write_tagS dict_Sail_values_Bitvector_a addr t = ( bindS + (maybe_failS (''unsigned'') ( + (unsigned_method dict_Sail_values_Bitvector_a) addr)) (\<lambda> addr . seqS + (updateS (\<lambda> s . ( s (| tagstate := (map_update addr t(tagstate s)) |)))) + (returnS True)))" + + +(*val read_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> monadS 'regs 'a 'e*) +definition read_regS :: "('regs,'rv,'a)register_ref \<Rightarrow> 'regs sequential_state \<Rightarrow>(('a,'e)result*'regs sequential_state)set " where + " read_regS reg = ( readS (\<lambda> s . (read_from reg)(regstate s)))" + + +(* TODO +let read_reg_range reg i j state = + let v = slice (get_reg state (name_of_reg reg)) i j in + [(Value (vec_to_bvec v),state)] +let read_reg_bit reg i state = + let v = access (get_reg state (name_of_reg reg)) i in + [(Value v,state)] +let read_reg_field reg regfield = + let (i,j) = register_field_indices reg regfield in + read_reg_range reg i j +let read_reg_bitfield reg regfield = + let (i,_) = register_field_indices reg regfield in + read_reg_bit reg i *) + +(*val read_regvalS : forall 'regs 'rv 'e. + register_accessors 'regs 'rv -> string -> monadS 'regs 'rv 'e*) +fun read_regvalS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow>('regs,'rv,'e)monadS " where + " read_regvalS (read, _) reg = ( bindS + (readS (\<lambda> s . read reg(regstate s))) (\<lambda>x . + (case x of + Some v => returnS v + | None => failS ((''read_regvalS '') @ reg) + )))" + + +(*val write_regvalS : forall 'regs 'rv 'e. + register_accessors 'regs 'rv -> string -> 'rv -> monadS 'regs unit 'e*) +fun write_regvalS :: "(string \<Rightarrow> 'regs \<Rightarrow> 'rv option)*(string \<Rightarrow> 'rv \<Rightarrow> 'regs \<Rightarrow> 'regs option)\<Rightarrow> string \<Rightarrow> 'rv \<Rightarrow>('regs,(unit),'e)monadS " where + " write_regvalS (_, write1) reg v = ( bindS + (readS (\<lambda> s . write1 reg v(regstate s))) (\<lambda>x . + (case x of + Some rs' => updateS (\<lambda> s . ( s (| regstate := rs' |))) + | None => failS ((''write_regvalS '') @ reg) + )))" + + +(*val write_regS : forall 'regs 'rv 'a 'e. register_ref 'regs 'rv 'a -> 'a -> monadS 'regs unit 'e*) +definition write_regS :: "('regs,'rv,'a)register_ref \<Rightarrow> 'a \<Rightarrow> 'regs sequential_state \<Rightarrow>(((unit),'e)result*'regs sequential_state)set " where + " write_regS reg v = ( + updateS (\<lambda> s . ( s (| regstate := ((write_to reg) v(regstate s)) |))))" + + +(* TODO +val update_reg : forall 'regs 'rv 'a 'b 'e. register_ref 'regs 'rv 'a -> ('a -> 'b -> 'a) -> 'b -> monadS 'regs unit 'e +let update_reg reg f v state = + let current_value = get_reg state reg in + let new_value = f current_value v in + [(Value (), set_reg state reg new_value)] + +let write_reg_field reg regfield = update_reg reg regfield.set_field + +val update_reg_range : forall 'regs 'rv 'a 'b. Bitvector 'a, Bitvector 'b => register_ref 'regs 'rv 'a -> integer -> integer -> 'a -> 'b -> 'a +let update_reg_range reg i j reg_val new_val = set_bits (reg.is_inc) reg_val i j (bits_of new_val) +let write_reg_range reg i j = update_reg reg (update_reg_range reg i j) + +let update_reg_pos reg i reg_val x = update_list reg.is_inc reg_val i x +let write_reg_pos reg i = update_reg reg (update_reg_pos reg i) + +let update_reg_bit reg i reg_val bit = set_bit (reg.is_inc) reg_val i (to_bitU bit) +let write_reg_bit reg i = update_reg reg (update_reg_bit reg i) + +let update_reg_field_range regfield i j reg_val new_val = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bits (regfield.field_is_inc) current_field_value i j (bits_of new_val) in + regfield.set_field reg_val new_field_value +let write_reg_field_range reg regfield i j = update_reg reg (update_reg_field_range regfield i j) + +let update_reg_field_pos regfield i reg_val x = + let current_field_value = regfield.get_field reg_val in + let new_field_value = update_list regfield.field_is_inc current_field_value i x in + regfield.set_field reg_val new_field_value +let write_reg_field_pos reg regfield i = update_reg reg (update_reg_field_pos regfield i) + +let update_reg_field_bit regfield i reg_val bit = + let current_field_value = regfield.get_field reg_val in + let new_field_value = set_bit (regfield.field_is_inc) current_field_value i (to_bitU bit) in + regfield.set_field reg_val new_field_value +let write_reg_field_bit reg regfield i = update_reg reg (update_reg_field_bit regfield i)*) + +(* TODO Add Show typeclass for value and exception type *) +(*val show_result : forall 'a 'e. result 'a 'e -> string*) +definition show_result :: "('a,'e)result \<Rightarrow> string " where + " show_result = ( \<lambda>x . + (case x of + Value _ => (''Value ()'') + | Ex (Failure msg) => (''Failure '') @ msg + | Ex (Throw _) => (''Throw'') + ) )" + + +(*val prerr_results : forall 'a 'e 's. SetType 's => set (result 'a 'e * 's) -> unit*) +definition prerr_results :: "(('a,'e)result*'s)set \<Rightarrow> unit " where + " prerr_results rs = ( + (let _ = (Set.image ( \<lambda>x . + (case x of (r, _) => (let _ = (prerr_endline (show_result r)) in () ) )) rs) in + () ))" + +end diff --git a/snapshots/isabelle/lib/sail/State_monad_lemmas.thy b/snapshots/isabelle/lib/sail/State_monad_lemmas.thy new file mode 100644 index 00000000..e0d684ba --- /dev/null +++ b/snapshots/isabelle/lib/sail/State_monad_lemmas.thy @@ -0,0 +1,232 @@ +theory State_monad_lemmas + imports + State_monad + Sail_values_lemmas +begin + +(*context + notes returnS_def[simp] and failS_def[simp] and throwS_def[simp] and readS_def[simp] and updateS_def[simp] +begin*) + +lemma bindS_ext_cong[fundef_cong]: + assumes m: "m1 s = m2 s" + and f: "\<And>a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'" + shows "bindS m1 f1 s = bindS m2 f2 s" + using assms unfolding bindS_def by (auto split: result.splits) + +lemma bindS_cong[fundef_cong]: + assumes m: "m1 = m2" + and f: "\<And>s a s'. (Value a, s') \<in> (m2 s) \<Longrightarrow> f1 a s' = f2 a s'" + shows "bindS m1 f1 = bindS m2 f2" + using assms by (intro ext bindS_ext_cong; blast) + +lemma bindS_returnS_left[simp]: "bindS (returnS x) f = f x" + by (auto simp add: bindS_def returnS_def) + +lemma bindS_returnS_right[simp]: "bindS m returnS = (m :: ('regs, 'a, 'e) monadS)" + by (intro ext) (auto simp: bindS_def returnS_def split: result.splits) + +lemma bindS_readS: "bindS (readS f) m = (\<lambda>s. m (f s) s)" + by (auto simp: bindS_def readS_def returnS_def) + +lemma bindS_updateS: "bindS (updateS f) m = (\<lambda>s. m () (f s))" + by (auto simp: bindS_def updateS_def returnS_def) + +lemma bindS_assertS_True[simp]: "bindS (assert_expS True msg) f = f ()" + by (auto simp: assert_expS_def) + + +lemma result_cases: + fixes r :: "('a, 'e) result" + obtains (Value) a where "r = Value a" + | (Throw) e where "r = Ex (Throw e)" + | (Failure) msg where "r = Ex (Failure msg)" +proof (cases r) + case (Ex ex) then show ?thesis by (cases ex; auto intro: that) +qed + +lemma result_state_cases: + fixes rs :: "('a, 'e) result \<times> 's" + obtains (Value) a s where "rs = (Value a, s)" + | (Throw) e s where "rs = (Ex (Throw e), s)" + | (Failure) msg s where "rs = (Ex (Failure msg), s)" +proof - + obtain r s where rs: "rs = (r, s)" by (cases rs) + then show thesis by (cases r rule: result_cases) (auto intro: that) +qed + +lemma monadS_ext_eqI: + fixes m m' :: "('regs, 'a, 'e) monadS" + assumes "\<And>a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s" + and "\<And>e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s" + and "\<And>msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s" + shows "m s = m' s" +proof (intro set_eqI) + fix x + show "x \<in> m s \<longleftrightarrow> x \<in> m' s" using assms by (cases x rule: result_state_cases) auto +qed + +lemma monadS_eqI: + fixes m m' :: "('regs, 'a, 'e) monadS" + assumes "\<And>s a s'. (Value a, s') \<in> m s \<longleftrightarrow> (Value a, s') \<in> m' s" + and "\<And>s e s'. (Ex (Throw e), s') \<in> m s \<longleftrightarrow> (Ex (Throw e), s') \<in> m' s" + and "\<And>s msg s'. (Ex (Failure msg), s') \<in> m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m' s" + shows "m = m'" + using assms by (intro ext monadS_ext_eqI) + +lemma bindS_cases: + assumes "(r, s') \<in> bindS m f s" + obtains (Value) a a' s'' where "r = Value a" and "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''" + | (Ex_Left) e where "r = Ex e" and "(Ex e, s') \<in> m s" + | (Ex_Right) e a s'' where "r = Ex e" and "(Value a, s'') \<in> m s" and "(Ex e, s') \<in> f a s''" + using assms by (cases r; auto simp: bindS_def split: result.splits) + +lemma bindS_intros: + "\<And>m f s a s' a' s''. (Value a', s'') \<in> m s \<Longrightarrow> (Value a, s') \<in> f a' s'' \<Longrightarrow> (Value a, s') \<in> bindS m f s" + "\<And>m f s e s'. (Ex e, s') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s" + "\<And>m f s e s' a s''. (Ex e, s') \<in> f a s'' \<Longrightarrow> (Value a, s'') \<in> m s \<Longrightarrow> (Ex e, s') \<in> bindS m f s" + by (auto simp: bindS_def intro: bexI[rotated]) + +lemma bindS_assoc[simp]: "bindS (bindS m f) g = bindS m (\<lambda>x. bindS (f x) g)" + by (auto elim!: bindS_cases intro: bindS_intros monadS_eqI) + +lemma bindS_failS[simp]: "bindS (failS msg) f = failS msg" by (auto simp: bindS_def failS_def) +lemma bindS_throwS[simp]: "bindS (throwS e) f = throwS e" by (auto simp: bindS_def throwS_def) +declare seqS_def[simp] + +lemma Value_bindS_elim: + assumes "(Value a, s') \<in> bindS m f s" + obtains s'' a' where "(Value a', s'') \<in> m s" and "(Value a, s') \<in> f a' s''" + using assms by (auto elim: bindS_cases) + +lemma Ex_bindS_elim: + assumes "(Ex e, s') \<in> bindS m f s" + obtains (Left) "(Ex e, s') \<in> m s" + | (Right) s'' a' where "(Value a', s'') \<in> m s" and "(Ex e, s') \<in> f a' s''" + using assms by (auto elim: bindS_cases) + +lemma try_catchS_returnS[simp]: "try_catchS (returnS a) h = returnS a" + and try_catchS_failS[simp]: "try_catchS (failS msg) h = failS msg" + and try_catchS_throwS[simp]: "try_catchS (throwS e) h = h e" + by (auto simp: try_catchS_def returnS_def failS_def throwS_def) + +lemma try_catchS_cong[cong]: + assumes "\<And>s. m1 s = m2 s" and "\<And>e s. h1 e s = h2 e s" + shows "try_catchS m1 h1 = try_catchS m2 h2" + using assms by (intro arg_cong2[where f = try_catchS] ext) auto + +lemma try_catchS_cases: + assumes "(r, s') \<in> try_catchS m h s" + obtains (Value) a where "r = Value a" and "(Value a, s') \<in> m s" + | (Fail) msg where "r = Ex (Failure msg)" and "(Ex (Failure msg), s') \<in> m s" + | (h) e s'' where "(Ex (Throw e), s'') \<in> m s" and "(r, s') \<in> h e s''" + using assms + by (cases r rule: result_cases) (auto simp: try_catchS_def returnS_def split: result.splits ex.splits) + +lemma try_catchS_intros: + "\<And>m h s a s'. (Value a, s') \<in> m s \<Longrightarrow> (Value a, s') \<in> try_catchS m h s" + "\<And>m h s msg s'. (Ex (Failure msg), s') \<in> m s \<Longrightarrow> (Ex (Failure msg), s') \<in> try_catchS m h s" + "\<And>m h s e s'' r s'. (Ex (Throw e), s'') \<in> m s \<Longrightarrow> (r, s') \<in> h e s'' \<Longrightarrow> (r, s') \<in> try_catchS m h s" + by (auto simp: try_catchS_def returnS_def intro: bexI[rotated]) + +lemma no_Ex_basic_builtins[simp]: + "\<And>s e s' a. (Ex e, s') \<in> returnS a s \<longleftrightarrow> False" + "\<And>s e s' f. (Ex e, s') \<in> readS f s \<longleftrightarrow> False" + "\<And>s e s' f. (Ex e, s') \<in> updateS f s \<longleftrightarrow> False" + "\<And>s e s' xs. (Ex e, s') \<in> chooseS xs s \<longleftrightarrow> False" + by (auto simp: readS_def updateS_def returnS_def chooseS_def) + +fun ignore_throw_aux :: "(('a, 'e1) result \<times> 's) \<Rightarrow> (('a, 'e2) result \<times> 's) set" where + "ignore_throw_aux (Value a, s') = {(Value a, s')}" +| "ignore_throw_aux (Ex (Throw e), s') = {}" +| "ignore_throw_aux (Ex (Failure msg), s') = {(Ex (Failure msg), s')}" +definition "ignore_throw m s \<equiv> \<Union>(ignore_throw_aux ` m s)" + +lemma ignore_throw_cong: + assumes "\<And>s. m1 s = m2 s" + shows "ignore_throw m1 = ignore_throw m2" + using assms by (auto simp: ignore_throw_def) + +lemma ignore_throw_aux_member_simps[simp]: + "(Value a, s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Value a, s')" + "(Ex (Throw e), s') \<in> ignore_throw_aux ms \<longleftrightarrow> False" + "(Ex (Failure msg), s') \<in> ignore_throw_aux ms \<longleftrightarrow> ms = (Ex (Failure msg), s')" + by (cases ms rule: result_state_cases; auto)+ + +lemma ignore_throw_member_simps[simp]: + "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s" + "(Value a, s') \<in> ignore_throw m s \<longleftrightarrow> (Value a, s') \<in> m s" + "(Ex (Throw e), s') \<in> ignore_throw m s \<longleftrightarrow> False" + "(Ex (Failure msg), s') \<in> ignore_throw m s \<longleftrightarrow> (Ex (Failure msg), s') \<in> m s" + by (auto simp: ignore_throw_def) + +lemma ignore_throw_cases: + assumes no_throw: "ignore_throw m s = m s" + and r: "(r, s') \<in> m s" + obtains (Value) a where "r = Value a" + | (Failure) msg where "r = Ex (Failure msg)" + using r unfolding no_throw[symmetric] + by (cases r rule: result_cases) (auto simp: ignore_throw_def) + +lemma ignore_throw_bindS[simp]: + "ignore_throw (bindS m f) = bindS (ignore_throw m) (ignore_throw \<circ> f)" + by (intro monadS_eqI) (auto simp: ignore_throw_def elim!: bindS_cases intro: bindS_intros) + +lemma try_catchS_bindS_no_throw: + fixes m1 :: "('r, 'a, 'e1) monadS" and m2 :: "('r, 'a, 'e2) monadS" + assumes m1: "\<And>s. ignore_throw m1 s = m1 s" + and m2: "\<And>s. ignore_throw m1 s = m2 s" + shows "try_catchS (bindS m1 f) h = bindS m2 (\<lambda>a. try_catchS (f a) h)" +proof + fix s + have "try_catchS (bindS m1 f) h s = bindS (ignore_throw m1) (\<lambda>a. try_catchS (f a) h) s" + by (intro monadS_ext_eqI; + auto elim!: bindS_cases try_catchS_cases elim: ignore_throw_cases[OF m1]; + auto simp: ignore_throw_def intro: bindS_intros try_catchS_intros) + also have "\<dots> = bindS m2 (\<lambda>a. try_catchS (f a) h) s" using m2 by (intro bindS_ext_cong) auto + finally show "try_catchS (bindS m1 f) h s = bindS m2 (\<lambda>a. try_catchS (f a) h) s" . +qed + +lemma no_throw_basic_builtins[simp]: + "ignore_throw (returnS a) = returnS a" + "\<And>f. ignore_throw (readS f) = readS f" + "\<And>f. ignore_throw (updateS f) = updateS f" + "ignore_throw (chooseS xs) = chooseS xs" + "ignore_throw (failS msg) = failS msg" + "ignore_throw (maybe_failS msg x) = maybe_failS msg x" + unfolding ignore_throw_def returnS_def chooseS_def maybe_failS_def failS_def readS_def updateS_def + by (intro ext; auto split: option.splits)+ + +lemmas ignore_throw_option_case_distrib = + option.case_distrib[where h = "\<lambda>c. ignore_throw c s" and option = "c s" for c s] + +lemma no_throw_mem_builtins: + "\<And>BC rk a sz s. ignore_throw (read_mem_bytesS BC rk a sz) s = read_mem_bytesS BC rk a sz s" + "\<And>BC a s. ignore_throw (read_tagS BC a) s = read_tagS BC a s" + "\<And>BC wk a sz s. ignore_throw (write_mem_eaS BC wk a sz) s = write_mem_eaS BC wk a sz s" + "\<And>v s. ignore_throw (write_mem_bytesS v) s = write_mem_bytesS v s" + "\<And>BC v s. ignore_throw (write_mem_valS BC v) s = write_mem_valS BC v s" + "\<And>BC a t s. ignore_throw (write_tagS BC a t) s = write_tagS BC a t s" + "\<And>s. ignore_throw (excl_resultS ()) s = excl_resultS () s" + "\<And>s. ignore_throw (undefined_boolS ()) s = undefined_boolS () s" + unfolding read_mem_bytesS_def read_memS_def read_tagS_def write_mem_eaS_def + unfolding write_mem_valS_def write_mem_bytesS_def write_tagS_def + unfolding excl_resultS_def undefined_boolS_def + by (auto cong: bindS_cong bindS_ext_cong ignore_throw_cong option.case_cong + simp: option.case_distrib prod.case_distrib ignore_throw_option_case_distrib comp_def) + +lemma no_throw_read_memS: "ignore_throw (read_memS BCa BCb rk a sz) s = read_memS BCa BCb rk a sz s" + by (auto simp: read_memS_def no_throw_mem_builtins cong: bindS_ext_cong) + +lemma no_throw_read_regvalS: "ignore_throw (read_regvalS r reg_name) s = read_regvalS r reg_name s" + by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong) + +lemma no_throw_write_regvalS: "ignore_throw (write_regvalS r reg_name v) s = write_regvalS r reg_name v s" + by (cases r) (auto simp: option.case_distrib cong: bindS_cong option.case_cong) + +lemmas no_throw_builtins[simp] = + no_throw_mem_builtins no_throw_read_regvalS no_throw_write_regvalS no_throw_read_memS + +(* end *) + +end diff --git a/snapshots/isabelle/riscv/Riscv.thy b/snapshots/isabelle/riscv/Riscv.thy new file mode 100644 index 00000000..71873cec --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv.thy @@ -0,0 +1,7876 @@ +chapter \<open>Generated by Lem from riscv.lem.\<close> + +theory "Riscv" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Riscv_types" + "Riscv_extras" + +begin + +(*Generated by Sail from riscv.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Riscv_types*) +(*open import Riscv_extras*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) + +definition GetSlice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) + +definition RISCV_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),(bool),(exception))monad " where + " RISCV_write addr width data = ( + write_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data \<then> + return True )" + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) + +definition RISCV_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(exception))monad " where + " RISCV_read addr width = ( + (read_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . + return (Some w__0)))" + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val ex_nat : ii -> integer*) + +definition ex_nat :: " int \<Rightarrow> int " where + " ex_nat n = ( n )" + + +(*val ex_int : ii -> integer*) + +definition ex_int :: " int \<Rightarrow> int " where + " ex_int n = ( n )" + + +(*val coerce_int_nat : ii -> M ii*) + +definition coerce_int_nat :: " int \<Rightarrow>((register_value),(int),(exception))monad " where + " coerce_int_nat x = ( assert_exp True ('''') \<then> return x )" + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition EXTS :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " EXTS (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" + + +definition EXTZ :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))" + + +definition zopz0zIzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \<Rightarrow> bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val vector64 : ii -> mword ty64*) + +definition vector64 :: " int \<Rightarrow>(64)Word.word " where + " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) + +definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where + " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" + + +(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) + +definition shift_right_arith64 :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word " where + " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = ( + (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in + (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))" + + +(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) + +definition shift_right_arith32 :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word " where + " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = ( + (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in + (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))" + + +definition xlen :: " int " where + " xlen = ( (( 64 :: int)::ii))" + + +definition xlen_max_unsigned :: " int " where + " xlen_max_unsigned = ( ((pow2 xlen)) - (( 1 :: int)::ii))" + + +definition xlen_max_signed :: " int " where + " xlen_max_signed = ( ((pow2 ((xlen - (( 1 :: int)::ii))))) - (( 1 :: int)::ii))" + + +definition xlen_min_signed :: " int " where + " xlen_min_signed = ( (( 0 :: int)::ii) - ((pow2 ((xlen - (( 1 :: int)::ii))))))" + + +(*val regbits_to_regno : mword ty5 -> integer*) + +definition regbits_to_regno :: "(5)Word.word \<Rightarrow> int " where + " regbits_to_regno b = ( + (let r = (Word.uint b) in + r))" + + +(*val creg2reg_bits : mword ty3 -> mword ty5*) + +definition creg2reg_bits :: "(3)Word.word \<Rightarrow>(5)Word.word " where + " creg2reg_bits creg = ( (concat_vec (vec_of_bits [B0,B1] :: 2 Word.word) creg :: 5 Word.word))" + + +definition zreg :: "(5)Word.word " where + " zreg = ( (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))" + + +definition ra :: "(5)Word.word " where + " ra = ( (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word))" + + +definition sp :: "(5)Word.word " where + " sp = ( (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word))" + + +(*val rX : integer -> M (mword ty64)*) + +definition rX :: " int \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " rX l__81 = ( + if (((l__81 = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlenbits list) . + return ((access_list_dec w__0 l__81 :: 64 Word.word))))" + + +(*val wX : integer -> mword ty64 -> M unit*) + +definition wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " wX r v = ( + if (((r \<noteq> (( 0 :: int)::ii)))) then + read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list)) \<then> + return ((prerr_endline + (((op@) (''x'') + (((op@) ((stringFromInteger r)) + (((op@) ('' <- '') ((string_of_vec v))))))))))) + else return () )" + + +(*val reg_name_abi : mword ty5 -> string*) + +definition reg_name_abi :: "(5)Word.word \<Rightarrow> string " where + " reg_name_abi r = ( + (let b__0 = r in + if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) then + (''zero'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''ra'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''sp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''gp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''tp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''t0'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''t1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''t2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''fp'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''a0'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''a1'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''a2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''a3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''a4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B1,B1] :: 5 Word.word)))))) then + (''a5'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) then + (''a6'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B1] :: 5 Word.word)))))) then + (''a7'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B0] :: 5 Word.word)))))) then + (''s2'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B1,B1] :: 5 Word.word)))))) then + (''s3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) then + (''s4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B1] :: 5 Word.word)))))) then + (''s5'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B0] :: 5 Word.word)))))) then + (''s6'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B1,B1] :: 5 Word.word)))))) then + (''s7'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) then + (''s8'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B1] :: 5 Word.word)))))) then + (''s9'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B0] :: 5 Word.word)))))) then + (''s10'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B1,B1] :: 5 Word.word)))))) then + (''s11'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) then + (''t3'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B1] :: 5 Word.word)))))) then + (''t4'') + else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word)))))) then + (''t5'') + else (''t6'')))" + + +(*val Architecture_of_num : integer -> Architecture*) + +definition Architecture_of_num :: " int \<Rightarrow> Architecture " where + " Architecture_of_num arg0 = ( + (let l__79 = arg0 in + if (((l__79 = (( 0 :: int)::ii)))) then RV32 + else if (((l__79 = (( 1 :: int)::ii)))) then RV64 + else RV128))" + + +(*val num_of_Architecture : Architecture -> integer*) + +fun num_of_Architecture :: " Architecture \<Rightarrow> int " where + " num_of_Architecture RV32 = ( (( 0 :: int)::ii))" +|" num_of_Architecture RV64 = ( (( 1 :: int)::ii))" +|" num_of_Architecture RV128 = ( (( 2 :: int)::ii))" + + +(*val architecture : mword ty2 -> maybe Architecture*) + +definition architecture :: "(2)Word.word \<Rightarrow>(Architecture)option " where + " architecture a = ( + (let b__0 = a in + if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Some RV32 + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Some RV64 + else if (((b__0 = (vec_of_bits [B1,B1] :: 2 Word.word)))) then Some RV128 + else None))" + + +(*val arch_to_bits : Architecture -> mword ty2*) + +fun arch_to_bits :: " Architecture \<Rightarrow>(2)Word.word " where + " arch_to_bits RV32 = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" arch_to_bits RV64 = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" arch_to_bits RV128 = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val Privilege_of_num : integer -> Privilege*) + +definition Privilege_of_num :: " int \<Rightarrow> Privilege " where + " Privilege_of_num arg0 = ( + (let l__77 = arg0 in + if (((l__77 = (( 0 :: int)::ii)))) then User + else if (((l__77 = (( 1 :: int)::ii)))) then Supervisor + else Machine))" + + +(*val num_of_Privilege : Privilege -> integer*) + +fun num_of_Privilege :: " Privilege \<Rightarrow> int " where + " num_of_Privilege User = ( (( 0 :: int)::ii))" +|" num_of_Privilege Supervisor = ( (( 1 :: int)::ii))" +|" num_of_Privilege Machine = ( (( 2 :: int)::ii))" + + +(*val privLevel_to_bits : Privilege -> mword ty2*) + +fun privLevel_to_bits :: " Privilege \<Rightarrow>(2)Word.word " where + " privLevel_to_bits User = ( (vec_of_bits [B0,B0] :: 2 Word.word))" +|" privLevel_to_bits Supervisor = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" privLevel_to_bits Machine = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val privLevel_of_bits : mword ty2 -> Privilege*) + +definition privLevel_of_bits :: "(2)Word.word \<Rightarrow> Privilege " where + " privLevel_of_bits p = ( + (let b__0 = p in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then User + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Supervisor + else Machine))" + + +(*val privLevel_to_str : Privilege -> string*) + +fun privLevel_to_str :: " Privilege \<Rightarrow> string " where + " privLevel_to_str User = ( (''U''))" +|" privLevel_to_str Supervisor = ( (''S''))" +|" privLevel_to_str Machine = ( (''M''))" + + +(*val AccessType_of_num : integer -> AccessType*) + +definition AccessType_of_num :: " int \<Rightarrow> AccessType " where + " AccessType_of_num arg0 = ( + (let l__74 = arg0 in + if (((l__74 = (( 0 :: int)::ii)))) then Read + else if (((l__74 = (( 1 :: int)::ii)))) then Write + else if (((l__74 = (( 2 :: int)::ii)))) then ReadWrite + else Execute))" + + +(*val num_of_AccessType : AccessType -> integer*) + +fun num_of_AccessType :: " AccessType \<Rightarrow> int " where + " num_of_AccessType Read = ( (( 0 :: int)::ii))" +|" num_of_AccessType Write = ( (( 1 :: int)::ii))" +|" num_of_AccessType ReadWrite = ( (( 2 :: int)::ii))" +|" num_of_AccessType Execute = ( (( 3 :: int)::ii))" + + +(*val ReadType_of_num : integer -> ReadType*) + +definition ReadType_of_num :: " int \<Rightarrow> ReadType " where + " ReadType_of_num arg0 = ( + (let l__73 = arg0 in + if (((l__73 = (( 0 :: int)::ii)))) then Instruction + else Data))" + + +(*val num_of_ReadType : ReadType -> integer*) + +fun num_of_ReadType :: " ReadType \<Rightarrow> int " where + " num_of_ReadType Instruction = ( (( 0 :: int)::ii))" +|" num_of_ReadType Data = ( (( 1 :: int)::ii))" + + +(*val ExceptionType_of_num : integer -> ExceptionType*) + +definition ExceptionType_of_num :: " int \<Rightarrow> ExceptionType " where + " ExceptionType_of_num arg0 = ( + (let l__58 = arg0 in + if (((l__58 = (( 0 :: int)::ii)))) then E_Fetch_Addr_Align + else if (((l__58 = (( 1 :: int)::ii)))) then E_Fetch_Access_Fault + else if (((l__58 = (( 2 :: int)::ii)))) then E_Illegal_Instr + else if (((l__58 = (( 3 :: int)::ii)))) then E_Breakpoint + else if (((l__58 = (( 4 :: int)::ii)))) then E_Load_Addr_Align + else if (((l__58 = (( 5 :: int)::ii)))) then E_Load_Access_Fault + else if (((l__58 = (( 6 :: int)::ii)))) then E_SAMO_Addr_Align + else if (((l__58 = (( 7 :: int)::ii)))) then E_SAMO_Access_Fault + else if (((l__58 = (( 8 :: int)::ii)))) then E_U_EnvCall + else if (((l__58 = (( 9 :: int)::ii)))) then E_S_EnvCall + else if (((l__58 = (( 10 :: int)::ii)))) then E_Reserved_10 + else if (((l__58 = (( 11 :: int)::ii)))) then E_M_EnvCall + else if (((l__58 = (( 12 :: int)::ii)))) then E_Fetch_Page_Fault + else if (((l__58 = (( 13 :: int)::ii)))) then E_Load_Page_Fault + else if (((l__58 = (( 14 :: int)::ii)))) then E_Reserved_14 + else E_SAMO_Page_Fault))" + + +(*val num_of_ExceptionType : ExceptionType -> integer*) + +fun num_of_ExceptionType :: " ExceptionType \<Rightarrow> int " where + " num_of_ExceptionType E_Fetch_Addr_Align = ( (( 0 :: int)::ii))" +|" num_of_ExceptionType E_Fetch_Access_Fault = ( (( 1 :: int)::ii))" +|" num_of_ExceptionType E_Illegal_Instr = ( (( 2 :: int)::ii))" +|" num_of_ExceptionType E_Breakpoint = ( (( 3 :: int)::ii))" +|" num_of_ExceptionType E_Load_Addr_Align = ( (( 4 :: int)::ii))" +|" num_of_ExceptionType E_Load_Access_Fault = ( (( 5 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Addr_Align = ( (( 6 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Access_Fault = ( (( 7 :: int)::ii))" +|" num_of_ExceptionType E_U_EnvCall = ( (( 8 :: int)::ii))" +|" num_of_ExceptionType E_S_EnvCall = ( (( 9 :: int)::ii))" +|" num_of_ExceptionType E_Reserved_10 = ( (( 10 :: int)::ii))" +|" num_of_ExceptionType E_M_EnvCall = ( (( 11 :: int)::ii))" +|" num_of_ExceptionType E_Fetch_Page_Fault = ( (( 12 :: int)::ii))" +|" num_of_ExceptionType E_Load_Page_Fault = ( (( 13 :: int)::ii))" +|" num_of_ExceptionType E_Reserved_14 = ( (( 14 :: int)::ii))" +|" num_of_ExceptionType E_SAMO_Page_Fault = ( (( 15 :: int)::ii))" + + +(*val exceptionType_to_bits : ExceptionType -> mword ty4*) + +fun exceptionType_to_bits :: " ExceptionType \<Rightarrow>(4)Word.word " where + " exceptionType_to_bits E_Fetch_Addr_Align = ( (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Fetch_Access_Fault = ( (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Illegal_Instr = ( (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Breakpoint = ( (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Addr_Align = ( (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Access_Fault = ( (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Addr_Align = ( (vec_of_bits [B0,B1,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Access_Fault = ( (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_U_EnvCall = ( (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_S_EnvCall = ( (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Reserved_10 = ( (vec_of_bits [B1,B0,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_M_EnvCall = ( (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Fetch_Page_Fault = ( (vec_of_bits [B1,B1,B0,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_Load_Page_Fault = ( (vec_of_bits [B1,B1,B0,B1] :: 4 Word.word))" +|" exceptionType_to_bits E_Reserved_14 = ( (vec_of_bits [B1,B1,B1,B0] :: 4 Word.word))" +|" exceptionType_to_bits E_SAMO_Page_Fault = ( (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word))" + + +(*val exceptionType_to_str : ExceptionType -> string*) + +fun exceptionType_to_str :: " ExceptionType \<Rightarrow> string " where + " exceptionType_to_str E_Fetch_Addr_Align = ( (''fisaligned-fetch''))" +|" exceptionType_to_str E_Fetch_Access_Fault = ( (''fetch-access-fault''))" +|" exceptionType_to_str E_Illegal_Instr = ( (''illegal-instruction''))" +|" exceptionType_to_str E_Breakpoint = ( (''breakpoint''))" +|" exceptionType_to_str E_Load_Addr_Align = ( (''misaligned-load''))" +|" exceptionType_to_str E_Load_Access_Fault = ( (''load-access-fault''))" +|" exceptionType_to_str E_SAMO_Addr_Align = ( (''misaliged-store/amo''))" +|" exceptionType_to_str E_SAMO_Access_Fault = ( (''store/amo-access-fault''))" +|" exceptionType_to_str E_U_EnvCall = ( (''u-call''))" +|" exceptionType_to_str E_S_EnvCall = ( (''s-call''))" +|" exceptionType_to_str E_Reserved_10 = ( (''reserved-0''))" +|" exceptionType_to_str E_M_EnvCall = ( (''m-call''))" +|" exceptionType_to_str E_Fetch_Page_Fault = ( (''fetch-page-fault''))" +|" exceptionType_to_str E_Load_Page_Fault = ( (''load-page-fault''))" +|" exceptionType_to_str E_Reserved_14 = ( (''reserved-1''))" +|" exceptionType_to_str E_SAMO_Page_Fault = ( (''store/amo-page-fault''))" + + +(*val InterruptType_of_num : integer -> InterruptType*) + +definition InterruptType_of_num :: " int \<Rightarrow> InterruptType " where + " InterruptType_of_num arg0 = ( + (let l__50 = arg0 in + if (((l__50 = (( 0 :: int)::ii)))) then I_U_Software + else if (((l__50 = (( 1 :: int)::ii)))) then I_S_Software + else if (((l__50 = (( 2 :: int)::ii)))) then I_M_Software + else if (((l__50 = (( 3 :: int)::ii)))) then I_U_Timer + else if (((l__50 = (( 4 :: int)::ii)))) then I_S_Timer + else if (((l__50 = (( 5 :: int)::ii)))) then I_M_Timer + else if (((l__50 = (( 6 :: int)::ii)))) then I_U_External + else if (((l__50 = (( 7 :: int)::ii)))) then I_S_External + else I_M_External))" + + +(*val num_of_InterruptType : InterruptType -> integer*) + +fun num_of_InterruptType :: " InterruptType \<Rightarrow> int " where + " num_of_InterruptType I_U_Software = ( (( 0 :: int)::ii))" +|" num_of_InterruptType I_S_Software = ( (( 1 :: int)::ii))" +|" num_of_InterruptType I_M_Software = ( (( 2 :: int)::ii))" +|" num_of_InterruptType I_U_Timer = ( (( 3 :: int)::ii))" +|" num_of_InterruptType I_S_Timer = ( (( 4 :: int)::ii))" +|" num_of_InterruptType I_M_Timer = ( (( 5 :: int)::ii))" +|" num_of_InterruptType I_U_External = ( (( 6 :: int)::ii))" +|" num_of_InterruptType I_S_External = ( (( 7 :: int)::ii))" +|" num_of_InterruptType I_M_External = ( (( 8 :: int)::ii))" + + +(*val interruptType_to_bits : InterruptType -> mword ty4*) + +fun interruptType_to_bits :: " InterruptType \<Rightarrow>(4)Word.word " where + " interruptType_to_bits I_U_Software = ( (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_Software = ( (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_Software = ( (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))" +|" interruptType_to_bits I_U_Timer = ( (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_Timer = ( (vec_of_bits [B0,B1,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_Timer = ( (vec_of_bits [B0,B1,B1,B1] :: 4 Word.word))" +|" interruptType_to_bits I_U_External = ( (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word))" +|" interruptType_to_bits I_S_External = ( (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word))" +|" interruptType_to_bits I_M_External = ( (vec_of_bits [B1,B0,B1,B1] :: 4 Word.word))" + + +(*val TrapVectorMode_of_num : integer -> TrapVectorMode*) + +definition TrapVectorMode_of_num :: " int \<Rightarrow> TrapVectorMode " where + " TrapVectorMode_of_num arg0 = ( + (let l__48 = arg0 in + if (((l__48 = (( 0 :: int)::ii)))) then TV_Direct + else if (((l__48 = (( 1 :: int)::ii)))) then TV_Vector + else TV_Reserved))" + + +(*val num_of_TrapVectorMode : TrapVectorMode -> integer*) + +fun num_of_TrapVectorMode :: " TrapVectorMode \<Rightarrow> int " where + " num_of_TrapVectorMode TV_Direct = ( (( 0 :: int)::ii))" +|" num_of_TrapVectorMode TV_Vector = ( (( 1 :: int)::ii))" +|" num_of_TrapVectorMode TV_Reserved = ( (( 2 :: int)::ii))" + + +(*val trapVectorMode_of_bits : mword ty2 -> TrapVectorMode*) + +definition trapVectorMode_of_bits :: "(2)Word.word \<Rightarrow> TrapVectorMode " where + " trapVectorMode_of_bits m = ( + (let b__0 = m in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then TV_Direct + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then TV_Vector + else TV_Reserved))" + + +(*val not_implemented : forall 'a. string -> M 'a*) + +definition not_implemented :: " string \<Rightarrow>((register_value),'a,(exception))monad " where + " not_implemented message = ( throw (Error_not_implemented message))" + + +(*val internal_error : forall 'a. string -> M 'a*) + +definition internal_error :: " string \<Rightarrow>((register_value),'a,(exception))monad " where + " internal_error s = ( assert_exp False s \<then> throw (Error_internal_error () ))" + + +(*val ExtStatus_of_num : integer -> ExtStatus*) + +definition ExtStatus_of_num :: " int \<Rightarrow> ExtStatus " where + " ExtStatus_of_num arg0 = ( + (let l__45 = arg0 in + if (((l__45 = (( 0 :: int)::ii)))) then Off + else if (((l__45 = (( 1 :: int)::ii)))) then Initial + else if (((l__45 = (( 2 :: int)::ii)))) then Clean + else Dirty))" + + +(*val num_of_ExtStatus : ExtStatus -> integer*) + +fun num_of_ExtStatus :: " ExtStatus \<Rightarrow> int " where + " num_of_ExtStatus Off = ( (( 0 :: int)::ii))" +|" num_of_ExtStatus Initial = ( (( 1 :: int)::ii))" +|" num_of_ExtStatus Clean = ( (( 2 :: int)::ii))" +|" num_of_ExtStatus Dirty = ( (( 3 :: int)::ii))" + + +(*val extStatus_to_bits : ExtStatus -> mword ty2*) + +fun extStatus_to_bits :: " ExtStatus \<Rightarrow>(2)Word.word " where + " extStatus_to_bits Off = ( (vec_of_bits [B0,B0] :: 2 Word.word))" +|" extStatus_to_bits Initial = ( (vec_of_bits [B0,B1] :: 2 Word.word))" +|" extStatus_to_bits Clean = ( (vec_of_bits [B1,B0] :: 2 Word.word))" +|" extStatus_to_bits Dirty = ( (vec_of_bits [B1,B1] :: 2 Word.word))" + + +(*val extStatus_of_bits : mword ty2 -> ExtStatus*) + +definition extStatus_of_bits :: "(2)Word.word \<Rightarrow> ExtStatus " where + " extStatus_of_bits e = ( + (let b__0 = e in + if (((b__0 = (vec_of_bits [B0,B0] :: 2 Word.word)))) then Off + else if (((b__0 = (vec_of_bits [B0,B1] :: 2 Word.word)))) then Initial + else if (((b__0 = (vec_of_bits [B1,B0] :: 2 Word.word)))) then Clean + else Dirty))" + + +(*val SATPMode_of_num : integer -> SATPMode*) + +definition SATPMode_of_num :: " int \<Rightarrow> SATPMode " where + " SATPMode_of_num arg0 = ( + (let l__43 = arg0 in + if (((l__43 = (( 0 :: int)::ii)))) then Sbare + else if (((l__43 = (( 1 :: int)::ii)))) then Sv32 + else Sv39))" + + +(*val num_of_SATPMode : SATPMode -> integer*) + +fun num_of_SATPMode :: " SATPMode \<Rightarrow> int " where + " num_of_SATPMode Sbare = ( (( 0 :: int)::ii))" +|" num_of_SATPMode Sv32 = ( (( 1 :: int)::ii))" +|" num_of_SATPMode Sv39 = ( (( 2 :: int)::ii))" + + +(*val satpMode_of_bits : Architecture -> mword ty4 -> maybe SATPMode*) + +definition satpMode_of_bits :: " Architecture \<Rightarrow>(4)Word.word \<Rightarrow>(SATPMode)option " where + " satpMode_of_bits (g__113 :: Architecture) (b__0 :: satp_mode) = ( Some Sbare )" + + +(*val uop_of_num : integer -> uop*) + +definition uop_of_num :: " int \<Rightarrow> uop " where + " uop_of_num arg0 = ( + (let l__42 = arg0 in + if (((l__42 = (( 0 :: int)::ii)))) then RISCV_LUI + else RISCV_AUIPC))" + + +(*val num_of_uop : uop -> integer*) + +fun num_of_uop :: " uop \<Rightarrow> int " where + " num_of_uop RISCV_LUI = ( (( 0 :: int)::ii))" +|" num_of_uop RISCV_AUIPC = ( (( 1 :: int)::ii))" + + +(*val bop_of_num : integer -> bop*) + +definition bop_of_num :: " int \<Rightarrow> bop " where + " bop_of_num arg0 = ( + (let l__37 = arg0 in + if (((l__37 = (( 0 :: int)::ii)))) then RISCV_BEQ + else if (((l__37 = (( 1 :: int)::ii)))) then RISCV_BNE + else if (((l__37 = (( 2 :: int)::ii)))) then RISCV_BLT + else if (((l__37 = (( 3 :: int)::ii)))) then RISCV_BGE + else if (((l__37 = (( 4 :: int)::ii)))) then RISCV_BLTU + else RISCV_BGEU))" + + +(*val num_of_bop : bop -> integer*) + +fun num_of_bop :: " bop \<Rightarrow> int " where + " num_of_bop RISCV_BEQ = ( (( 0 :: int)::ii))" +|" num_of_bop RISCV_BNE = ( (( 1 :: int)::ii))" +|" num_of_bop RISCV_BLT = ( (( 2 :: int)::ii))" +|" num_of_bop RISCV_BGE = ( (( 3 :: int)::ii))" +|" num_of_bop RISCV_BLTU = ( (( 4 :: int)::ii))" +|" num_of_bop RISCV_BGEU = ( (( 5 :: int)::ii))" + + +(*val iop_of_num : integer -> iop*) + +definition iop_of_num :: " int \<Rightarrow> iop " where + " iop_of_num arg0 = ( + (let l__32 = arg0 in + if (((l__32 = (( 0 :: int)::ii)))) then RISCV_ADDI + else if (((l__32 = (( 1 :: int)::ii)))) then RISCV_SLTI + else if (((l__32 = (( 2 :: int)::ii)))) then RISCV_SLTIU + else if (((l__32 = (( 3 :: int)::ii)))) then RISCV_XORI + else if (((l__32 = (( 4 :: int)::ii)))) then RISCV_ORI + else RISCV_ANDI))" + + +(*val num_of_iop : iop -> integer*) + +fun num_of_iop :: " iop \<Rightarrow> int " where + " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))" +|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))" +|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))" +|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))" +|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))" +|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))" + + +(*val sop_of_num : integer -> sop*) + +definition sop_of_num :: " int \<Rightarrow> sop " where + " sop_of_num arg0 = ( + (let l__30 = arg0 in + if (((l__30 = (( 0 :: int)::ii)))) then RISCV_SLLI + else if (((l__30 = (( 1 :: int)::ii)))) then RISCV_SRLI + else RISCV_SRAI))" + + +(*val num_of_sop : sop -> integer*) + +fun num_of_sop :: " sop \<Rightarrow> int " where + " num_of_sop RISCV_SLLI = ( (( 0 :: int)::ii))" +|" num_of_sop RISCV_SRLI = ( (( 1 :: int)::ii))" +|" num_of_sop RISCV_SRAI = ( (( 2 :: int)::ii))" + + +(*val rop_of_num : integer -> rop*) + +definition rop_of_num :: " int \<Rightarrow> rop " where + " rop_of_num arg0 = ( + (let l__21 = arg0 in + if (((l__21 = (( 0 :: int)::ii)))) then RISCV_ADD + else if (((l__21 = (( 1 :: int)::ii)))) then RISCV_SUB + else if (((l__21 = (( 2 :: int)::ii)))) then RISCV_SLL + else if (((l__21 = (( 3 :: int)::ii)))) then RISCV_SLT + else if (((l__21 = (( 4 :: int)::ii)))) then RISCV_SLTU + else if (((l__21 = (( 5 :: int)::ii)))) then RISCV_XOR + else if (((l__21 = (( 6 :: int)::ii)))) then RISCV_SRL + else if (((l__21 = (( 7 :: int)::ii)))) then RISCV_SRA + else if (((l__21 = (( 8 :: int)::ii)))) then RISCV_OR + else RISCV_AND))" + + +(*val num_of_rop : rop -> integer*) + +fun num_of_rop :: " rop \<Rightarrow> int " where + " num_of_rop RISCV_ADD = ( (( 0 :: int)::ii))" +|" num_of_rop RISCV_SUB = ( (( 1 :: int)::ii))" +|" num_of_rop RISCV_SLL = ( (( 2 :: int)::ii))" +|" num_of_rop RISCV_SLT = ( (( 3 :: int)::ii))" +|" num_of_rop RISCV_SLTU = ( (( 4 :: int)::ii))" +|" num_of_rop RISCV_XOR = ( (( 5 :: int)::ii))" +|" num_of_rop RISCV_SRL = ( (( 6 :: int)::ii))" +|" num_of_rop RISCV_SRA = ( (( 7 :: int)::ii))" +|" num_of_rop RISCV_OR = ( (( 8 :: int)::ii))" +|" num_of_rop RISCV_AND = ( (( 9 :: int)::ii))" + + +(*val ropw_of_num : integer -> ropw*) + +definition ropw_of_num :: " int \<Rightarrow> ropw " where + " ropw_of_num arg0 = ( + (let l__17 = arg0 in + if (((l__17 = (( 0 :: int)::ii)))) then RISCV_ADDW + else if (((l__17 = (( 1 :: int)::ii)))) then RISCV_SUBW + else if (((l__17 = (( 2 :: int)::ii)))) then RISCV_SLLW + else if (((l__17 = (( 3 :: int)::ii)))) then RISCV_SRLW + else RISCV_SRAW))" + + +(*val num_of_ropw : ropw -> integer*) + +fun num_of_ropw :: " ropw \<Rightarrow> int " where + " num_of_ropw RISCV_ADDW = ( (( 0 :: int)::ii))" +|" num_of_ropw RISCV_SUBW = ( (( 1 :: int)::ii))" +|" num_of_ropw RISCV_SLLW = ( (( 2 :: int)::ii))" +|" num_of_ropw RISCV_SRLW = ( (( 3 :: int)::ii))" +|" num_of_ropw RISCV_SRAW = ( (( 4 :: int)::ii))" + + +(*val amoop_of_num : integer -> amoop*) + +definition amoop_of_num :: " int \<Rightarrow> amoop " where + " amoop_of_num arg0 = ( + (let l__9 = arg0 in + if (((l__9 = (( 0 :: int)::ii)))) then AMOSWAP + else if (((l__9 = (( 1 :: int)::ii)))) then AMOADD + else if (((l__9 = (( 2 :: int)::ii)))) then AMOXOR + else if (((l__9 = (( 3 :: int)::ii)))) then AMOAND + else if (((l__9 = (( 4 :: int)::ii)))) then AMOOR + else if (((l__9 = (( 5 :: int)::ii)))) then AMOMIN + else if (((l__9 = (( 6 :: int)::ii)))) then AMOMAX + else if (((l__9 = (( 7 :: int)::ii)))) then AMOMINU + else AMOMAXU))" + + +(*val num_of_amoop : amoop -> integer*) + +fun num_of_amoop :: " amoop \<Rightarrow> int " where + " num_of_amoop AMOSWAP = ( (( 0 :: int)::ii))" +|" num_of_amoop AMOADD = ( (( 1 :: int)::ii))" +|" num_of_amoop AMOXOR = ( (( 2 :: int)::ii))" +|" num_of_amoop AMOAND = ( (( 3 :: int)::ii))" +|" num_of_amoop AMOOR = ( (( 4 :: int)::ii))" +|" num_of_amoop AMOMIN = ( (( 5 :: int)::ii))" +|" num_of_amoop AMOMAX = ( (( 6 :: int)::ii))" +|" num_of_amoop AMOMINU = ( (( 7 :: int)::ii))" +|" num_of_amoop AMOMAXU = ( (( 8 :: int)::ii))" + + +(*val csrop_of_num : integer -> csrop*) + +definition csrop_of_num :: " int \<Rightarrow> csrop " where + " csrop_of_num arg0 = ( + (let l__7 = arg0 in + if (((l__7 = (( 0 :: int)::ii)))) then CSRRW + else if (((l__7 = (( 1 :: int)::ii)))) then CSRRS + else CSRRC))" + + +(*val num_of_csrop : csrop -> integer*) + +fun num_of_csrop :: " csrop \<Rightarrow> int " where + " num_of_csrop CSRRW = ( (( 0 :: int)::ii))" +|" num_of_csrop CSRRS = ( (( 1 :: int)::ii))" +|" num_of_csrop CSRRC = ( (( 2 :: int)::ii))" + + +(*val word_width_of_num : integer -> word_width*) + +definition word_width_of_num :: " int \<Rightarrow> word_width " where + " word_width_of_num arg0 = ( + (let l__4 = arg0 in + if (((l__4 = (( 0 :: int)::ii)))) then BYTE + else if (((l__4 = (( 1 :: int)::ii)))) then HALF + else if (((l__4 = (( 2 :: int)::ii)))) then WORD + else DOUBLE))" + + +(*val num_of_word_width : word_width -> integer*) + +fun num_of_word_width :: " word_width \<Rightarrow> int " where + " num_of_word_width BYTE = ( (( 0 :: int)::ii))" +|" num_of_word_width HALF = ( (( 1 :: int)::ii))" +|" num_of_word_width WORD = ( (( 2 :: int)::ii))" +|" num_of_word_width DOUBLE = ( (( 3 :: int)::ii))" + + +(*val is_aligned_addr : mword ty64 -> integer -> bool*) + +definition is_aligned_addr :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool " where + " is_aligned_addr (addr :: xlenbits) (width :: int) = ( + (((ex_int ((hardware_mod ((Word.uint addr)) width)))) = (( 0 :: int)::ii)))" + + +(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => ReadType -> mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition checked_mem_read :: " ReadType \<Rightarrow>(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " checked_mem_read (t :: ReadType) (addr :: xlenbits) (width :: int) = ( + (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 :: + (( 'int8_times_n::len)Word.word)option) . + return ((case (t, w__0) of + (Instruction, None) => MemException E_Fetch_Access_Fault + | (Data, None) => MemException E_Load_Access_Fault + | (_, Some (v)) => MemValue v + ))))" + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition MEMr :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr addr width = ( (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_strong_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_strong_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +definition MEMr_reserved_strong_acquire :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " MEMr_reserved_strong_acquire addr width = ( + (checked_mem_read Data addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M))" + + +(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult (mword 'int8_times_n))*) + +definition mem_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)MemoryOpResult),(exception))monad " where + " mem_read addr width aq rl res = ( + if ((((((aq \<or> res))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_Load_Addr_Align) + else + (case (aq, rl, res) of + (False, False, False) => (MEMr addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, False) => (MEMr_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, False, True) => + (MEMr_reserved addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (True, False, True) => + (MEMr_reserved_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, False) => throw (Error_not_implemented (''load.rl'')) + | (True, True, False) => + (MEMr_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + | (False, True, True) => throw (Error_not_implemented (''lr.rl'')) + | (True, True, True) => + (MEMr_reserved_strong_acquire addr width :: ( (( 'int8_times_n::len)Word.word)MemoryOpResult) M) + ))" + + +(*val mem_write_ea : mword ty64 -> integer -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_ea :: "(64)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_ea addr width aq rl con = ( + if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => MEMea addr width \<then> return (MemValue () ) + | (False, True, False) => MEMea_release addr width \<then> return (MemValue () ) + | (False, False, True) => MEMea_conditional addr width \<then> return (MemValue () ) + | (False, True, True) => MEMea_conditional_release addr width \<then> return (MemValue () ) + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMea_strong_release addr width \<then> return (MemValue () ) + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMea_conditional_strong_release addr width \<then> return (MemValue () ) + ))" + + +(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition checked_mem_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " checked_mem_write (addr :: xlenbits) (width :: int) (data :: 'int8_times_n bits) = ( + RISCV_write addr width data \<bind> (\<lambda> (w__0 :: bool) . + return (if w__0 then MemValue () + else MemException E_SAMO_Access_Fault)))" + + +(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M (MemoryOpResult unit)*) + +definition MEMval :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_strong_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_release addr width data = ( checked_mem_write addr width data )" + + +definition MEMval_conditional_strong_release :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " MEMval_conditional_strong_release addr width data = ( checked_mem_write addr width data )" + + +(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> bool -> bool -> bool -> M (MemoryOpResult unit)*) + +definition mem_write_value :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),((unit)MemoryOpResult),(exception))monad " where + " mem_write_value addr width value1 aq rl con = ( + if ((((((rl \<or> con))) \<and> ((\<not> ((is_aligned_addr addr width))))))) then + return (MemException E_SAMO_Addr_Align) + else + (case (aq, rl, con) of + (False, False, False) => MEMval addr width value1 + | (False, True, False) => MEMval_release addr width value1 + | (False, False, True) => MEMval_conditional addr width value1 + | (False, True, True) => MEMval_conditional_release addr width value1 + | (True, False, False) => throw (Error_not_implemented (''store.aq'')) + | (True, True, False) => MEMval_strong_release addr width value1 + | (True, False, True) => throw (Error_not_implemented (''sc.aq'')) + | (True, True, True) => MEMval_conditional_strong_release addr width value1 + ))" + + +(*val _get_Misa : Misa -> mword ty64*) + +fun get_Misa :: " Misa \<Rightarrow>(64)Word.word " where + " get_Misa (Mk_Misa (v)) = ( v )" + + +(*val _set_Misa : register_ref regstate register_value Misa -> mword ty64 -> M unit*) + +definition set_Misa :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Misa v) in + write_reg r_ref r)))" + + +(*val _get_SV39_PTE : SV39_PTE -> mword ty64*) + +(*val _set_SV39_PTE : register_ref regstate register_value SV39_PTE -> mword ty64 -> M unit*) + +(*val _get_Misa_MXL : Misa -> mword ty2*) + +fun get_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word " where + " get_Misa_MXL (Mk_Misa (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Misa_MXL : register_ref regstate register_value Misa -> mword ty2 -> M unit*) + +definition set_Misa_MXL :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_MXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 62 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_MXL : Misa -> mword ty2 -> Misa*) + +fun update_Misa_MXL :: " Misa \<Rightarrow>(2)Word.word \<Rightarrow> Misa " where + " update_Misa_MXL (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 62 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_Z : Misa -> mword ty1*) + +fun get_Misa_Z :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Z (Mk_Misa (v)) = ( (subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Z : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Z :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_Z r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 25 :: int)::ii) (( 25 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Z : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Z :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Z (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 25 :: int)::ii) (( 25 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_Y : Misa -> mword ty1*) + +fun get_Misa_Y :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Y (Mk_Misa (v)) = ( (subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Y : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Y :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_Y r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 24 :: int)::ii) (( 24 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Y : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Y :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Y (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 24 :: int)::ii) (( 24 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_X : Misa -> mword ty1*) + +fun get_Misa_X :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_X (Mk_Misa (v)) = ( (subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_X : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_X :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_X r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 23 :: int)::ii) (( 23 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_X : Misa -> mword ty1 -> Misa*) + +fun update_Misa_X :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_X (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 23 :: int)::ii) (( 23 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_X : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_X : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_X : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_W : Misa -> mword ty1*) + +fun get_Misa_W :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_W (Mk_Misa (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_W : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_W :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_W r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_W : Misa -> mword ty1 -> Misa*) + +fun update_Misa_W :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_W (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_W : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_W : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_W : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_V : Misa -> mword ty1*) + +fun get_Misa_V :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_V (Mk_Misa (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_V : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_V :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_V r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_V : Misa -> mword ty1 -> Misa*) + +fun update_Misa_V :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_V (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_V : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_V : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_V : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_U : Misa -> mword ty1*) + +fun get_Misa_U :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_U (Mk_Misa (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_U : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_U :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_U r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_U : Misa -> mword ty1 -> Misa*) + +fun update_Misa_U :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_U (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_U : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_U : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_U : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_T : Misa -> mword ty1*) + +fun get_Misa_T :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_T (Mk_Misa (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_T : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_T :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_T r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_T : Misa -> mword ty1 -> Misa*) + +fun update_Misa_T :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_T (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_S : Misa -> mword ty1*) + +fun get_Misa_S :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_S (Mk_Misa (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_S : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_S :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_S r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_S : Misa -> mword ty1 -> Misa*) + +fun update_Misa_S :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_S (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_R : Misa -> mword ty1*) + +fun get_Misa_R :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_R (Mk_Misa (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_R : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_R :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_R r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_R : Misa -> mword ty1 -> Misa*) + +fun update_Misa_R :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_R (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_R : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_R : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_R : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_Q : Misa -> mword ty1*) + +fun get_Misa_Q :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_Q (Mk_Misa (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_Q : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_Q :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_Q r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 16 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_Q : Misa -> mword ty1 -> Misa*) + +fun update_Misa_Q :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_Q (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 16 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_P : Misa -> mword ty1*) + +fun get_Misa_P :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_P (Mk_Misa (v)) = ( (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_P : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_P :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_P r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_P : Misa -> mword ty1 -> Misa*) + +fun update_Misa_P :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_P (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_O : Misa -> mword ty1*) + +fun get_Misa_O :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_O (Mk_Misa (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_O : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_O :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_O r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 14 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_O : Misa -> mword ty1 -> Misa*) + +fun update_Misa_O :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_O (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 14 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_N : Misa -> mword ty1*) + +fun get_Misa_N :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_N (Mk_Misa (v)) = ( (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_N : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_N :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_N r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_N : Misa -> mword ty1 -> Misa*) + +fun update_Misa_N :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_N (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_M : Misa -> mword ty1*) + +fun get_Misa_M :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_M (Mk_Misa (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_M : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_M :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_M r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_M : Misa -> mword ty1 -> Misa*) + +fun update_Misa_M :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_M (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_L : Misa -> mword ty1*) + +fun get_Misa_L :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_L (Mk_Misa (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_L : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_L :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_L r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_L : Misa -> mword ty1 -> Misa*) + +fun update_Misa_L :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_L (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_K : Misa -> mword ty1*) + +fun get_Misa_K :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_K (Mk_Misa (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_K : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_K :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_K r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_K : Misa -> mword ty1 -> Misa*) + +fun update_Misa_K :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_K (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_J : Misa -> mword ty1*) + +fun get_Misa_J :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_J (Mk_Misa (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_J : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_J :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_J r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_J : Misa -> mword ty1 -> Misa*) + +fun update_Misa_J :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_J (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_I : Misa -> mword ty1*) + +fun get_Misa_I :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_I (Mk_Misa (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_I : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_I :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_I r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_I : Misa -> mword ty1 -> Misa*) + +fun update_Misa_I :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_I (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_H : Misa -> mword ty1*) + +fun get_Misa_H :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_H (Mk_Misa (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_H : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_H :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_H r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_H : Misa -> mword ty1 -> Misa*) + +fun update_Misa_H :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_H (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_G : Misa -> mword ty1*) + +fun get_Misa_G :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_G (Mk_Misa (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_G : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_G :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_G r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_G : Misa -> mword ty1 -> Misa*) + +fun update_Misa_G :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_G (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_G : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_G : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_G : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_F : Misa -> mword ty1*) + +fun get_Misa_F :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_F (Mk_Misa (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_F : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_F :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_F r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_F : Misa -> mword ty1 -> Misa*) + +fun update_Misa_F :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_F (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_E : Misa -> mword ty1*) + +fun get_Misa_E :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_E (Mk_Misa (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_E : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_E :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_E r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_E : Misa -> mword ty1 -> Misa*) + +fun update_Misa_E :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_E (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_D : Misa -> mword ty1*) + +fun get_Misa_D :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_D (Mk_Misa (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_D : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_D :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_D r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_D : Misa -> mword ty1 -> Misa*) + +fun update_Misa_D :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_D (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_D : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_D : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_D : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val _get_Misa_C : Misa -> mword ty1*) + +fun get_Misa_C :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_C (Mk_Misa (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_C : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_C :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_C r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_C : Misa -> mword ty1 -> Misa*) + +fun update_Misa_C :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_C (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_B : Misa -> mword ty1*) + +fun get_Misa_B :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_B (Mk_Misa (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_B : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_B :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_B r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_B : Misa -> mword ty1 -> Misa*) + +fun update_Misa_B :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_B (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Misa_A : Misa -> mword ty1*) + +fun get_Misa_A :: " Misa \<Rightarrow>(1)Word.word " where + " get_Misa_A (Mk_Misa (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Misa_A : register_ref regstate register_value Misa -> mword ty1 -> M unit*) + +definition set_Misa_A :: "((regstate),(register_value),(Misa))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Misa_A r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Misa) . + (let r = ((get_Misa w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Misa r)))))" + + +(*val _update_Misa_A : Misa -> mword ty1 -> Misa*) + +fun update_Misa_A :: " Misa \<Rightarrow>(1)Word.word \<Rightarrow> Misa " where + " update_Misa_A (Mk_Misa (v)) x = ( + Mk_Misa ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_PTE_Bits_A : PTE_Bits -> mword ty1 -> PTE_Bits*) + +(*val _get_PTE_Bits_A : PTE_Bits -> mword ty1*) + +(*val _set_PTE_Bits_A : register_ref regstate register_value PTE_Bits -> mword ty1 -> M unit*) + +(*val legalize_misa : Misa -> mword ty64 -> Misa*) + +definition legalize_misa :: " Misa \<Rightarrow>(64)Word.word \<Rightarrow> Misa " where + " legalize_misa (m :: Misa) (v :: xlenbits) = ( m )" + + +(*val _get_Mstatus : Mstatus -> mword ty64*) + +fun get_Mstatus :: " Mstatus \<Rightarrow>(64)Word.word " where + " get_Mstatus (Mk_Mstatus (v)) = ( v )" + + +(*val _set_Mstatus : register_ref regstate register_value Mstatus -> mword ty64 -> M unit*) + +definition set_Mstatus :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Mstatus v) in + write_reg r_ref r)))" + + +(*val _get_Mstatus_SD : Mstatus -> mword ty1*) + +fun get_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SD (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SD : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SD :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SD r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SD : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SD :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SD (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SD : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SD : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SD : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SXL : Mstatus -> mword ty2*) + +fun get_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_SXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_SXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_SXL :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 35 :: int)::ii) (( 34 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SXL : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_SXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SXL (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 35 :: int)::ii) (( 34 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_UXL : Mstatus -> mword ty2*) + +fun get_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_UXL (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_UXL : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_UXL :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_UXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UXL : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_UXL :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UXL (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UXL : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_UXL : Sstatus -> mword ty2*) + +(*val _set_Sstatus_UXL : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_TSR : Mstatus -> mword ty1*) + +fun get_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TSR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TSR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TSR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_TSR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 22 :: int)::ii) (( 22 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TSR : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TSR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TSR (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 22 :: int)::ii) (( 22 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_TW : Mstatus -> mword ty1*) + +fun get_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TW (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TW : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TW :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_TW r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 21 :: int)::ii) (( 21 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TW : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TW :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TW (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 21 :: int)::ii) (( 21 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_TVM : Mstatus -> mword ty1*) + +fun get_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_TVM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_TVM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_TVM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_TVM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 20 :: int)::ii) (( 20 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_TVM : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_TVM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_TVM (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 20 :: int)::ii) (( 20 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_MXR : Mstatus -> mword ty1*) + +fun get_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MXR (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MXR : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MXR :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_MXR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MXR : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MXR :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MXR (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_MXR : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_MXR : Sstatus -> mword ty1*) + +(*val _set_Sstatus_MXR : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_SUM : Mstatus -> mword ty1*) + +fun get_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SUM (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SUM : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SUM :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SUM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SUM : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SUM :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SUM (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SUM : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SUM : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SUM : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPRV : Mstatus -> mword ty1*) + +fun get_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MPRV (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MPRV : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MPRV :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_MPRV r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 17 :: int)::ii) (( 17 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPRV : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MPRV :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPRV (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 17 :: int)::ii) (( 17 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_XS : Mstatus -> mword ty2*) + +fun get_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_XS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_XS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_XS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_XS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_XS : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_XS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_XS (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_XS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_XS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_XS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_FS : Mstatus -> mword ty2*) + +fun get_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_FS (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_FS : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_FS :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_FS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_FS : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_FS :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_FS (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_FS : Sstatus -> mword ty2 -> Sstatus*) + +(*val _get_Sstatus_FS : Sstatus -> mword ty2*) + +(*val _set_Sstatus_FS : register_ref regstate register_value Sstatus -> mword ty2 -> M unit*) + +(*val _get_Mstatus_MPP : Mstatus -> mword ty2*) + +fun get_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word " where + " get_Mstatus_MPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mstatus_MPP : register_ref regstate register_value Mstatus -> mword ty2 -> M unit*) + +definition set_Mstatus_MPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_MPP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPP : Mstatus -> mword ty2 -> Mstatus*) + +fun update_Mstatus_MPP :: " Mstatus \<Rightarrow>(2)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPP (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SPP : Mstatus -> mword ty1*) + +fun get_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SPP (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SPP : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SPP :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SPP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SPP : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SPP :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SPP (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SPP : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPP : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPP : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_MPIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SPIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UPIE : Mstatus -> mword ty1*) + +fun get_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_UPIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_UPIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_UPIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_UPIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UPIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_UPIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UPIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UPIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UPIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UPIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_MIE : Mstatus -> mword ty1*) + +fun get_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_MIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_MIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_MIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_MIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_MIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_MIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_MIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mstatus_SIE : Mstatus -> mword ty1*) + +fun get_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_SIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_SIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_SIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_SIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_SIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_SIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_SIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_SIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_SIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_SIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val _get_Mstatus_UIE : Mstatus -> mword ty1*) + +fun get_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word " where + " get_Mstatus_UIE (Mk_Mstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mstatus_UIE : register_ref regstate register_value Mstatus -> mword ty1 -> M unit*) + +definition set_Mstatus_UIE :: "((regstate),(register_value),(Mstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mstatus_UIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let r = ((get_Mstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mstatus r)))))" + + +(*val _update_Mstatus_UIE : Mstatus -> mword ty1 -> Mstatus*) + +fun update_Mstatus_UIE :: " Mstatus \<Rightarrow>(1)Word.word \<Rightarrow> Mstatus " where + " update_Mstatus_UIE (Mk_Mstatus (v)) x = ( + Mk_Mstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sstatus_UIE : Sstatus -> mword ty1 -> Sstatus*) + +(*val _get_Sstatus_UIE : Sstatus -> mword ty1*) + +(*val _set_Sstatus_UIE : register_ref regstate register_value Sstatus -> mword ty1 -> M unit*) + +(*val legalize_mstatus : Mstatus -> mword ty64 -> Mstatus*) + +definition legalize_mstatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus " where + " legalize_mstatus (o1 :: Mstatus) (v :: xlenbits) = ( + (let (m :: Mstatus) = (Mk_Mstatus v) in + (let m = (update_Mstatus_XS m ((extStatus_to_bits Off :: 2 Word.word))) in + (let m = + (update_Mstatus_SD m + ((bool_to_bits + ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m :: 2 Word.word)))) + :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word))))) \<or> (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m :: 2 Word.word)))) + :: 2 Word.word)) = ((extStatus_to_bits Dirty :: 2 Word.word)))))))) + :: 1 Word.word))) in + (let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1 :: 2 Word.word))) in + (let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1 :: 2 Word.word))) in + (let m = (update_Mstatus_UPIE m ((bool_to_bits False :: 1 Word.word))) in + update_Mstatus_UIE m ((bool_to_bits False :: 1 Word.word)))))))))" + + +(*val cur_Architecture : unit -> M Architecture*) + +definition cur_Architecture :: " unit \<Rightarrow>((register_value),(Architecture),(exception))monad " where + " cur_Architecture _ = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (case w__0 of + Machine => + read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) . return ((get_Misa_MXL w__1 :: 2 Word.word))) + | Supervisor => + read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . return ((get_Mstatus_SXL w__2 :: 2 Word.word))) + | User => + read_reg mstatus_ref \<bind> (\<lambda> (w__3 :: Mstatus) . return ((get_Mstatus_UXL w__3 :: 2 Word.word))) + ) \<bind> (\<lambda> (a :: arch_xlen) . + (case ((architecture a)) of + Some (a) => return a + | None => internal_error (''Invalid current architecture'') + ))))" + + +(*val in32BitMode : unit -> M bool*) + +definition in32BitMode :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " in32BitMode _ = ( cur_Architecture () \<bind> (\<lambda> (w__0 :: Architecture) . return (((w__0 = RV32)))))" + + +(*val haveAtomics : unit -> M bool*) + +definition haveAtomics :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " haveAtomics _ = ( + read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . + return (((((get_Misa_A w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveRVC : unit -> M bool*) + +definition haveRVC :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " haveRVC _ = ( + read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . + return (((((get_Misa_C w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveMulDiv : unit -> M bool*) + +definition haveMulDiv :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " haveMulDiv _ = ( + read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . + return (((((get_Misa_M w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))" + + +(*val haveFP : unit -> M bool*) + +definition haveFP :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " haveFP _ = ( + or_boolM + (read_reg misa_ref \<bind> (\<lambda> (w__0 :: Misa) . + return (((((get_Misa_F w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (read_reg misa_ref \<bind> (\<lambda> (w__1 :: Misa) . + return (((((get_Misa_D w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))))" + + +(*val _get_Minterrupts : Minterrupts -> mword ty64*) + +fun get_Minterrupts :: " Minterrupts \<Rightarrow>(64)Word.word " where + " get_Minterrupts (Mk_Minterrupts (v)) = ( v )" + + +(*val _set_Minterrupts : register_ref regstate register_value Minterrupts -> mword ty64 -> M unit*) + +definition set_Minterrupts :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Minterrupts v) in + write_reg r_ref r)))" + + +(*val _get_Minterrupts_MEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_MEI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 11 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 11 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_SEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_SEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_SEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_SEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_SEI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_SEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_SEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_SEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_SEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UEI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_UEI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_UEI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_UEI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_UEI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_UEI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_UEI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_UEI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_UEI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UEI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UEI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MTI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_MTI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MTI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MTI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_STI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_STI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_STI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_STI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_STI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_STI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_STI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_STI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_STI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_STI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_STI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_UTI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_UTI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_UTI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_UTI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_UTI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_UTI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_UTI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_UTI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_UTI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_UTI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_UTI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_MSI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_MSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_MSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_MSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_MSI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_MSI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_MSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_MSI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Minterrupts_SSI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_SSI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_SSI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_SSI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_SSI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_SSI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_SSI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_SSI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_SSI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_SSI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_SSI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val _get_Minterrupts_USI : Minterrupts -> mword ty1*) + +fun get_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word " where + " get_Minterrupts_USI (Mk_Minterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Minterrupts_USI : register_ref regstate register_value Minterrupts -> mword ty1 -> M unit*) + +definition set_Minterrupts_USI :: "((regstate),(register_value),(Minterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Minterrupts_USI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + (let r = ((get_Minterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Minterrupts r)))))" + + +(*val _update_Minterrupts_USI : Minterrupts -> mword ty1 -> Minterrupts*) + +fun update_Minterrupts_USI :: " Minterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Minterrupts " where + " update_Minterrupts_USI (Mk_Minterrupts (v)) x = ( + Mk_Minterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sinterrupts_USI : Sinterrupts -> mword ty1 -> Sinterrupts*) + +(*val _get_Sinterrupts_USI : Sinterrupts -> mword ty1*) + +(*val _set_Sinterrupts_USI : register_ref regstate register_value Sinterrupts -> mword ty1 -> M unit*) + +(*val legalize_mip : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mip :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " legalize_mip (o1 :: Minterrupts) (v :: xlenbits) = ( + (let v = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word))))))" + + +(*val legalize_mie : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mie :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " legalize_mie (o1 :: Minterrupts) (v :: xlenbits) = ( + (let v = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v :: 1 Word.word))) in + (let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v :: 1 Word.word))) in + (let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v :: 1 Word.word))) in + (let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v :: 1 Word.word))) in + update_Minterrupts_SSI m ((get_Minterrupts_SSI v :: 1 Word.word)))))))))" + + +(*val legalize_mideleg : Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_mideleg :: " Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " legalize_mideleg (o1 :: Minterrupts) (v :: xlenbits) = ( + (let m = (Mk_Minterrupts v) in + (let m = (update_Minterrupts_MEI m ((bool_to_bits False :: 1 Word.word))) in + (let m = (update_Minterrupts_MTI m ((bool_to_bits False :: 1 Word.word))) in + update_Minterrupts_MSI m ((bool_to_bits False :: 1 Word.word))))))" + + +(*val _get_Medeleg : Medeleg -> mword ty64*) + +fun get_Medeleg :: " Medeleg \<Rightarrow>(64)Word.word " where + " get_Medeleg (Mk_Medeleg (v)) = ( v )" + + +(*val _set_Medeleg : register_ref regstate register_value Medeleg -> mword ty64 -> M unit*) + +definition set_Medeleg :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Medeleg v) in + write_reg r_ref r)))" + + +(*val _get_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Page_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 15 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 15 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_Load_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Page_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 13 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 13 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Page_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Page_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Page_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 12 :: int)::ii) (( 12 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Page_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Page_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Page_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 12 :: int)::ii) (( 12 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_MEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_MEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_MEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_MEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_MEnvCall r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 10 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_MEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_MEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_MEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 10 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_SEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_SEnvCall r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Medeleg_UEnvCall : Medeleg -> mword ty1*) + +fun get_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_UEnvCall (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_UEnvCall : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_UEnvCall :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_UEnvCall r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_UEnvCall : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_UEnvCall :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_UEnvCall (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_UEnvCall : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_UEnvCall : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_UEnvCall : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_SAMO_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_SAMO_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_SAMO_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_SAMO_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_SAMO_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_SAMO_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_SAMO_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Load_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Load_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Load_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Load_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Load_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Load_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Load_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Load_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Load_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Breakpoint : Medeleg -> mword ty1*) + +fun get_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Breakpoint (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Breakpoint : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Breakpoint :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Breakpoint r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Breakpoint : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Breakpoint :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Breakpoint (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Breakpoint : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Breakpoint : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Breakpoint : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Illegal_Instr : Medeleg -> mword ty1*) + +fun get_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Illegal_Instr (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Illegal_Instr : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Illegal_Instr :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Illegal_Instr r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Illegal_Instr : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Illegal_Instr :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Illegal_Instr (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Illegal_Instr : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Illegal_Instr : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) = ( + (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Access_Fault : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Access_Fault : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Access_Fault :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Access_Fault (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Access_Fault : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Access_Fault : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val _get_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1*) + +fun get_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word " where + " get_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Medeleg_Fetch_Addr_Align : register_ref regstate register_value Medeleg -> mword ty1 -> M unit*) + +definition set_Medeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Medeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Medeleg_Fetch_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let r = ((get_Medeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Medeleg r)))))" + + +(*val _update_Medeleg_Fetch_Addr_Align : Medeleg -> mword ty1 -> Medeleg*) + +fun update_Medeleg_Fetch_Addr_Align :: " Medeleg \<Rightarrow>(1)Word.word \<Rightarrow> Medeleg " where + " update_Medeleg_Fetch_Addr_Align (Mk_Medeleg (v)) x = ( + Mk_Medeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1 -> Sedeleg*) + +(*val _get_Sedeleg_Fetch_Addr_Align : Sedeleg -> mword ty1*) + +(*val _set_Sedeleg_Fetch_Addr_Align : register_ref regstate register_value Sedeleg -> mword ty1 -> M unit*) + +(*val legalize_medeleg : Medeleg -> mword ty64 -> Medeleg*) + +definition legalize_medeleg :: " Medeleg \<Rightarrow>(64)Word.word \<Rightarrow> Medeleg " where + " legalize_medeleg (o1 :: Medeleg) (v :: xlenbits) = ( + (let m = (Mk_Medeleg v) in + update_Medeleg_MEnvCall m ((bool_to_bits False :: 1 Word.word))))" + + +(*val _get_Mtvec : Mtvec -> mword ty64*) + +fun get_Mtvec :: " Mtvec \<Rightarrow>(64)Word.word " where + " get_Mtvec (Mk_Mtvec (v)) = ( v )" + + +(*val _set_Mtvec : register_ref regstate register_value Mtvec -> mword ty64 -> M unit*) + +definition set_Mtvec :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mtvec r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Mtvec v) in + write_reg r_ref r)))" + + +(*val _get_Mtvec_Base : Mtvec -> mword ty62*) + +fun get_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word " where + " get_Mtvec_Base (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) :: 62 Word.word))" + + +(*val _set_Mtvec_Base : register_ref regstate register_value Mtvec -> mword ty62 -> M unit*) + +definition set_Mtvec_Base :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(62)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mtvec_Base r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . + (let r = ((get_Mtvec w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mtvec r)))))" + + +(*val _update_Mtvec_Base : Mtvec -> mword ty62 -> Mtvec*) + +fun update_Mtvec_Base :: " Mtvec \<Rightarrow>(62)Word.word \<Rightarrow> Mtvec " where + " update_Mtvec_Base (Mk_Mtvec (v)) x = ( + Mk_Mtvec ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mtvec_Mode : Mtvec -> mword ty2*) + +fun get_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word " where + " get_Mtvec_Mode (Mk_Mtvec (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word))" + + +(*val _set_Mtvec_Mode : register_ref regstate register_value Mtvec -> mword ty2 -> M unit*) + +definition set_Mtvec_Mode :: "((regstate),(register_value),(Mtvec))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mtvec_Mode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mtvec) . + (let r = ((get_Mtvec w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mtvec r)))))" + + +(*val _update_Mtvec_Mode : Mtvec -> mword ty2 -> Mtvec*) + +fun update_Mtvec_Mode :: " Mtvec \<Rightarrow>(2)Word.word \<Rightarrow> Mtvec " where + " update_Mtvec_Mode (Mk_Mtvec (v)) x = ( + Mk_Mtvec ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val _update_Satp64_Mode : Satp64 -> mword ty4 -> Satp64*) + +(*val _get_Satp64_Mode : Satp64 -> mword ty4*) + +(*val _set_Satp64_Mode : register_ref regstate register_value Satp64 -> mword ty4 -> M unit*) + +(*val legalize_tvec : Mtvec -> mword ty64 -> Mtvec*) + +definition legalize_tvec :: " Mtvec \<Rightarrow>(64)Word.word \<Rightarrow> Mtvec " where + " legalize_tvec (o1 :: Mtvec) (v :: xlenbits) = ( + (let v = (Mk_Mtvec v) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v :: 2 Word.word)))) of + TV_Direct => v + | TV_Vector => v + | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1 :: 2 Word.word)) + )))" + + +(*val _get_Mcause : Mcause -> mword ty64*) + +fun get_Mcause :: " Mcause \<Rightarrow>(64)Word.word " where + " get_Mcause (Mk_Mcause (v)) = ( v )" + + +(*val _set_Mcause : register_ref regstate register_value Mcause -> mword ty64 -> M unit*) + +definition set_Mcause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mcause r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Mcause v) in + write_reg r_ref r)))" + + +(*val _get_Mcause_IsInterrupt : Mcause -> mword ty1*) + +fun get_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word " where + " get_Mcause_IsInterrupt (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +(*val _set_Mcause_IsInterrupt : register_ref regstate register_value Mcause -> mword ty1 -> M unit*) + +definition set_Mcause_IsInterrupt :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mcause_IsInterrupt r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . + (let r = ((get_Mcause w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mcause r)))))" + + +(*val _update_Mcause_IsInterrupt : Mcause -> mword ty1 -> Mcause*) + +fun update_Mcause_IsInterrupt :: " Mcause \<Rightarrow>(1)Word.word \<Rightarrow> Mcause " where + " update_Mcause_IsInterrupt (Mk_Mcause (v)) x = ( + Mk_Mcause ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Mcause_Cause : Mcause -> mword ty63*) + +fun get_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word " where + " get_Mcause_Cause (Mk_Mcause (v)) = ( (subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) :: 63 Word.word))" + + +(*val _set_Mcause_Cause : register_ref regstate register_value Mcause -> mword ty63 -> M unit*) + +definition set_Mcause_Cause :: "((regstate),(register_value),(Mcause))register_ref \<Rightarrow>(63)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Mcause_Cause r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Mcause) . + (let r = ((get_Mcause w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 62 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Mcause r)))))" + + +(*val _update_Mcause_Cause : Mcause -> mword ty63 -> Mcause*) + +fun update_Mcause_Cause :: " Mcause \<Rightarrow>(63)Word.word \<Rightarrow> Mcause " where + " update_Mcause_Cause (Mk_Mcause (v)) x = ( + Mk_Mcause ((update_subrange_vec_dec v (( 62 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val tvec_addr : Mtvec -> Mcause -> maybe (mword ty64)*) + +definition tvec_addr :: " Mtvec \<Rightarrow> Mcause \<Rightarrow>((64)Word.word)option " where + " tvec_addr (m :: Mtvec) (c :: Mcause) = ( + (let (base :: xlenbits) = + ((concat_vec ((get_Mtvec_Base m :: 62 Word.word)) (vec_of_bits [B0,B0] :: 2 Word.word) + :: 64 Word.word)) in + (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m :: 2 Word.word)))) of + TV_Direct => Some base + | TV_Vector => + if (((((get_Mcause_IsInterrupt c :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some ((add_vec base + ((shift_bits_left + ((EXTZ (( 64 :: int)::ii) ((get_Mcause_Cause c :: 63 Word.word)) :: 64 Word.word)) + (vec_of_bits [B1,B0] :: 2 Word.word) + :: 64 Word.word)) + :: 64 Word.word)) + else Some base + | TV_Reserved => None + )))" + + +(*val legalize_xepc : mword ty64 -> M (mword ty64)*) + +definition legalize_xepc :: "(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " legalize_xepc v = ( + haveRVC () \<bind> (\<lambda> (w__0 :: bool) . + return ((and_vec v + ((EXTS (( 64 :: int)::ii) + (if w__0 then (vec_of_bits [B1,B1,B0] :: 3 Word.word) + else (vec_of_bits [B1,B0,B0] :: 3 Word.word)) + :: 64 Word.word)) + :: 64 Word.word))))" + + +(*val _get_Sstatus : Sstatus -> mword ty64*) + +fun get_Sstatus :: " Sstatus \<Rightarrow>(64)Word.word " where + " get_Sstatus (Mk_Sstatus (v)) = ( v )" + + +(*val _set_Sstatus : register_ref regstate register_value Sstatus -> mword ty64 -> M unit*) + +definition set_Sstatus :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Sstatus v) in + write_reg r_ref r)))" + + +fun get_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SD (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SD :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_SD r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 63 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SD :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SD (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 63 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_UXL (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_UXL :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_UXL r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 33 :: int)::ii) (( 32 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UXL :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UXL (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 33 :: int)::ii) (( 32 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_MXR (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_MXR :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_MXR r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 19 :: int)::ii) (( 19 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_MXR :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_MXR (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 19 :: int)::ii) (( 19 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SUM (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SUM :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_SUM r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 18 :: int)::ii) (( 18 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SUM :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SUM (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 18 :: int)::ii) (( 18 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_XS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_XS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_XS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 16 :: int)::ii) (( 15 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_XS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_XS (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 16 :: int)::ii) (( 15 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word " where + " get_Sstatus_FS (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) :: 2 Word.word))" + + +definition set_Sstatus_FS :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_FS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 14 :: int)::ii) (( 13 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_FS :: " Sstatus \<Rightarrow>(2)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_FS (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 14 :: int)::ii) (( 13 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SPP (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SPP :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_SPP r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SPP :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SPP (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_SPIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SPIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_UPIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_UPIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_UPIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UPIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UPIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_SIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_SIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_SIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_SIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_SIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word " where + " get_Sstatus_UIE (Mk_Sstatus (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sstatus_UIE :: "((regstate),(register_value),(Sstatus))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sstatus_UIE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sstatus) . + (let r = ((get_Sstatus w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sstatus r)))))" + + +fun update_Sstatus_UIE :: " Sstatus \<Rightarrow>(1)Word.word \<Rightarrow> Sstatus " where + " update_Sstatus_UIE (Mk_Sstatus (v)) x = ( + Mk_Sstatus ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val lower_mstatus : Mstatus -> Sstatus*) + +definition lower_mstatus :: " Mstatus \<Rightarrow> Sstatus " where + " lower_mstatus m = ( + (let s = (Mk_Sstatus ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = (update_Sstatus_SD s ((get_Mstatus_SD m :: 1 Word.word))) in + (let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m :: 2 Word.word))) in + (let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m :: 1 Word.word))) in + (let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m :: 1 Word.word))) in + (let s = (update_Sstatus_XS s ((get_Mstatus_XS m :: 2 Word.word))) in + (let s = (update_Sstatus_FS s ((get_Mstatus_FS m :: 2 Word.word))) in + (let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m :: 1 Word.word))) in + (let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m :: 1 Word.word))) in + (let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m :: 1 Word.word))) in + (let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m :: 1 Word.word))) in + update_Sstatus_UIE s ((get_Mstatus_UIE m :: 1 Word.word))))))))))))))" + + +(*val lift_sstatus : Mstatus -> Sstatus -> Mstatus*) + +definition lift_sstatus :: " Mstatus \<Rightarrow> Sstatus \<Rightarrow> Mstatus " where + " lift_sstatus (m :: Mstatus) (s :: Sstatus) = ( + (let m = (update_Mstatus_SD m ((get_Sstatus_SD s :: 1 Word.word))) in + (let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s :: 2 Word.word))) in + (let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s :: 1 Word.word))) in + (let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s :: 1 Word.word))) in + (let m = (update_Mstatus_XS m ((get_Sstatus_XS s :: 2 Word.word))) in + (let m = (update_Mstatus_FS m ((get_Sstatus_FS s :: 2 Word.word))) in + (let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s :: 1 Word.word))) in + (let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s :: 1 Word.word))) in + (let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s :: 1 Word.word))) in + (let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s :: 1 Word.word))) in + update_Mstatus_UIE m ((get_Sstatus_UIE s :: 1 Word.word)))))))))))))" + + +(*val legalize_sstatus : Mstatus -> mword ty64 -> Mstatus*) + +definition legalize_sstatus :: " Mstatus \<Rightarrow>(64)Word.word \<Rightarrow> Mstatus " where + " legalize_sstatus (m :: Mstatus) (v :: xlenbits) = ( lift_sstatus m (Mk_Sstatus v))" + + +(*val _get_Sedeleg : Sedeleg -> mword ty64*) + +fun get_Sedeleg :: " Sedeleg \<Rightarrow>(64)Word.word " where + " get_Sedeleg (Mk_Sedeleg (v)) = ( v )" + + +(*val _set_Sedeleg : register_ref regstate register_value Sedeleg -> mword ty64 -> M unit*) + +definition set_Sedeleg :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Sedeleg v) in + write_reg r_ref r)))" + + +fun get_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_UEnvCall (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_UEnvCall :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_UEnvCall r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_UEnvCall :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_UEnvCall (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_SAMO_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_SAMO_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_SAMO_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_SAMO_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_SAMO_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_SAMO_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_SAMO_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_SAMO_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Load_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Load_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Load_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Load_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Load_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Load_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Load_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Load_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Breakpoint (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Breakpoint :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Breakpoint r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Breakpoint :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Breakpoint (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Illegal_Instr :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Illegal_Instr r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Illegal_Instr :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Illegal_Instr (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) = ( + (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Fetch_Access_Fault :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Fetch_Access_Fault r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Fetch_Access_Fault :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Fetch_Access_Fault (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word " where + " get_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sedeleg_Fetch_Addr_Align :: "((regstate),(register_value),(Sedeleg))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sedeleg_Fetch_Addr_Align r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sedeleg) . + (let r = ((get_Sedeleg w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sedeleg r)))))" + + +fun update_Sedeleg_Fetch_Addr_Align :: " Sedeleg \<Rightarrow>(1)Word.word \<Rightarrow> Sedeleg " where + " update_Sedeleg_Fetch_Addr_Align (Mk_Sedeleg (v)) x = ( + Mk_Sedeleg ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val legalize_sedeleg : Sedeleg -> mword ty64 -> Sedeleg*) + +definition legalize_sedeleg :: " Sedeleg \<Rightarrow>(64)Word.word \<Rightarrow> Sedeleg " where + " legalize_sedeleg (s :: Sedeleg) (v :: xlenbits) = ( + Mk_Sedeleg ((EXTZ (( 64 :: int)::ii) ((subrange_vec_dec v (( 8 :: int)::ii) (( 0 :: int)::ii) :: 9 Word.word)) :: 64 Word.word)))" + + +(*val _get_Sinterrupts : Sinterrupts -> mword ty64*) + +fun get_Sinterrupts :: " Sinterrupts \<Rightarrow>(64)Word.word " where + " get_Sinterrupts (Mk_Sinterrupts (v)) = ( v )" + + +(*val _set_Sinterrupts : register_ref regstate register_value Sinterrupts -> mword ty64 -> M unit*) + +definition set_Sinterrupts :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Sinterrupts v) in + write_reg r_ref r)))" + + +fun get_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_SEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_SEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_SEI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 9 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_SEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_SEI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 9 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_UEI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_UEI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_UEI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 8 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_UEI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_UEI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_STI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_STI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_STI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_STI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_STI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_UTI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_UTI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_UTI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_UTI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_UTI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_SSI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_SSI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_SSI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_SSI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_SSI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 64 Word.word)))" + + +fun get_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word " where + " get_Sinterrupts_USI (Mk_Sinterrupts (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_Sinterrupts_USI :: "((regstate),(register_value),(Sinterrupts))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Sinterrupts_USI r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Sinterrupts) . + (let r = ((get_Sinterrupts w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Sinterrupts r)))))" + + +fun update_Sinterrupts_USI :: " Sinterrupts \<Rightarrow>(1)Word.word \<Rightarrow> Sinterrupts " where + " update_Sinterrupts_USI (Mk_Sinterrupts (v)) x = ( + Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val lower_mip : Minterrupts -> Minterrupts -> Sinterrupts*) + +definition lower_mip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where + " lower_mip (m :: Minterrupts) (d :: Minterrupts) = ( + (let (s :: Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word)))))))))" + + +(*val lower_mie : Minterrupts -> Minterrupts -> Sinterrupts*) + +definition lower_mie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts " where + " lower_mie (m :: Minterrupts) (d :: Minterrupts) = ( + (let (s :: Sinterrupts) = + (Mk_Sinterrupts ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))) in + (let s = + (update_Sinterrupts_SEI s + ((and_vec ((get_Minterrupts_SEI m :: 1 Word.word)) ((get_Minterrupts_SEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_STI s + ((and_vec ((get_Minterrupts_STI m :: 1 Word.word)) ((get_Minterrupts_STI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_SSI s + ((and_vec ((get_Minterrupts_SSI m :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UEI s + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + (let s = + (update_Sinterrupts_UTI s + ((and_vec ((get_Minterrupts_UTI m :: 1 Word.word)) ((get_Minterrupts_UTI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Sinterrupts_USI s + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word)))))))))" + + +(*val lift_sip : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +definition lift_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Minterrupts " where + " lift_sip (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = ( + (let (m :: Minterrupts) = o1 in + (let m = + (update_Minterrupts_SSI m + ((and_vec ((get_Sinterrupts_SSI s :: 1 Word.word)) ((get_Minterrupts_SSI d :: 1 Word.word)) + :: 1 Word.word))) in + (let m = + (update_Minterrupts_UEI m + ((and_vec ((get_Minterrupts_UEI m :: 1 Word.word)) ((get_Minterrupts_UEI d :: 1 Word.word)) + :: 1 Word.word))) in + update_Minterrupts_USI m + ((and_vec ((get_Minterrupts_USI m :: 1 Word.word)) ((get_Minterrupts_USI d :: 1 Word.word)) + :: 1 Word.word))))))" + + +(*val legalize_sip : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_sip :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " legalize_sip (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( + lift_sip m d (Mk_Sinterrupts v))" + + +(*val lift_sie : Minterrupts -> Minterrupts -> Sinterrupts -> Minterrupts*) + +definition lift_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Sinterrupts \<Rightarrow> Minterrupts " where + " lift_sie (o1 :: Minterrupts) (d :: Minterrupts) (s :: Sinterrupts) = ( + (let (m :: Minterrupts) = o1 in + (let m = + (if (((((get_Minterrupts_SEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_SEI m ((get_Sinterrupts_SEI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_STI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_STI m ((get_Sinterrupts_STI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_SSI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_SSI m ((get_Sinterrupts_SSI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_UEI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_UEI m ((get_Sinterrupts_UEI s :: 1 Word.word)) + else m) in + (let m = + (if (((((get_Minterrupts_UTI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_UTI m ((get_Sinterrupts_UTI s :: 1 Word.word)) + else m) in + if (((((get_Minterrupts_USI d :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + update_Minterrupts_USI m ((get_Sinterrupts_USI s :: 1 Word.word)) + else m)))))))" + + +(*val legalize_sie : Minterrupts -> Minterrupts -> mword ty64 -> Minterrupts*) + +definition legalize_sie :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>(64)Word.word \<Rightarrow> Minterrupts " where + " legalize_sie (m :: Minterrupts) (d :: Minterrupts) (v :: xlenbits) = ( + lift_sie m d (Mk_Sinterrupts v))" + + +(*val _get_Satp64 : Satp64 -> mword ty64*) + +fun get_Satp64 :: " Satp64 \<Rightarrow>(64)Word.word " where + " get_Satp64 (Mk_Satp64 (v)) = ( v )" + + +(*val _set_Satp64 : register_ref regstate register_value Satp64 -> mword ty64 -> M unit*) + +definition set_Satp64 :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Satp64 r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_Satp64 v) in + write_reg r_ref r)))" + + +fun get_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word " where + " get_Satp64_Mode (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) :: 4 Word.word))" + + +definition set_Satp64_Mode :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Satp64_Mode r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 63 :: int)::ii) (( 60 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +fun update_Satp64_Mode :: " Satp64 \<Rightarrow>(4)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_Mode (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 63 :: int)::ii) (( 60 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Satp64_Asid : Satp64 -> mword ty16*) + +fun get_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word " where + " get_Satp64_Asid (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) :: 16 Word.word))" + + +(*val _set_Satp64_Asid : register_ref regstate register_value Satp64 -> mword ty16 -> M unit*) + +definition set_Satp64_Asid :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(16)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Satp64_Asid r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 59 :: int)::ii) (( 44 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +(*val _update_Satp64_Asid : Satp64 -> mword ty16 -> Satp64*) + +fun update_Satp64_Asid :: " Satp64 \<Rightarrow>(16)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_Asid (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 59 :: int)::ii) (( 44 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_Satp64_PPN : Satp64 -> mword ty44*) + +fun get_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word " where + " get_Satp64_PPN (Mk_Satp64 (v)) = ( (subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) :: 44 Word.word))" + + +(*val _set_Satp64_PPN : register_ref regstate register_value Satp64 -> mword ty44 -> M unit*) + +definition set_Satp64_PPN :: "((regstate),(register_value),(Satp64))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_Satp64_PPN r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: Satp64) . + (let r = ((get_Satp64 w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 43 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_Satp64 r)))))" + + +(*val _update_Satp64_PPN : Satp64 -> mword ty44 -> Satp64*) + +fun update_Satp64_PPN :: " Satp64 \<Rightarrow>(44)Word.word \<Rightarrow> Satp64 " where + " update_Satp64_PPN (Mk_Satp64 (v)) x = ( + Mk_Satp64 ((update_subrange_vec_dec v (( 43 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val legalize_satp : Architecture -> mword ty64 -> mword ty64 -> mword ty64*) + +definition legalize_satp :: " Architecture \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(64)Word.word " where + " legalize_satp (a :: Architecture) (o1 :: xlenbits) (v :: xlenbits) = ( + (let s = (Mk_Satp64 v) in + (case ((satpMode_of_bits a ((get_Satp64_Mode s :: 4 Word.word)))) of + None => o1 + | Some (Sv32) => o1 + | Some (_) => (get_Satp64 s :: 64 Word.word) + )))" + + +(*val csr_name : mword ty12 -> string*) + +definition csr_name :: "(12)Word.word \<Rightarrow> string " where + " csr_name csr = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''ustatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''uie'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''utvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''fflags'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''frm'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''fcsr'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycle'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''time'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instret'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''cycleh'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''timeh'') + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''instreth'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sstatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''sedeleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''sideleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sie'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''stvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''scounteren'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''sscratch'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''sepc'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''scause'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''stval'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''sip'') + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''satp'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mvendorid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (''marchid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mimpid'') + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mhartid'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mstatus'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''misa'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''medeleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mideleg'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mie'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (''mtvec'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (''mcounteren'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mscratch'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (''mepc'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''mcause'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (''mtval'') + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (''mip'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycle'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstret'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''mcycleh'') + else if (((b__0 = (vec_of_bits [B1,B0,B1,B1,B1,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (''minstreth'') + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (''tselect'') + else (''UNKNOWN'')))" + + +(*val csrAccess : mword ty12 -> mword ty2*) + +definition csrAccess :: "(12)Word.word \<Rightarrow>(2)Word.word " where + " csrAccess csr = ( (subrange_vec_dec csr (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word))" + + +(*val csrPriv : mword ty12 -> mword ty2*) + +definition csrPriv :: "(12)Word.word \<Rightarrow>(2)Word.word " where + " csrPriv csr = ( (subrange_vec_dec csr (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" + + +(*val is_CSR_defined : mword ty12 -> Privilege -> bool*) + +definition is_CSR_defined :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool " where + " is_CSR_defined (csr :: 12 bits) (p :: Privilege) = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + ((((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) \<or> (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))) + else False))" + + +(*val check_CSR_access : mword ty2 -> mword ty2 -> Privilege -> bool -> bool*) + +definition check_CSR_access :: "(2)Word.word \<Rightarrow>(2)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool " where + " check_CSR_access csrrw csrpr p isWrite = ( + (((\<not> ((((((((bool_to_bits isWrite :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((csrrw = (vec_of_bits [B1,B1] :: 2 Word.word))))))))) \<and> ((zopz0zKzJ_u ((privLevel_to_bits p :: 2 Word.word)) csrpr))))" + + +(*val check_TVM_SATP : mword ty12 -> Privilege -> M bool*) + +definition check_TVM_SATP :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow>((register_value),(bool),(exception))monad " where + " check_TVM_SATP (csr :: csreg) (p :: Privilege) = ( + and_boolM + (return (((csr = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word))))) + (and_boolM + (return (((((privLevel_to_bits p :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word)))))) + (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + return (((((get_Mstatus_TVM w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))) \<bind> (\<lambda> (w__2 :: + bool) . + return ((\<not> w__2))))" + + +(*val check_CSR : mword ty12 -> Privilege -> bool -> M bool*) + +definition check_CSR :: "(12)Word.word \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow>((register_value),(bool),(exception))monad " where + " check_CSR (csr :: csreg) (p :: Privilege) (isWrite :: bool) = ( + and_boolM (return ((is_CSR_defined csr p))) + (and_boolM + (return ((check_CSR_access ((csrAccess csr :: 2 Word.word)) ((csrPriv csr :: 2 Word.word)) p + isWrite))) ((check_TVM_SATP csr p))))" + + +(*val exception_delegatee : ExceptionType -> Privilege -> M Privilege*) + +definition exception_delegatee :: " ExceptionType \<Rightarrow> Privilege \<Rightarrow>((register_value),(Privilege),(exception))monad " where + " exception_delegatee (e :: ExceptionType) (p :: Privilege) = ( + (let idx = (num_of_ExceptionType e) in + read_reg medeleg_ref \<bind> (\<lambda> (w__0 :: Medeleg) . + (let super = (access_vec_dec ((get_Medeleg w__0 :: 64 Word.word)) idx) in + read_reg sedeleg_ref \<bind> (\<lambda> (w__1 :: Sedeleg) . + (let user = (access_vec_dec ((get_Sedeleg w__1 :: 64 Word.word)) idx) in + and_boolM + (read_reg misa_ref \<bind> (\<lambda> (w__2 :: Misa) . + return (((((get_Misa_S w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (return ((bit_to_bool super))) \<bind> (\<lambda> (w__3 :: bool) . + (let deleg = (if w__3 then Supervisor else Machine) in + return (if ((zopz0zI_u ((privLevel_to_bits deleg :: 2 Word.word)) + ((privLevel_to_bits p :: 2 Word.word)))) then + p + else deleg)))))))))" + + +(*val findPendingInterrupt : mword ty64 -> maybe InterruptType*) + +definition findPendingInterrupt :: "(64)Word.word \<Rightarrow>(InterruptType)option " where + " findPendingInterrupt ip = ( + (let ip = (Mk_Minterrupts ip) in + if (((((get_Minterrupts_MEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + Some I_M_External + else if (((((get_Minterrupts_MSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_M_Software + else if (((((get_Minterrupts_MTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_M_Timer + else if (((((get_Minterrupts_SEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_External + else if (((((get_Minterrupts_SSI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_Software + else if (((((get_Minterrupts_STI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_S_Timer + else if (((((get_Minterrupts_UEI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_External + else if (((((get_Minterrupts_USI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_Software + else if (((((get_Minterrupts_UTI ip :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Some I_U_Timer + else None))" + + +(*val curInterrupt : Minterrupts -> Minterrupts -> Minterrupts -> M (maybe ((InterruptType * Privilege)))*) + +definition curInterrupt :: " Minterrupts \<Rightarrow> Minterrupts \<Rightarrow> Minterrupts \<Rightarrow>((register_value),((InterruptType*Privilege)option),(exception))monad " where + " curInterrupt (pend :: Minterrupts) (enbl :: Minterrupts) (delg :: Minterrupts) = ( + (let (en_mip :: xlenbits) = + ((and_vec ((get_Minterrupts pend :: 64 Word.word)) ((get_Minterrupts enbl :: 64 Word.word)) + :: 64 Word.word)) in + if (((en_mip = ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))))) then + return None + else + (let eff_mip = + ((and_vec en_mip ((not_vec ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) + :: 64 Word.word)) in + (let eff_sip = ((and_vec en_mip ((get_Minterrupts delg :: 64 Word.word)) :: 64 Word.word)) in + and_boolM + (read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + return (((((get_Mstatus_MIE w__0 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (return (((eff_mip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) \<bind> (\<lambda> (w__1 :: + bool) . + if w__1 then + return ((case ((findPendingInterrupt eff_mip)) of + Some (i) => + (let r = (i, Machine) in + Some r) + | None => None + )) + else + and_boolM + (read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . + return (((((get_Mstatus_SIE w__2 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))))) + (and_boolM + (return (((eff_sip \<noteq> ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))) + (or_boolM + (read_reg cur_privilege_ref \<bind> (\<lambda> (w__3 :: Privilege) . + return (((((privLevel_to_bits w__3 :: 2 Word.word)) = ((privLevel_to_bits Supervisor :: 2 Word.word))))))) + (read_reg cur_privilege_ref \<bind> (\<lambda> (w__4 :: Privilege) . + return (((((privLevel_to_bits w__4 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))))))) \<bind> (\<lambda> (w__7 :: bool) . + return (if w__7 then + (case ((findPendingInterrupt eff_sip)) of + Some (i) => + (let r = (i, Supervisor) in + Some r) + | None => None + ) + else None)))))))" + + +(*val tval : maybe (mword ty64) -> mword ty64*) + +fun tval :: "((64)Word.word)option \<Rightarrow>(64)Word.word " where + " tval (Some (e)) = ( e )" +|" tval None = ( (EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word))" + + +(*val handle_trap : Privilege -> bool -> mword ty4 -> mword ty64 -> maybe (mword ty64) -> M (mword ty64)*) + +definition handle_trap :: " Privilege \<Rightarrow> bool \<Rightarrow>(4)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(xlenbits)option \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " handle_trap (del_priv :: Privilege) (intr :: bool) (c :: exc_code) (pc :: xlenbits) (info :: + xlenbits option) = ( + (let (_ :: unit) = + (prerr_endline + (((op@) (''handling '') + (((op@) (if intr then (''int#'') else (''exc#'')) + (((op@) ((string_of_vec c)) + (((op@) ('' at priv '') + (((op@) ((privLevel_to_str del_priv)) + (((op@) ('' with tval '') + ((string_of_vec ((tval info :: 64 Word.word))))))))))))))))) in + (case del_priv of + Machine => + ((set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr :: 1 Word.word)) \<then> + set_Mcause_Cause mcause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__0 :: Mstatus) . + ((set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0 :: 1 Word.word)) \<then> + set_Mstatus_MIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> + read_reg cur_privilege_ref) \<bind> (\<lambda> (w__1 :: Privilege) . + ((((set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1 :: 2 Word.word)) \<then> + write_reg mtval_ref ((tval info :: 64 Word.word))) \<then> + write_reg mepc_ref pc) \<then> + write_reg cur_privilege_ref del_priv) \<then> + read_reg mtvec_ref) \<bind> (\<lambda> (w__2 :: Mtvec) . + read_reg mcause_ref \<bind> (\<lambda> (w__3 :: Mcause) . + (case ((tvec_addr w__2 w__3 :: ( 64 Word.word)option)) of + Some (epc) => return epc + | None => (internal_error (''Invalid mtvec mode'') :: ( 64 Word.word) M) + ))))) + | Supervisor => + ((set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr :: 1 Word.word)) \<then> + set_Mcause_Cause scause_ref ((EXTZ (( 63 :: int)::ii) c :: 63 Word.word))) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . + ((set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6 :: 1 Word.word)) \<then> + set_Mstatus_SIE mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> + read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . + (case w__7 of + User => return ((bool_to_bits False :: 1 Word.word)) + | Supervisor => return ((bool_to_bits True :: 1 Word.word)) + | Machine => (internal_error (''invalid privilege for s-mode trap'') :: ( 1 Word.word) M) + ) \<bind> (\<lambda> (w__9 :: 1 Word.word) . + ((((set_Mstatus_SPP mstatus_ref w__9 \<then> + write_reg stval_ref ((tval info :: 64 Word.word))) \<then> + write_reg sepc_ref pc) \<then> + write_reg cur_privilege_ref del_priv) \<then> + read_reg stvec_ref) \<bind> (\<lambda> (w__10 :: Mtvec) . + read_reg scause_ref \<bind> (\<lambda> (w__11 :: Mcause) . + (case ((tvec_addr w__10 w__11 :: ( 64 Word.word)option)) of + Some (epc) => return epc + | None => (internal_error (''Invalid stvec mode'') :: ( 64 Word.word) M) + )))))) + | User => (internal_error (''the N extension is currently unsupported'') :: ( 64 Word.word) M) + )))" + + +(*val handle_exception : Privilege -> ctl_result -> mword ty64 -> M (mword ty64)*) + +definition handle_exception :: " Privilege \<Rightarrow> ctl_result \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " handle_exception (cur_priv :: Privilege) (ctl :: ctl_result) (pc :: xlenbits) = ( + (case (cur_priv, ctl) of + (_, CTL_TRAP (e)) => + exception_delegatee(sync_exception_trap e) cur_priv \<bind> (\<lambda> del_priv . + (let (_ :: unit) = + (prerr_endline + (((op@) (''trapping from '') + (((op@) ((privLevel_to_str cur_priv)) + (((op@) ('' to '') + (((op@) ((privLevel_to_str del_priv)) + (((op@) ('' to handle '') + ((exceptionType_to_str(sync_exception_trap e)))))))))))))) in + (handle_trap del_priv False ((exceptionType_to_bits(sync_exception_trap e) :: 4 Word.word)) pc(sync_exception_excinfo + e) + :: ( 64 Word.word) M))) + | (_, CTL_MRET (_)) => + read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv . + read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . + ((set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1 :: 1 Word.word)) \<then> + set_Mstatus_MPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__2 :: Mstatus) . + ((write_reg cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word)))) \<then> + set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User :: 2 Word.word))) \<then> + read_reg cur_privilege_ref) \<bind> (\<lambda> (w__3 :: Privilege) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''ret-ing from '') + (((op@) ((privLevel_to_str prev_priv)) + (((op@) ('' to '') ((privLevel_to_str w__3))))))))) in + (read_reg mepc_ref :: ( 64 Word.word) M)))))) + | (_, CTL_SRET (_)) => + read_reg cur_privilege_ref \<bind> (\<lambda> prev_priv . + read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . + ((set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5 :: 1 Word.word)) \<then> + set_Mstatus_SPIE mstatus_ref ((bool_to_bits True :: 1 Word.word))) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__6 :: Mstatus) . + ((write_reg + cur_privilege_ref + (if (((((get_Mstatus_SPP w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) + then + Supervisor + else User) \<then> + set_Mstatus_SPP mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> + read_reg cur_privilege_ref) \<bind> (\<lambda> (w__7 :: Privilege) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''ret-ing from '') + (((op@) ((privLevel_to_str prev_priv)) + (((op@) ('' to '') ((privLevel_to_str w__7))))))))) in + (read_reg sepc_ref :: ( 64 Word.word) M)))))) + ))" + + +(*val handle_mem_exception : mword ty64 -> ExceptionType -> M unit*) + +definition handle_mem_exception :: "(64)Word.word \<Rightarrow> ExceptionType \<Rightarrow>((register_value),(unit),(exception))monad " where + " handle_mem_exception (addr :: xlenbits) (e :: ExceptionType) = ( + (let (t :: sync_exception) = ((| sync_exception_trap = e, sync_exception_excinfo = (Some addr) |)) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val handle_decode_exception : mword ty64 -> M unit*) + +definition handle_decode_exception :: "(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " handle_decode_exception instbits = ( + (let (t :: sync_exception) = + ((| sync_exception_trap = E_Illegal_Instr, + sync_exception_excinfo = (Some instbits) |)) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val handle_interrupt : InterruptType -> Privilege -> M unit*) + +definition handle_interrupt :: " InterruptType \<Rightarrow> Privilege \<Rightarrow>((register_value),(unit),(exception))monad " where + " handle_interrupt (i :: InterruptType) (del_priv :: Privilege) = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (handle_trap del_priv True ((interruptType_to_bits i :: 4 Word.word)) w__0 None + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . + write_reg nextPC_ref w__1)))" + + +(*val handle_illegal : unit -> M unit*) + +definition handle_illegal :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " handle_illegal _ = ( + (let (t :: sync_exception) = + ((| sync_exception_trap = E_Illegal_Instr, + sync_exception_excinfo = None |)) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (handle_exception w__0 (CTL_TRAP t) w__1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: xlenbits) . + write_reg nextPC_ref w__2)))))" + + +(*val init_sys : unit -> M unit*) + +definition init_sys :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " init_sys _ = ( + (((((write_reg cur_privilege_ref Machine \<then> + set_Misa_MXL misa_ref ((arch_to_bits RV64 :: 2 Word.word))) \<then> + set_Misa_C misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> + set_Misa_U misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> + set_Misa_S misa_ref ((bool_to_bits True :: 1 Word.word))) \<then> + read_reg misa_ref) \<bind> (\<lambda> (w__0 :: Misa) . + (set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0 :: 2 Word.word)) \<then> + read_reg misa_ref) \<bind> (\<lambda> (w__1 :: Misa) . + (set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1 :: 2 Word.word)) \<then> + set_Mstatus_SD mstatus_ref ((bool_to_bits False :: 1 Word.word))) \<then> + write_reg mhartid_ref ((EXTZ (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))))" + + +(*val tick_clock : unit -> M unit*) + +definition tick_clock :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " tick_clock _ = ( + (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + write_reg mcycle_ref ((add_vec_int w__0 (( 1 :: int)::ii) :: 64 Word.word))))" + + +definition PAGESIZE_BITS :: " int " where + " PAGESIZE_BITS = ( (( 12 :: int)::ii))" + + +(*val _get_PTE_Bits : PTE_Bits -> mword ty8*) + +fun get_PTE_Bits :: " PTE_Bits \<Rightarrow>(8)Word.word " where + " get_PTE_Bits (Mk_PTE_Bits (v)) = ( v )" + + +(*val _set_PTE_Bits : register_ref regstate register_value PTE_Bits -> mword ty8 -> M unit*) + +definition set_PTE_Bits :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_PTE_Bits v) in + write_reg r_ref r)))" + + +fun get_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_D (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_D :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_D r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 7 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_D :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_D (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 7 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_A (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_A :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_A r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 6 :: int)::ii) (( 6 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_A :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_A (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 :: int)::ii) (( 6 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_G (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_G :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_G r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 5 :: int)::ii) (( 5 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_G :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_G (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 :: int)::ii) (( 5 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_U (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_U :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_U r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 4 :: int)::ii) (( 4 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_U :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_U (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 :: int)::ii) (( 4 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_X (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_X :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_X r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 3 :: int)::ii) (( 3 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_X :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_X (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 :: int)::ii) (( 3 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_W (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_W :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_W r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 2 :: int)::ii) (( 2 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_W :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_W (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 :: int)::ii) (( 2 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_R (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_R :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_R r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 1 :: int)::ii) (( 1 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_R :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_R (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 :: int)::ii) (( 1 :: int)::ii) x :: 8 Word.word)))" + + +fun get_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word " where + " get_PTE_Bits_V (Mk_PTE_Bits (v)) = ( (subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) :: 1 Word.word))" + + +definition set_PTE_Bits_V :: "((regstate),(register_value),(PTE_Bits))register_ref \<Rightarrow>(1)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_PTE_Bits_V r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: PTE_Bits) . + (let r = ((get_PTE_Bits w__0 :: 8 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 0 :: int)::ii) (( 0 :: int)::ii) v :: 8 Word.word)) in + write_reg r_ref (Mk_PTE_Bits r)))))" + + +fun update_PTE_Bits_V :: " PTE_Bits \<Rightarrow>(1)Word.word \<Rightarrow> PTE_Bits " where + " update_PTE_Bits_V (Mk_PTE_Bits (v)) x = ( + Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 :: int)::ii) (( 0 :: int)::ii) x :: 8 Word.word)))" + + +(*val isPTEPtr : mword ty8 -> bool*) + +definition isPTEPtr :: "(8)Word.word \<Rightarrow> bool " where + " isPTEPtr p = ( + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))" + + +(*val isInvalidPTE : mword ty8 -> bool*) + +definition isInvalidPTE :: "(8)Word.word \<Rightarrow> bool " where + " isInvalidPTE p = ( + (let a = (Mk_PTE_Bits p) in + ((((((get_PTE_Bits_V a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_W a :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_R a :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))))))))" + + +(*val checkPTEPermission : AccessType -> Privilege -> bool -> bool -> PTE_Bits -> M bool*) + +fun checkPTEPermission :: " AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> PTE_Bits \<Rightarrow>((register_value),(bool),(exception))monad " where + " checkPTEPermission (Read :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))" +|" checkPTEPermission (Write :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (ReadWrite :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))" +|" checkPTEPermission (Execute :: AccessType) (User :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (Read :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr))))))))))" +|" checkPTEPermission (Write :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> (((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (ReadWrite :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return (((((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<or> do_sum))) \<and> ((((((((get_PTE_Bits_W p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> ((((((((get_PTE_Bits_R p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<or> ((((((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) \<and> mxr)))))))))))))" +|" checkPTEPermission (Execute :: AccessType) (Supervisor :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( + return ((((((((get_PTE_Bits_U p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))))) \<and> (((((get_PTE_Bits_X p :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))))))" +|" checkPTEPermission (_ :: AccessType) (Machine :: Privilege) (mxr :: bool) (do_sum :: bool) (p :: + PTE_Bits) = ( internal_error (''m-mode mem perm check''))" + + +(*val update_PTE_Bits : PTE_Bits -> AccessType -> maybe PTE_Bits*) + +definition update_PTE_Bits :: " PTE_Bits \<Rightarrow> AccessType \<Rightarrow>(PTE_Bits)option " where + " update_PTE_Bits (p :: PTE_Bits) (a :: AccessType) = ( + (let update_d = + (((((((a = Write))) \<or> (((a = ReadWrite)))))) \<and> (((((get_PTE_Bits_D p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word)))))) in + (let update_a = (((get_PTE_Bits_A p :: 1 Word.word)) = ((bool_to_bits False :: 1 Word.word))) in + if (((update_d \<or> update_a))) then + (let np = (update_PTE_Bits_A p ((bool_to_bits True :: 1 Word.word))) in + (let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits True :: 1 Word.word)) else np) in + Some np)) + else None)))" + + +(*val PTW_Error_of_num : integer -> PTW_Error*) + +definition PTW_Error_of_num :: " int \<Rightarrow> PTW_Error " where + " PTW_Error_of_num arg0 = ( + (let l__0 = arg0 in + if (((l__0 = (( 0 :: int)::ii)))) then PTW_Access + else if (((l__0 = (( 1 :: int)::ii)))) then PTW_Invalid_PTE + else if (((l__0 = (( 2 :: int)::ii)))) then PTW_No_Permission + else if (((l__0 = (( 3 :: int)::ii)))) then PTW_Misaligned + else PTW_PTE_Update))" + + +(*val num_of_PTW_Error : PTW_Error -> integer*) + +fun num_of_PTW_Error :: " PTW_Error \<Rightarrow> int " where + " num_of_PTW_Error PTW_Access = ( (( 0 :: int)::ii))" +|" num_of_PTW_Error PTW_Invalid_PTE = ( (( 1 :: int)::ii))" +|" num_of_PTW_Error PTW_No_Permission = ( (( 2 :: int)::ii))" +|" num_of_PTW_Error PTW_Misaligned = ( (( 3 :: int)::ii))" +|" num_of_PTW_Error PTW_PTE_Update = ( (( 4 :: int)::ii))" + + +(*val translationException : AccessType -> PTW_Error -> ExceptionType*) + +fun translationException :: " AccessType \<Rightarrow> PTW_Error \<Rightarrow> ExceptionType " where + " translationException (Read :: AccessType) (PTW_Access :: PTW_Error) = ( E_Load_Access_Fault )" +|" translationException (Read :: AccessType) (_ :: PTW_Error) = ( E_Load_Page_Fault )" +|" translationException (Write :: AccessType) (PTW_Access :: PTW_Error) = ( E_SAMO_Access_Fault )" +|" translationException (Write :: AccessType) (_ :: PTW_Error) = ( E_SAMO_Page_Fault )" +|" translationException (Fetch :: AccessType) (PTW_Access :: PTW_Error) = ( E_Fetch_Access_Fault )" +|" translationException (Fetch :: AccessType) (_ :: PTW_Error) = ( E_Fetch_Page_Fault )" + + +definition SV39_LEVEL_BITS :: " int " where + " SV39_LEVEL_BITS = ( (( 9 :: int)::ii))" + + +definition SV39_LEVELS :: " int " where + " SV39_LEVELS = ( (( 3 :: int)::ii))" + + +definition PTE39_LOG_SIZE :: " int " where + " PTE39_LOG_SIZE = ( (( 3 :: int)::ii))" + + +definition PTE39_SIZE :: " int " where + " PTE39_SIZE = ( (( 8 :: int)::ii))" + + +(*val _get_SV39_Vaddr : SV39_Vaddr -> mword ty39*) + +fun get_SV39_Vaddr :: " SV39_Vaddr \<Rightarrow>(39)Word.word " where + " get_SV39_Vaddr (Mk_SV39_Vaddr (v)) = ( v )" + + +(*val _set_SV39_Vaddr : register_ref regstate register_value SV39_Vaddr -> mword ty39 -> M unit*) + +definition set_SV39_Vaddr :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_SV39_Vaddr v) in + write_reg r_ref r)))" + + +(*val _get_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27*) + +fun get_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word " where + " get_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) :: 27 Word.word))" + + +(*val _set_SV39_Vaddr_VPNi : register_ref regstate register_value SV39_Vaddr -> mword ty27 -> M unit*) + +definition set_SV39_Vaddr_VPNi :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(27)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr_VPNi r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . + (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 38 :: int)::ii) (( 12 :: int)::ii) v :: 39 Word.word)) in + write_reg r_ref (Mk_SV39_Vaddr r)))))" + + +(*val _update_SV39_Vaddr_VPNi : SV39_Vaddr -> mword ty27 -> SV39_Vaddr*) + +fun update_SV39_Vaddr_VPNi :: " SV39_Vaddr \<Rightarrow>(27)Word.word \<Rightarrow> SV39_Vaddr " where + " update_SV39_Vaddr_VPNi (Mk_SV39_Vaddr (v)) x = ( + Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 :: int)::ii) (( 12 :: int)::ii) x :: 39 Word.word)))" + + +(*val _get_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12*) + +fun get_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word " where + " get_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" + + +(*val _set_SV39_Vaddr_PgOfs : register_ref regstate register_value SV39_Vaddr -> mword ty12 -> M unit*) + +definition set_SV39_Vaddr_PgOfs :: "((regstate),(register_value),(SV39_Vaddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Vaddr_PgOfs r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Vaddr) . + (let r = ((get_SV39_Vaddr w__0 :: 39 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 39 Word.word)) in + write_reg r_ref (Mk_SV39_Vaddr r)))))" + + +(*val _update_SV39_Vaddr_PgOfs : SV39_Vaddr -> mword ty12 -> SV39_Vaddr*) + +fun update_SV39_Vaddr_PgOfs :: " SV39_Vaddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Vaddr " where + " update_SV39_Vaddr_PgOfs (Mk_SV39_Vaddr (v)) x = ( + Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 39 Word.word)))" + + +(*val _update_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12 -> SV39_Paddr*) + +(*val _get_SV39_Paddr_PgOfs : SV39_Paddr -> mword ty12*) + +(*val _set_SV39_Paddr_PgOfs : register_ref regstate register_value SV39_Paddr -> mword ty12 -> M unit*) + +(*val _get_SV39_Paddr : SV39_Paddr -> mword ty56*) + +fun get_SV39_Paddr :: " SV39_Paddr \<Rightarrow>(56)Word.word " where + " get_SV39_Paddr (Mk_SV39_Paddr (v)) = ( v )" + + +(*val _set_SV39_Paddr : register_ref regstate register_value SV39_Paddr -> mword ty56 -> M unit*) + +definition set_SV39_Paddr :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Paddr r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_SV39_Paddr v) in + write_reg r_ref r)))" + + +(*val _get_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44*) + +fun get_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word " where + " get_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) :: 44 Word.word))" + + +(*val _set_SV39_Paddr_PPNi : register_ref regstate register_value SV39_Paddr -> mword ty44 -> M unit*) + +definition set_SV39_Paddr_PPNi :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Paddr_PPNi r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . + (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 55 :: int)::ii) (( 12 :: int)::ii) v :: 56 Word.word)) in + write_reg r_ref (Mk_SV39_Paddr r)))))" + + +(*val _update_SV39_Paddr_PPNi : SV39_Paddr -> mword ty44 -> SV39_Paddr*) + +fun update_SV39_Paddr_PPNi :: " SV39_Paddr \<Rightarrow>(44)Word.word \<Rightarrow> SV39_Paddr " where + " update_SV39_Paddr_PPNi (Mk_SV39_Paddr (v)) x = ( + Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 :: int)::ii) (( 12 :: int)::ii) x :: 56 Word.word)))" + + +(*val _update_SV39_PTE_PPNi : SV39_PTE -> mword ty44 -> SV39_PTE*) + +(*val _get_SV39_PTE_PPNi : SV39_PTE -> mword ty44*) + +(*val _set_SV39_PTE_PPNi : register_ref regstate register_value SV39_PTE -> mword ty44 -> M unit*) + +fun get_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word " where + " get_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) = ( (subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) :: 12 Word.word))" + + +definition set_SV39_Paddr_PgOfs :: "((regstate),(register_value),(SV39_Paddr))register_ref \<Rightarrow>(12)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_Paddr_PgOfs r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_Paddr) . + (let r = ((get_SV39_Paddr w__0 :: 56 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 11 :: int)::ii) (( 0 :: int)::ii) v :: 56 Word.word)) in + write_reg r_ref (Mk_SV39_Paddr r)))))" + + +fun update_SV39_Paddr_PgOfs :: " SV39_Paddr \<Rightarrow>(12)Word.word \<Rightarrow> SV39_Paddr " where + " update_SV39_Paddr_PgOfs (Mk_SV39_Paddr (v)) x = ( + Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 :: int)::ii) (( 0 :: int)::ii) x :: 56 Word.word)))" + + +fun get_SV39_PTE :: " SV39_PTE \<Rightarrow>(64)Word.word " where + " get_SV39_PTE (Mk_SV39_PTE (v)) = ( v )" + + +definition set_SV39_PTE :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_PTE r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> r . + (let r = (Mk_SV39_PTE v) in + write_reg r_ref r)))" + + +fun get_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word " where + " get_SV39_PTE_PPNi (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) :: 44 Word.word))" + + +definition set_SV39_PTE_PPNi :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(44)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_PTE_PPNi r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 53 :: int)::ii) (( 10 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +fun update_SV39_PTE_PPNi :: " SV39_PTE \<Rightarrow>(44)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_PPNi (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 :: int)::ii) (( 10 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_SV39_PTE_RSW : SV39_PTE -> mword ty2*) + +fun get_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word " where + " get_SV39_PTE_RSW (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) :: 2 Word.word))" + + +(*val _set_SV39_PTE_RSW : register_ref regstate register_value SV39_PTE -> mword ty2 -> M unit*) + +definition set_SV39_PTE_RSW :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(2)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_PTE_RSW r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 9 :: int)::ii) (( 8 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +(*val _update_SV39_PTE_RSW : SV39_PTE -> mword ty2 -> SV39_PTE*) + +fun update_SV39_PTE_RSW :: " SV39_PTE \<Rightarrow>(2)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_RSW (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 :: int)::ii) (( 8 :: int)::ii) x :: 64 Word.word)))" + + +(*val _get_SV39_PTE_BITS : SV39_PTE -> mword ty8*) + +fun get_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word " where + " get_SV39_PTE_BITS (Mk_SV39_PTE (v)) = ( (subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word))" + + +(*val _set_SV39_PTE_BITS : register_ref regstate register_value SV39_PTE -> mword ty8 -> M unit*) + +definition set_SV39_PTE_BITS :: "((regstate),(register_value),(SV39_PTE))register_ref \<Rightarrow>(8)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " set_SV39_PTE_BITS r_ref v = ( + reg_deref r_ref \<bind> (\<lambda> (w__0 :: SV39_PTE) . + (let r = ((get_SV39_PTE w__0 :: 64 Word.word)) in + (let r = ((update_subrange_vec_dec r (( 7 :: int)::ii) (( 0 :: int)::ii) v :: 64 Word.word)) in + write_reg r_ref (Mk_SV39_PTE r)))))" + + +(*val _update_SV39_PTE_BITS : SV39_PTE -> mword ty8 -> SV39_PTE*) + +fun update_SV39_PTE_BITS :: " SV39_PTE \<Rightarrow>(8)Word.word \<Rightarrow> SV39_PTE " where + " update_SV39_PTE_BITS (Mk_SV39_PTE (v)) x = ( + Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 :: int)::ii) (( 0 :: int)::ii) x :: 64 Word.word)))" + + +(*val curAsid64 : unit -> M (mword ty16)*) + +definition curAsid64 :: " unit \<Rightarrow>((register_value),((16)Word.word),(exception))monad " where + " curAsid64 _ = ( + (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let satp64 = (Mk_Satp64 w__0) in + return ((get_Satp64_Asid satp64 :: 16 Word.word)))))" + + +(*val curPTB39 : unit -> M (mword ty56)*) + +definition curPTB39 :: " unit \<Rightarrow>((register_value),((56)Word.word),(exception))monad " where + " curPTB39 _ = ( + (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let satp64 = (Mk_Satp64 w__0) in + return ((EXTZ (( 56 :: int)::ii) + ((shiftl ((get_Satp64_PPN satp64 :: 44 Word.word)) PAGESIZE_BITS :: 44 Word.word)) + :: 56 Word.word)))))" + + +(*val walk39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> mword ty56 -> ii -> bool -> M PTW_Result*) + +function (sequential,domintros) walk39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(PTW_Result),(exception))monad " where + " walk39 vaddr ac priv mxr do_sum ptb level global1 = ( + (let va = (Mk_SV39_Vaddr vaddr) in + (let (pt_ofs :: paddr39) = + ((shiftl + ((EXTZ (( 56 :: int)::ii) + ((subrange_vec_dec + ((shiftr ((get_SV39_Vaddr_VPNi va :: 27 Word.word)) + ((level * SV39_LEVEL_BITS)) + :: 27 Word.word)) ((SV39_LEVEL_BITS - (( 1 :: int)::ii))) (( 0 :: int)::ii) + :: 9 Word.word)) + :: 56 Word.word)) PTE39_LOG_SIZE + :: 56 Word.word)) in + (let pte_addr = ((add_vec ptb pt_ofs :: 56 Word.word)) in + (checked_mem_read Data ((EXTZ (( 64 :: int)::ii) pte_addr :: 64 Word.word)) (( 8 :: int)::ii) + :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__0 :: ( 64 Word.word) MemoryOpResult) . + (case w__0 of + MemException (_) => return (PTW_Failure PTW_Access) + | MemValue (v) => + (let pte = (Mk_SV39_PTE v) in + (let pbits = ((get_SV39_PTE_BITS pte :: 8 Word.word)) in + (let pattr = (Mk_PTE_Bits pbits) in + (let is_global = + (global1 \<or> (((((get_PTE_Bits_G pattr :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word)))))) in + if ((isInvalidPTE pbits)) then return (PTW_Failure PTW_Invalid_PTE) + else if ((isPTEPtr pbits)) then + if (((level = (( 0 :: int)::ii)))) then return (PTW_Failure PTW_Invalid_PTE) + else + walk39 vaddr ac priv mxr do_sum + ((EXTZ (( 56 :: int)::ii) + ((shiftl ((get_SV39_PTE_PPNi pte :: 44 Word.word)) PAGESIZE_BITS :: 44 Word.word)) + :: 56 Word.word)) ((level - (( 1 :: int)::ii))) is_global + else + checkPTEPermission ac priv mxr do_sum pattr \<bind> (\<lambda> (w__3 :: bool) . + return (if ((\<not> w__3)) then PTW_Failure PTW_No_Permission + else if ((level > (( 0 :: int)::ii))) then + (let mask1 = + ((sub_vec_int + ((shiftl + ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((xor_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 44 Word.word)) + :: 44 Word.word)) + :: 44 Word.word)) ((level * SV39_LEVEL_BITS)) + :: 44 Word.word)) (( 1 :: int)::ii) + :: 44 Word.word)) in + if (((((and_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) mask1 :: 44 Word.word)) \<noteq> ((EXTZ (( 44 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 44 Word.word))))) then + PTW_Failure PTW_Misaligned + else + (let ppn = + ((or_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((and_vec + ((EXTZ (( 44 :: int)::ii) ((get_SV39_Vaddr_VPNi va :: 27 Word.word)) :: 44 Word.word)) + mask1 + :: 44 Word.word)) + :: 44 Word.word)) in + PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va :: 12 Word.word)) + :: 56 Word.word),pte,pte_addr,level,is_global))) + else + PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte :: 44 Word.word)) + ((get_SV39_Vaddr_PgOfs va :: 12 Word.word)) + :: 56 Word.word),pte,pte_addr,level,is_global))))))) + ))))))" +by pat_completeness auto + + +(*val make_TLB39_Entry : mword ty16 -> bool -> mword ty39 -> mword ty56 -> SV39_PTE -> ii -> mword ty56 -> M TLB39_Entry*) + +definition make_TLB39_Entry :: "(16)Word.word \<Rightarrow> bool \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow> int \<Rightarrow>(56)Word.word \<Rightarrow>((register_value),(TLB39_Entry),(exception))monad " where + " make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr = ( + (let (shift :: ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in + (let (vAddrMask :: vaddr39) = + ((sub_vec_int + ((shiftl + ((xor_vec vAddr + ((xor_vec vAddr ((EXTZ (( 39 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 39 Word.word)) + :: 39 Word.word)) + :: 39 Word.word)) shift + :: 39 Word.word)) (( 1 :: int)::ii) + :: 39 Word.word)) in + (let (vMatchMask :: vaddr39) = ((not_vec vAddrMask :: 39 Word.word)) in + (read_reg mcycle_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + return ((| TLB39_Entry_asid = asid, + TLB39_Entry_global = global1, + TLB39_Entry_vAddr = ((and_vec vAddr vMatchMask :: 39 Word.word)), + TLB39_Entry_pAddr = + ((shiftl ((shiftr pAddr shift :: 56 Word.word)) shift :: 56 Word.word)), + TLB39_Entry_vMatchMask = vMatchMask, + TLB39_Entry_vAddrMask = vAddrMask, + TLB39_Entry_pte = pte, + TLB39_Entry_pteAddr = pteAddr, + TLB39_Entry_age = w__0 |)))))))" + + +definition TLBEntries :: " int " where + " TLBEntries = ( (( 32 :: int)::ii))" + + +(*val lookupTLB39 : mword ty16 -> mword ty39 -> M (maybe ((ii * TLB39_Entry)))*) + +definition lookupTLB39 :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>((register_value),((int*TLB39_Entry)option),(exception))monad " where + " lookupTLB39 asid vaddr = ( + read_reg tlb39_ref \<bind> (\<lambda> (w__0 :: TLB39_Entry option) . + return ((case w__0 of + None => None + | Some (e) => + if (((((((TLB39_Entry_global e) \<or> ((((TLB39_Entry_asid e) = asid)))))) \<and> ((((TLB39_Entry_vAddr e) = ((and_vec(TLB39_Entry_vMatchMask e) vaddr :: 39 Word.word)))))))) + then + Some ((( 0 :: int)::ii), e) + else None + ))))" + + +(*val addToTLB39 : mword ty16 -> mword ty39 -> mword ty56 -> SV39_PTE -> mword ty56 -> ii -> bool -> M unit*) + +definition addToTLB39 :: "(16)Word.word \<Rightarrow>(39)Word.word \<Rightarrow>(56)Word.word \<Rightarrow> SV39_PTE \<Rightarrow>(56)Word.word \<Rightarrow> int \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " addToTLB39 asid vAddr pAddr pte pteAddr level global1 = ( + make_TLB39_Entry asid global1 vAddr pAddr pte level pteAddr \<bind> (\<lambda> ent . + write_reg tlb39_ref (Some ent)))" + + +(*val writeTLB39 : ii -> TLB39_Entry -> M unit*) + +definition writeTLB39 :: " int \<Rightarrow> TLB39_Entry \<Rightarrow>((register_value),(unit),(exception))monad " where + " writeTLB39 (idx :: ii) (ent :: TLB39_Entry) = ( write_reg tlb39_ref (Some ent))" + + +(*val flushTLB : maybe (mword ty16) -> maybe (mword ty39) -> M unit*) + +definition flushTLB :: "((16)Word.word)option \<Rightarrow>((39)Word.word)option \<Rightarrow>((register_value),(unit),(exception))monad " where + " flushTLB asid addr = ( + read_reg tlb39_ref \<bind> (\<lambda> (w__0 :: TLB39_Entry option) . + (let (ent :: TLB39_Entry option) = + ((case (w__0, asid, addr) of + (None, _, _) => None + | (Some (e), None, None) => None + | (Some (e), None, Some (a)) => + if ((((TLB39_Entry_vAddr e) = ((and_vec(TLB39_Entry_vMatchMask e) a :: 39 Word.word))))) then + None + else Some e + | (Some (e), Some (i), None) => + if (((((((TLB39_Entry_asid e) = i))) \<and> ((\<not>(TLB39_Entry_global e)))))) then None + else Some e + | (Some (e), Some (i), Some (a)) => + if (((((((TLB39_Entry_asid e) = i))) \<and> (((((((TLB39_Entry_vAddr e) = ((and_vec a(TLB39_Entry_vMatchMask e) :: 39 Word.word))))) \<and> ((\<not>(TLB39_Entry_global e))))))))) then + None + else Some e + )) in + write_reg tlb39_ref ent)))" + + +definition enable_dirty_update :: " bool " where + " enable_dirty_update = ( False )" + + +(*val translate39 : mword ty39 -> AccessType -> Privilege -> bool -> bool -> ii -> M TR39_Result*) + +definition translate39 :: "(39)Word.word \<Rightarrow> AccessType \<Rightarrow> Privilege \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> int \<Rightarrow>((register_value),(TR39_Result),(exception))monad " where + " translate39 vAddr ac priv mxr do_sum level = ( + (curAsid64 () :: ( 16 Word.word) M) \<bind> (\<lambda> asid . + lookupTLB39 asid vAddr \<bind> (\<lambda> (w__0 :: ((ii * TLB39_Entry))option) . + (case w__0 of + Some (idx,ent) => + (let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS(TLB39_Entry_pte ent) :: 8 Word.word))) in + checkPTEPermission ac priv mxr do_sum pteBits \<bind> (\<lambda> (w__1 :: bool) . + if ((\<not> w__1)) then return (TR39_Failure PTW_No_Permission) + else + (case ((update_PTE_Bits pteBits ac)) of + None => + return (TR39_Address ((or_vec(TLB39_Entry_pAddr ent) + ((EXTZ (( 56 :: int)::ii) + ((and_vec vAddr(TLB39_Entry_vAddrMask ent) :: 39 Word.word)) + :: 56 Word.word)) + :: 56 Word.word))) + | Some (pbits) => + if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + else + (let (n_ent :: TLB39_Entry) = ent in + (let n_ent = + ((n_ent (| + TLB39_Entry_pte := + ((update_SV39_PTE_BITS(TLB39_Entry_pte ent) ((get_PTE_Bits pbits :: 8 Word.word))))|))) in + (writeTLB39 idx n_ent \<then> + checked_mem_write ((EXTZ (( 64 :: int)::ii)(TLB39_Entry_pteAddr ent) :: 64 Word.word)) (( 8 :: int)::ii) + ((get_SV39_PTE(TLB39_Entry_pte ent) :: 64 Word.word))) \<bind> (\<lambda> (w__2 :: unit + MemoryOpResult) . + (case w__2 of + MemValue (_) => return () + | MemException (e) => internal_error (''invalid physical address in TLB'') + ) \<then> + return (TR39_Address ((or_vec(TLB39_Entry_pAddr ent) + ((EXTZ (( 56 :: int)::ii) + ((and_vec vAddr(TLB39_Entry_vAddrMask ent) :: 39 Word.word)) + :: 56 Word.word)) + :: 56 Word.word)))))) + ))) + | None => + (curPTB39 () :: ( 56 Word.word) M) \<bind> (\<lambda> (w__6 :: 56 Word.word) . + walk39 vAddr ac priv mxr do_sum w__6 level False \<bind> (\<lambda> (w__7 :: PTW_Result) . + (case w__7 of + PTW_Failure (f) => return (TR39_Failure f) + | PTW_Success (pAddr,pte,pteAddr,level,global1) => + (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte :: 8 Word.word))) ac)) of + None => + addToTLB39 asid vAddr pAddr pte pteAddr level global1 \<then> return (TR39_Address pAddr) + | Some (pbits) => + if ((\<not> enable_dirty_update)) then return (TR39_Failure PTW_PTE_Update) + else + (let (w_pte :: SV39_PTE) = + (update_SV39_PTE_BITS pte ((get_PTE_Bits pbits :: 8 Word.word))) in + checked_mem_write ((EXTZ (( 64 :: int)::ii) pteAddr :: 64 Word.word)) (( 8 :: int)::ii) + ((get_SV39_PTE w_pte :: 64 Word.word)) \<bind> (\<lambda> (w__8 :: unit MemoryOpResult) . + (case w__8 of + MemValue (_) => + addToTLB39 asid vAddr pAddr w_pte pteAddr level global1 \<then> + return (TR39_Address pAddr) + | MemException (e) => return (TR39_Failure PTW_Access) + ))) + ) + ))) + ))))" + + +(*val translationMode : Privilege -> M SATPMode*) + +definition translationMode :: " Privilege \<Rightarrow>((register_value),(SATPMode),(exception))monad " where + " translationMode priv = ( + if (((((privLevel_to_bits priv :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) + then + return Sbare + else + read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (let arch = (architecture ((get_Mstatus_SXL w__0 :: 2 Word.word))) in + (case arch of + Some (RV64) => + (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (mbits :: satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1) :: 4 Word.word)) in + (case ((satpMode_of_bits RV64 mbits)) of + Some (m) => return m + | None => internal_error (''invalid RV64 translation mode in satp'') + ))) + | _ => internal_error (''unsupported address translation arch'') + ))))" + + +(*val translateAddr : mword ty64 -> AccessType -> ReadType -> M TR_Result*) + +definition translateAddr :: "(64)Word.word \<Rightarrow> AccessType \<Rightarrow> ReadType \<Rightarrow>((register_value),(TR_Result),(exception))monad " where + " translateAddr vAddr ac rt = ( + (case rt of + Instruction => read_reg cur_privilege_ref + | Data => + read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . + if (((((get_Mstatus_MPRV w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . + return ((privLevel_of_bits ((get_Mstatus_MPP w__2 :: 2 Word.word))))) + else read_reg cur_privilege_ref) + ) \<bind> (\<lambda> (effPriv :: Privilege) . + read_reg mstatus_ref \<bind> (\<lambda> (w__5 :: Mstatus) . + (let (mxr :: bool) = + (((get_Mstatus_MXR w__5 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in + read_reg mstatus_ref \<bind> (\<lambda> (w__6 :: Mstatus) . + (let (do_sum :: bool) = + (((get_Mstatus_SUM w__6 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))) in + translationMode effPriv \<bind> (\<lambda> (mode :: SATPMode) . + (case mode of + Sbare => return (TR_Address vAddr) + | SV39 => + translate39 + ((subrange_vec_dec vAddr (( 38 :: int):: ii) (( 0 :: int):: ii) :: 39 Word.word)) + ac effPriv mxr do_sum ((SV39_LEVELS - (( 1 :: int):: ii))) \<bind> + (\<lambda> (w__7 :: TR39_Result) . + return + ((case w__7 of + TR39_Address (pa) => TR_Address + ((EXTZ (( 64 :: int):: ii) pa :: 64 Word.word)) + | TR39_Failure (f) => TR_Failure ((translationException ac f)) + ))) + ))))))))" + + +(*val decode : mword ty32 -> maybe ast*) + +(*val decodeCompressed : mword ty16 -> maybe ast*) + +(*val execute : ast -> M unit*) + +(*val print_insn : ast -> string*) + +(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> MemoryOpResult (mword 'int8_times_n) -> MemoryOpResult (mword ty64)*) + +fun extend_value :: " bool \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow>((64)Word.word)MemoryOpResult " where + " extend_value is_unsigned (MemValue (v)) = ( + MemValue (if is_unsigned then (EXTZ (( 64 :: int)::ii) v :: 64 Word.word) + else (EXTS (( 64 :: int)::ii) v :: 64 Word.word)))" +|" extend_value is_unsigned (MemException (e)) = ( MemException e )" + + +(*val process_load : forall 'int8_times_n . Size 'int8_times_n => mword ty5 -> mword ty64 -> MemoryOpResult (mword 'int8_times_n) -> bool -> M unit*) + +definition process_load :: "(5)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(('int8_times_n::len)Word.word)MemoryOpResult \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " process_load rd addr value1 is_unsigned = ( + (case ((extend_value is_unsigned value1 :: ( 64 Word.word) MemoryOpResult)) of + MemValue (result) => wX ((regbits_to_regno rd)) result + | MemException (e) => handle_mem_exception addr e + ))" + + +(*val process_loadres : forall 'int8_times_n . regbits -> xlenbits -> MemoryOpResult (bits 'int8_times_n) -> bool -> unit*) + +(*val readCSR : mword ty12 -> M (mword ty64)*) + +definition readCSR :: "(12)Word.word \<Rightarrow>((register_value),((64)Word.word),(exception))monad " where + " readCSR csr = ( + (let b__0 = csr in + if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mvendorid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg marchid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mimpid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B1,B1,B0,B0,B0,B1,B0,B1,B0,B0] :: 12 Word.word)))) then + (read_reg mhartid_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__4 :: Mstatus) . return ((get_Mstatus w__4 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + read_reg misa_ref \<bind> (\<lambda> (w__5 :: Misa) . return ((get_Misa w__5 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg medeleg_ref \<bind> (\<lambda> (w__6 :: Medeleg) . return ((get_Medeleg w__6 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg mideleg_ref \<bind> (\<lambda> (w__7 :: Minterrupts) . + return ((get_Minterrupts w__7 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__8 :: Minterrupts) . return ((get_Minterrupts w__8 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg mtvec_ref \<bind> (\<lambda> (w__9 :: Mtvec) . return ((get_Mtvec w__9 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mepc_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg mcause_ref \<bind> (\<lambda> (w__12 :: Mcause) . return ((get_Mcause w__12 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg mtval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__14 :: Minterrupts) . + return ((get_Minterrupts w__14 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__15 :: Mstatus) . return ((get_Mstatus w__15 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg sedeleg_ref \<bind> (\<lambda> (w__16 :: Sedeleg) . return ((get_Sedeleg w__16 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg sideleg_ref \<bind> (\<lambda> (w__17 :: Sinterrupts) . + return ((get_Sinterrupts w__17 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__18 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__19 :: Minterrupts) . + return ((get_Sinterrupts ((lower_mie w__18 w__19)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg stvec_ref \<bind> (\<lambda> (w__20 :: Mtvec) . return ((get_Mtvec w__20 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg sscratch_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg sepc_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg scause_ref \<bind> (\<lambda> (w__23 :: Mcause) . return ((get_Mcause w__23 :: 64 Word.word))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (read_reg stval_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__25 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__26 :: Minterrupts) . + return ((get_Sinterrupts ((lower_mip w__25 w__26)) :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg satp_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg mcycle_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (read_reg mtime_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (read_reg minstret_ref :: ( 64 Word.word) M) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (read_reg tselect_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__31 :: 64 Word.word) . + return ((not_vec w__31 :: 64 Word.word))) + else + (let (_ :: unit) = (print_bits (''unhandled read to CSR '') csr) in + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word))))" + + +(*val writeCSR : mword ty12 -> mword ty64 -> M unit*) + +definition writeCSR :: "(12)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " writeCSR (csr :: csreg) (value1 :: xlenbits) = ( + (let b__0 = csr in + (if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__0 :: Mstatus) . + (write_reg mstatus_ref ((legalize_mstatus w__0 value1)) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__1 :: Mstatus) . + return (Some ((get_Mstatus w__1 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg medeleg_ref \<bind> (\<lambda> (w__2 :: Medeleg) . + (write_reg medeleg_ref ((legalize_medeleg w__2 value1)) \<then> + read_reg medeleg_ref) \<bind> (\<lambda> (w__3 :: Medeleg) . + return (Some ((get_Medeleg w__3 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + read_reg mideleg_ref \<bind> (\<lambda> (w__4 :: Minterrupts) . + (write_reg mideleg_ref ((legalize_mideleg w__4 value1)) \<then> + read_reg mideleg_ref) \<bind> (\<lambda> (w__5 :: Minterrupts) . + return (Some ((get_Minterrupts w__5 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__6 :: Minterrupts) . + (write_reg mie_ref ((legalize_mie w__6 value1)) \<then> + read_reg mie_ref) \<bind> (\<lambda> (w__7 :: Minterrupts) . + return (Some ((get_Minterrupts w__7 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg mtvec_ref \<bind> (\<lambda> (w__8 :: Mtvec) . + (write_reg mtvec_ref ((legalize_tvec w__8 value1)) \<then> + read_reg mtvec_ref) \<bind> (\<lambda> (w__9 :: Mtvec) . return (Some ((get_Mtvec w__9 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg mscratch_ref value1 \<then> + (read_reg mscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__10 :: 64 Word.word) . return (Some w__10)) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: xlenbits) . + (write_reg mepc_ref w__11 \<then> + (read_reg mepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__12 :: 64 Word.word) . return (Some w__12))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (set_Mcause mcause_ref value1 \<then> + read_reg mcause_ref) \<bind> (\<lambda> (w__13 :: Mcause) . + return (Some ((get_Mcause w__13 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (write_reg mtval_ref value1 \<then> + (read_reg mtval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) . return (Some w__14)) + else if (((b__0 = (vec_of_bits [B0,B0,B1,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__15 :: Minterrupts) . + (write_reg mip_ref ((legalize_mip w__15 value1)) \<then> + read_reg mip_ref) \<bind> (\<lambda> (w__16 :: Minterrupts) . + return (Some ((get_Minterrupts w__16 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + read_reg mstatus_ref \<bind> (\<lambda> (w__17 :: Mstatus) . + (write_reg mstatus_ref ((legalize_sstatus w__17 value1)) \<then> + read_reg mstatus_ref) \<bind> (\<lambda> (w__18 :: Mstatus) . + return (Some ((get_Mstatus w__18 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + read_reg sedeleg_ref \<bind> (\<lambda> (w__19 :: Sedeleg) . + (write_reg sedeleg_ref ((legalize_sedeleg w__19 value1)) \<then> + read_reg sedeleg_ref) \<bind> (\<lambda> (w__20 :: Sedeleg) . + return (Some ((get_Sedeleg w__20 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (set_Sinterrupts sideleg_ref value1 \<then> + read_reg sideleg_ref) \<bind> (\<lambda> (w__21 :: Sinterrupts) . + return (Some ((get_Sinterrupts w__21 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mie_ref \<bind> (\<lambda> (w__22 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__23 :: Minterrupts) . + (write_reg mie_ref ((legalize_sie w__22 w__23 value1)) \<then> + read_reg mie_ref) \<bind> (\<lambda> (w__24 :: Minterrupts) . + return (Some ((get_Minterrupts w__24 :: 64 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1] :: 12 Word.word)))) then + read_reg stvec_ref \<bind> (\<lambda> (w__25 :: Mtvec) . + (write_reg stvec_ref ((legalize_tvec w__25 value1)) \<then> + read_reg stvec_ref) \<bind> (\<lambda> (w__26 :: Mtvec) . return (Some ((get_Mtvec w__26 :: 64 Word.word))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg sscratch_ref value1 \<then> + (read_reg sscratch_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__27 :: 64 Word.word) . return (Some w__27)) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B1] :: 12 Word.word)))) then + (legalize_xepc value1 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: xlenbits) . + (write_reg sepc_ref w__28 \<then> + (read_reg sepc_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__29 :: 64 Word.word) . return (Some w__29))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B0] :: 12 Word.word)))) then + (set_Mcause scause_ref value1 \<then> + read_reg scause_ref) \<bind> (\<lambda> (w__30 :: Mcause) . + return (Some ((get_Mcause w__30 :: 64 Word.word)))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B1,B1] :: 12 Word.word)))) then + (write_reg stval_ref value1 \<then> + (read_reg stval_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 Word.word) . return (Some w__31)) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B0,B1,B0,B0,B0,B1,B0,B0] :: 12 Word.word)))) then + read_reg mip_ref \<bind> (\<lambda> (w__32 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__33 :: Minterrupts) . + (write_reg mip_ref ((legalize_sip w__32 w__33 value1)) \<then> + read_reg mip_ref) \<bind> (\<lambda> (w__34 :: Minterrupts) . + return (Some ((get_Minterrupts w__34 :: 64 Word.word)))))) + else if (((b__0 = (vec_of_bits [B0,B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + cur_Architecture () \<bind> (\<lambda> (w__35 :: Architecture) . + (read_reg satp_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__36 :: 64 Word.word) . + (write_reg satp_ref ((legalize_satp w__35 w__36 value1 :: 64 Word.word)) \<then> + (read_reg satp_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__37 :: 64 Word.word) . return (Some w__37)))) + else if (((b__0 = (vec_of_bits [B0,B1,B1,B1,B1,B0,B1,B0,B0,B0,B0,B0] :: 12 Word.word)))) then + (write_reg tselect_ref value1 \<then> + (read_reg tselect_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__38 :: 64 Word.word) . return (Some w__38)) + else return None) \<bind> (\<lambda> (res :: xlenbits option) . + return ((case res of + Some (v) => + prerr_endline + (((op@) (''CSR '') + (((op@) ((csr_name csr)) + (((op@) ('' <- '') + (((op@) ((string_of_vec v)) + (((op@) ('' (input: '') (((op@) ((string_of_vec value1)) ('')''))))))))))))) + | None => print_bits (''unhandled write to CSR '') csr + )))))" + + +definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where + " decode v__0 = ( + if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (UTYPE (imm,rd,RISCV_LUI)))) + else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (UTYPE (imm,rd,RISCV_AUIPC)))) + else if (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))) then + (let (imm :: 20 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 12 :: int)::ii) :: 20 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) + ((concat_vec + ((cast_unit_vec0 ((access_vec_dec imm (( 8 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm (( 18 :: int)::ii) (( 13 :: int)::ii) :: 6 Word.word)) + ((concat_vec + ((subrange_vec_dec imm (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 20 Word.word)) + :: 21 Word.word),rd)))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B1,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RISCV_JALR (imm,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BEQ)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BNE)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BLT)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BGE)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BLTU)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 :: int)::ii))) :: 1 Word.word)) + ((concat_vec ((subrange_vec_dec imm7 (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + ((concat_vec ((subrange_vec_dec imm5 (( 4 :: int)::ii) (( 1 :: int)::ii) :: 4 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 5 Word.word)) + :: 11 Word.word)) + :: 12 Word.word)) + :: 13 Word.word),rs2,rs1,RISCV_BGEU)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_SLTI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_SLTIU))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_XORI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ORI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ANDI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 26 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 6 bits) = ((subrange_vec_dec v__0 (( 25 :: int)::ii) (( 20 :: int)::ii) :: 6 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_ADD))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SUB))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLL))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLT))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SLTU))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_XOR))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SRL))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_SRA))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_OR))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPE (rs2,rs1,rd,RISCV_AND))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,BYTE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,HALF,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,WORD,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,False,DOUBLE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,BYTE,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,HALF,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd,True,WORD,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,BYTE,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,HALF,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,WORD,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm7 :: 7 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (imm5 :: 5 bits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORE ((concat_vec imm7 imm5 :: 12 Word.word),rs2,rs1,DOUBLE,False,False)))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ADDIW (imm,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SLLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SRLI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (shamt :: 5 bits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (SHIFTW (shamt,rs1,rd,RISCV_SRAI))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_ADDW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SUBW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SLLW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SRLW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B0,B0,B0,B0] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (RTYPEW (rs2,rs1,rd,RISCV_SRAW))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,False,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,True,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,True,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MUL (rs2,rs1,rd,True,False,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIV (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REM (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B0,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REM (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (MULW (rs2,rs1,rd))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIVW (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (DIVW (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REMW (rs2,rs1,rd,True))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B1] :: 7 Word.word)))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B1,B1,B0,B1,B1] :: 7 Word.word)))))))))) then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (REMW (rs2,rs1,rd,False))))) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 28 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 0 :: int)::ii) :: 20 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B1] + :: 20 Word.word))))))) then + (let (pred :: 4 bits) = ((subrange_vec_dec v__0 (( 27 :: int)::ii) (( 24 :: int)::ii) :: 4 Word.word)) in + (let (succ :: 4 bits) = ((subrange_vec_dec v__0 (( 23 :: int)::ii) (( 20 :: int)::ii) :: 4 Word.word)) in + Some (FENCE (pred,succ)))) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0, + B0,B0,B0,B0,B1,B1,B1,B1] + :: 32 Word.word)))) then + Some (FENCEI () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (ECALL () ) + else if (((v__0 = (vec_of_bits [B0,B0,B1,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (MRET () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (SRET () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (EBREAK () ) + else if (((v__0 = (vec_of_bits [B0,B0,B0,B1,B0,B0,B0,B0,B0,B1,B0,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B1,B1,B1,B0,B0,B1,B1] + :: 32 Word.word)))) then + Some (WFI () ) + else if ((((((((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 25 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B1,B0,B0,B1] :: 7 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 0 :: int)::ii) :: 15 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B1,B1,B1,B0,B0,B1,B1] :: 15 Word.word))))))) + then + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + Some (SFENCE_VMA (rs1,rs2)))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd)))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word))))))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd)))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B1] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B0,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B0,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))))))) + else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 27 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))))) \<and> ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B1,B0,B1,B1,B1,B1] :: 7 Word.word)))))))))) then + (let aq = (access_vec_dec v__0 (( 26 :: int)::ii)) in + (let rl = (access_vec_dec v__0 (( 25 :: int)::ii)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__0 (( 24 :: int)::ii) (( 20 :: int)::ii) :: 5 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRW))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRS))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,False,CSRRC))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRW))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRS))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (csr :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (CSR (csr,rs1,rd,True,CSRRC))))) + else None )" + + +definition decodeCompressed :: "(16)Word.word \<Rightarrow>(ast)option " where + " decodeCompressed v__418 = ( + if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi1 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi0 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((nzi1 = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B0,B0] :: 5 Word.word))))))))) then + Some (NOP () ) + else None)) + else if (((v__418 = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word)))) then + Some (ILLEGAL () ) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (nz54 :: 2 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 11 :: int)::ii) :: 2 Word.word)) in + (let (nz96 :: 4 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 7 :: int)::ii) :: 4 Word.word)) in + (let (nz2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nz3 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let nzimm = + ((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2 :: 2 Word.word)) :: 4 Word.word)) + :: 8 Word.word)) in + if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word)))) then None + else Some (C_ADDI4SPN (rd,nzimm)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in + Some (C_LW (uimm,rs1,rd)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rd :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in + Some (C_LD (uimm,rs1,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui2 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (ui6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2 :: 4 Word.word)) :: 5 Word.word)) in + Some (C_SW (uimm,rs1,rs2)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (rs1 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let uimm = ((concat_vec ui76 ui53 :: 5 Word.word)) in + Some (C_SD (uimm,rs1,rs2))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzi40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let nzi = ((concat_vec nzi5 nzi40 :: 6 Word.word)) in + if ((((((nzi = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_ADDI (nzi,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + Some (C_ADDIW ((concat_vec imm5 imm40 :: 6 Word.word),rsd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LI ((concat_vec imm5 imm40 :: 6 Word.word),rd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)))) = ((regbits_to_regno (vec_of_bits [B0,B0,B0,B1,B0] :: 5 Word.word)))))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzi9 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (nzi4 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (nzi6 :: 1 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 5 :: int)::ii) :: 1 Word.word)) in + (let (nzi87 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (nzi5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + (let nzimm = + ((concat_vec nzi9 + ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4 :: 2 Word.word)) :: 3 Word.word)) + :: 5 Word.word)) + :: 6 Word.word)) in + if (((nzimm = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_ADDI16SP nzimm))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (imm17 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (imm1612 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then + None + else Some (C_LUI ((concat_vec imm17 imm1612 :: 6 Word.word),rd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_SRLI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if (((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) then None + else Some (C_SRAI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B0] :: 3 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + Some (C_ANDI ((concat_vec i5 i40 :: 6 Word.word),rsd))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_SUB (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_XOR (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_OR (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B0,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_AND (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B0] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_SUBW (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 10 :: int)::ii) :: 6 Word.word)) = (vec_of_bits [B1,B0,B0,B1,B1,B1] :: 6 Word.word)))) \<and> ((((((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word)))))))))) then + (let (rsd :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: cregbits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + Some (C_ADDW (rsd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i11 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i4 :: 1 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 11 :: int)::ii) :: 1 Word.word)) in + (let (i98 :: 2 bits) = ((subrange_vec_dec v__418 (( 10 :: int)::ii) (( 9 :: int)::ii) :: 2 Word.word)) in + (let (i10 :: 1 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word)) in + (let (i6 :: 1 bits) = ((subrange_vec_dec v__418 (( 7 :: int)::ii) (( 7 :: int)::ii) :: 1 Word.word)) in + (let (i7 :: 1 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 6 :: int)::ii) :: 1 Word.word)) in + (let (i31 :: 3 bits) = ((subrange_vec_dec v__418 (( 5 :: int)::ii) (( 3 :: int)::ii) :: 3 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_J ((concat_vec i11 + ((concat_vec i10 + ((concat_vec i98 + ((concat_vec i7 + ((concat_vec i6 + ((concat_vec i5 ((concat_vec i4 i31 :: 4 Word.word)) :: 5 Word.word)) + :: 6 Word.word)) + :: 7 Word.word)) + :: 9 Word.word)) + :: 10 Word.word)) + :: 11 Word.word))))))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_BEQZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word),rs)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then + (let (i8 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (i43 :: 2 bits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 10 :: int)::ii) :: 2 Word.word)) in + (let (rs :: cregbits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (i76 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (i21 :: 2 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 3 :: int)::ii) :: 2 Word.word)) in + (let (i5 :: 1 bits) = ((subrange_vec_dec v__418 (( 2 :: int)::ii) (( 2 :: int)::ii) :: 1 Word.word)) in + Some (C_BNEZ ((concat_vec i8 + ((concat_vec i76 + ((concat_vec i5 ((concat_vec i43 i21 :: 4 Word.word)) :: 5 Word.word)) + :: 7 Word.word)) + :: 8 Word.word),rs)))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (nzui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (nzui40 :: 5 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (shamt :: 6 bits) = ((concat_vec nzui5 nzui40 :: 6 Word.word)) in + if ((((((shamt = (vec_of_bits [B0,B0,B0,B0,B0,B0] :: 6 Word.word)))) \<or> (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_SLLI (shamt,rsd)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui42 :: 3 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 4 :: int)::ii) :: 3 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 3 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui76 ((concat_vec ui5 ui42 :: 4 Word.word)) :: 6 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LWSP (uimm,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui5 :: 1 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (ui43 :: 2 bits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 5 :: int)::ii) :: 2 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 4 :: int)::ii) (( 2 :: int)::ii) :: 3 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui86 ((concat_vec ui5 ui43 :: 3 Word.word)) :: 6 Word.word)) in + if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then None + else Some (C_LDSP (uimm,rd))))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui52 :: 4 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 9 :: int)::ii) :: 4 Word.word)) in + (let (ui76 :: 2 bits) = ((subrange_vec_dec v__418 (( 8 :: int)::ii) (( 7 :: int)::ii) :: 2 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui76 ui52 :: 6 Word.word)) in + Some (C_SWSP (uimm,rs2)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 13 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B1,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (ui53 :: 3 bits) = ((subrange_vec_dec v__418 (( 12 :: int)::ii) (( 10 :: int)::ii) :: 3 Word.word)) in + (let (ui86 :: 3 bits) = ((subrange_vec_dec v__418 (( 9 :: int)::ii) (( 7 :: int)::ii) :: 3 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + (let (uimm :: 6 bits) = ((concat_vec ui86 ui53 :: 6 Word.word)) in + Some (C_SDSP (uimm,rs2)))))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None + else Some (C_JR rs1)) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B0] :: 7 Word.word))))))) then + (let (rs1 :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then None + else Some (C_JALR rs1)) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B0] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_MV (rd,rs2)))) + else if ((((((((subrange_vec_dec v__418 (( 15 :: int)::ii) (( 12 :: int)::ii) :: 4 Word.word)) = (vec_of_bits [B1,B0,B0,B1] :: 4 Word.word)))) \<and> (((((subrange_vec_dec v__418 (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B0] :: 2 Word.word))))))) then + (let (rsd :: regbits) = ((subrange_vec_dec v__418 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + (let (rs2 :: regbits) = ((subrange_vec_dec v__418 (( 6 :: int)::ii) (( 2 :: int)::ii) :: 5 Word.word)) in + if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \<or> (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then + None + else Some (C_ADD (rsd,rs2)))) + else None )" + + +(*val execute_WFI : unit -> M unit*) + +fun execute_WFI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_WFI g__110 = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (case w__0 of + Machine => return () + | Supervisor => + read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . + if (((((get_Mstatus_TW w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + handle_illegal () + else return () ) + | User => handle_illegal () + )))" + + +(*val execute_UTYPE : mword ty20 -> mword ty5 -> uop -> M unit*) + +fun execute_UTYPE :: "(20)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> uop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_UTYPE imm rd op1 = ( + (let (off :: xlenbits) = + ((EXTS (( 64 :: int)::ii) + ((concat_vec imm (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 12 Word.word) + :: 32 Word.word)) + :: 64 Word.word)) in + (case op1 of + RISCV_LUI => return off + | RISCV_AUIPC => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + return ((add_vec w__0 off :: 64 Word.word))) + ) \<bind> (\<lambda> (ret :: xlenbits) . + wX ((regbits_to_regno rd)) ret)))" + + +(*val execute_STORECON : bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_STORECON :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_STORECON aq rl rs2 rs1 width rd = ( + speculate_conditional_success () \<bind> (\<lambda> (w__0 :: bool) . + (let (status :: 1 bits) = + (if w__0 then (vec_of_bits [B0] :: 1 Word.word) + else (vec_of_bits [B1] :: 1 Word.word)) in + wX ((regbits_to_regno rd)) ((EXTZ (( 64 :: int)::ii) status :: 64 Word.word)) \<then> + (if (((status = (vec_of_bits [B1] :: 1 Word.word)))) then return () + else + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . + translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl True + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (case width of + WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + aq rl True + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl True + | _ => internal_error (''STORECON expected word or double'') + ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . + (case res of + MemValue (_) => return () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))))" + + +(*val execute_STORE : mword ty12 -> mword ty5 -> mword ty5 -> word_width -> bool -> bool -> M unit*) + +fun execute_STORE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_STORE imm rs2 rs1 width aq rl = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + translateAddr vaddr Write Data \<bind> (\<lambda> (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => mem_write_ea addr (( 1 :: int)::ii) aq rl False + | HALF => mem_write_ea addr (( 2 :: int)::ii) aq rl False + | WORD => mem_write_ea addr (( 4 :: int)::ii) aq rl False + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) aq rl False + ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (case width of + BYTE => + mem_write_value addr (( 1 :: int)::ii) ((subrange_vec_dec rs2_val (( 7 :: int)::ii) (( 0 :: int)::ii) :: 8 Word.word)) aq + rl False + | HALF => + mem_write_value addr (( 2 :: int)::ii) ((subrange_vec_dec rs2_val (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word)) aq + rl False + | WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec rs2_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) aq + rl False + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) rs2_val aq rl False + ) \<bind> (\<lambda> (res :: unit MemoryOpResult) . + (case res of + MemValue (_) => return () + | MemException (e) => handle_mem_exception addr e + ))) + )) + )))))" + + +(*val execute_SRET : unit -> M unit*) + +fun execute_SRET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SRET g__108 = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (case w__0 of + User => handle_illegal () + | Supervisor => + read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . + if (((((get_Mstatus_TSR w__1 :: 1 Word.word)) = ((bool_to_bits True :: 1 Word.word))))) then + handle_illegal () + else + read_reg cur_privilege_ref \<bind> (\<lambda> (w__2 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + (handle_exception w__2 (CTL_SRET () ) w__3 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: xlenbits) . + write_reg nextPC_ref w__4)))) + | Machine => + read_reg cur_privilege_ref \<bind> (\<lambda> (w__5 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . + (handle_exception w__5 (CTL_SRET () ) w__6 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: xlenbits) . + write_reg nextPC_ref w__7))) + )))" + + +(*val execute_SHIFTW : mword ty5 -> mword ty5 -> mword ty5 -> sop -> M unit*) + +fun execute_SHIFTW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SHIFTW shamt rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (result :: 32 bits) = + ((case op1 of + RISCV_SLLI => (shift_bits_left rs1_val shamt :: 32 Word.word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 32 Word.word) + | RISCV_SRAI => (shift_right_arith32 rs1_val shamt :: 32 Word.word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))" + + +(*val execute_SHIFTIOP : mword ty6 -> mword ty5 -> mword ty5 -> sop -> M unit*) + +fun execute_SHIFTIOP :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> sop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SHIFTIOP shamt rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (let (result :: xlenbits) = + ((case op1 of + RISCV_SLLI => (shift_bits_left rs1_val shamt :: 64 Word.word) + | RISCV_SRLI => (shift_bits_right rs1_val shamt :: 64 Word.word) + | RISCV_SRAI => (shift_right_arith64 rs1_val shamt :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result)))" + + +(*val execute_SFENCE_VMA : mword ty5 -> mword ty5 -> M unit*) + +fun execute_SFENCE_VMA :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_SFENCE_VMA rs1 rs2 = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits User :: 2 Word.word))))) + then + handle_illegal () + else + read_reg mstatus_ref \<bind> (\<lambda> (w__1 :: Mstatus) . + read_reg mstatus_ref \<bind> (\<lambda> (w__2 :: Mstatus) . + (let p__104 = + (architecture ((get_Mstatus_SXL w__1 :: 2 Word.word)), (get_Mstatus_TVM w__2 :: 1 Word.word)) in + (case p__104 of + (Some (RV64), v_0) => + if (((v_0 = ((bool_to_bits True :: 1 Word.word))))) then handle_illegal () + else + (if (((((regbits_to_regno rs1)) = (( 0 :: int)::ii)))) then return None + else + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . + return (Some ((subrange_vec_dec w__3 (( 38 :: int)::ii) (( 0 :: int)::ii) :: 39 Word.word))))) \<bind> (\<lambda> (addr :: + vaddr39 option) . + (if (((((regbits_to_regno rs2)) = (( 0 :: int)::ii)))) then return None + else + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . + return (Some ((subrange_vec_dec w__4 (( 15 :: int)::ii) (( 0 :: int)::ii) :: 16 Word.word))))) \<bind> (\<lambda> (asid :: + asid64 option) . + flushTLB asid addr)) + | (g__102, g__103) => internal_error (''unimplemented sfence architecture'') + ))))))" + + +(*val execute_RTYPEW : mword ty5 -> mword ty5 -> mword ty5 -> ropw -> M unit*) + +fun execute_RTYPEW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> ropw \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RTYPEW rs2 rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (result :: 32 bits) = + ((case op1 of + RISCV_ADDW => (add_vec rs1_val rs2_val :: 32 Word.word) + | RISCV_SUBW => (sub_vec rs1_val rs2_val :: 32 Word.word) + | RISCV_SLLW => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + | RISCV_SRLW => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + | RISCV_SRAW => + (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 :: int)::ii) (( 0 :: int)::ii) :: 5 Word.word)) + :: 32 Word.word) + )) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) result :: 64 Word.word))))))))" + + +(*val execute_RTYPE : mword ty5 -> mword ty5 -> mword ty5 -> rop -> M unit*) + +fun execute_RTYPE :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> rop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RTYPE rs2 rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (let (result :: xlenbits) = + ((case op1 of + RISCV_ADD => (add_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SUB => (sub_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SLL => + (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_SLT => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_SLTU => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val rs2_val)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_XOR => (xor_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_SRL => + (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_SRA => + (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 :: int)::ii) (( 0 :: int)::ii) :: 6 Word.word)) + :: 64 Word.word) + | RISCV_OR => (or_vec rs1_val rs2_val :: 64 Word.word) + | RISCV_AND => (and_vec rs1_val rs2_val :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_RISCV_JALR : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_RISCV_JALR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RISCV_JALR imm rs1 rd = ( + (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (wX ((regbits_to_regno rd)) w__0 \<then> + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let (newPC :: xlenbits) = ((add_vec w__1 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + write_reg + nextPC_ref + ((concat_vec ((subrange_vec_dec newPC (( 63 :: int)::ii) (( 1 :: int)::ii) :: 63 Word.word)) + (vec_of_bits [B0] :: 1 Word.word) + :: 64 Word.word))))))" + + +(*val execute_RISCV_JAL : mword ty21 -> mword ty5 -> M unit*) + +fun execute_RISCV_JAL :: "(21)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_RISCV_JAL imm rd = ( + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (pc :: xlenbits) . + (read_reg nextPC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + wX ((regbits_to_regno rd)) w__0 \<then> + ((let (offset :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + write_reg nextPC_ref ((add_vec pc offset :: 64 Word.word)))))))" + + +(*val execute_REMW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_REMW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_REMW rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) r :: 32 Word.word)) :: 64 Word.word))))))))))" + + +(*val execute_REM : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_REM :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_REM rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (r :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in + wX ((regbits_to_regno rd)) ((to_bits xlen r :: 64 Word.word))))))))" + + +(*val execute_NOP : unit -> unit*) + +fun execute_NOP :: " unit \<Rightarrow> unit " where + " execute_NOP g__111 = ( () )" + + +(*val execute_MULW : mword ty5 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_MULW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MULW rs2 rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (Word.sint rs1_val) in + (let (rs2_int :: ii) = (Word.sint rs2_val) in + (let result32 = + ((subrange_vec_dec ((to_bits (( 64 :: int)::ii) ((rs1_int * rs2_int)) :: 64 Word.word)) (( 31 :: int)::ii) + (( 0 :: int)::ii) + :: 32 Word.word)) in + (let (result :: xlenbits) = ((EXTS (( 64 :: int)::ii) result32 :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result)))))))))" + + +(*val execute_MUL : mword ty5 -> mword ty5 -> mword ty5 -> bool -> bool -> bool -> M unit*) + +fun execute_MUL :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MUL rs2 rs1 rd high signed1 signed2 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (let (rs1_int :: ii) = (if signed1 then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if signed2 then Word.sint rs2_val else Word.uint rs2_val) in + (let result128 = ((to_bits (( 128 :: int)::ii) ((rs1_int * rs2_int)) :: 128 Word.word)) in + (let result = + (if high then (subrange_vec_dec result128 (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word) + else (subrange_vec_dec result128 (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result)))))))" + + +(*val execute_MRET : unit -> M unit*) + +fun execute_MRET :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_MRET g__107 = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + if (((((privLevel_to_bits w__0 :: 2 Word.word)) = ((privLevel_to_bits Machine :: 2 Word.word))))) + then + read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (handle_exception w__1 (CTL_MRET () ) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + write_reg nextPC_ref w__3))) + else handle_illegal () ))" + + +(*val execute_LOADRES : bool -> bool -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_LOADRES :: " bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LOADRES aq rl rs1 width rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . + translateAddr vaddr Read Data \<bind> (\<lambda> (w__0 :: TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => + (mem_read addr (( 4 :: int)::ii) aq rl True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__1 :: ( 32 Word.word) + MemoryOpResult) . + process_load rd addr w__1 False) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl True :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 64 Word.word) + MemoryOpResult) . + process_load rd addr w__2 False) + | _ => internal_error (''LOADRES expected WORD or DOUBLE'') + ) + ))))" + + +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> bool -> word_width -> bool -> bool -> M unit*) + +fun execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> word_width \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_LOAD imm rs1 rd is_unsigned width aq rl = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (vaddr :: xlenbits) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + translateAddr vaddr Read Data \<bind> (\<lambda> (w__1 :: TR_Result) . + (case w__1 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + BYTE => + (mem_read addr (( 1 :: int)::ii) aq rl False :: ( ( 8 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__2 :: ( 8 Word.word) + MemoryOpResult) . + process_load rd vaddr w__2 is_unsigned) + | HALF => + (mem_read addr (( 2 :: int)::ii) aq rl False :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__3 :: ( 16 Word.word) + MemoryOpResult) . + process_load rd vaddr w__3 is_unsigned) + | WORD => + (mem_read addr (( 4 :: int)::ii) aq rl False :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 32 Word.word) + MemoryOpResult) . + process_load rd vaddr w__4 is_unsigned) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq rl False :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 64 Word.word) + MemoryOpResult) . + process_load rd vaddr w__5 is_unsigned) + ) + )))))" + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + +fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ITYPE imm rs1 rd op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (let (immext :: xlenbits) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let (result :: xlenbits) = + ((case op1 of + RISCV_ADDI => (add_vec rs1_val immext :: 64 Word.word) + | RISCV_SLTI => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_s rs1_val immext)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_SLTIU => + (EXTZ (( 64 :: int)::ii) ((bool_to_bits ((zopz0zI_u rs1_val immext)) :: 1 Word.word)) :: 64 Word.word) + | RISCV_XORI => (xor_vec rs1_val immext :: 64 Word.word) + | RISCV_ORI => (or_vec rs1_val immext :: 64 Word.word) + | RISCV_ANDI => (and_vec rs1_val immext :: 64 Word.word) + )) in + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_ILLEGAL : unit -> M unit*) + +fun execute_ILLEGAL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ILLEGAL g__112 = ( handle_illegal () )" + + +(*val execute_FENCEI : unit -> M unit*) + +fun execute_FENCEI :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_FENCEI g__105 = ( MEM_fence_i () )" + + +(*val execute_FENCE : mword ty4 -> mword ty4 -> M unit*) + +fun execute_FENCE :: "(4)Word.word \<Rightarrow>(4)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_FENCE b__0 b__1 = ( + if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then + MEM_fence_rw_rw () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word))))))) then + MEM_fence_r_rw () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B1,B0] :: 4 Word.word))))))) then + MEM_fence_r_r () + else if ((((((b__0 = (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word)))) \<and> (((b__1 = (vec_of_bits [B0,B0,B0,B1] :: 4 Word.word))))))) then + MEM_fence_rw_w () + else MEM_fence_w_w () )" + + +(*val execute_ECALL : unit -> M unit*) + +fun execute_ECALL :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ECALL g__106 = ( + read_reg cur_privilege_ref \<bind> (\<lambda> (w__0 :: Privilege) . + (let (t :: sync_exception) = + ((| sync_exception_trap = + ((case w__0 of + User => E_U_EnvCall + | Supervisor => E_S_EnvCall + | Machine => E_M_EnvCall + )), + sync_exception_excinfo = None |)) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (handle_exception w__1 (CTL_TRAP t) w__2 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: xlenbits) . + write_reg nextPC_ref w__3))))))" + + +(*val execute_EBREAK : unit -> M unit*) + +fun execute_EBREAK :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_EBREAK g__109 = ( throw (Error_EBREAK () ))" + + +(*val execute_DIVW : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_DIVW :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIVW rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let rs1_val = ((subrange_vec_dec w__0 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (let rs2_val = ((subrange_vec_dec w__1 (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) in + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in + (let (q' :: ii) = + (if (((s \<and> ((q > ((((pow2 (( 31 :: int)::ii))) - (( 1 :: int)::ii)))))))) then + (( 0 :: int)::ii) - ((ex_int ((pow (( 2 :: int)::ii) (( 31 :: int)::ii))))) + else q) in + wX ((regbits_to_regno rd)) ((EXTS (( 64 :: int)::ii) ((to_bits (( 32 :: int)::ii) q' :: 32 Word.word)) :: 64 Word.word)))))))))))" + + +(*val execute_DIV : mword ty5 -> mword ty5 -> mword ty5 -> bool -> M unit*) + +fun execute_DIV :: "(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_DIV rs2 rs1 rd s = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (let (rs1_int :: ii) = (if s then Word.sint rs1_val else Word.uint rs1_val) in + (let (rs2_int :: ii) = (if s then Word.sint rs2_val else Word.uint rs2_val) in + (let (q :: ii) = (if (((rs2_int = (( 0 :: int)::ii)))) then ((( 0 :: int)-( 1 :: int))::ii) else hardware_quot rs1_int rs2_int) in + (let (q' :: ii) = (if (((s \<and> ((q > xlen_max_signed))))) then xlen_min_signed else q) in + wX ((regbits_to_regno rd)) ((to_bits xlen q' :: 64 Word.word)))))))))" + + +(*val execute_C_ADDIW : mword ty6 -> mword ty5 -> M unit*) + +fun execute_C_ADDIW :: "(6)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_C_ADDIW imm rsd = ( + (let (imm :: 32 bits) = ((EXTS (( 32 :: int)::ii) imm :: 32 Word.word)) in + (rX ((regbits_to_regno rsd)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs_val . + (let (res :: 32 bits) = + ((add_vec ((subrange_vec_dec rs_val (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) imm :: 32 Word.word)) in + wX ((regbits_to_regno rsd)) ((EXTS (( 64 :: int)::ii) res :: 64 Word.word))))))" + + +(*val execute_CSR : mword ty12 -> mword ty5 -> mword ty5 -> bool -> csrop -> M unit*) + +fun execute_CSR :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bool \<Rightarrow> csrop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_CSR csr rs1 rd is_imm op1 = ( + (if is_imm then return ((EXTZ (( 64 :: int)::ii) rs1 :: 64 Word.word)) + else (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (rs1_val :: xlenbits) . + (let (isWrite :: bool) = + ((case op1 of + CSRRW => True + | _ => if is_imm then (((Word.uint rs1_val)) \<noteq> (( 0 :: int)::ii)) else (((Word.uint rs1)) \<noteq> (( 0 :: int)::ii)) + )) in + read_reg cur_privilege_ref \<bind> (\<lambda> (w__1 :: Privilege) . + check_CSR csr w__1 isWrite \<bind> (\<lambda> (w__2 :: bool) . + if ((\<not> w__2)) then handle_illegal () + else + (readCSR csr :: ( 64 Word.word) M) \<bind> (\<lambda> csr_val . + (if isWrite then + (let (new_val :: xlenbits) = + ((case op1 of + CSRRW => rs1_val + | CSRRS => (or_vec csr_val rs1_val :: 64 Word.word) + | CSRRC => (and_vec csr_val ((not_vec rs1_val :: 64 Word.word)) :: 64 Word.word) + )) in + writeCSR csr new_val) + else return () ) \<then> + wX ((regbits_to_regno rd)) csr_val))))))" + + +(*val execute_BTYPE : mword ty13 -> mword ty5 -> mword ty5 -> bop -> M unit*) + +fun execute_BTYPE :: "(13)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> bop \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_BTYPE imm rs2 rs1 op1 = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs2_val . + (let (taken :: bool) = + ((case op1 of + RISCV_BEQ => (rs1_val = rs2_val) + | RISCV_BNE => (rs1_val \<noteq> rs2_val) + | RISCV_BLT => zopz0zI_s rs1_val rs2_val + | RISCV_BGE => zopz0zKzJ_s rs1_val rs2_val + | RISCV_BLTU => zopz0zI_u rs1_val rs2_val + | RISCV_BGEU => zopz0zKzJ_u rs1_val rs2_val + )) in + if taken then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + write_reg nextPC_ref ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word))) + else return () ))))" + + +(*val execute_AMO : amoop -> bool -> bool -> mword ty5 -> mword ty5 -> word_width -> mword ty5 -> M unit*) + +fun execute_AMO :: " amoop \<Rightarrow> bool \<Rightarrow> bool \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> word_width \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_AMO op1 aq rl rs2 rs1 width rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddr :: xlenbits) . + translateAddr vaddr ReadWrite Data \<bind> (\<lambda> (w__0 :: TR_Result) . + (case w__0 of + TR_Failure (e) => handle_mem_exception vaddr e + | TR_Address (addr) => + (case width of + WORD => mem_write_ea addr (( 4 :: int)::ii) (((aq \<and> rl))) rl True + | DOUBLE => mem_write_ea addr (( 8 :: int)::ii) (((aq \<and> rl))) rl True + | _ => internal_error (''AMO expected WORD or DOUBLE'') + ) \<bind> (\<lambda> (eares :: unit MemoryOpResult) . + (case eares of + MemException (e) => handle_mem_exception addr e + | MemValue (_) => + (case width of + WORD => + (mem_read addr (( 4 :: int)::ii) aq (((aq \<and> rl))) True :: ( ( 32 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__4 :: ( 32 Word.word) + MemoryOpResult) . + return ((extend_value False w__4 :: ( 64 Word.word) MemoryOpResult))) + | DOUBLE => + (mem_read addr (( 8 :: int)::ii) aq (((aq \<and> rl))) True :: ( ( 64 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__5 :: ( 64 Word.word) + MemoryOpResult) . + return ((extend_value False w__5 :: ( 64 Word.word) MemoryOpResult))) + | _ => (internal_error (''AMO expected WORD or DOUBLE'') :: ( ( 64 Word.word)MemoryOpResult) M) + ) \<bind> (\<lambda> (rval :: xlenbits MemoryOpResult) . + (case rval of + MemException (e) => handle_mem_exception addr e + | MemValue (loaded) => + (rX ((regbits_to_regno rs2)) :: ( 64 Word.word) M) \<bind> (\<lambda> (rs2_val :: xlenbits) . + (let (result :: xlenbits) = + ((case op1 of + AMOSWAP => rs2_val + | AMOADD => (add_vec rs2_val loaded :: 64 Word.word) + | AMOXOR => (xor_vec rs2_val loaded :: 64 Word.word) + | AMOAND => (and_vec rs2_val loaded :: 64 Word.word) + | AMOOR => (or_vec rs2_val loaded :: 64 Word.word) + | AMOMIN => (vector64 ((min ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word) + | AMOMAX => (vector64 ((max ((Word.sint rs2_val)) ((Word.sint loaded)))) :: 64 Word.word) + | AMOMINU => (vector64 ((min ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word) + | AMOMAXU => (vector64 ((max ((Word.uint rs2_val)) ((Word.uint loaded)))) :: 64 Word.word) + )) in + (case width of + WORD => + mem_write_value addr (( 4 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) + (((aq \<and> rl))) rl True + | DOUBLE => mem_write_value addr (( 8 :: int)::ii) result (((aq \<and> rl))) rl True + | _ => internal_error (''AMO expected WORD or DOUBLE'') + ) \<bind> (\<lambda> (wval :: unit MemoryOpResult) . + (case wval of + MemValue (_) => wX ((regbits_to_regno rd)) loaded + | MemException (e) => handle_mem_exception addr e + )))) + )) + )) + ))))" + + +(*val execute_ADDIW : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +fun execute_ADDIW :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute_ADDIW imm rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (result :: xlenbits) = ((add_vec ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) w__0 :: 64 Word.word)) in + wX ((regbits_to_regno rd)) + ((EXTS (( 64 :: int)::ii) ((subrange_vec_dec result (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)) :: 64 Word.word)))))" + + +function (sequential,domintros) execute :: " ast \<Rightarrow>((register_value),(unit),(exception))monad " where + " execute (C_ADDI4SPN (rdc,nzimm)) = ( + (let (imm :: 12 bits) = + ((concat_vec (vec_of_bits [B0,B0] :: 2 Word.word) + ((concat_vec nzimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 10 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + execute (ITYPE (imm,sp,rd,RISCV_ADDI)))))" +|" execute (C_LW (uimm,rsc,rdc)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + (let rs = ((creg2reg_bits rsc :: 5 Word.word)) in + execute (LOAD (imm,rs,rd,False,WORD,False,False))))))" +|" execute (C_LD (uimm,rsc,rdc)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + (let rd = ((creg2reg_bits rdc :: 5 Word.word)) in + (let rs = ((creg2reg_bits rsc :: 5 Word.word)) in + execute (LOAD (imm,rs,rd,False,DOUBLE,False,False))))))" +|" execute (C_SW (uimm,rsc1,rsc2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 7 Word.word)) + :: 12 Word.word)) in + (let rs1 = ((creg2reg_bits rsc1 :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rsc2 :: 5 Word.word)) in + execute (STORE (imm,rs2,rs1,WORD,False,False))))))" +|" execute (C_SD (uimm,rsc1,rsc2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + (let rs1 = ((creg2reg_bits rsc1 :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rsc2 :: 5 Word.word)) in + execute (STORE (imm,rs2,rs1,DOUBLE,False,False))))))" +|" execute (C_ADDI (nzi,rsd)) = ( + (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) nzi :: 12 Word.word)) in + execute (ITYPE (imm,rsd,rsd,RISCV_ADDI))))" +|" execute (C_JAL (imm)) = ( + execute + (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)) + :: 21 Word.word),ra)))" +|" execute (C_LI (imm,rd)) = ( + (let (imm :: 12 bits) = ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word)) in + execute (ITYPE (imm,zreg,rd,RISCV_ADDI))))" +|" execute (C_ADDI16SP (imm)) = ( + (let (imm :: 12 bits) = + ((EXTS (( 12 :: int)::ii) ((concat_vec imm (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word) :: 10 Word.word)) + :: 12 Word.word)) in + execute (ITYPE (imm,sp,sp,RISCV_ADDI))))" +|" execute (C_LUI (imm,rd)) = ( + (let (res :: 20 bits) = ((EXTS (( 20 :: int)::ii) imm :: 20 Word.word)) in + execute (UTYPE (res,rd,RISCV_LUI))))" +|" execute (C_SRLI (shamt,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI))))" +|" execute (C_SRAI (shamt,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI))))" +|" execute (C_ANDI (imm,rsd)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + execute (ITYPE ((EXTS (( 12 :: int)::ii) imm :: 12 Word.word),rsd,rsd,RISCV_ANDI))))" +|" execute (C_SUB (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_SUB)))))" +|" execute (C_XOR (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_XOR)))))" +|" execute (C_OR (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_OR)))))" +|" execute (C_AND (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPE (rs2,rsd,rsd,RISCV_AND)))))" +|" execute (C_SUBW (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW)))))" +|" execute (C_ADDW (rsd,rs2)) = ( + (let rsd = ((creg2reg_bits rsd :: 5 Word.word)) in + (let rs2 = ((creg2reg_bits rs2 :: 5 Word.word)) in + execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW)))))" +|" execute (C_J (imm)) = ( + execute + (RISCV_JAL ((EXTS (( 21 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word)) + :: 21 Word.word),zreg)))" +|" execute (C_BEQZ (imm,rs)) = ( + execute + (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word)) + :: 13 Word.word),zreg,(creg2reg_bits rs :: 5 Word.word),RISCV_BEQ)))" +|" execute (C_BNEZ (imm,rs)) = ( + execute + (BTYPE ((EXTS (( 13 :: int)::ii) ((concat_vec imm (vec_of_bits [B0] :: 1 Word.word) :: 9 Word.word)) + :: 13 Word.word),zreg,(creg2reg_bits rs :: 5 Word.word),RISCV_BNE)))" +|" execute (C_SLLI (shamt,rsd)) = ( execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI)))" +|" execute (C_LWSP (uimm,rd)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + execute (LOAD (imm,sp,rd,False,WORD,False,False))))" +|" execute (C_LDSP (uimm,rd)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word)) + :: 12 Word.word)) in + execute (LOAD (imm,sp,rd,False,DOUBLE,False,False))))" +|" execute (C_SWSP (uimm,rs2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0] :: 2 Word.word) :: 8 Word.word)) + :: 12 Word.word)) in + execute (STORE (imm,rs2,sp,WORD,False,False))))" +|" execute (C_SDSP (uimm,rs2)) = ( + (let (imm :: 12 bits) = + ((EXTZ (( 12 :: int)::ii) ((concat_vec uimm (vec_of_bits [B0,B0,B0] :: 3 Word.word) :: 9 Word.word)) + :: 12 Word.word)) in + execute (STORE (imm,rs2,sp,DOUBLE,False,False))))" +|" execute (C_JR (rs1)) = ( + execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word),rs1,zreg)))" +|" execute (C_JALR (rs1)) = ( + execute (RISCV_JALR ((EXTZ (( 12 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 12 Word.word),rs1,ra)))" +|" execute (C_MV (rd,rs2)) = ( execute (RTYPE (rs2,zreg,rd,RISCV_ADD)))" +|" execute (C_ADD (rsd,rs2)) = ( execute (RTYPE (rs2,rsd,rsd,RISCV_ADD)))" +|" execute (UTYPE (imm,rd,op1)) = ( execute_UTYPE imm rd op1 )" +|" execute (RISCV_JAL (imm,rd)) = ( execute_RISCV_JAL imm rd )" +|" execute (RISCV_JALR (imm,rs1,rd)) = ( execute_RISCV_JALR imm rs1 rd )" +|" execute (BTYPE (imm,rs2,rs1,op1)) = ( execute_BTYPE imm rs2 rs1 op1 )" +|" execute (ITYPE (imm,rs1,rd,op1)) = ( execute_ITYPE imm rs1 rd op1 )" +|" execute (SHIFTIOP (shamt,rs1,rd,op1)) = ( execute_SHIFTIOP shamt rs1 rd op1 )" +|" execute (RTYPE (rs2,rs1,rd,op1)) = ( execute_RTYPE rs2 rs1 rd op1 )" +|" execute (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = ( execute_LOAD imm rs1 rd is_unsigned width aq rl )" +|" execute (STORE (imm,rs2,rs1,width,aq,rl)) = ( execute_STORE imm rs2 rs1 width aq rl )" +|" execute (ADDIW (imm,rs1,rd)) = ( execute_ADDIW imm rs1 rd )" +|" execute (SHIFTW (shamt,rs1,rd,op1)) = ( execute_SHIFTW shamt rs1 rd op1 )" +|" execute (RTYPEW (rs2,rs1,rd,op1)) = ( execute_RTYPEW rs2 rs1 rd op1 )" +|" execute (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( execute_MUL rs2 rs1 rd high signed1 signed2 )" +|" execute (DIV (rs2,rs1,rd,s)) = ( execute_DIV rs2 rs1 rd s )" +|" execute (REM (rs2,rs1,rd,s)) = ( execute_REM rs2 rs1 rd s )" +|" execute (MULW (rs2,rs1,rd)) = ( execute_MULW rs2 rs1 rd )" +|" execute (DIVW (rs2,rs1,rd,s)) = ( execute_DIVW rs2 rs1 rd s )" +|" execute (REMW (rs2,rs1,rd,s)) = ( execute_REMW rs2 rs1 rd s )" +|" execute (FENCE (pred,succ)) = ( execute_FENCE pred succ )" +|" execute (FENCEI (g__105)) = ( execute_FENCEI g__105 )" +|" execute (ECALL (g__106)) = ( execute_ECALL g__106 )" +|" execute (MRET (g__107)) = ( execute_MRET g__107 )" +|" execute (SRET (g__108)) = ( execute_SRET g__108 )" +|" execute (EBREAK (g__109)) = ( execute_EBREAK g__109 )" +|" execute (WFI (g__110)) = ( execute_WFI g__110 )" +|" execute (SFENCE_VMA (rs1,rs2)) = ( execute_SFENCE_VMA rs1 rs2 )" +|" execute (LOADRES (aq,rl,rs1,width,rd)) = ( execute_LOADRES aq rl rs1 width rd )" +|" execute (STORECON (aq,rl,rs2,rs1,width,rd)) = ( execute_STORECON aq rl rs2 rs1 width rd )" +|" execute (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( execute_AMO op1 aq rl rs2 rs1 width rd )" +|" execute (CSR (csr,rs1,rd,is_imm,op1)) = ( execute_CSR csr rs1 rd is_imm op1 )" +|" execute (NOP (g__111)) = ( return ((execute_NOP g__111)))" +|" execute (ILLEGAL (g__112)) = ( execute_ILLEGAL g__112 )" +|" execute (C_ADDIW (imm,rsd)) = ( execute_C_ADDIW imm rsd )" +by pat_completeness auto + + +fun print_insn :: " ast \<Rightarrow> string " where + " print_insn (UTYPE (imm,rd,op1)) = ( + (case op1 of + RISCV_LUI => + (op@) (''lui '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) + | RISCV_AUIPC => + (op@) (''auipc '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))) + ))" +|" print_insn (RISCV_JAL (imm,rd)) = ( + (op@) (''jal '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (RISCV_JALR (imm,rs1,rd)) = ( + (op@) (''jalr '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" +|" print_insn (BTYPE (imm,rs2,rs1,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_BEQ => (''beq '') + | RISCV_BNE => (''bne '') + | RISCV_BLT => (''blt '') + | RISCV_BGE => (''bge '') + | RISCV_BLTU => (''bltu '') + | RISCV_BGEU => (''bgeu '') + )) in + (op@) insn + (((op@) ((reg_name_abi rs1)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs2)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (ITYPE (imm,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADDI => (''addi '') + | RISCV_SLTI => (''slti '') + | RISCV_SLTIU => (''sltiu '') + | RISCV_XORI => (''xori '') + | RISCV_ORI => (''ori '') + | RISCV_ANDI => (''andi '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (SHIFTIOP (shamt,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" +|" print_insn (RTYPE (rs2,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADD => (''add '') + | RISCV_SUB => (''sub '') + | RISCV_SLL => (''sll '') + | RISCV_SLT => (''slt '') + | RISCV_SLTU => (''sltu '') + | RISCV_XOR => (''xor '') + | RISCV_SRL => (''srl '') + | RISCV_SRA => (''sra '') + | RISCV_OR => (''or '') + | RISCV_AND => (''and '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (LOAD (imm,rs1,rd,is_unsigned,width,aq,rl)) = ( + (let (insn :: string) = + ((case (width, is_unsigned) of + (BYTE, False) => (''lb '') + | (BYTE, True) => (''lbu '') + | (HALF, False) => (''lh '') + | (HALF, True) => (''lhu '') + | (WORD, False) => (''lw '') + | (WORD, True) => (''lwu '') + | (DOUBLE, False) => (''ld '') + | (DOUBLE, True) => (''ldu '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (STORE (imm,rs2,rs1,width,aq,rl)) = ( + (let (insn :: string) = + ((case width of + BYTE => (''sb '') + | HALF => (''sh '') + | WORD => (''sw '') + | DOUBLE => (''sd '') + )) in + (op@) insn + (((op@) ((reg_name_abi rs2)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm))))))))))))" +|" print_insn (ADDIW (imm,rs1,rd)) = ( + (op@) (''addiw '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec imm)))))))))))" +|" print_insn (SHIFTW (shamt,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of RISCV_SLLI => (''slli '') | RISCV_SRLI => (''srli '') | RISCV_SRAI => (''srai '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((string_of_vec shamt))))))))))))" +|" print_insn (RTYPEW (rs2,rs1,rd,op1)) = ( + (let (insn :: string) = + ((case op1 of + RISCV_ADDW => (''addw '') + | RISCV_SUBW => (''subw '') + | RISCV_SLLW => (''sllw '') + | RISCV_SRLW => (''srlw '') + | RISCV_SRAW => (''sraw '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (MUL (rs2,rs1,rd,high,signed1,signed2)) = ( + (let (insn :: string) = + ((case (high, signed1, signed2) of + (False, True, True) => (''mul '') + | (True, True, True) => (''mulh '') + | (True, True, False) => (''mulhsu '') + | (True, False, False) => (''mulhu'') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (DIV (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''div '') else (''divu '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (REM (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''rem '') else (''remu '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (MULW (rs2,rs1,rd)) = ( + (op@) (''mulw '') + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))))))" +|" print_insn (DIVW (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''divw '') else (''divuw '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (REMW (rs2,rs1,rd,s)) = ( + (let (insn :: string) = (if s then (''remw '') else (''remuw '')) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (FENCE (pred,succ)) = ( (''fence''))" +|" print_insn (FENCEI (g__93)) = ( (''fence.i''))" +|" print_insn (ECALL (g__94)) = ( (''ecall''))" +|" print_insn (MRET (g__95)) = ( (''mret''))" +|" print_insn (SRET (g__96)) = ( (''sret''))" +|" print_insn (EBREAK (g__97)) = ( (''ebreak''))" +|" print_insn (WFI (g__98)) = ( (''wfi''))" +|" print_insn (SFENCE_VMA (rs1,rs2)) = ( + (op@) (''sfence.vma '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2)))))))" +|" print_insn (LOADRES (aq,rl,rs1,width,rd)) = ( + (let (insn :: string) = + ((case width of WORD => (''lr.w '') | DOUBLE => (''lr.d '') | _ => (''lr.bad '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs1))))))))" +|" print_insn (STORECON (aq,rl,rs2,rs1,width,rd)) = ( + (let (insn :: string) = + ((case width of WORD => (''sc.w '') | DOUBLE => (''sc.d '') | _ => (''sc.bad '') )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (AMO (op1,aq,rl,rs2,rs1,width,rd)) = ( + (let (insn :: string) = + ((case (op1, width) of + (AMOSWAP, WORD) => (''amoswap.w '') + | (AMOADD, WORD) => (''amoadd.w '') + | (AMOXOR, WORD) => (''amoxor.w '') + | (AMOAND, WORD) => (''amoand.w '') + | (AMOOR, WORD) => (''amoor.w '') + | (AMOMIN, WORD) => (''amomin.w '') + | (AMOMAX, WORD) => (''amomax.w '') + | (AMOMINU, WORD) => (''amominu.w '') + | (AMOMAXU, WORD) => (''amomaxu.w '') + | (AMOSWAP, DOUBLE) => (''amoswap.d '') + | (AMOADD, DOUBLE) => (''amoadd.d '') + | (AMOXOR, DOUBLE) => (''amoxor.d '') + | (AMOAND, DOUBLE) => (''amoand.d '') + | (AMOOR, DOUBLE) => (''amoor.d '') + | (AMOMIN, DOUBLE) => (''amomin.d '') + | (AMOMAX, DOUBLE) => (''amomax.d '') + | (AMOMINU, DOUBLE) => (''amominu.d '') + | (AMOMAXU, DOUBLE) => (''amomaxu.d '') + | (_, _) => (''amo.bad '') + )) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') + (((op@) ((reg_name_abi rs1)) (((op@) ('', '') ((reg_name_abi rs2))))))))))))" +|" print_insn (CSR (csr,rs1,rd,is_imm,op1)) = ( + (let (insn :: string) = + ((case (op1, is_imm) of + (CSRRW, True) => (''csrrwi '') + | (CSRRW, False) => (''csrrw '') + | (CSRRS, True) => (''csrrsi '') + | (CSRRS, False) => (''csrrs '') + | (CSRRC, True) => (''csrrci '') + | (CSRRC, False) => (''csrrc '') + )) in + (let (rs1_str :: string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in + (op@) insn + (((op@) ((reg_name_abi rd)) + (((op@) ('', '') (((op@) rs1_str (((op@) ('', '') ((csr_name csr)))))))))))))" +|" print_insn (NOP (g__99)) = ( (''nop''))" +|" print_insn (ILLEGAL (g__100)) = ( (''illegal''))" +|" print_insn (C_ADDI4SPN (rdc,nzimm)) = ( + (op@) (''c.addi4spn '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec nzimm)))))))" +|" print_insn (C_LW (uimm,rsc,rdc)) = ( + (op@) (''c.lw '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_LD (uimm,rsc,rdc)) = ( + (op@) (''c.ld '') + (((op@) ((reg_name_abi ((creg2reg_bits rdc :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_SW (uimm,rsc1,rsc2)) = ( + (op@) (''c.sw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_SD (uimm,rsc1,rsc2)) = ( + (op@) (''c.sd '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc1 :: 5 Word.word)))) + (((op@) ('', '') + (((op@) ((reg_name_abi ((creg2reg_bits rsc2 :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec uimm)))))))))))" +|" print_insn (C_ADDI (nzi,rsd)) = ( + (op@) (''c.addi '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec nzi)))))))" +|" print_insn (C_JAL (imm)) = ( (op@) (''c.jal '') ((string_of_vec imm)))" +|" print_insn (C_ADDIW (imm,rsd)) = ( + (op@) (''c.addiw '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_LI (imm,rd)) = ( + (op@) (''c.li '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_ADDI16SP (imm)) = ( (op@) (''c.addi16sp '') ((string_of_vec imm)))" +|" print_insn (C_LUI (imm,rd)) = ( + (op@) (''c.lui '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SRLI (shamt,rsd)) = ( + (op@) (''c.srli '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_SRAI (shamt,rsd)) = ( + (op@) (''c.srai '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_ANDI (imm,rsd)) = ( + (op@) (''c.andi '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SUB (rsd,rs2)) = ( + (op@) (''c.sub '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_XOR (rsd,rs2)) = ( + (op@) (''c.xor '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_OR (rsd,rs2)) = ( + (op@) (''c.or '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_AND (rsd,rs2)) = ( + (op@) (''c.and '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_SUBW (rsd,rs2)) = ( + (op@) (''c.subw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_ADDW (rsd,rs2)) = ( + (op@) (''c.addw '') + (((op@) ((reg_name_abi ((creg2reg_bits rsd :: 5 Word.word)))) + (((op@) ('', '') ((reg_name_abi ((creg2reg_bits rs2 :: 5 Word.word)))))))))" +|" print_insn (C_J (imm)) = ( (op@) (''c.j '') ((string_of_vec imm)))" +|" print_insn (C_BEQZ (imm,rs)) = ( + (op@) (''c.beqz '') + (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_BNEZ (imm,rs)) = ( + (op@) (''c.bnez '') + (((op@) ((reg_name_abi ((creg2reg_bits rs :: 5 Word.word)))) + (((op@) ('', '') ((string_of_vec imm)))))))" +|" print_insn (C_SLLI (shamt,rsd)) = ( + (op@) (''c.slli '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((string_of_vec shamt)))))))" +|" print_insn (C_LWSP (uimm,rd)) = ( + (op@) (''c.lwsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_LDSP (uimm,rd)) = ( + (op@) (''c.ldsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_SWSP (uimm,rd)) = ( + (op@) (''c.swsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_SDSP (uimm,rd)) = ( + (op@) (''c.sdsp '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((string_of_vec uimm)))))))" +|" print_insn (C_JR (rs1)) = ( (op@) (''c.jr '') ((reg_name_abi rs1)))" +|" print_insn (C_JALR (rs1)) = ( (op@) (''c.jalr '') ((reg_name_abi rs1)))" +|" print_insn (C_MV (rd,rs2)) = ( + (op@) (''c.mv '') + (((op@) ((reg_name_abi rd)) (((op@) ('', '') ((reg_name_abi rs2)))))))" +|" print_insn (C_ADD (rsd,rs2)) = ( + (op@) (''c.add '') + (((op@) ((reg_name_abi rsd)) (((op@) ('', '') ((reg_name_abi rs2)))))))" + + +(*val isRVC : mword ty16 -> bool*) + +definition isRVC :: "(16)Word.word \<Rightarrow> bool " where + " isRVC h = ( + \<not> (((((subrange_vec_dec h (( 1 :: int)::ii) (( 0 :: int)::ii) :: 2 Word.word)) = (vec_of_bits [B1,B1] :: 2 Word.word)))))" + + +(*val fetch : unit -> M FetchResult*) + +definition fetch :: " unit \<Rightarrow>((register_value),(FetchResult),(exception))monad " where + " fetch _ = ( + or_boolM + ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: xlenbits) . + return (((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))) + (and_boolM + ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: xlenbits) . + return (((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 :: int)::ii))) :: 1 Word.word)) \<noteq> (vec_of_bits [B0] :: 1 Word.word)))))) + (haveRVC () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2))))) \<bind> (\<lambda> (w__4 :: bool) . + if w__4 then + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) . + return (F_Error (E_Fetch_Addr_Align,w__5))) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . + translateAddr w__6 Execute Instruction \<bind> (\<lambda> (w__7 :: TR_Result) . + (case w__7 of + TR_Failure (e) => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) . return (F_Error (e,w__8))) + | TR_Address (ppclo) => + (checked_mem_read Instruction ppclo (( 2 :: int)::ii) :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__9 :: ( 16 Word.word) + MemoryOpResult) . + (case w__9 of + MemException (e) => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) . + return (F_Error (E_Fetch_Access_Fault,w__10))) + | MemValue (ilo) => + if ((isRVC ilo)) then return (F_RVC ilo) + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 Word.word) . + (let (PChi :: xlenbits) = ((add_vec_int w__11 (( 2 :: int)::ii) :: 64 Word.word)) in + translateAddr PChi Execute Instruction \<bind> (\<lambda> (w__12 :: TR_Result) . + (case w__12 of + TR_Failure (e) => return (F_Error (e,PChi)) + | TR_Address (ppchi) => + (checked_mem_read Instruction ppchi (( 2 :: int)::ii) :: ( ( 16 Word.word)MemoryOpResult) M) \<bind> (\<lambda> (w__13 :: ( 16 Word.word) + MemoryOpResult) . + return ((case w__13 of + MemException (e) => F_Error (E_Fetch_Access_Fault,PChi) + | MemValue (ihi) => F_Base ((concat_vec ihi ilo :: 32 Word.word)) + ))) + )))) + )) + )))))" + + +(*val step : unit -> M bool*) + +definition step :: " unit \<Rightarrow>((register_value),(bool),(exception))monad " where + " step _ = ( + read_reg mip_ref \<bind> (\<lambda> (w__0 :: Minterrupts) . + read_reg mie_ref \<bind> (\<lambda> (w__1 :: Minterrupts) . + read_reg mideleg_ref \<bind> (\<lambda> (w__2 :: Minterrupts) . + curInterrupt w__0 w__1 w__2 \<bind> (\<lambda> (w__3 :: ((InterruptType * Privilege))option) . + (case w__3 of + Some (intr,priv) => + (let (_ :: unit) = (print_bits (''Handling interrupt: '') ((interruptType_to_bits intr :: 4 Word.word))) in + handle_interrupt intr priv \<then> return False) + | None => + fetch () \<bind> (\<lambda> (w__4 :: FetchResult) . + (case w__4 of + F_Error (e,addr) => handle_mem_exception addr e \<then> return False + | F_RVC (h) => + (case ((decodeCompressed h)) of + None => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__5)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec h)) ('' : <no-decode>'')))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) h :: 64 Word.word)) \<then> return False)) + | Some (ast) => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__6)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec h)) + (((op@) ('' : '') ((print_insn ast))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__7 (( 2 :: int)::ii) :: 64 Word.word)) \<then> + execute ast) \<then> return True))) + ) + | F_Base (w) => + (case ((decode w)) of + None => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__9)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec w)) ('' : <no-decode>'')))))))))) in + handle_decode_exception ((EXTZ (( 64 :: int)::ii) w :: 64 Word.word)) \<then> return False)) + | Some (ast) => + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: xlenbits) . + (let (_ :: unit) = + (prerr_endline + (((op@) (''PC: '') + (((op@) ((string_of_vec w__10)) + (((op@) ('' instr: '') + (((op@) ((string_of_vec w)) + (((op@) ('' : '') ((print_insn ast))))))))))))) in + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 Word.word) . + (write_reg nextPC_ref ((add_vec_int w__11 (( 4 :: int)::ii) :: 64 Word.word)) \<then> + execute ast) \<then> return True))) + ) + )) + ))))))" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| tlb39 = None, + tselect = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + stval = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + scause = + (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sepc = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sscratch = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + stvec = + (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + satp = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + sideleg = + (Mk_Sinterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + sedeleg = + (Mk_Sedeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + pmpcfg0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + pmpaddr0 = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mhartid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + marchid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mimpid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mvendorid = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + minstret = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtime = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mcycle = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mscratch = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtval = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mepc = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mcause = + (Mk_Mcause (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mtvec = + (Mk_Mtvec (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + medeleg = + (Mk_Medeleg (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + mideleg = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mie = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mip = + (Mk_Minterrupts (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0] + :: 64 Word.word)), + mstatus = + (Mk_Mstatus (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + misa = + (Mk_Misa (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + cur_inst = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + cur_privilege = User, + Xs = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod.thy b/snapshots/isabelle/riscv/Riscv_duopod.thy new file mode 100644 index 00000000..9087ec9c --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod.thy @@ -0,0 +1,461 @@ +chapter \<open>Generated by Lem from riscv_duopod.lem.\<close> + +theory "Riscv_duopod" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + "Riscv_duopod_types" + "Riscv_extras" + +begin + +(*Generated by Sail from riscv_duopod.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +(*open import Riscv_duopod_types*) +(*open import Riscv_extras*) + + + + + + + + + +(*val builtin_and_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val builtin_or_vec : forall 'n. bits 'n -> bits 'n -> bits 'n*) + + + +(*val __raw_SetSlice_int : forall 'w. integer -> ii -> ii -> bits 'w -> ii*) + +(*val __GetSlice_int : forall 'n. Size 'n => integer -> ii -> ii -> mword 'n*) + +definition GetSlice_int :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where + " GetSlice_int n m o1 = ( (get_slice_int0 n m o1 :: ( 'n::len)Word.word))" + + +(*val __raw_SetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w -> bits 'n*) + +(*val __raw_GetSlice_bits : forall 'n 'w. integer -> integer -> bits 'n -> ii -> bits 'w*) + +(*val cast_unit_vec : bitU -> mword ty1*) + +fun cast_unit_vec0 :: " bitU \<Rightarrow>(1)Word.word " where + " cast_unit_vec0 B0 = ( (vec_of_bits [B0] :: 1 Word.word))" +|" cast_unit_vec0 B1 = ( (vec_of_bits [B1] :: 1 Word.word))" + + +(*val DecStr : ii -> string*) + +(*val HexStr : ii -> string*) + +(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> mword 'int8_times_n -> M bool*) + +definition RISCV_write :: "(64)Word.word \<Rightarrow> int \<Rightarrow>('int8_times_n::len)Word.word \<Rightarrow>((register_value),(bool),(unit))monad " where + " RISCV_write addr width data = ( + write_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr data \<then> + return True )" + + +(*val __TraceMemoryWrite : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (maybe (mword 'int8_times_n))*) + +definition RISCV_read :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),((('int8_times_n::len)Word.word)option),(unit))monad " where + " RISCV_read addr width = ( + (read_ram (( 64 :: int)::ii) width + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) addr + :: (( 'int8_times_n::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'int8_times_n::len)Word.word) . + return (Some w__0)))" + + +(*val __TraceMemoryRead : forall 'int8_times_n 'm. integer -> bits 'm -> bits 'int8_times_n -> unit*) + +(*val ex_nat : ii -> integer*) + +definition ex_nat :: " int \<Rightarrow> int " where + " ex_nat n = ( n )" + + +(*val ex_int : ii -> integer*) + +definition ex_int :: " int \<Rightarrow> int " where + " ex_int n = ( n )" + + +(*val coerce_int_nat : ii -> M ii*) + +definition coerce_int_nat :: " int \<Rightarrow>((register_value),(int),(unit))monad " where + " coerce_int_nat x = ( assert_exp True ('''') \<then> return x )" + + +(*val EXTS : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => integer -> mword 'n -> mword 'm*) + +definition EXTS :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " EXTS (m__tv :: int) v = ( (sign_extend v m__tv :: ( 'm::len)Word.word))" + + +definition EXTZ :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len)Word.word " where + " EXTZ (m__tv :: int) v = ( (zero_extend v m__tv :: ( 'm::len)Word.word))" + + +(*val zopz0zI_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_s : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zI_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zKzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +(*val zopz0zIzJ_u : forall 'n. Size 'n => mword 'n -> mword 'n -> bool*) + +definition zopz0zI_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_s x y = ( ((Word.sint x)) < ((Word.sint y)))" + + +definition zopz0zKzJ_s :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_s x y = ( ((Word.sint x)) \<ge> ((Word.sint y)))" + + +definition zopz0zI_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zI_u x y = ( ((Word.uint x)) < ((Word.uint y)))" + + +definition zopz0zKzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zKzJ_u x y = ( ((Word.uint x)) \<ge> ((Word.uint y)))" + + +definition zopz0zIzJ_u :: "('n::len)Word.word \<Rightarrow>('n::len)Word.word \<Rightarrow> bool " where + " zopz0zIzJ_u x y = ( ((Word.uint x)) \<le> ((Word.uint y)))" + + +(*val bool_to_bits : bool -> mword ty1*) + +definition bool_to_bits :: " bool \<Rightarrow>(1)Word.word " where + " bool_to_bits x = ( if x then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word))" + + +(*val bit_to_bool : bitU -> bool*) + +fun bit_to_bool :: " bitU \<Rightarrow> bool " where + " bit_to_bool B1 = ( True )" +|" bit_to_bool B0 = ( False )" + + +(*val vector64 : ii -> mword ty64*) + +definition vector64 :: " int \<Rightarrow>(64)Word.word " where + " vector64 n = ( (get_slice_int0 (( 64 :: int)::ii) n (( 0 :: int)::ii) :: 64 Word.word))" + + +(*val to_bits : forall 'l. Size 'l => integer -> ii -> mword 'l*) + +definition to_bits :: " int \<Rightarrow> int \<Rightarrow>('l::len)Word.word " where + " to_bits l n = ( (get_slice_int0 l n (( 0 :: int)::ii) :: ( 'l::len)Word.word))" + + +(*val shift_right_arith64 : mword ty64 -> mword ty6 -> mword ty64*) + +definition shift_right_arith64 :: "(64)Word.word \<Rightarrow>(6)Word.word \<Rightarrow>(64)Word.word " where + " shift_right_arith64 (v :: 64 bits) (shift :: 6 bits) = ( + (let (v128 :: 128 bits) = ((EXTS (( 128 :: int)::ii) v :: 128 Word.word)) in + (subrange_vec_dec ((shift_bits_right v128 shift :: 128 Word.word)) (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)))" + + +(*val shift_right_arith32 : mword ty32 -> mword ty5 -> mword ty32*) + +definition shift_right_arith32 :: "(32)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word.word " where + " shift_right_arith32 (v :: 32 bits) (shift :: 5 bits) = ( + (let (v64 :: 64 bits) = ((EXTS (( 64 :: int)::ii) v :: 64 Word.word)) in + (subrange_vec_dec ((shift_bits_right v64 shift :: 64 Word.word)) (( 31 :: int)::ii) (( 0 :: int)::ii) :: 32 Word.word)))" + + +(*val zeros : forall 'n. Size 'n => integer -> mword 'n*) + +definition zeros0 :: " int \<Rightarrow>('n::len)Word.word " where + " zeros0 n = ( (replicate_bits (vec_of_bits [B0] :: 1 Word.word) n :: ( 'n::len)Word.word))" + + +(*val regbits_to_regno : mword ty5 -> integer*) + +definition regbits_to_regno :: "(5)Word.word \<Rightarrow> int " where + " regbits_to_regno b = ( + (let r = (Word.uint b) in + r))" + + +(*val rX : integer -> M (mword ty64)*) + +definition rX :: " int \<Rightarrow>((register_value),((64)Word.word),(unit))monad " where + " rX l__5 = ( + if (((l__5 = (( 0 :: int)::ii)))) then + return (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word) + else + read_reg Xs_ref \<bind> (\<lambda> (w__0 :: xlen_t list) . + return ((access_list_dec w__0 l__5 :: 64 Word.word))))" + + +(*val wX : integer -> mword ty64 -> M unit*) + +definition wX :: " int \<Rightarrow>(64)Word.word \<Rightarrow>((register_value),(unit),(unit))monad " where + " wX r v = ( + if (((r \<noteq> (( 0 :: int)::ii)))) then + read_reg Xs_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + write_reg Xs_ref ((update_list_dec w__0 r v :: ( 64 Word.word) list))) + else return () )" + + +(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => mword ty64 -> integer -> M (mword 'int8_times_n)*) + +definition MEMr :: "(64)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('int8_times_n::len)Word.word),(unit))monad " where + " MEMr addr width = ( + (RISCV_read addr width :: ( (( 'int8_times_n::len)Word.word)option) M) \<bind> (\<lambda> (w__0 :: + (( 'int8_times_n::len)Word.word)option) . + return ((case w__0 of + Some (v) => v + | None => (zeros0 (((( 8 :: int)::ii) * width)) :: ( 'int8_times_n::len)Word.word) + ))))" + + +(*val iop_of_num : integer -> iop*) + +definition iop_of_num :: " int \<Rightarrow> iop " where + " iop_of_num arg0 = ( + (let l__0 = arg0 in + if (((l__0 = (( 0 :: int)::ii)))) then RISCV_ADDI + else if (((l__0 = (( 1 :: int)::ii)))) then RISCV_SLTI + else if (((l__0 = (( 2 :: int)::ii)))) then RISCV_SLTIU + else if (((l__0 = (( 3 :: int)::ii)))) then RISCV_XORI + else if (((l__0 = (( 4 :: int)::ii)))) then RISCV_ORI + else RISCV_ANDI))" + + +(*val num_of_iop : iop -> integer*) + +fun num_of_iop :: " iop \<Rightarrow> int " where + " num_of_iop RISCV_ADDI = ( (( 0 :: int)::ii))" +|" num_of_iop RISCV_SLTI = ( (( 1 :: int)::ii))" +|" num_of_iop RISCV_SLTIU = ( (( 2 :: int)::ii))" +|" num_of_iop RISCV_XORI = ( (( 3 :: int)::ii))" +|" num_of_iop RISCV_ORI = ( (( 4 :: int)::ii))" +|" num_of_iop RISCV_ANDI = ( (( 5 :: int)::ii))" + + +(*val decode : mword ty32 -> maybe ast*) + +(*val execute : ast -> M unit*) + +definition decode :: "(32)Word.word \<Rightarrow>(ast)option " where + " decode v__0 = ( + if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B1,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (ITYPE (imm,rs1,rd,RISCV_ADDI))))) + else if ((((((((subrange_vec_dec v__0 (( 14 :: int)::ii) (( 12 :: int)::ii) :: 3 Word.word)) = (vec_of_bits [B0,B1,B1] :: 3 Word.word)))) \<and> (((((subrange_vec_dec v__0 (( 6 :: int)::ii) (( 0 :: int)::ii) :: 7 Word.word)) = (vec_of_bits [B0,B0,B0,B0,B0,B1,B1] :: 7 Word.word))))))) then + (let (imm :: 12 bits) = ((subrange_vec_dec v__0 (( 31 :: int)::ii) (( 20 :: int)::ii) :: 12 Word.word)) in + (let (rs1 :: regbits) = ((subrange_vec_dec v__0 (( 19 :: int)::ii) (( 15 :: int)::ii) :: 5 Word.word)) in + (let (rd :: regbits) = ((subrange_vec_dec v__0 (( 11 :: int)::ii) (( 7 :: int)::ii) :: 5 Word.word)) in + Some (LOAD (imm,rs1,rd))))) + else None )" + + +(*val execute_LOAD : mword ty12 -> mword ty5 -> mword ty5 -> M unit*) + +definition execute_LOAD :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>((register_value),(unit),(unit))monad " where + " execute_LOAD imm rs1 rd = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (let (addr :: xlen_t) = ((add_vec w__0 ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) :: 64 Word.word)) in + (MEMr addr (( 8 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (result :: xlen_t) . + wX ((regbits_to_regno rd)) result))))" + + +(*val execute_ITYPE : mword ty12 -> mword ty5 -> mword ty5 -> iop -> M unit*) + +fun execute_ITYPE :: "(12)Word.word \<Rightarrow>(5)Word.word \<Rightarrow>(5)Word.word \<Rightarrow> iop \<Rightarrow>((register_value),(unit),(unit))monad " where + " execute_ITYPE imm rs1 rd RISCV_ADDI = ( + (rX ((regbits_to_regno rs1)) :: ( 64 Word.word) M) \<bind> (\<lambda> rs1_val . + (let (imm_ext :: xlen_t) = ((EXTS (( 64 :: int)::ii) imm :: 64 Word.word)) in + (let result = ((add_vec rs1_val imm_ext :: 64 Word.word)) in + wX ((regbits_to_regno rd)) result))))" + + +fun execute :: " ast \<Rightarrow>((register_value),(unit),(unit))monad " where + " execute (ITYPE (imm,rs1,rd,arg3)) = ( execute_ITYPE imm rs1 rd arg3 )" +|" execute (LOAD (imm,rs1,rd)) = ( execute_LOAD imm rs1 rd )" + + +definition initial_regstate :: " regstate " where + " initial_regstate = ( + (| Xs = + ([(vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word), + (vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)]), + nextPC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)), + PC = + ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0, + B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] + :: 64 Word.word)) |) )" + + + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy new file mode 100644 index 00000000..d6ca4d7d --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod_lemmas.thy @@ -0,0 +1,48 @@ +theory Riscv_duopod_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Riscv_duopod +begin + +abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def Xs_ref_def nextPC_ref_def PC_ref_def + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_Xs[simp]: + "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Xs[simp]: + "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/riscv/Riscv_duopod_types.thy b/snapshots/isabelle/riscv/Riscv_duopod_types.thy new file mode 100644 index 00000000..8e92ede0 --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_duopod_types.thy @@ -0,0 +1,170 @@ +chapter \<open>Generated by Lem from riscv_duopod_types.lem.\<close> + +theory "Riscv_duopod_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from riscv_duopod.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +type_synonym xlen =" int " + +type_synonym xlen_t =" 64 bits " + +type_synonym 'n regno =" int " + +type_synonym regbits =" 5 bits " + +datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI + + + +datatype ast = + ITYPE " (( 12 bits * regbits * regbits * iop))" | LOAD " (( 12 bits * regbits * regbits))" + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + + + +record regstate = + Xs ::" ( 64 Word.word) list " + nextPC ::" 64 Word.word " + PC ::" 64 Word.word " + + + + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__6 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " vector_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " list_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where + " option_of_regval of_regval1 = ( \<lambda>x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " Xs_ref = ( (| + name = (''Xs''), + read_from = (\<lambda> s . (Xs s)), + write_to = (\<lambda> v s . (( s (| Xs := v |)))), + of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v), + regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\<lambda> s . (nextPC s)), + write_to = (\<lambda> v s . (( s (| nextPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\<lambda> s . (PC s)), + write_to = (\<lambda> v s . (( s (| PC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else + if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, unit) monadR " +type_synonym 'a M =" (register_value, 'a, unit) monad " +end diff --git a/snapshots/isabelle/riscv/Riscv_extras.thy b/snapshots/isabelle/riscv/Riscv_extras.thy new file mode 100644 index 00000000..fc83385b --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_extras.thy @@ -0,0 +1,126 @@ +chapter \<open>Generated by Lem from riscv_extras.lem.\<close> + +theory "Riscv_extras" + +imports + Main + "Lem_pervasives" + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + +begin + +(*open import Pervasives*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) + +type_synonym 'a bitvector =" ( 'a::len)Word.word " + +definition MEM_fence_rw_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_rw_rw _ = ( barrier Barrier_RISCV_rw_rw )" + +definition MEM_fence_r_rw :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_r_rw _ = ( barrier Barrier_RISCV_r_rw )" + +definition MEM_fence_r_r :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_r_r _ = ( barrier Barrier_RISCV_r_r )" + +definition MEM_fence_rw_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_rw_w _ = ( barrier Barrier_RISCV_rw_w )" + +definition MEM_fence_w_w :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_w_w _ = ( barrier Barrier_RISCV_w_w )" + +definition MEM_fence_i :: " unit \<Rightarrow>('b,(unit),'a)monad " where + " MEM_fence_i _ = ( barrier Barrier_RISCV_i )" + + +(*val MEMea : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) +(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> integer -> monad 'rv unit 'e*) + +definition MEMea :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " MEMea addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr size1 )" + +definition MEMea_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " MEMea_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr size1 )" + +definition MEMea_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " MEMea_strong_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr size1 )" + +definition MEMea_conditional :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " MEMea_conditional addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr size1 )" + +definition MEMea_conditional_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " where + " MEMea_conditional_release addr size1 = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr size1 )" + +definition MEMea_conditional_strong_release :: "('a::len)Word.word \<Rightarrow> int \<Rightarrow>('rv,(unit),'e)monad " + where + " MEMea_conditional_strong_release addr size1 + = ( write_mem_ea + instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr size1 )" + + +(*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> monad 'rv unit 'e*) +definition write_ram :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('rv,(unit),'e)monad " where + " write_ram addrsize size1 hexRAM address value1 = ( + (write_mem_ea instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address size1 \<then> + write_mem_val instance_Sail_values_Bitvector_Machine_word_mword_dict value1) \<bind> (\<lambda>x . (case x of _ => return () )) )" + + +(*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b => + integer -> integer -> bitvector 'a -> bitvector 'a -> monad 'rv (bitvector 'b) 'e*) +definition read_ram :: " int \<Rightarrow> int \<Rightarrow>('a::len)Word.word \<Rightarrow>('a::len)Word.word \<Rightarrow>('rv,(('b::len)Word.word),'e)monad " where + " read_ram addrsize size1 hexRAM address = ( + read_mem instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1 )" + + +definition speculate_conditional_success :: " unit \<Rightarrow>('b,(bool),'a)monad " where + " speculate_conditional_success _ = ( excl_result () )" + + +(*val get_slice_int : forall 'a. Size 'a => integer -> integer -> integer -> bitvector 'a*) +definition get_slice_int0 :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('a::len)Word.word " where + " get_slice_int0 len n lo = ( + (* TODO: Is this the intended behaviour? *) + (let hi = ((lo + len) -( 1 :: int)) in + (let bits = (bits_of_int (hi +( 1 :: int)) n) in + of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list False bits hi lo))))" + + +(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +definition shift_bits_right :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " shift_bits_right v m = ( shiftr v (Word.uint m))" + +(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*) +definition shift_bits_left :: "('a::len)Word.word \<Rightarrow>('b::len)Word.word \<Rightarrow>('a::len)Word.word " where + " shift_bits_left v m = ( shiftl v (Word.uint m))" + + +(*val print_string : string -> string -> unit*) +definition print_string :: " string \<Rightarrow> string \<Rightarrow> unit " where + " print_string msg s = ( prerr_endline (msg @ s))" + + +(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*) +definition print_bits :: " string \<Rightarrow>('a::len)Word.word \<Rightarrow> unit " where + " print_bits msg bs = ( prerr_endline (msg @ (show_bitlist (List.map bitU_of_bool (Word.to_bl bs)))))" + +end diff --git a/snapshots/isabelle/riscv/Riscv_lemmas.thy b/snapshots/isabelle/riscv/Riscv_lemmas.thy new file mode 100644 index 00000000..b2f4e80d --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_lemmas.thy @@ -0,0 +1,350 @@ +theory Riscv_lemmas + imports + Sail.Sail_values_lemmas + Sail.State_lemmas + Riscv +begin + +abbreviation "liftS \<equiv> liftState (get_regval, set_regval)" + +lemmas register_defs = get_regval_def set_regval_def tlb39_ref_def tselect_ref_def stval_ref_def + scause_ref_def sepc_ref_def sscratch_ref_def stvec_ref_def satp_ref_def sideleg_ref_def + sedeleg_ref_def pmpcfg0_ref_def pmpaddr0_ref_def mhartid_ref_def marchid_ref_def mimpid_ref_def + mvendorid_ref_def minstret_ref_def mtime_ref_def mcycle_ref_def mscratch_ref_def mtval_ref_def + mepc_ref_def mcause_ref_def mtvec_ref_def medeleg_ref_def mideleg_ref_def mie_ref_def mip_ref_def + mstatus_ref_def misa_ref_def cur_inst_ref_def cur_privilege_ref_def Xs_ref_def nextPC_ref_def + PC_ref_def + +lemma regval_Mcause[simp]: + "Mcause_of_regval (regval_of_Mcause v) = Some v" + by (auto simp: regval_of_Mcause_def) + +lemma regval_Medeleg[simp]: + "Medeleg_of_regval (regval_of_Medeleg v) = Some v" + by (auto simp: regval_of_Medeleg_def) + +lemma regval_Minterrupts[simp]: + "Minterrupts_of_regval (regval_of_Minterrupts v) = Some v" + by (auto simp: regval_of_Minterrupts_def) + +lemma regval_Misa[simp]: + "Misa_of_regval (regval_of_Misa v) = Some v" + by (auto simp: regval_of_Misa_def) + +lemma regval_Mstatus[simp]: + "Mstatus_of_regval (regval_of_Mstatus v) = Some v" + by (auto simp: regval_of_Mstatus_def) + +lemma regval_Mtvec[simp]: + "Mtvec_of_regval (regval_of_Mtvec v) = Some v" + by (auto simp: regval_of_Mtvec_def) + +lemma regval_Privilege[simp]: + "Privilege_of_regval (regval_of_Privilege v) = Some v" + by (auto simp: regval_of_Privilege_def) + +lemma regval_Sedeleg[simp]: + "Sedeleg_of_regval (regval_of_Sedeleg v) = Some v" + by (auto simp: regval_of_Sedeleg_def) + +lemma regval_Sinterrupts[simp]: + "Sinterrupts_of_regval (regval_of_Sinterrupts v) = Some v" + by (auto simp: regval_of_Sinterrupts_def) + +lemma regval_TLB39_Entry[simp]: + "TLB39_Entry_of_regval (regval_of_TLB39_Entry v) = Some v" + by (auto simp: regval_of_TLB39_Entry_def) + +lemma regval_vector_64_dec_bit[simp]: + "vector_64_dec_bit_of_regval (regval_of_vector_64_dec_bit v) = Some v" + by (auto simp: regval_of_vector_64_dec_bit_def) + +lemma vector_of_rv_rv_of_vector[simp]: + assumes "\<And>v. of_rv (rv_of v) = Some v" + shows "vector_of_regval of_rv (regval_of_vector rv_of len is_inc v) = Some v" +proof - + from assms have "of_rv \<circ> rv_of = Some" by auto + then show ?thesis by (auto simp: vector_of_regval_def regval_of_vector_def) +qed + +lemma liftS_read_reg_tlb39[simp]: + "liftS (read_reg tlb39_ref) = readS (tlb39 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tlb39[simp]: + "liftS (write_reg tlb39_ref v) = updateS (regstate_update (tlb39_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_tselect[simp]: + "liftS (read_reg tselect_ref) = readS (tselect \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_tselect[simp]: + "liftS (write_reg tselect_ref v) = updateS (regstate_update (tselect_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stval[simp]: + "liftS (read_reg stval_ref) = readS (stval \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stval[simp]: + "liftS (write_reg stval_ref v) = updateS (regstate_update (stval_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_scause[simp]: + "liftS (read_reg scause_ref) = readS (scause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_scause[simp]: + "liftS (write_reg scause_ref v) = updateS (regstate_update (scause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sepc[simp]: + "liftS (read_reg sepc_ref) = readS (sepc \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sepc[simp]: + "liftS (write_reg sepc_ref v) = updateS (regstate_update (sepc_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sscratch[simp]: + "liftS (read_reg sscratch_ref) = readS (sscratch \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sscratch[simp]: + "liftS (write_reg sscratch_ref v) = updateS (regstate_update (sscratch_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_stvec[simp]: + "liftS (read_reg stvec_ref) = readS (stvec \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_stvec[simp]: + "liftS (write_reg stvec_ref v) = updateS (regstate_update (stvec_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_satp[simp]: + "liftS (read_reg satp_ref) = readS (satp \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_satp[simp]: + "liftS (write_reg satp_ref v) = updateS (regstate_update (satp_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sideleg[simp]: + "liftS (read_reg sideleg_ref) = readS (sideleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sideleg[simp]: + "liftS (write_reg sideleg_ref v) = updateS (regstate_update (sideleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_sedeleg[simp]: + "liftS (read_reg sedeleg_ref) = readS (sedeleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_sedeleg[simp]: + "liftS (write_reg sedeleg_ref v) = updateS (regstate_update (sedeleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpcfg0[simp]: + "liftS (read_reg pmpcfg0_ref) = readS (pmpcfg0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpcfg0[simp]: + "liftS (write_reg pmpcfg0_ref v) = updateS (regstate_update (pmpcfg0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_pmpaddr0[simp]: + "liftS (read_reg pmpaddr0_ref) = readS (pmpaddr0 \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_pmpaddr0[simp]: + "liftS (write_reg pmpaddr0_ref v) = updateS (regstate_update (pmpaddr0_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mhartid[simp]: + "liftS (read_reg mhartid_ref) = readS (mhartid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mhartid[simp]: + "liftS (write_reg mhartid_ref v) = updateS (regstate_update (mhartid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_marchid[simp]: + "liftS (read_reg marchid_ref) = readS (marchid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_marchid[simp]: + "liftS (write_reg marchid_ref v) = updateS (regstate_update (marchid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mimpid[simp]: + "liftS (read_reg mimpid_ref) = readS (mimpid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mimpid[simp]: + "liftS (write_reg mimpid_ref v) = updateS (regstate_update (mimpid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mvendorid[simp]: + "liftS (read_reg mvendorid_ref) = readS (mvendorid \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mvendorid[simp]: + "liftS (write_reg mvendorid_ref v) = updateS (regstate_update (mvendorid_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_minstret[simp]: + "liftS (read_reg minstret_ref) = readS (minstret \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_minstret[simp]: + "liftS (write_reg minstret_ref v) = updateS (regstate_update (minstret_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtime[simp]: + "liftS (read_reg mtime_ref) = readS (mtime \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtime[simp]: + "liftS (write_reg mtime_ref v) = updateS (regstate_update (mtime_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcycle[simp]: + "liftS (read_reg mcycle_ref) = readS (mcycle \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcycle[simp]: + "liftS (write_reg mcycle_ref v) = updateS (regstate_update (mcycle_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mscratch[simp]: + "liftS (read_reg mscratch_ref) = readS (mscratch \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mscratch[simp]: + "liftS (write_reg mscratch_ref v) = updateS (regstate_update (mscratch_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtval[simp]: + "liftS (read_reg mtval_ref) = readS (mtval \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtval[simp]: + "liftS (write_reg mtval_ref v) = updateS (regstate_update (mtval_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mepc[simp]: + "liftS (read_reg mepc_ref) = readS (mepc \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mepc[simp]: + "liftS (write_reg mepc_ref v) = updateS (regstate_update (mepc_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mcause[simp]: + "liftS (read_reg mcause_ref) = readS (mcause \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mcause[simp]: + "liftS (write_reg mcause_ref v) = updateS (regstate_update (mcause_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mtvec[simp]: + "liftS (read_reg mtvec_ref) = readS (mtvec \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mtvec[simp]: + "liftS (write_reg mtvec_ref v) = updateS (regstate_update (mtvec_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_medeleg[simp]: + "liftS (read_reg medeleg_ref) = readS (medeleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_medeleg[simp]: + "liftS (write_reg medeleg_ref v) = updateS (regstate_update (medeleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mideleg[simp]: + "liftS (read_reg mideleg_ref) = readS (mideleg \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mideleg[simp]: + "liftS (write_reg mideleg_ref v) = updateS (regstate_update (mideleg_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mie[simp]: + "liftS (read_reg mie_ref) = readS (mie \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mie[simp]: + "liftS (write_reg mie_ref v) = updateS (regstate_update (mie_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mip[simp]: + "liftS (read_reg mip_ref) = readS (mip \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mip[simp]: + "liftS (write_reg mip_ref v) = updateS (regstate_update (mip_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_mstatus[simp]: + "liftS (read_reg mstatus_ref) = readS (mstatus \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_mstatus[simp]: + "liftS (write_reg mstatus_ref v) = updateS (regstate_update (mstatus_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_misa[simp]: + "liftS (read_reg misa_ref) = readS (misa \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_misa[simp]: + "liftS (write_reg misa_ref v) = updateS (regstate_update (misa_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_inst[simp]: + "liftS (read_reg cur_inst_ref) = readS (cur_inst \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_cur_inst[simp]: + "liftS (write_reg cur_inst_ref v) = updateS (regstate_update (cur_inst_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_cur_privilege[simp]: + "liftS (read_reg cur_privilege_ref) = readS (cur_privilege \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_cur_privilege[simp]: + "liftS (write_reg cur_privilege_ref v) = updateS (regstate_update (cur_privilege_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_Xs[simp]: + "liftS (read_reg Xs_ref) = readS (Xs \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_Xs[simp]: + "liftS (write_reg Xs_ref v) = updateS (regstate_update (Xs_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_nextPC[simp]: + "liftS (read_reg nextPC_ref) = readS (nextPC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_nextPC[simp]: + "liftS (write_reg nextPC_ref v) = updateS (regstate_update (nextPC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +lemma liftS_read_reg_PC[simp]: + "liftS (read_reg PC_ref) = readS (PC \<circ> regstate)" + by (auto simp: liftState_read_reg_readS register_defs) + +lemma liftS_write_reg_PC[simp]: + "liftS (write_reg PC_ref v) = updateS (regstate_update (PC_update (\<lambda>_. v)))" + by (auto simp: liftState_write_reg_updateS register_defs) + +end diff --git a/snapshots/isabelle/riscv/Riscv_types.thy b/snapshots/isabelle/riscv/Riscv_types.thy new file mode 100644 index 00000000..b4fc7f6c --- /dev/null +++ b/snapshots/isabelle/riscv/Riscv_types.thy @@ -0,0 +1,1052 @@ +chapter \<open>Generated by Lem from riscv_types.lem.\<close> + +theory "Riscv_types" + +imports + Main + "Lem_pervasives_extra" + "Sail_instr_kinds" + "Sail_values" + "Sail_operators_mwords" + "Prompt_monad" + "Prompt" + "State" + +begin + +(*Generated by Sail from riscv.*) +(*open import Pervasives_extra*) +(*open import Sail_instr_kinds*) +(*open import Sail_values*) +(*open import Sail_operators_mwords*) +(*open import Prompt_monad*) +(*open import Prompt*) +(*open import State*) +type_synonym 'n bits =" ( 'n::len)Word.word " + + + +type_synonym xlenbits =" 64 bits " + +type_synonym half =" 16 bits " + +type_synonym word0 =" 32 bits " + +type_synonym 'n regno =" int " + +type_synonym regbits =" 5 bits " + +type_synonym cregbits =" 3 bits " + +type_synonym csreg =" 12 bits " + +type_synonym opcode =" 7 bits " + +type_synonym imm12 =" 12 bits " + +type_synonym imm20 =" 20 bits " + +type_synonym amo =" 1 bits " + +datatype Architecture = RV32 | RV64 | RV128 + + + +type_synonym arch_xlen =" 2 bits " + +type_synonym priv_level =" 2 bits " + +datatype Privilege = User | Supervisor | Machine + + + +datatype AccessType = Read | Write | ReadWrite | Execute + + + +datatype ReadType = Instruction | Data + + + +type_synonym exc_code =" 4 bits " + +datatype ExceptionType = + E_Fetch_Addr_Align + | E_Fetch_Access_Fault + | E_Illegal_Instr + | E_Breakpoint + | E_Load_Addr_Align + | E_Load_Access_Fault + | E_SAMO_Addr_Align + | E_SAMO_Access_Fault + | E_U_EnvCall + | E_S_EnvCall + | E_Reserved_10 + | E_M_EnvCall + | E_Fetch_Page_Fault + | E_Load_Page_Fault + | E_Reserved_14 + | E_SAMO_Page_Fault + + + +datatype InterruptType = + I_U_Software + | I_S_Software + | I_M_Software + | I_U_Timer + | I_S_Timer + | I_M_Timer + | I_U_External + | I_S_External + | I_M_External + + + +type_synonym tv_mode =" 2 bits " + +datatype TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved + + + +datatype exception = + Error_not_implemented " (string)" | Error_EBREAK " (unit)" | Error_internal_error " (unit)" + + + +type_synonym ext_status =" 2 bits " + +datatype ExtStatus = Off | Initial | Clean | Dirty + + + +type_synonym satp_mode =" 4 bits " + +datatype SATPMode = Sbare | Sv32 | Sv39 + + + +type_synonym csrRW =" 2 bits " + +datatype uop = RISCV_LUI | RISCV_AUIPC + + + +datatype bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU + + + +datatype iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI + + + +datatype sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI + + + +datatype rop = + RISCV_ADD + | RISCV_SUB + | RISCV_SLL + | RISCV_SLT + | RISCV_SLTU + | RISCV_XOR + | RISCV_SRL + | RISCV_SRA + | RISCV_OR + | RISCV_AND + + + +datatype ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW + + + +datatype amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU + + + +datatype csrop = CSRRW | CSRRS | CSRRC + + + +datatype word_width = BYTE | HALF | WORD | DOUBLE + + + +datatype 'a MemoryOpResult = MemValue " ('a)" | MemException " (ExceptionType)" + + + +datatype Misa = Mk_Misa " ( 64 Word.word)" + + + +datatype SV39_PTE = Mk_SV39_PTE " ( 64 Word.word)" + + + +datatype PTE_Bits = Mk_PTE_Bits " ( 8 Word.word)" + + + +datatype Mstatus = Mk_Mstatus " ( 64 Word.word)" + + + +datatype Sstatus = Mk_Sstatus " ( 64 Word.word)" + + + +datatype Minterrupts = Mk_Minterrupts " ( 64 Word.word)" + + + +datatype Sinterrupts = Mk_Sinterrupts " ( 64 Word.word)" + + + +datatype Medeleg = Mk_Medeleg " ( 64 Word.word)" + + + +datatype Sedeleg = Mk_Sedeleg " ( 64 Word.word)" + + + +datatype Mtvec = Mk_Mtvec " ( 64 Word.word)" + + + +datatype Satp64 = Mk_Satp64 " ( 64 Word.word)" + + + +datatype Mcause = Mk_Mcause " ( 64 Word.word)" + + + +record sync_exception = + + sync_exception_trap ::" ExceptionType " + sync_exception_excinfo ::" xlenbits option " + + + +datatype ctl_result = CTL_TRAP " (sync_exception)" | CTL_SRET " (unit)" | CTL_MRET " (unit)" + + + +type_synonym pteAttribs =" 8 bits " + +datatype PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update + + + +type_synonym vaddr39 =" 39 bits " + +type_synonym paddr39 =" 56 bits " + +type_synonym pte39 =" xlenbits " + +datatype SV39_Vaddr = Mk_SV39_Vaddr " ( 39 Word.word)" + + + +datatype SV39_Paddr = Mk_SV39_Paddr " ( 56 Word.word)" + + + +type_synonym asid64 =" 16 bits " + +datatype PTW_Result = + PTW_Success " ((paddr39 * SV39_PTE * paddr39 * ii * bool))" | PTW_Failure " (PTW_Error)" + + + +record TLB39_Entry = + + TLB39_Entry_asid ::" asid64 " + + TLB39_Entry_global ::" bool " + + TLB39_Entry_vAddr ::" vaddr39 " + + TLB39_Entry_pAddr ::" paddr39 " + + TLB39_Entry_vMatchMask ::" vaddr39 " + + TLB39_Entry_vAddrMask ::" vaddr39 " + + TLB39_Entry_pte ::" SV39_PTE " + + TLB39_Entry_pteAddr ::" paddr39 " + + TLB39_Entry_age ::" xlenbits " + + + +datatype TR39_Result = TR39_Address " (paddr39)" | TR39_Failure " (PTW_Error)" + + + +datatype TR_Result = TR_Address " (xlenbits)" | TR_Failure " (ExceptionType)" + + + +datatype (plugins only: size) ast = + UTYPE " (( 20 bits * regbits * uop))" + | RISCV_JAL " (( 21 bits * regbits))" + | RISCV_JALR " (( 12 bits * regbits * regbits))" + | BTYPE " (( 13 bits * regbits * regbits * bop))" + | ITYPE " (( 12 bits * regbits * regbits * iop))" + | SHIFTIOP " (( 6 bits * regbits * regbits * sop))" + | RTYPE " ((regbits * regbits * regbits * rop))" + | LOAD " (( 12 bits * regbits * regbits * bool * word_width * bool * bool))" + | STORE " (( 12 bits * regbits * regbits * word_width * bool * bool))" + | ADDIW " (( 12 bits * regbits * regbits))" + | SHIFTW " (( 5 bits * regbits * regbits * sop))" + | RTYPEW " ((regbits * regbits * regbits * ropw))" + | MUL " ((regbits * regbits * regbits * bool * bool * bool))" + | DIV " ((regbits * regbits * regbits * bool))" + | REM " ((regbits * regbits * regbits * bool))" + | MULW " ((regbits * regbits * regbits))" + | DIVW " ((regbits * regbits * regbits * bool))" + | REMW " ((regbits * regbits * regbits * bool))" + | FENCE " (( 4 bits * 4 bits))" + | FENCEI " (unit)" + | ECALL " (unit)" + | MRET " (unit)" + | SRET " (unit)" + | EBREAK " (unit)" + | WFI " (unit)" + | SFENCE_VMA " ((regbits * regbits))" + | LOADRES " ((bool * bool * regbits * word_width * regbits))" + | STORECON " ((bool * bool * regbits * regbits * word_width * regbits))" + | AMO " ((amoop * bool * bool * regbits * regbits * word_width * regbits))" + | CSR " (( 12 bits * regbits * regbits * bool * csrop))" + | NOP " (unit)" + | ILLEGAL " (unit)" + | C_ADDI4SPN " ((cregbits * 8 bits))" + | C_LW " (( 5 bits * cregbits * cregbits))" + | C_LD " (( 5 bits * cregbits * cregbits))" + | C_SW " (( 5 bits * cregbits * cregbits))" + | C_SD " (( 5 bits * cregbits * cregbits))" + | C_ADDI " (( 6 bits * regbits))" + | C_JAL " ( 11 bits)" + | C_ADDIW " (( 6 bits * regbits))" + | C_LI " (( 6 bits * regbits))" + | C_ADDI16SP " ( 6 bits)" + | C_LUI " (( 6 bits * regbits))" + | C_SRLI " (( 6 bits * cregbits))" + | C_SRAI " (( 6 bits * cregbits))" + | C_ANDI " (( 6 bits * cregbits))" + | C_SUB " ((cregbits * cregbits))" + | C_XOR " ((cregbits * cregbits))" + | C_OR " ((cregbits * cregbits))" + | C_AND " ((cregbits * cregbits))" + | C_SUBW " ((cregbits * cregbits))" + | C_ADDW " ((cregbits * cregbits))" + | C_J " ( 11 bits)" + | C_BEQZ " (( 8 bits * cregbits))" + | C_BNEZ " (( 8 bits * cregbits))" + | C_SLLI " (( 6 bits * regbits))" + | C_LWSP " (( 6 bits * regbits))" + | C_LDSP " (( 6 bits * regbits))" + | C_SWSP " (( 6 bits * regbits))" + | C_SDSP " (( 6 bits * regbits))" + | C_JR " (regbits)" + | C_JALR " (regbits)" + | C_MV " ((regbits * regbits))" + | C_ADD " ((regbits * regbits))" + + + +datatype FetchResult = F_Base " (word0)" | F_RVC " (half)" | F_Error " ((ExceptionType * xlenbits))" + + + +datatype register_value = + Regval_vector " ((ii * bool * register_value list))" + | Regval_list " ( register_value list)" + | Regval_option " ( register_value option)" + | Regval_Mcause " (Mcause)" + | Regval_Medeleg " (Medeleg)" + | Regval_Minterrupts " (Minterrupts)" + | Regval_Misa " (Misa)" + | Regval_Mstatus " (Mstatus)" + | Regval_Mtvec " (Mtvec)" + | Regval_Privilege " (Privilege)" + | Regval_Sedeleg " (Sedeleg)" + | Regval_Sinterrupts " (Sinterrupts)" + | Regval_TLB39_Entry " (TLB39_Entry)" + | Regval_vector_64_dec_bit " ( 64 Word.word)" + + + +record regstate = + + tlb39 ::" TLB39_Entry option " + + tselect ::" 64 Word.word " + + stval ::" 64 Word.word " + + scause ::" Mcause " + + sepc ::" 64 Word.word " + + sscratch ::" 64 Word.word " + + stvec ::" Mtvec " + + satp ::" 64 Word.word " + + sideleg ::" Sinterrupts " + + sedeleg ::" Sedeleg " + + pmpcfg0 ::" 64 Word.word " + + pmpaddr0 ::" 64 Word.word " + + mhartid ::" 64 Word.word " + + marchid ::" 64 Word.word " + + mimpid ::" 64 Word.word " + + mvendorid ::" 64 Word.word " + + minstret ::" 64 Word.word " + + mtime ::" 64 Word.word " + + mcycle ::" 64 Word.word " + + mscratch ::" 64 Word.word " + + mtval ::" 64 Word.word " + + mepc ::" 64 Word.word " + + mcause ::" Mcause " + + mtvec ::" Mtvec " + + medeleg ::" Medeleg " + + mideleg ::" Minterrupts " + + mie ::" Minterrupts " + + mip ::" Minterrupts " + + mstatus ::" Mstatus " + + misa ::" Misa " + + cur_inst ::" 64 Word.word " + + cur_privilege ::" Privilege " + + Xs ::" ( 64 Word.word) list " + + nextPC ::" 64 Word.word " + + PC ::" 64 Word.word " + + + + + +(*val Mcause_of_regval : register_value -> maybe Mcause*) + +fun Mcause_of_regval :: " register_value \<Rightarrow>(Mcause)option " where + " Mcause_of_regval (Regval_Mcause (v)) = ( Some v )" +|" Mcause_of_regval g__92 = ( None )" + + +(*val regval_of_Mcause : Mcause -> register_value*) + +definition regval_of_Mcause :: " Mcause \<Rightarrow> register_value " where + " regval_of_Mcause v = ( Regval_Mcause v )" + + +(*val Medeleg_of_regval : register_value -> maybe Medeleg*) + +fun Medeleg_of_regval :: " register_value \<Rightarrow>(Medeleg)option " where + " Medeleg_of_regval (Regval_Medeleg (v)) = ( Some v )" +|" Medeleg_of_regval g__91 = ( None )" + + +(*val regval_of_Medeleg : Medeleg -> register_value*) + +definition regval_of_Medeleg :: " Medeleg \<Rightarrow> register_value " where + " regval_of_Medeleg v = ( Regval_Medeleg v )" + + +(*val Minterrupts_of_regval : register_value -> maybe Minterrupts*) + +fun Minterrupts_of_regval :: " register_value \<Rightarrow>(Minterrupts)option " where + " Minterrupts_of_regval (Regval_Minterrupts (v)) = ( Some v )" +|" Minterrupts_of_regval g__90 = ( None )" + + +(*val regval_of_Minterrupts : Minterrupts -> register_value*) + +definition regval_of_Minterrupts :: " Minterrupts \<Rightarrow> register_value " where + " regval_of_Minterrupts v = ( Regval_Minterrupts v )" + + +(*val Misa_of_regval : register_value -> maybe Misa*) + +fun Misa_of_regval :: " register_value \<Rightarrow>(Misa)option " where + " Misa_of_regval (Regval_Misa (v)) = ( Some v )" +|" Misa_of_regval g__89 = ( None )" + + +(*val regval_of_Misa : Misa -> register_value*) + +definition regval_of_Misa :: " Misa \<Rightarrow> register_value " where + " regval_of_Misa v = ( Regval_Misa v )" + + +(*val Mstatus_of_regval : register_value -> maybe Mstatus*) + +fun Mstatus_of_regval :: " register_value \<Rightarrow>(Mstatus)option " where + " Mstatus_of_regval (Regval_Mstatus (v)) = ( Some v )" +|" Mstatus_of_regval g__88 = ( None )" + + +(*val regval_of_Mstatus : Mstatus -> register_value*) + +definition regval_of_Mstatus :: " Mstatus \<Rightarrow> register_value " where + " regval_of_Mstatus v = ( Regval_Mstatus v )" + + +(*val Mtvec_of_regval : register_value -> maybe Mtvec*) + +fun Mtvec_of_regval :: " register_value \<Rightarrow>(Mtvec)option " where + " Mtvec_of_regval (Regval_Mtvec (v)) = ( Some v )" +|" Mtvec_of_regval g__87 = ( None )" + + +(*val regval_of_Mtvec : Mtvec -> register_value*) + +definition regval_of_Mtvec :: " Mtvec \<Rightarrow> register_value " where + " regval_of_Mtvec v = ( Regval_Mtvec v )" + + +(*val Privilege_of_regval : register_value -> maybe Privilege*) + +fun Privilege_of_regval :: " register_value \<Rightarrow>(Privilege)option " where + " Privilege_of_regval (Regval_Privilege (v)) = ( Some v )" +|" Privilege_of_regval g__86 = ( None )" + + +(*val regval_of_Privilege : Privilege -> register_value*) + +definition regval_of_Privilege :: " Privilege \<Rightarrow> register_value " where + " regval_of_Privilege v = ( Regval_Privilege v )" + + +(*val Sedeleg_of_regval : register_value -> maybe Sedeleg*) + +fun Sedeleg_of_regval :: " register_value \<Rightarrow>(Sedeleg)option " where + " Sedeleg_of_regval (Regval_Sedeleg (v)) = ( Some v )" +|" Sedeleg_of_regval g__85 = ( None )" + + +(*val regval_of_Sedeleg : Sedeleg -> register_value*) + +definition regval_of_Sedeleg :: " Sedeleg \<Rightarrow> register_value " where + " regval_of_Sedeleg v = ( Regval_Sedeleg v )" + + +(*val Sinterrupts_of_regval : register_value -> maybe Sinterrupts*) + +fun Sinterrupts_of_regval :: " register_value \<Rightarrow>(Sinterrupts)option " where + " Sinterrupts_of_regval (Regval_Sinterrupts (v)) = ( Some v )" +|" Sinterrupts_of_regval g__84 = ( None )" + + +(*val regval_of_Sinterrupts : Sinterrupts -> register_value*) + +definition regval_of_Sinterrupts :: " Sinterrupts \<Rightarrow> register_value " where + " regval_of_Sinterrupts v = ( Regval_Sinterrupts v )" + + +(*val TLB39_Entry_of_regval : register_value -> maybe TLB39_Entry*) + +fun TLB39_Entry_of_regval :: " register_value \<Rightarrow>(TLB39_Entry)option " where + " TLB39_Entry_of_regval (Regval_TLB39_Entry (v)) = ( Some v )" +|" TLB39_Entry_of_regval g__83 = ( None )" + + +(*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*) + +definition regval_of_TLB39_Entry :: " TLB39_Entry \<Rightarrow> register_value " where + " regval_of_TLB39_Entry v = ( Regval_TLB39_Entry v )" + + +(*val vector_64_dec_bit_of_regval : register_value -> maybe (mword ty64)*) + +fun vector_64_dec_bit_of_regval :: " register_value \<Rightarrow>((64)Word.word)option " where + " vector_64_dec_bit_of_regval (Regval_vector_64_dec_bit (v)) = ( Some v )" +|" vector_64_dec_bit_of_regval g__82 = ( None )" + + +(*val regval_of_vector_64_dec_bit : mword ty64 -> register_value*) + +definition regval_of_vector_64_dec_bit :: "(64)Word.word \<Rightarrow> register_value " where + " regval_of_vector_64_dec_bit v = ( Regval_vector_64_dec_bit v )" + + + + +(*val vector_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition vector_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " vector_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_vector (_, _, v) => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_vector : forall 'a. ('a -> register_value) -> integer -> bool -> list 'a -> register_value*) +definition regval_of_vector :: "('a \<Rightarrow> register_value)\<Rightarrow> int \<Rightarrow> bool \<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_vector regval_of1 size1 is_inc xs = ( Regval_vector (size1, is_inc, List.map regval_of1 xs))" + + +(*val list_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (list 'a)*) +definition list_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a list)option " where + " list_of_regval of_regval1 = ( \<lambda>x . + (case x of + Regval_list v => just_list (List.map of_regval1 v) + | _ => None + ) )" + + +(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*) +definition regval_of_list :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a list \<Rightarrow> register_value " where + " regval_of_list regval_of1 xs = ( Regval_list (List.map regval_of1 xs))" + + +(*val option_of_regval : forall 'a. (register_value -> maybe 'a) -> register_value -> maybe (maybe 'a)*) +definition option_of_regval :: "(register_value \<Rightarrow> 'a option)\<Rightarrow> register_value \<Rightarrow>('a option)option " where + " option_of_regval of_regval1 = ( \<lambda>x . + (case x of Regval_option v => map_option of_regval1 v | _ => None ) )" + + +(*val regval_of_option : forall 'a. ('a -> register_value) -> maybe 'a -> register_value*) +definition regval_of_option :: "('a \<Rightarrow> register_value)\<Rightarrow> 'a option \<Rightarrow> register_value " where + " regval_of_option regval_of1 v = ( Regval_option (map_option regval_of1 v))" + + + +definition tlb39_ref :: "((regstate),(register_value),((TLB39_Entry)option))register_ref " where + " tlb39_ref = ( (| + name = (''tlb39''), + read_from = (\<lambda> s . (tlb39 s)), + write_to = (\<lambda> v s . (( s (| tlb39 := v |)))), + of_regval = (\<lambda> v . option_of_regval (\<lambda> v . TLB39_Entry_of_regval v) v), + regval_of = (\<lambda> v . regval_of_option (\<lambda> v . regval_of_TLB39_Entry v) v) |) )" + + +definition tselect_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " tselect_ref = ( (| + name = (''tselect''), + read_from = (\<lambda> s . (tselect s)), + write_to = (\<lambda> v s . (( s (| tselect := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition stval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " stval_ref = ( (| + name = (''stval''), + read_from = (\<lambda> s . (stval s)), + write_to = (\<lambda> v s . (( s (| stval := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition scause_ref :: "((regstate),(register_value),(Mcause))register_ref " where + " scause_ref = ( (| + name = (''scause''), + read_from = (\<lambda> s . (scause s)), + write_to = (\<lambda> v s . (( s (| scause := v |)))), + of_regval = (\<lambda> v . Mcause_of_regval v), + regval_of = (\<lambda> v . regval_of_Mcause v) |) )" + + +definition sepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " sepc_ref = ( (| + name = (''sepc''), + read_from = (\<lambda> s . (sepc s)), + write_to = (\<lambda> v s . (( s (| sepc := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition sscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " sscratch_ref = ( (| + name = (''sscratch''), + read_from = (\<lambda> s . (sscratch s)), + write_to = (\<lambda> v s . (( s (| sscratch := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition stvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where + " stvec_ref = ( (| + name = (''stvec''), + read_from = (\<lambda> s . (stvec s)), + write_to = (\<lambda> v s . (( s (| stvec := v |)))), + of_regval = (\<lambda> v . Mtvec_of_regval v), + regval_of = (\<lambda> v . regval_of_Mtvec v) |) )" + + +definition satp_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " satp_ref = ( (| + name = (''satp''), + read_from = (\<lambda> s . (satp s)), + write_to = (\<lambda> v s . (( s (| satp := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition sideleg_ref :: "((regstate),(register_value),(Sinterrupts))register_ref " where + " sideleg_ref = ( (| + name = (''sideleg''), + read_from = (\<lambda> s . (sideleg s)), + write_to = (\<lambda> v s . (( s (| sideleg := v |)))), + of_regval = (\<lambda> v . Sinterrupts_of_regval v), + regval_of = (\<lambda> v . regval_of_Sinterrupts v) |) )" + + +definition sedeleg_ref :: "((regstate),(register_value),(Sedeleg))register_ref " where + " sedeleg_ref = ( (| + name = (''sedeleg''), + read_from = (\<lambda> s . (sedeleg s)), + write_to = (\<lambda> v s . (( s (| sedeleg := v |)))), + of_regval = (\<lambda> v . Sedeleg_of_regval v), + regval_of = (\<lambda> v . regval_of_Sedeleg v) |) )" + + +definition pmpcfg0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " pmpcfg0_ref = ( (| + name = (''pmpcfg0''), + read_from = (\<lambda> s . (pmpcfg0 s)), + write_to = (\<lambda> v s . (( s (| pmpcfg0 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition pmpaddr0_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " pmpaddr0_ref = ( (| + name = (''pmpaddr0''), + read_from = (\<lambda> s . (pmpaddr0 s)), + write_to = (\<lambda> v s . (( s (| pmpaddr0 := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mhartid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mhartid_ref = ( (| + name = (''mhartid''), + read_from = (\<lambda> s . (mhartid s)), + write_to = (\<lambda> v s . (( s (| mhartid := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition marchid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " marchid_ref = ( (| + name = (''marchid''), + read_from = (\<lambda> s . (marchid s)), + write_to = (\<lambda> v s . (( s (| marchid := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mimpid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mimpid_ref = ( (| + name = (''mimpid''), + read_from = (\<lambda> s . (mimpid s)), + write_to = (\<lambda> v s . (( s (| mimpid := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mvendorid_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mvendorid_ref = ( (| + name = (''mvendorid''), + read_from = (\<lambda> s . (mvendorid s)), + write_to = (\<lambda> v s . (( s (| mvendorid := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition minstret_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " minstret_ref = ( (| + name = (''minstret''), + read_from = (\<lambda> s . (minstret s)), + write_to = (\<lambda> v s . (( s (| minstret := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mtime_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mtime_ref = ( (| + name = (''mtime''), + read_from = (\<lambda> s . (mtime s)), + write_to = (\<lambda> v s . (( s (| mtime := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mcycle_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mcycle_ref = ( (| + name = (''mcycle''), + read_from = (\<lambda> s . (mcycle s)), + write_to = (\<lambda> v s . (( s (| mcycle := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mscratch_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mscratch_ref = ( (| + name = (''mscratch''), + read_from = (\<lambda> s . (mscratch s)), + write_to = (\<lambda> v s . (( s (| mscratch := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mtval_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mtval_ref = ( (| + name = (''mtval''), + read_from = (\<lambda> s . (mtval s)), + write_to = (\<lambda> v s . (( s (| mtval := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mepc_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " mepc_ref = ( (| + name = (''mepc''), + read_from = (\<lambda> s . (mepc s)), + write_to = (\<lambda> v s . (( s (| mepc := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition mcause_ref :: "((regstate),(register_value),(Mcause))register_ref " where + " mcause_ref = ( (| + name = (''mcause''), + read_from = (\<lambda> s . (mcause s)), + write_to = (\<lambda> v s . (( s (| mcause := v |)))), + of_regval = (\<lambda> v . Mcause_of_regval v), + regval_of = (\<lambda> v . regval_of_Mcause v) |) )" + + +definition mtvec_ref :: "((regstate),(register_value),(Mtvec))register_ref " where + " mtvec_ref = ( (| + name = (''mtvec''), + read_from = (\<lambda> s . (mtvec s)), + write_to = (\<lambda> v s . (( s (| mtvec := v |)))), + of_regval = (\<lambda> v . Mtvec_of_regval v), + regval_of = (\<lambda> v . regval_of_Mtvec v) |) )" + + +definition medeleg_ref :: "((regstate),(register_value),(Medeleg))register_ref " where + " medeleg_ref = ( (| + name = (''medeleg''), + read_from = (\<lambda> s . (medeleg s)), + write_to = (\<lambda> v s . (( s (| medeleg := v |)))), + of_regval = (\<lambda> v . Medeleg_of_regval v), + regval_of = (\<lambda> v . regval_of_Medeleg v) |) )" + + +definition mideleg_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mideleg_ref = ( (| + name = (''mideleg''), + read_from = (\<lambda> s . (mideleg s)), + write_to = (\<lambda> v s . (( s (| mideleg := v |)))), + of_regval = (\<lambda> v . Minterrupts_of_regval v), + regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )" + + +definition mie_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mie_ref = ( (| + name = (''mie''), + read_from = (\<lambda> s . (mie s)), + write_to = (\<lambda> v s . (( s (| mie := v |)))), + of_regval = (\<lambda> v . Minterrupts_of_regval v), + regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )" + + +definition mip_ref :: "((regstate),(register_value),(Minterrupts))register_ref " where + " mip_ref = ( (| + name = (''mip''), + read_from = (\<lambda> s . (mip s)), + write_to = (\<lambda> v s . (( s (| mip := v |)))), + of_regval = (\<lambda> v . Minterrupts_of_regval v), + regval_of = (\<lambda> v . regval_of_Minterrupts v) |) )" + + +definition mstatus_ref :: "((regstate),(register_value),(Mstatus))register_ref " where + " mstatus_ref = ( (| + name = (''mstatus''), + read_from = (\<lambda> s . (mstatus s)), + write_to = (\<lambda> v s . (( s (| mstatus := v |)))), + of_regval = (\<lambda> v . Mstatus_of_regval v), + regval_of = (\<lambda> v . regval_of_Mstatus v) |) )" + + +definition misa_ref :: "((regstate),(register_value),(Misa))register_ref " where + " misa_ref = ( (| + name = (''misa''), + read_from = (\<lambda> s . (misa s)), + write_to = (\<lambda> v s . (( s (| misa := v |)))), + of_regval = (\<lambda> v . Misa_of_regval v), + regval_of = (\<lambda> v . regval_of_Misa v) |) )" + + +definition cur_inst_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " cur_inst_ref = ( (| + name = (''cur_inst''), + read_from = (\<lambda> s . (cur_inst s)), + write_to = (\<lambda> v s . (( s (| cur_inst := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition cur_privilege_ref :: "((regstate),(register_value),(Privilege))register_ref " where + " cur_privilege_ref = ( (| + name = (''cur_privilege''), + read_from = (\<lambda> s . (cur_privilege s)), + write_to = (\<lambda> v s . (( s (| cur_privilege := v |)))), + of_regval = (\<lambda> v . Privilege_of_regval v), + regval_of = (\<lambda> v . regval_of_Privilege v) |) )" + + +definition Xs_ref :: "((regstate),(register_value),(((64)Word.word)list))register_ref " where + " Xs_ref = ( (| + name = (''Xs''), + read_from = (\<lambda> s . (Xs s)), + write_to = (\<lambda> v s . (( s (| Xs := v |)))), + of_regval = (\<lambda> v . vector_of_regval (\<lambda> v . vector_64_dec_bit_of_regval v) v), + regval_of = (\<lambda> v . regval_of_vector (\<lambda> v . regval_of_vector_64_dec_bit v)(( 32 :: int)) False v) |) )" + + +definition nextPC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " nextPC_ref = ( (| + name = (''nextPC''), + read_from = (\<lambda> s . (nextPC s)), + write_to = (\<lambda> v s . (( s (| nextPC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +definition PC_ref :: "((regstate),(register_value),((64)Word.word))register_ref " where + " PC_ref = ( (| + name = (''PC''), + read_from = (\<lambda> s . (PC s)), + write_to = (\<lambda> v s . (( s (| PC := v |)))), + of_regval = (\<lambda> v . vector_64_dec_bit_of_regval v), + regval_of = (\<lambda> v . regval_of_vector_64_dec_bit v) |) )" + + +(*val get_regval : string -> regstate -> maybe register_value*) +definition get_regval :: " string \<Rightarrow> regstate \<Rightarrow>(register_value)option " where + " get_regval reg_name s = ( + if reg_name = (''tlb39'') then Some ((regval_of tlb39_ref) ((read_from tlb39_ref) s)) else + if reg_name = (''tselect'') then Some ((regval_of tselect_ref) ((read_from tselect_ref) s)) else + if reg_name = (''stval'') then Some ((regval_of stval_ref) ((read_from stval_ref) s)) else + if reg_name = (''scause'') then Some ((regval_of scause_ref) ((read_from scause_ref) s)) else + if reg_name = (''sepc'') then Some ((regval_of sepc_ref) ((read_from sepc_ref) s)) else + if reg_name = (''sscratch'') then Some ((regval_of sscratch_ref) ((read_from sscratch_ref) s)) else + if reg_name = (''stvec'') then Some ((regval_of stvec_ref) ((read_from stvec_ref) s)) else + if reg_name = (''satp'') then Some ((regval_of satp_ref) ((read_from satp_ref) s)) else + if reg_name = (''sideleg'') then Some ((regval_of sideleg_ref) ((read_from sideleg_ref) s)) else + if reg_name = (''sedeleg'') then Some ((regval_of sedeleg_ref) ((read_from sedeleg_ref) s)) else + if reg_name = (''pmpcfg0'') then Some ((regval_of pmpcfg0_ref) ((read_from pmpcfg0_ref) s)) else + if reg_name = (''pmpaddr0'') then Some ((regval_of pmpaddr0_ref) ((read_from pmpaddr0_ref) s)) else + if reg_name = (''mhartid'') then Some ((regval_of mhartid_ref) ((read_from mhartid_ref) s)) else + if reg_name = (''marchid'') then Some ((regval_of marchid_ref) ((read_from marchid_ref) s)) else + if reg_name = (''mimpid'') then Some ((regval_of mimpid_ref) ((read_from mimpid_ref) s)) else + if reg_name = (''mvendorid'') then Some ((regval_of mvendorid_ref) ((read_from mvendorid_ref) s)) else + if reg_name = (''minstret'') then Some ((regval_of minstret_ref) ((read_from minstret_ref) s)) else + if reg_name = (''mtime'') then Some ((regval_of mtime_ref) ((read_from mtime_ref) s)) else + if reg_name = (''mcycle'') then Some ((regval_of mcycle_ref) ((read_from mcycle_ref) s)) else + if reg_name = (''mscratch'') then Some ((regval_of mscratch_ref) ((read_from mscratch_ref) s)) else + if reg_name = (''mtval'') then Some ((regval_of mtval_ref) ((read_from mtval_ref) s)) else + if reg_name = (''mepc'') then Some ((regval_of mepc_ref) ((read_from mepc_ref) s)) else + if reg_name = (''mcause'') then Some ((regval_of mcause_ref) ((read_from mcause_ref) s)) else + if reg_name = (''mtvec'') then Some ((regval_of mtvec_ref) ((read_from mtvec_ref) s)) else + if reg_name = (''medeleg'') then Some ((regval_of medeleg_ref) ((read_from medeleg_ref) s)) else + if reg_name = (''mideleg'') then Some ((regval_of mideleg_ref) ((read_from mideleg_ref) s)) else + if reg_name = (''mie'') then Some ((regval_of mie_ref) ((read_from mie_ref) s)) else + if reg_name = (''mip'') then Some ((regval_of mip_ref) ((read_from mip_ref) s)) else + if reg_name = (''mstatus'') then Some ((regval_of mstatus_ref) ((read_from mstatus_ref) s)) else + if reg_name = (''misa'') then Some ((regval_of misa_ref) ((read_from misa_ref) s)) else + if reg_name = (''cur_inst'') then Some ((regval_of cur_inst_ref) ((read_from cur_inst_ref) s)) else + if reg_name = (''cur_privilege'') then Some ((regval_of cur_privilege_ref) ((read_from cur_privilege_ref) s)) else + if reg_name = (''Xs'') then Some ((regval_of Xs_ref) ((read_from Xs_ref) s)) else + if reg_name = (''nextPC'') then Some ((regval_of nextPC_ref) ((read_from nextPC_ref) s)) else + if reg_name = (''PC'') then Some ((regval_of PC_ref) ((read_from PC_ref) s)) else + None )" + + +(*val set_regval : string -> register_value -> regstate -> maybe regstate*) +definition set_regval :: " string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option " where + " set_regval reg_name v s = ( + if reg_name = (''tlb39'') then map_option (\<lambda> v . (write_to tlb39_ref) v s) ((of_regval tlb39_ref) v) else + if reg_name = (''tselect'') then map_option (\<lambda> v . (write_to tselect_ref) v s) ((of_regval tselect_ref) v) else + if reg_name = (''stval'') then map_option (\<lambda> v . (write_to stval_ref) v s) ((of_regval stval_ref) v) else + if reg_name = (''scause'') then map_option (\<lambda> v . (write_to scause_ref) v s) ((of_regval scause_ref) v) else + if reg_name = (''sepc'') then map_option (\<lambda> v . (write_to sepc_ref) v s) ((of_regval sepc_ref) v) else + if reg_name = (''sscratch'') then map_option (\<lambda> v . (write_to sscratch_ref) v s) ((of_regval sscratch_ref) v) else + if reg_name = (''stvec'') then map_option (\<lambda> v . (write_to stvec_ref) v s) ((of_regval stvec_ref) v) else + if reg_name = (''satp'') then map_option (\<lambda> v . (write_to satp_ref) v s) ((of_regval satp_ref) v) else + if reg_name = (''sideleg'') then map_option (\<lambda> v . (write_to sideleg_ref) v s) ((of_regval sideleg_ref) v) else + if reg_name = (''sedeleg'') then map_option (\<lambda> v . (write_to sedeleg_ref) v s) ((of_regval sedeleg_ref) v) else + if reg_name = (''pmpcfg0'') then map_option (\<lambda> v . (write_to pmpcfg0_ref) v s) ((of_regval pmpcfg0_ref) v) else + if reg_name = (''pmpaddr0'') then map_option (\<lambda> v . (write_to pmpaddr0_ref) v s) ((of_regval pmpaddr0_ref) v) else + if reg_name = (''mhartid'') then map_option (\<lambda> v . (write_to mhartid_ref) v s) ((of_regval mhartid_ref) v) else + if reg_name = (''marchid'') then map_option (\<lambda> v . (write_to marchid_ref) v s) ((of_regval marchid_ref) v) else + if reg_name = (''mimpid'') then map_option (\<lambda> v . (write_to mimpid_ref) v s) ((of_regval mimpid_ref) v) else + if reg_name = (''mvendorid'') then map_option (\<lambda> v . (write_to mvendorid_ref) v s) ((of_regval mvendorid_ref) v) else + if reg_name = (''minstret'') then map_option (\<lambda> v . (write_to minstret_ref) v s) ((of_regval minstret_ref) v) else + if reg_name = (''mtime'') then map_option (\<lambda> v . (write_to mtime_ref) v s) ((of_regval mtime_ref) v) else + if reg_name = (''mcycle'') then map_option (\<lambda> v . (write_to mcycle_ref) v s) ((of_regval mcycle_ref) v) else + if reg_name = (''mscratch'') then map_option (\<lambda> v . (write_to mscratch_ref) v s) ((of_regval mscratch_ref) v) else + if reg_name = (''mtval'') then map_option (\<lambda> v . (write_to mtval_ref) v s) ((of_regval mtval_ref) v) else + if reg_name = (''mepc'') then map_option (\<lambda> v . (write_to mepc_ref) v s) ((of_regval mepc_ref) v) else + if reg_name = (''mcause'') then map_option (\<lambda> v . (write_to mcause_ref) v s) ((of_regval mcause_ref) v) else + if reg_name = (''mtvec'') then map_option (\<lambda> v . (write_to mtvec_ref) v s) ((of_regval mtvec_ref) v) else + if reg_name = (''medeleg'') then map_option (\<lambda> v . (write_to medeleg_ref) v s) ((of_regval medeleg_ref) v) else + if reg_name = (''mideleg'') then map_option (\<lambda> v . (write_to mideleg_ref) v s) ((of_regval mideleg_ref) v) else + if reg_name = (''mie'') then map_option (\<lambda> v . (write_to mie_ref) v s) ((of_regval mie_ref) v) else + if reg_name = (''mip'') then map_option (\<lambda> v . (write_to mip_ref) v s) ((of_regval mip_ref) v) else + if reg_name = (''mstatus'') then map_option (\<lambda> v . (write_to mstatus_ref) v s) ((of_regval mstatus_ref) v) else + if reg_name = (''misa'') then map_option (\<lambda> v . (write_to misa_ref) v s) ((of_regval misa_ref) v) else + if reg_name = (''cur_inst'') then map_option (\<lambda> v . (write_to cur_inst_ref) v s) ((of_regval cur_inst_ref) v) else + if reg_name = (''cur_privilege'') then map_option (\<lambda> v . (write_to cur_privilege_ref) v s) ((of_regval cur_privilege_ref) v) else + if reg_name = (''Xs'') then map_option (\<lambda> v . (write_to Xs_ref) v s) ((of_regval Xs_ref) v) else + if reg_name = (''nextPC'') then map_option (\<lambda> v . (write_to nextPC_ref) v s) ((of_regval nextPC_ref) v) else + if reg_name = (''PC'') then map_option (\<lambda> v . (write_to PC_ref) v s) ((of_regval PC_ref) v) else + None )" + + +definition register_accessors :: "(string \<Rightarrow> regstate \<Rightarrow>(register_value)option)*(string \<Rightarrow> register_value \<Rightarrow> regstate \<Rightarrow>(regstate)option)" where + " register_accessors = ( (get_regval, set_regval))" + + + +type_synonym( 'a, 'r) MR =" (register_value, 'a, 'r, exception) monadR " +type_synonym 'a M =" (register_value, 'a, exception) monad " +end |