diff options
| -rw-r--r-- | riscv/riscv.sail | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 27ec8a2f..ca30f4b4 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -790,8 +790,11 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = WORD => vaddr[1..0] == 0b00, DOUBLE => vaddr[2..0] == 0b000 } in + /* "LR faults like a normal load, even though it's in the AMO major opcode space." + - Andrew Waterman, isa-dev, 10 Jul 2018. + */ if (~ (aligned)) - then { handle_mem_exception(vaddr, E_SAMO_Addr_Align); false } + then { handle_mem_exception(vaddr, E_Load_Addr_Align); false } else match translateAddr(vaddr, Read, Data) { TR_Failure(e) => { handle_mem_exception(vaddr, e); false }, TR_Address(addr) => |