diff options
| -rw-r--r-- | riscv/riscv_all.sail | 3 | ||||
| -rw-r--r-- | riscv/riscv_platform.sail | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/riscv/riscv_all.sail b/riscv/riscv_all.sail index 32356ea9..192b049d 100644 --- a/riscv/riscv_all.sail +++ b/riscv/riscv_all.sail @@ -4,6 +4,9 @@ $include "riscv_sys.sail" $include "riscv_platform.sail" $include "riscv_mem.sail" $include "riscv_vmem.sail" +$include "riscv_insts_begin.sail" $include "riscv.sail" +$include "riscv_jalr_seq.sail" +$include "riscv_insts_end.sail" $include "riscv_step.sail" $include "riscv_analysis.sail" diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index aac6b587..9041c7f4 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -42,6 +42,7 @@ function plat_enable_misaligned_access () = false val plat_mtval_has_illegal_inst_bits = {ocaml: "Platform.mtval_has_illegal_inst_bits", c: "plat_mtval_has_illegal_inst_bits", lem: "plat_mtval_has_illegal_inst_bits"} : unit -> bool +function plat_mtval_has_illegal_inst_bits () = false /* ROM holding reset vector and device-tree DTB */ val plat_rom_base = {ocaml: "Platform.rom_base", c: "plat_rom_base", lem: "plat_rom_base"} : unit -> xlenbits |