Rename some functions in vector_dec library file to avoid clashes with functions in mips spec in prepartion for using this file in mips prelude. Also modify tests that use this header. We should consider prefixing library builtins to avoid name clashes. overload can then be used to provide aliases if desired.

3 files changed, 5 insertions, 5 deletions

diff --git a/test/c/bitvector.sail b/test/c/bitvector.sail
index 5311caff..8a80234e 100644
--- a/test/c/bitvector.sail
+++ b/test/c/bitvector.sail
@@ -13,10 +13,10 @@ function test (x, y)  = {
 val main : unit -> unit
 
 function main () = {
-  if test(0xBEEF, zeros(200)) then () else ();
+  if test(0xBEEF, sail_zeros(200)) then () else ();
   let z = 0xCAFE;
   print_bits("z = ", z);
-  print_bits("zero_extend(z) = ", zero_extend(z, 32));
+  print_bits("zero_extend(z) = ", sail_zero_extend(z, 32));
   let q = 0xAB_FEED_DEAD_BEEF_CAFE;
   print_bits("q = ", q);
   let k = 0xFF;
diff --git a/test/ocaml/lsl/lsl.sail b/test/ocaml/lsl/lsl.sail
index 74d2b8e5..ce270c4e 100644
--- a/test/ocaml/lsl/lsl.sail
+++ b/test/ocaml/lsl/lsl.sail
@@ -4,7 +4,7 @@ val lslc : forall ('n : Int) ('shift : Int), 'n >= 1.
 
 function lslc (vec, shift) = {
   assert(constraint('shift >= 1), "shift must be positive");
-  extended : bits('shift + 'n) = vec @ zeros(shift);
+  extended : bits('shift + 'n) = vec @ sail_zeros(shift);
   result : bits('n) = extended[sizeof('n - 1) .. 0];
   c : bit = extended['n];
   return((result, c))
diff --git a/test/ocaml/vec_32_64/vec_32_64.sail b/test/ocaml/vec_32_64/vec_32_64.sail
index ac44d9ae..5dc58cc3 100644
--- a/test/ocaml/vec_32_64/vec_32_64.sail
+++ b/test/ocaml/vec_32_64/vec_32_64.sail
@@ -12,12 +12,12 @@ val main : unit -> unit
 
 function main () = {
   let 'len = get_size ();
-  let xs = zeros(len);
+  let xs = sail_zeros(len);
   if (len == 32) then {
     ()
   } else {
     only64(xs)
   };
   print_bits("xs = ", xs);
-  print_bits("zeros(64) = ", zeros(64))
+  print_bits("zeros(64) = ", sail_zeros(64))
 }
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