diff options
| author | Alasdair Armstrong | 2019-05-14 18:19:57 +0100 |
|---|---|---|
| committer | Alasdair Armstrong | 2019-05-14 18:24:00 +0100 |
| commit | 16f394156cbabeeb774eccf1cdb3ac6004f99a36 (patch) | |
| tree | 9b46f7bf579aa6dcc6c97b9904a550d1e4ba5517 /test/typecheck | |
| parent | 94f44553d4ca93d89713b279a1d5590cb002b70f (diff) | |
Fix test case for previous commit
Previous commit changed the bitfield desugaring very slightly which
this test case relied upon.
Diffstat (limited to 'test/typecheck')
| -rw-r--r-- | test/typecheck/pass/bitvector_param.sail | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/test/typecheck/pass/bitvector_param.sail b/test/typecheck/pass/bitvector_param.sail index ffebeb6e..77fe7dc3 100644 --- a/test/typecheck/pass/bitvector_param.sail +++ b/test/typecheck/pass/bitvector_param.sail @@ -1,5 +1,7 @@ -/* from prelude */ default Order dec + +$include <flow.sail> + type bits ('n : Int) = vector('n, dec, bit) val vector_subrange = { @@ -26,10 +28,6 @@ val vector_concat = {ocaml: "append", lem: "append_list"} : forall ('n : Int) (' overload append = {bitvector_concat, vector_concat} -val "reg_deref" : forall ('a : Type). register('a) -> 'a effect {rreg} -/* sneaky deref with no effect necessary for bitfield writes */ -val _reg_deref = "reg_deref" : forall ('a : Type). register('a) -> 'a - type xlen : Int = 64 type ylen : Int = 1 |