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authorAlasdair Armstrong2018-06-21 16:22:03 +0100
committerAlasdair Armstrong2018-06-21 17:02:01 +0100
commitbb694008780f63d84a68893016044b660a1558bf (patch)
tree9cef428d8f19673459a07f8387df4b423bba5505 /test/c/read_write_ram.sail
parent326f0dd88df92d3936b7acadb5073802d3f9d77b (diff)
parent3658789d204eb100e901a2adb67b6bf8a30157bf (diff)
Merge branch 'tracing' into sail2
Diffstat (limited to 'test/c/read_write_ram.sail')
-rw-r--r--test/c/read_write_ram.sail29
1 files changed, 29 insertions, 0 deletions
diff --git a/test/c/read_write_ram.sail b/test/c/read_write_ram.sail
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+++ b/test/c/read_write_ram.sail
@@ -0,0 +1,29 @@
+default Order dec
+
+$include <flow.sail>
+$include <arith.sail>
+$include <vector_dec.sail>
+$include <string.sail>
+$include <exception_basic.sail>
+
+val write_ram = "write_ram" : forall 'n 'm.
+ (atom('m), atom('n), bits('m), bits('m), bits(8 * 'n)) -> unit effect {wmem}
+
+val read_ram = "read_ram" : forall 'n 'm.
+ (atom('m), atom('n), bits('m), bits('m)) -> bits(8 * 'n) effect {rmem}
+
+val main : unit -> unit effect {escape, wmem, rmem}
+
+function main() = {
+ write_ram(64, 4, 64^0x0, 64^0x8000_0000, 0x01020304);
+ let data = read_ram(64, 4, 64^0x0, 64^0x8000_0000);
+ assert(data == 0x01020304);
+ let data = read_ram(64, 3, 64^0x0, 64^0x8000_0001);
+ assert(data == 0x010203);
+ let data = read_ram(64, 3, 64^0x0, 64^0x8000_0000);
+ assert(data == 0x020304);
+ write_ram(64, 4, 64^0x0, 64^0x7fff_ffff, 0xA1B2C3D4);
+ let data = read_ram(64, 3, 64^0x0, 64^0x8000_0000);
+ assert(data == 0xA1B2C3);
+ print_endline("ok");
+} \ No newline at end of file