diff options
| author | Jon French | 2018-07-05 13:09:41 +0100 |
|---|---|---|
| committer | Jon French | 2018-07-05 13:09:46 +0100 |
| commit | c080665a6fbd8c88b66440a7bddc31a9634741cf (patch) | |
| tree | bbd54114de4afe2abea9e7b4e7b1bf9e103b8eaa /src | |
| parent | eb306a0d3e3abc96d5227b9f240666c5bff6869f (diff) | |
restore missing RISC-V fence types in sail2; ignore io bits in fences more cleanly
Diffstat (limited to 'src')
| -rw-r--r-- | src/lem_interp/sail2_instr_kinds.lem | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/lem_interp/sail2_instr_kinds.lem b/src/lem_interp/sail2_instr_kinds.lem index 13e5304e..938b693d 100644 --- a/src/lem_interp/sail2_instr_kinds.lem +++ b/src/lem_interp/sail2_instr_kinds.lem @@ -151,6 +151,10 @@ type barrier_kind = | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w + | Barrier_RISCV_w_rw + | Barrier_RISCV_rw_r + | Barrier_RISCV_r_w + | Barrier_RISCV_w_r | Barrier_RISCV_i (* X86 *) | Barrier_x86_MFENCE @@ -176,6 +180,10 @@ instance (Show barrier_kind) | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" + | Barrier_RISCV_w_rw -> "Barrier_RISCV_w_rw" + | Barrier_RISCV_rw_r -> "Barrier_RISCV_rw_r" + | Barrier_RISCV_r_w -> "Barrier_RISCV_r_w" + | Barrier_RISCV_w_r -> "Barrier_RISCV_w_r" | Barrier_RISCV_i -> "Barrier_RISCV_i" | Barrier_x86_MFENCE -> "Barrier_x86_MFENCE" end @@ -288,7 +296,11 @@ instance (EnumerationType barrier_kind) | Barrier_RISCV_r_r -> 15 | Barrier_RISCV_rw_w -> 16 | Barrier_RISCV_w_w -> 17 - | Barrier_RISCV_i -> 18 - | Barrier_x86_MFENCE -> 19 + | Barrier_RISCV_w_rw -> 18 + | Barrier_RISCV_rw_r -> 19 + | Barrier_RISCV_r_w -> 20 + | Barrier_RISCV_w_r -> 21 + | Barrier_RISCV_i -> 22 + | Barrier_x86_MFENCE -> 23 end end |