add support for x86 lock prefix (also remove unused Read/Write_tag kind in etc/regfp.sail.

1 files changed, 6 insertions, 0 deletions

diff --git a/src/lem_interp/sail_impl_base.lem b/src/lem_interp/sail_impl_base.lem
index e6169762..e39c4421 100644
--- a/src/lem_interp/sail_impl_base.lem
+++ b/src/lem_interp/sail_impl_base.lem
@@ -441,6 +441,7 @@ type read_kind =
   | Read_RISCV_acquire  | Read_RISCV_strong_acquire
   | Read_RISCV_reserved | Read_RISCV_reserved_acquire
   | Read_RISCV_reserved_strong_acquire
+  | Read_X86_locked
 
 instance (Show read_kind)
   let show = function
@@ -455,6 +456,7 @@ instance (Show read_kind)
     | Read_RISCV_reserved -> "Read_RISCV_reserved"
     | Read_RISCV_reserved_acquire -> "Read_RISCV_reserved_acquire"
     | Read_RISCV_reserved_strong_acquire -> "Read_RISCV_reserved_strong_acquire"
+    | Read_X86_locked -> "Read_X86_locked"
   end
 end
 
@@ -469,6 +471,7 @@ type write_kind =
   | Write_RISCV_release     | Write_RISCV_strong_release
   | Write_RISCV_conditional | Write_RISCV_conditional_release
   | Write_RISCV_conditional_strong_release
+  | Write_X86_locked
 
 instance (Show write_kind)
   let show = function
@@ -482,6 +485,7 @@ instance (Show write_kind)
     | Write_RISCV_conditional -> "Write_RISCV_conditional"
     | Write_RISCV_conditional_release -> "Write_RISCV_conditional_release"
     | Write_RISCV_conditional_strong_release -> "Write_RISCV_conditional_strong_release"
+    | Write_X86_locked -> "Write_X86_locked"
   end
 end
 
@@ -580,6 +584,7 @@ instance (EnumerationType read_kind)
     | Read_RISCV_reserved -> 8
     | Read_RISCV_reserved_acquire -> 9
     | Read_RISCV_reserved_strong_acquire -> 10
+    | Read_X86_locked -> 11
   end
 end
 
@@ -595,6 +600,7 @@ instance (EnumerationType write_kind)
     | Write_RISCV_conditional -> 7
     | Write_RISCV_conditional_release -> 8
     | Write_RISCV_conditional_strong_release -> 9
+    | Write_X86_locked -> 10
   end
 end