diff options
| author | Alasdair Armstrong | 2018-07-05 19:09:26 +0100 |
|---|---|---|
| committer | Alasdair Armstrong | 2018-07-05 19:11:21 +0100 |
| commit | 9a0cbbedbe281807f70bf2206756624315096642 (patch) | |
| tree | b4bab037fd3e68444d9a15b709d6e9ee5ebe769f /src | |
| parent | e5654331c24391e984484e590993887b499af9f8 (diff) | |
Fix CHERI test that was failing when compiled to C
Non bitvector literals for decreasing vectors were not being reversed
correctly, so the list of capability registers was effectively in
reverse order.
Added a test case to test/c/ based on this aspect of CHERI
Diffstat (limited to 'src')
| -rw-r--r-- | src/c_backend.ml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/c_backend.ml b/src/c_backend.ml index eeb3390e..6f1379e3 100644 --- a/src/c_backend.ml +++ b/src/c_backend.ml @@ -691,7 +691,7 @@ let rec compile_aval ctx = function in [idecl vector_ctyp gs; iextern (CL_id gs) (mk_id "internal_vector_init") [(F_lit (V_int (Big_int.of_int len)), CT_int64)] vector_ctyp] - @ List.concat (List.mapi aval_set avals), + @ List.concat (List.mapi aval_set (if direction then List.rev avals else avals)), (F_id gs, vector_ctyp), [iclear vector_ctyp gs] |