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authorGabriel Kerneis2014-06-02 15:46:40 +0100
committerGabriel Kerneis2014-06-02 15:47:43 +0100
commit978f5bc208248afe284bb9488c4e892e9315c8a2 (patch)
treecdf934555f7fb91a48cac8f4a36d9a1fac6279fd /src
parent709066442759bdf4bb4fb16a66da3a31ba55e24c (diff)
Fix dependent-type for MEM in power.sail
Now, constraint resolution works for test/power.sail
Diffstat (limited to 'src')
-rw-r--r--src/Makefile2
-rw-r--r--src/test/power.sail2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/Makefile b/src/Makefile
index b4265016..92ca2246 100644
--- a/src/Makefile
+++ b/src/Makefile
@@ -8,7 +8,7 @@ test: all
test_power:
#../../../rsem/idl/power/binary/run.sh
- SAIL_OPTS=-skip_constraints ocamlbuild -classic-display sail.native test/run_power.native
+ ocamlbuild -classic-display sail.native test/run_power.native
./run_power.native --file ../../../rsem/idl/power/binary/main.bin
test_idempotence:
diff --git a/src/test/power.sail b/src/test/power.sail
index 9cf49dc3..02b4555f 100644
--- a/src/test/power.sail
+++ b/src/test/power.sail
@@ -91,7 +91,7 @@ register (vector <0, 64, inc, bit>) DCR1
let (vector <0, 2, inc, (register<(vector<0, 64, inc, bit>)>) >) DCR =
[ DCR0, DCR1 ]
-val extern ( nat , nat ) -> (bit[64]) effect { wmem , rmem } MEM
+val extern forall Nat 'n. ( nat , [|'n|] ) -> (bit[8 * 'n]) effect { wmem , rmem } MEM
(* XXX effect for trap? *)
val extern unit -> unit effect pure trap