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authorGabriel Kerneis2014-06-07 09:15:43 +0100
committerGabriel Kerneis2014-06-07 09:15:43 +0100
commit6b0fe4487e652d304c6866a4369e363244e12aed (patch)
treeb29c70632bc3e102d1ad1957ac75e6e60ed4296c /src
parent7cbf9c854d9ea6dd69b11b9172c53f446d388244 (diff)
Pattern-matching exhaustiveness
Diffstat (limited to 'src')
-rw-r--r--src/test/run_power.ml11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/test/run_power.ml b/src/test/run_power.ml
index 0369ac83..dfc6eddd 100644
--- a/src/test/run_power.ml
+++ b/src/test/run_power.ml
@@ -61,8 +61,10 @@ let lr_init_value = Big_int.zero_big_int
let init_reg () =
let init name value size =
(* fix index - this is necessary for CR, indexed from 32 *)
- let offset (V_vector(_, inc, v)) =
- V_vector(Big_int.big_int_of_int (64 - size), inc, v) in
+ let offset = function
+ V_vector(_, inc, v) ->
+ V_vector(Big_int.big_int_of_int (64 - size), inc, v)
+ | _ -> assert false in
Id_aux(Id name, Unknown), offset (big_int_to_vec value size) in
List.fold_left (fun r (k,v) -> Reg.add k v r) Reg.empty [
(* XXX execute main() directly until we can handle the init phase *)
@@ -96,8 +98,9 @@ let time_it action arg =
let get_reg reg name =
let reg_content = Reg.find (Id_aux(Id name, Unknown)) reg in
- let V_lit(L_aux(L_num n, Unknown)) = to_num true reg_content in
- n
+ match to_num true reg_content with
+ | V_lit(L_aux(L_num n, Unknown)) -> n
+ | _ -> assert false
;;
let rec fde_loop count entry mem reg prog =