diff options
| author | Kathy Gray | 2015-01-16 14:30:26 +0000 |
|---|---|---|
| committer | Kathy Gray | 2015-01-16 14:30:26 +0000 |
| commit | 0eda3ccb8f3003bbc0366ee1bead89c9408e185f (patch) | |
| tree | 9a97e7f9cb003260d3ac3cea99d245ec6e2a08f7 /src | |
| parent | 0e3bc29828896585d0cf43817218fc3de1d1bd25 (diff) | |
more for loop corrections, as well as pattern match error
Diffstat (limited to 'src')
| -rw-r--r-- | src/lem_interp/interp.lem | 6 | ||||
| -rw-r--r-- | src/lem_interp/interp_interface.lem | 8 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/lem_interp/interp.lem b/src/lem_interp/interp.lem index 42073bf1..6b92b66f 100644 --- a/src/lem_interp/interp.lem +++ b/src/lem_interp/interp.lem @@ -412,9 +412,9 @@ let retaint orig updated = end val detaint: value -> value -let detaint value = +let rec detaint value = match value with - | V_track value _ -> value + | V_track value _ -> detaint value | v -> v end @@ -1238,7 +1238,7 @@ and interp_main mode t_level l_env l_mem (E_aux exp (l,annot)) = let (by_e,env) = to_exp mode le by_val_whole in match by_val with | V_lit (L_aux (L_num by_num) bl) -> - if ((is_inc && (from_num >= to_num)) || (not(is_inc) && (from_num <= to_num))) + if ((is_inc && (from_num > to_num)) || (not(is_inc) && (from_num < to_num))) then (Value(V_lit (L_aux L_unit l)),lm,le) else let (ftyp,ttyp,btyp) = (val_typ from_val,val_typ to_val,val_typ by_val) in diff --git a/src/lem_interp/interp_interface.lem b/src/lem_interp/interp_interface.lem index a5966c6a..ae29a2e9 100644 --- a/src/lem_interp/interp_interface.lem +++ b/src/lem_interp/interp_interface.lem @@ -126,12 +126,14 @@ specifies a part of the field, indexed w.r.t. the register as a whole *) (* because reg_name contains slice which currently contains Big_int.big_int, the default OCaml comparison is not sufficient and we need to define explicit type classes *) +let slice_eq (s1l,s1r) (s2l,s2r) = (s1l = s2l) && (s1r = s2r) + let reg_nameEqual r1 r2 = match (r1,r2) with | (Reg s1 l1, Reg s2 l2) -> s1=s2 && l1=l2 - | (Reg_slice s1 sl1, Reg_slice s2 sl2) -> s1=s2 && sl1=sl2 - | (Reg_field s1 f1 sl1, Reg_field s2 f2 sl2) -> s1=s2 && f1=f2 && sl1=sl2 - | (Reg_f_slice s1 f1 sl1 sl1', Reg_f_slice s2 f2 sl2 sl2') -> s1=s2 && f1=f2 && sl1=sl2 && sl1'=sl2' + | (Reg_slice s1 sl1, Reg_slice s2 sl2) -> s1=s2 && (slice_eq sl1 sl2) + | (Reg_field s1 f1 sl1, Reg_field s2 f2 sl2) -> s1=s2 && f1=f2 && (slice_eq sl1 sl2) + | (Reg_f_slice s1 f1 sl1 sl1', Reg_f_slice s2 f2 sl2 sl2') -> s1=s2 && f1=f2 && (slice_eq sl1 sl2) && (slice_eq sl1' sl2') | _ -> false end |