diff options
| author | Gabriel Kerneis | 2014-04-03 13:57:58 +0100 |
|---|---|---|
| committer | Gabriel Kerneis | 2014-04-03 13:57:58 +0100 |
| commit | cf99ac1175bd0bb754cdd776f18b109eced0ed03 (patch) | |
| tree | 12190f575742bccad07f0b66cc0bcdccb3549ae7 /src/test | |
| parent | 371a90826771efad2da8b9d0cc984eee5f166741 (diff) | |
Exhibit two bugs about bitwise operators and vector casts
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/power.sail | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/test/power.sail b/src/test/power.sail index 704fc475..9ed7178b 100644 --- a/src/test/power.sail +++ b/src/test/power.sail @@ -111,10 +111,15 @@ scattered function ast decode function clause execute ( BranchConditionaltoLinkRegister ( BH, BI, BO, LK ) ) = { { if mode64bit then M := 0 else M := 32 ; - if ( ~ ( (( BO )[ 2 ]) )) then CTR := ( CTR - 1 ) ; + (bit[1]) tmp := BO[2]; + (* bug 1: tmp is vector<0,1,inc,bit> but expected vector<0,?,inc,bit> *) + if ( ~ (tmp) ) then CTR := ( CTR - 1 ) ; ctr_ok := ( (( BO )[ 2 ]) | ( ( (( CTR )[ M .. 63 ]) != 0 ) ^ (( BO )[ 3 ]) ) ) ; cond_ok := ( (( BO )[ 0 ]) | ( (( CR )[ ( BI + 32 ) ]) ^ ( ~ ( (( BO )[ 1 ]) )) ) ) ; - if ( ctr_ok & cond_ok ) then NIA := ( (( LR )[ 0 .. 61 ]) : 0b00 ) ; + (* XXX bug2: workaround to force cast; if we substitute tmp inside + the if, cast fails *) + tmp := (ctr_ok & cond_ok ); + if ( tmp ) then NIA := ( (( LR )[ 0 .. 61 ]) : 0b00 ) ; if LK then LR := ( CIA + 4 ) ; } } |