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authorKathy Gray2014-08-18 18:43:14 +0100
committerKathy Gray2014-08-18 18:43:14 +0100
commit3c86cf03071bef70c1909b13dcb1db28f8cd5c33 (patch)
tree01d6230242279088bde252c6323e80193a1029c6 /src/test
parent9f2ec1fcb16191ad9c54f68152f03ca80f85522e (diff)
Handling many register reads, writes, and memory reads.
There are problems that warrant discussion about handling special registers that hold records or data structures previously.
Diffstat (limited to 'src/test')
-rw-r--r--src/test/power.sail4
-rw-r--r--src/test/run_power.ml2
2 files changed, 4 insertions, 2 deletions
diff --git a/src/test/power.sail b/src/test/power.sail
index 5f1f532b..9a89c9e4 100644
--- a/src/test/power.sail
+++ b/src/test/power.sail
@@ -333,8 +333,8 @@ register (bit[64]) NIA (* next instruction address *)
register (bit[64]) CIA (* current instruction address *)
-val extern forall Nat 'n. ( nat , [|'n|] , bit[8*'n]) -> unit effect { wmem } MEMw
-val extern forall Nat 'n. ( nat , [|'n|] ) -> (bit[8 * 'n]) effect { rmem } MEMr
+val extern forall Nat 'n. ( bit[64] , [|'n|] , bit[8*'n]) -> unit effect { wmem } MEMw
+val extern forall Nat 'n. ( bit[64] , [|'n|] ) -> (bit[8 * 'n]) effect { rmem } MEMr
(* XXX effect for trap? *)
val extern unit -> unit effect pure trap
diff --git a/src/test/run_power.ml b/src/test/run_power.ml
index 667792c0..70cf5d4b 100644
--- a/src/test/run_power.ml
+++ b/src/test/run_power.ml
@@ -33,7 +33,9 @@ let mem = ref Mem.empty ;;
let add_mem byte addr =
assert(byte >= 0 && byte < 256);
+ (*Printf.printf "adder is %s, byte is %s\n" (Big_int.string_of_big_int addr) (string_of_int byte);*)
let addr = big_int_to_vec true addr (Big_int.big_int_of_int 64) in
+ (*Printf.printf "adder is %s byte is %s\n" (val_to_string addr) (string_of_int byte);*)
match addr with
| Bytevector addr -> mem := Mem.add addr byte !mem
;;