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| author | Gabriel Kerneis | 2014-02-14 17:11:41 +0000 |
|---|---|---|
| committer | Gabriel Kerneis | 2014-02-14 17:11:41 +0000 |
| commit | b5d3093499666f6af80544b2a35a0b425d4375e0 (patch) | |
| tree | 6ef8f13f98917752044a4e31a282d985663ee64b /src/test/test3.sail | |
| parent | e63004599c19e8e741918c6e64ec0a5362abc8ed (diff) | |
Write slice to memory
I'm not sure whether this is useful at all. It is currently a bit
broken when subrange is not in the "correct" order. Presumably the
typechecker should catch this? I'm not quite sure what the intended
semantics should be. Probably the same bug occurs with register slices
too.
Diffstat (limited to 'src/test/test3.sail')
| -rw-r--r-- | src/test/test3.sail | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/test/test3.sail b/src/test/test3.sail index 154ce5b6..e6bf4cdd 100644 --- a/src/test/test3.sail +++ b/src/test/test3.sail @@ -6,6 +6,8 @@ val nat -> nat effect { wmem , rmem } MEM val nat -> nat effect { wmem , rmem } MEM_GPU val ( nat * nat ) -> nat effect { wmem , rmem } MEM_SIZE +val nat -> (bit[8]) effect { wmem , rmem } MEM_WORD + function unit ignore(x) = () (* extern functions *) @@ -24,6 +26,15 @@ function nat main _ = { (* register read, thanks to register declaration *) ignore(dummy_reg); + + MEM_WORD(0) := 0b10101010; + (MEM_WORD(0))[3..4] := 0b10; + (* XXX this one is broken - I don't what it should do, + or even if we should accept it, but the current result + is to eat up one bit, ending up with a 7-bit word. *) + (MEM_WORD(0))[4..3] := 0b10; + ignore(MEM_WORD(0)); + (* infix call *) ignore(7 * 9); |