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authorKathy Gray2014-06-04 18:17:32 +0100
committerKathy Gray2014-06-04 18:17:32 +0100
commit68ea054c0a26fd8da8198a449fc248ed621311c5 (patch)
tree2d404f4a8f5a13ea06d7f04b3a873a170b3d5ec9 /src/test/power.sail
parent978f5bc208248afe284bb9488c4e892e9315c8a2 (diff)
Fixup type coercions and overloading
Reduce the number of implicit coercions we're doing, expanding overloading and fixing up types of functions. Warning: test_power does not run as not all overloaded funcitons are implemented Warning: vector concatenation does not pretty print to sail source yet
Diffstat (limited to 'src/test/power.sail')
-rw-r--r--src/test/power.sail6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/test/power.sail b/src/test/power.sail
index 02b4555f..adcd0d9f 100644
--- a/src/test/power.sail
+++ b/src/test/power.sail
@@ -126,7 +126,7 @@ scattered function ast decode
function clause execute ( LoadWordandZero ( D, RA, RT ) ) =
{ (bit[64]) EA := 0; (bit[64]) b := 0; {
- if((bit) ( RA == 0 ) ) then b := 0 else b := (GPR[ RA ]) ;
+ if((bit) ( (nat) RA == 0 ) ) then b := 0 else b := (GPR[ RA ]) ;
EA := ( b + ( exts ( D )) ) ;
GPR[ RT ] := ( 0b00000000000000000000000000000000 : MEM( EA , 4 ) ) ;
} }
@@ -139,7 +139,7 @@ scattered function ast decode
function clause execute ( StoreWord ( D, RA, RS ) ) =
{ (bit[64]) EA := 0; (bit[64]) b := 0; {
- if((bit) ( RA == 0 ) ) then b := 0 else b := (GPR[ RA ]) ;
+ if((bit) ( (nat) RA == 0 ) ) then b := 0 else b := (GPR[ RA ]) ;
EA := ( b + ( exts ( D )) ) ;
MEM( EA , 4 ) := (( (GPR[ RS ]) )[ 32 .. 63 ]) ;
} }
@@ -165,7 +165,7 @@ scattered function ast decode
function clause execute ( AddImmediate ( RA, RT, SI ) ) =
{ {
- if((bit) ( RA == 0 ) ) then GPR[ RT ] := ( exts ( SI )) else GPR[ RT ] := ( (GPR[ RA ]) + ( exts ( SI )) ) ;
+ if((bit) ( (nat) RA == 0 ) ) then GPR[ RT ] := (bit[64]) ( exts ( SI )) else GPR[ RT ] := ( (GPR[ RA ]) + ( exts ( SI )) ) ;
} }