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| author | Kathy Gray | 2014-11-04 16:12:21 +0000 |
|---|---|---|
| committer | Kathy Gray | 2014-11-04 16:12:21 +0000 |
| commit | 4122b87486fab99baa85170ae59fb3643ec8c63f (patch) | |
| tree | a2b09b2c1cf98b48686e629a8b84631cd6e1cccd /src/test/power.sail | |
| parent | 4f11262900c31c05118eaa42b85feafa41ae72b5 (diff) | |
Fixes bugs:
not setting starting bit of vector properly
not treating properly if when given a non boolean --- bool largely removed in place of bit, removing many/most is_one casts but true and false are still possible values
coerces between bit vectors of length one and bits again, because reading from a register can otherwise be wrong with respect to the interface
Diffstat (limited to 'src/test/power.sail')
| -rw-r--r-- | src/test/power.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/test/power.sail b/src/test/power.sail index a57193fd..4305c099 100644 --- a/src/test/power.sail +++ b/src/test/power.sail @@ -347,7 +347,7 @@ val extern unit -> unit effect { barr } EIEIO_Sync (* XXX effect for trap? *) val extern unit -> unit effect pure trap -register (bool) mode64bit +register (bit[1]) mode64bit register (bool) bigendianmode val bit[64] -> unit effect {rreg,wreg} set_overflow_cr0 |