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| author | Alasdair Armstrong | 2018-11-12 20:39:17 +0000 |
|---|---|---|
| committer | Alasdair Armstrong | 2018-11-12 20:39:17 +0000 |
| commit | 76d5e3227d529f6ef23a822e498b476e9bccae5c (patch) | |
| tree | 934dc9c304ea4c656c22c73ac903563eaf0deee3 /src/spec_analysis.ml | |
| parent | e5b80f77cb481938f6ddaab629e017083723a5c6 (diff) | |
Make type checker smarter at inferring l-expressions
Previously the following would fail:
```
default Order dec
$include <prelude.sail>
register V : vector(1, dec, vector(32, dec, bit))
val zeros : forall 'n, 'n >= 0. unit -> vector('n, dec, bit)
function main() : unit -> unit = {
V[0] = zeros()
}
```
Since the type-checker wouldn't see that zeros() must have type
`vector(32, dec, bit)` from the type of `V[0]`. It now tries both to
infer the expression, and use that to check the assignment, and if
that fails we infer the lexp to check the assignment. This pattern
occurs a lot in ASL, and we often had to patch zeros() to zeros(32) or
similar there.
Diffstat (limited to 'src/spec_analysis.ml')
0 files changed, 0 insertions, 0 deletions
