diff options
| author | Robert Norton | 2018-06-04 15:12:13 +0100 |
|---|---|---|
| committer | Robert Norton | 2018-06-04 15:12:27 +0100 |
| commit | a498df208e75ad0ae84c7697547600c221224316 (patch) | |
| tree | 39924fc9388ee7a16496a46a60f16df0fb12d21d /src/sail_lib.ml | |
| parent | 51f621e7e215c30fa9742f84f43de52dacc4aee0 (diff) | |
switch to using a Map data structure for cheri tags in ocaml backend. This solves a problem where the Hashtbl module was encountering a stack overflow booting CheriBSD. There seems to be little or no performance impact.
Diffstat (limited to 'src/sail_lib.ml')
| -rw-r--r-- | src/sail_lib.ml | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/src/sail_lib.ml b/src/sail_lib.ml index e4b5619c..afacf681 100644 --- a/src/sail_lib.ml +++ b/src/sail_lib.ml @@ -397,16 +397,14 @@ let rec bits_of_int bit n = let byte_of_int n = bits_of_int 128 n -module BigIntHash = - struct - type t = Big_int.num - let equal = Big_int.equal - let hash = Hashtbl.hash - end - -module RAM = Hashtbl.Make(BigIntHash) +module Mem = struct + include Map.Make(struct + type t = Big_int.num + let compare = Big_int.compare + end) +end -let mem_pages : Bytes.t RAM.t = RAM.create 256 +let mem_pages = (ref Mem.empty : (Bytes.t Mem.t) ref);; let page_shift_bits = 20 (* 1M page *) let page_size_bytes = 1 lsl page_shift_bits;; @@ -416,10 +414,10 @@ let bottom_addr_of_page p = Big_int.shift_left p page_shift_bits let top_addr_of_page p = Big_int.shift_left (Big_int.succ p) page_shift_bits let get_mem_page p = try - RAM.find mem_pages p + Mem.find p !mem_pages with Not_found -> let new_page = Bytes.create page_size_bytes in - RAM.add mem_pages p new_page; + mem_pages := Mem.add p new_page !mem_pages; new_page let rec add_mem_bytes addr buf off len = @@ -469,15 +467,15 @@ let read_ram (addr_size, data_size, hex_ram, addr) = Bytes.iter (fun byte -> vector := (byte_of_int (int_of_char byte)) @ !vector) bytes; !vector -let tag_ram : bool RAM.t = RAM.create 256 - +let tag_ram = (ref Mem.empty : (bool Mem.t) ref);; + let write_tag_bool (addr, tag) = let addri = uint addr in - RAM.add tag_ram addri tag + tag_ram := Mem.add addri tag !tag_ram let read_tag_bool addr = let addri = uint addr in - try RAM.find tag_ram addri with Not_found -> false + try Mem.find addri !tag_ram with Not_found -> false let rec reverse_endianness bits = if List.length bits <= 8 then bits else |
