summaryrefslogtreecommitdiff
path: root/src/sail_lib.ml
diff options
context:
space:
mode:
authorAlasdair2019-01-22 13:22:30 +0000
committerAlasdair2019-01-22 13:22:30 +0000
commit8c457ba46217978c1845ae9d6ebb0970e9b30cb9 (patch)
tree445a9343802e46ccdde81d77de60ff057899758a /src/sail_lib.ml
parent63a3cdcd18972cdc2b6fa24d6a2deb5cae7549cc (diff)
Make sure there is an ocaml representation for optimized memory read for
RISC-V
Diffstat (limited to 'src/sail_lib.ml')
-rw-r--r--src/sail_lib.ml7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/sail_lib.ml b/src/sail_lib.ml
index c0bf80fa..d1a21b73 100644
--- a/src/sail_lib.ml
+++ b/src/sail_lib.ml
@@ -508,6 +508,13 @@ let read_ram (addr_size, data_size, hex_ram, addr) =
Bytes.iter (fun byte -> vector := (byte_of_int (int_of_char byte)) @ !vector) bytes;
!vector
+let fast_read_ram (data_size, addr) =
+ let addr = uint addr in
+ let bytes = read_mem_bytes addr (Big_int.to_int data_size) in
+ let vector = ref [] in
+ Bytes.iter (fun byte -> vector := (byte_of_int (int_of_char byte)) @ !vector) bytes;
+ !vector
+
let tag_ram = (ref Mem.empty : (bool Mem.t) ref);;
let write_tag_bool (addr, tag) =