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| author | Alasdair Armstrong | 2018-07-24 18:09:18 +0100 |
|---|---|---|
| committer | Alasdair Armstrong | 2018-07-24 18:09:18 +0100 |
| commit | 6b4f407ad34ca7d4d8a89a5a4d401ac80c7413b0 (patch) | |
| tree | ed09b22b7ea4ca20fbcc89b761f1955caea85041 /src/sail_lib.ml | |
| parent | dafb09e7c26840dce3d522fef3cf359729ca5b61 (diff) | |
| parent | 8114501b7b956ee4a98fa8599c7efee62fc19206 (diff) | |
Merge remote-tracking branch 'origin/sail2' into c_fixes
Diffstat (limited to 'src/sail_lib.ml')
| -rw-r--r-- | src/sail_lib.ml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/sail_lib.ml b/src/sail_lib.ml index ab621342..16b1d3cc 100644 --- a/src/sail_lib.ml +++ b/src/sail_lib.ml @@ -419,7 +419,7 @@ let get_mem_page p = try Mem.find p !mem_pages with Not_found -> - let new_page = Bytes.create page_size_bytes in + let new_page = Bytes.make page_size_bytes '\000' in mem_pages := Mem.add p new_page !mem_pages; new_page @@ -457,7 +457,7 @@ let write_ram' (data_size, addr, data) = end let write_ram (addr_size, data_size, hex_ram, addr, data) = - write_ram' (data_size, uint addr, data) + write_ram' (data_size, uint addr, data); true let wram addr byte = let bytes = Bytes.make 1 (char_of_int byte) in |
