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authorShaked Flur2017-08-17 09:28:35 +0100
committerShaked Flur2017-08-17 09:28:35 +0100
commitc6d639e0f03053b905a9cb0ab6929f4efe6153f4 (patch)
tree95f10a5d765158bee2e7b108fc01f6a355350899 /src/lem_interp/sail_impl_base.lem
parente62c1e3615d1c0b54afcd88bf0938b92f1408f13 (diff)
fixed the RISC-V fences (3 types: "rw,rw"/"r,rw"/"rw,w")
Diffstat (limited to 'src/lem_interp/sail_impl_base.lem')
-rw-r--r--src/lem_interp/sail_impl_base.lem5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/lem_interp/sail_impl_base.lem b/src/lem_interp/sail_impl_base.lem
index 0cdeb414..cda6702c 100644
--- a/src/lem_interp/sail_impl_base.lem
+++ b/src/lem_interp/sail_impl_base.lem
@@ -465,6 +465,11 @@ type barrier_kind =
| Barrier_TM_COMMIT
(* MIPS barriers *)
| Barrier_MIPS_SYNC
+ (* RISC-V barriers *)
+ | Barrier_RISCV_rw_rw
+ | Barrier_RISCV_r_rw
+ | Barrier_RISCV_rw_w
+
instance (Show barrier_kind)
let show = function