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authorRobert Norton2017-04-07 16:53:31 +0100
committerRobert Norton2017-04-07 16:54:20 +0100
commit8ed0f4599e1edd018c061ef77975768f76a65578 (patch)
treeb4302b35fa16b5fad6a0ae03791e453dc6d36a3f /src/gen_lib
parent5892c5e2a3b8f528218f983e2b8ecab1af827ff0 (diff)
fix error in generated ocaml where writing single bit of register was not taking account of register direction.
Diffstat (limited to 'src/gen_lib')
-rw-r--r--src/gen_lib/sail_values.ml7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gen_lib/sail_values.ml b/src/gen_lib/sail_values.ml
index 19aa4709..aa3141ed 100644
--- a/src/gen_lib/sail_values.ml
+++ b/src/gen_lib/sail_values.ml
@@ -201,6 +201,13 @@ let set_vector_subrange_bit_big v n m new_v =
set_vector_subrange_bit_int v (int_of_big_int n) (int_of_big_int m) new_v
let set_vector_subrange_bit = set_vector_subrange_bit_int
+let set_register_bit_int reg n v =
+ match reg with
+ | Vregister(array,start,inc,fields) ->
+ (!array).(if inc then (n - start) else (start - n)) <- v
+ | _ -> failwith "set_register_bit of non-register"
+let set_register_bit_big reg n v = set_register_bit_int reg (int_of_big_int n) v
+let set_register_bit = set_register_bit_big
let set_register_field_v reg field new_v =
match reg with