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authorRobert Norton2018-02-02 16:59:22 +0000
committerRobert Norton2018-02-02 16:59:26 +0000
commit2ad42f91f4f13d6e57f76b17dc93785381d32066 (patch)
treed61e7fccfcbe53b49cc56e7741d715dee02a2a29 /src/gen_lib/sail_values.lem
parentf5723aebea8a0e22def3072710384f2410f65e46 (diff)
Add M extension to RISCV. Slightly inelegant implementation for now but passing tests.
Diffstat (limited to 'src/gen_lib/sail_values.lem')
-rw-r--r--src/gen_lib/sail_values.lem9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/gen_lib/sail_values.lem b/src/gen_lib/sail_values.lem
index 92ef7037..50dacf5e 100644
--- a/src/gen_lib/sail_values.lem
+++ b/src/gen_lib/sail_values.lem
@@ -69,12 +69,11 @@ let rec replace bs (n : integer) b' = match bs with
let upper n = n
+(* Modulus operation corresponding to quot below -- result
+ has sign of dividend. *)
let hardware_mod (a: integer) (b:integer) : integer =
- if a < 0 && b < 0
- then (abs a) mod (abs b)
- else if (a < 0 && b >= 0)
- then (a mod b) - b
- else a mod b
+ let m = (abs a) mod (abs b) in
+ if a < 0 then ~m else m
(* There are different possible answers for integer divide regarding
rounding behaviour on negative operands. Positive operands always