summaryrefslogtreecommitdiff
path: root/src/gen_lib/sail_operators.lem
diff options
context:
space:
mode:
authorThomas Bauereiss2017-10-19 15:14:28 +0100
committerThomas Bauereiss2017-10-19 15:41:28 +0100
commiteaa4a5efa3789efdb5eab4e60225becd5859d0e8 (patch)
treee5af527af85fef1d77e3272e877a4a0836387e42 /src/gen_lib/sail_operators.lem
parentc316e9f9741413219d4824a578bd294ef2561a97 (diff)
Make some potentially non-terminating library functions terminate
Diffstat (limited to 'src/gen_lib/sail_operators.lem')
-rw-r--r--src/gen_lib/sail_operators.lem4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gen_lib/sail_operators.lem b/src/gen_lib/sail_operators.lem
index b94257f0..cbc55367 100644
--- a/src/gen_lib/sail_operators.lem
+++ b/src/gen_lib/sail_operators.lem
@@ -144,7 +144,7 @@ let to_bin n = List.reverse (to_bin_aux n)
val pad_zero : list bitU -> integer -> list bitU
let rec pad_zero bits n =
- if n = 0 then bits else pad_zero (B0 :: bits) (n -1)
+ if n <= 0 then bits else pad_zero (B0 :: bits) (n -1)
let rec add_one_bit_ignore_overflow_aux bits = match bits with
@@ -439,7 +439,7 @@ let mod_VIV = arith_op_vec_range_no0 hardware_mod false 1
val repeat : forall 'a. list 'a -> integer -> list 'a
let rec repeat xs n =
- if n = 0 then []
+ if n <= 0 then []
else xs ++ repeat xs (n-1)
(* Assumes decreasing bit vectors *)