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authorBrian Campbell2017-10-25 12:19:08 +0100
committerBrian Campbell2017-10-25 12:19:08 +0100
commitd1d7f0ef16080200187230d9708155668af6edbf (patch)
tree505dce3dc7a2f3f4841909422d822b292ca91d9b /src/gen_lib/sail_operators.lem
parent05b00c86ee484a3e7f108f306e77ae200816a8ad (diff)
Avoid name clash in generated Lem
(complains due to added val spec)
Diffstat (limited to 'src/gen_lib/sail_operators.lem')
-rw-r--r--src/gen_lib/sail_operators.lem2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gen_lib/sail_operators.lem b/src/gen_lib/sail_operators.lem
index d9bf8454..524d7ef6 100644
--- a/src/gen_lib/sail_operators.lem
+++ b/src/gen_lib/sail_operators.lem
@@ -36,7 +36,7 @@ let norm_dec = reset_vector_start
let adjust_start_index (start, v) = set_vector_start (start, v)
let cast_vec_bool v = bitU_to_bool (extract_only_element v)
-let cast_bit_vec (start, len, b) = Vector (repeat [b] len) start false
+let cast_bit_vec_basic (start, len, b) = Vector (repeat [b] len) start false
let cast_boolvec_bitvec (Vector bs start inc) =
Vector (List.map bool_to_bitU bs) start inc