nicer lem output: no more unecessary 'unit' returns if if-expressions, for-loops or case-expressions also return updated variables

1 files changed, 6 insertions, 6 deletions

diff --git a/src/gen_lib/prompt.lem b/src/gen_lib/prompt.lem
index 4cd76156..a9aa3218 100644
--- a/src/gen_lib/prompt.lem
+++ b/src/gen_lib/prompt.lem
@@ -247,23 +247,23 @@ val write_reg_bitfield : forall 'e. register -> register_bitfield -> bit -> M 'e
 let write_reg_bitfield reg rbit = write_reg_bit reg (field_index_bit rbit)
 
 val foreachM_inc : forall 'e 'vars. (nat * nat * nat) -> 'vars ->
-                  (nat -> 'vars -> M 'e (unit * 'vars)) -> M 'e (unit * 'vars)
+                  (nat -> 'vars -> M 'e 'vars) -> M 'e 'vars
 let rec foreachM_inc (i,stop,by) vars body = 
   if i <= stop
   then
-    body i vars >>= fun (_,vars) ->
+    body i vars >>= fun vars ->
     foreachM_inc (i + by,stop,by) vars body
-  else return ((),vars)
+  else return vars
 
 
 val foreachM_dec : forall 'e 'vars. (nat * nat * nat) -> 'vars ->
-                  (nat -> 'vars -> M 'e (unit * 'vars)) -> M 'e (unit * 'vars)
+                  (nat -> 'vars -> M 'e 'vars) -> M 'e 'vars
 let rec foreachM_dec (i,stop,by) vars body = 
   if i >= stop
   then
-    body i vars >>= fun (_,vars) ->
+    body i vars >>= fun vars ->
     foreachM_dec (i - by,stop,by) vars body
-  else return ((),vars)
+  else return vars
 
 
 let write_two_regs r1 r2 vec =