diff options
| author | Christopher | 2015-12-09 17:16:02 +0000 |
|---|---|---|
| committer | Christopher | 2015-12-09 17:16:02 +0000 |
| commit | c78d27967766480138599da36f2f3bb20f7a01c9 (patch) | |
| tree | ad8420407f9cd63ef1989083c47000c9f4e34a8a /src/gen_lib/power_extras.lem | |
| parent | 3c709c896023b5952e5481311307ddecccfad83c (diff) | |
adapted for Kathy's lexp effect typing changes: register writes should be correct now, fixes, pp
Diffstat (limited to 'src/gen_lib/power_extras.lem')
| -rw-r--r-- | src/gen_lib/power_extras.lem | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/gen_lib/power_extras.lem b/src/gen_lib/power_extras.lem index f2941aff..8515a406 100644 --- a/src/gen_lib/power_extras.lem +++ b/src/gen_lib/power_extras.lem @@ -1,4 +1,5 @@ open import Pervasives +open import Vector open import State open import Sail_values @@ -33,3 +34,13 @@ let H_Sync () = return () let LW_Sync () = return () let EIEIO_Sync () = return () +let recalculate_dependency () = return () + +let trap () = () +(* this needs to change, but for that we'd have to make the type checker know about trap + * as an effect *) + +val countLeadingZeroes : vector bit * integer -> integer +let countLeadingZeroes (V bits _ _ ,n) = + let (_,bits) = List.splitAt (natFromInteger n) bits in + integerFromNat (List.length (takeWhile ((=) O) bits)) |
