Add snapshot of HOL4 output for CHERI and RISC-V

44 files changed, 27378 insertions, 0 deletions

diff --git a/snapshots/hol4/README.md b/snapshots/hol4/README.md
new file mode 100644
index 00000000..2a8208c9
--- /dev/null
+++ b/snapshots/hol4/README.md
@@ -0,0 +1,13 @@
+# Snapshot of HOL4 output for Sail CHERI and RISC-V models
+
+These theories are a snapshot of the generated files for the Sail
+CHERI and RISC-V models, translated to HOL4 via Lem.  These are all
+accepted by the current source repository version of HOL4 (from
+roughly 7th May 2018), although we have not done any further testing
+of them yet.
+
+They were generated using the `cheri-mono` branch of Sail, and the
+`hol-with-extra-types` branch of Lem, which currently contain some
+changes that are not yet ready of the main branches of these projects.
+
+11th May 2018.
diff --git a/snapshots/hol4/build b/snapshots/hol4/build
new file mode 100755
index 00000000..2b8be130
--- /dev/null
+++ b/snapshots/hol4/build
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do
+  (cd $d; Holmake)
+done
diff --git a/snapshots/hol4/clean b/snapshots/hol4/clean
new file mode 100755
index 00000000..f4301d3f
--- /dev/null
+++ b/snapshots/hol4/clean
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+for d in lem/hol-lib sail/lib/hol sail/cheri sail/riscv; do
+  (cd $d; Holmake cleanAll)
+done
diff --git a/snapshots/hol4/lem/hol-lib/Holmakefile b/snapshots/hol4/lem/hol-lib/Holmakefile
new file mode 100644
index 00000000..0d07567c
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/Holmakefile
@@ -0,0 +1,14 @@
+ifdef POLY
+HOLHEAP_NAME = lemheap
+EXTRA_CLEANS = $(HOLHEAP_NAME) $(HOLHEAP_NAME).o 
+
+BARE_DEPS = lemLib lemTheory lem_pervasivesTheory lem_pervasives_extraTheory lem_stringTheory lem_wordTheory
+DEPS = $(patsubst %,%.uo,$(BARE_DEPS))
+
+.PHONY: all
+all: $(HOLHEAP_NAME) 
+
+$(HOLHEAP_NAME): $(DEPS)
+	rm -f $(HOLHEAP_NAME)
+	$(protect $(HOLDIR)/bin/buildheap) -o $@ $(BARE_DEPS)
+endif
diff --git a/snapshots/hol4/lem/hol-lib/lemLib.sml b/snapshots/hol4/lem/hol-lib/lemLib.sml
new file mode 100644
index 00000000..93d06dc2
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lemLib.sml
@@ -0,0 +1,105 @@
+(*========================================================================*)
+(*                        Lem                                             *)
+(*                                                                        *)
+(*          Dominic Mulligan, University of Cambridge                     *)
+(*          Francesco Zappa Nardelli, INRIA Paris-Rocquencourt            *)
+(*          Gabriel Kerneis, University of Cambridge                      *)
+(*          Kathy Gray, University of Cambridge                           *)
+(*          Peter Boehm, University of Cambridge (while working on Lem)   *)
+(*          Peter Sewell, University of Cambridge                         *)
+(*          Scott Owens, University of Kent                               *)
+(*          Thomas Tuerk, University of Cambridge                         *)
+(*                                                                        *)
+(*  The Lem sources are copyright 2010-2013                               *)
+(*  by the UK authors above and Institut National de Recherche en         *)
+(*  Informatique et en Automatique (INRIA).                               *)
+(*                                                                        *)
+(*  All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli}   *)
+(*  are distributed under the license below.  The former are distributed  *)
+(*  under the LGPLv2, as in the LICENSE file.                             *)
+(*                                                                        *)
+(*                                                                        *)
+(*  Redistribution and use in source and binary forms, with or without    *)
+(*  modification, are permitted provided that the following conditions    *)
+(*  are met:                                                              *)
+(*  1. Redistributions of source code must retain the above copyright     *)
+(*  notice, this list of conditions and the following disclaimer.         *)
+(*  2. Redistributions in binary form must reproduce the above copyright  *)
+(*  notice, this list of conditions and the following disclaimer in the   *)
+(*  documentation and/or other materials provided with the distribution.  *)
+(*  3. The names of the authors may not be used to endorse or promote     *)
+(*  products derived from this software without specific prior written    *)
+(*  permission.                                                           *)
+(*                                                                        *)
+(*  THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS    *)
+(*  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED     *)
+(*  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE    *)
+(*  ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY       *)
+(*  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL    *)
+(*  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     *)
+(*  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS         *)
+(*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER  *)
+(*  IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR       *)
+(*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN   *)
+(*  IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                         *)
+(*========================================================================*)
+
+
+structure lemLib =
+struct
+
+open HolKernel Parse boolLib bossLib;
+open lemTheory intReduce wordsLib;
+
+val run_interactive = ref false
+val lem_conv_eval = computeLib.EVAL_CONV
+val lem_conv_simp = SIMP_CONV (srw_ss()++permLib.PERM_ss) [] 
+
+
+val lem_convs = [lem_conv_eval, lem_conv_simp];
+
+
+datatype test_result =
+    Success
+  | Fail
+  | Unknown of term
+
+
+fun lem_run_single_test (t:term) conv = 
+case total conv t of
+    NONE => NONE
+  | SOME thm => 
+      if (can EQT_ELIM thm) then SOME Success else
+      if (can EQF_ELIM thm) then SOME Fail else
+      NONE
+;
+
+fun lem_run_test t = 
+  case Lib.get_first (lem_run_single_test t) lem_convs of
+      NONE => Unknown (rhs (concl (EVAL t)))
+    | SOME r => r
+
+
+fun lem_assertion s t =
+let
+    open PPBackEnd Parse;
+    fun terminal_print sty s = (if !run_interactive then print_with_style sty s else
+      Lib.with_flag (Parse.current_backend, PPBackEnd.vt100_terminal) (print_with_style sty) s);
+    val _ = print "Testing ";
+    val _ = terminal_print [FG LightBlue] s;
+    val _ = print ": ``";
+    val _ = print_term t;
+    val _ = print ("`` ");
+    val result = lem_run_test t;
+    val _ = case result of
+                Success => terminal_print [FG Green] "OK\n"
+              | Fail => (terminal_print [FG OrangeRed] "FAILED\n";
+                         if (not (!run_interactive)) then Process.exit Process.failure else ())
+              | Unknown t => (terminal_print [FG Yellow] "evaluation failed\n")
+(*                            print_term t;
+                              print "\n\n"*) 
+in
+    ()
+end;
+
+end
diff --git a/snapshots/hol4/lem/hol-lib/lemScript.sml b/snapshots/hol4/lem/hol-lib/lemScript.sml
new file mode 100644
index 00000000..d6bb1bc8
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lemScript.sml
@@ -0,0 +1,284 @@
+(*========================================================================*)
+(*                        Lem                                             *)
+(*                                                                        *)
+(*          Dominic Mulligan, University of Cambridge                     *)
+(*          Francesco Zappa Nardelli, INRIA Paris-Rocquencourt            *)
+(*          Gabriel Kerneis, University of Cambridge                      *)
+(*          Kathy Gray, University of Cambridge                           *)
+(*          Peter Boehm, University of Cambridge (while working on Lem)   *)
+(*          Peter Sewell, University of Cambridge                         *)
+(*          Scott Owens, University of Kent                               *)
+(*          Thomas Tuerk, University of Cambridge                         *)
+(*                                                                        *)
+(*  The Lem sources are copyright 2010-2013                               *)
+(*  by the UK authors above and Institut National de Recherche en         *)
+(*  Informatique et en Automatique (INRIA).                               *)
+(*                                                                        *)
+(*  All files except ocaml-lib/pmap.{ml,mli} and ocaml-libpset.{ml,mli}   *)
+(*  are distributed under the license below.  The former are distributed  *)
+(*  under the LGPLv2, as in the LICENSE file.                             *)
+(*                                                                        *)
+(*                                                                        *)
+(*  Redistribution and use in source and binary forms, with or without    *)
+(*  modification, are permitted provided that the following conditions    *)
+(*  are met:                                                              *)
+(*  1. Redistributions of source code must retain the above copyright     *)
+(*  notice, this list of conditions and the following disclaimer.         *)
+(*  2. Redistributions in binary form must reproduce the above copyright  *)
+(*  notice, this list of conditions and the following disclaimer in the   *)
+(*  documentation and/or other materials provided with the distribution.  *)
+(*  3. The names of the authors may not be used to endorse or promote     *)
+(*  products derived from this software without specific prior written    *)
+(*  permission.                                                           *)
+(*                                                                        *)
+(*  THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS    *)
+(*  OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED     *)
+(*  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE    *)
+(*  ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY       *)
+(*  DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL    *)
+(*  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     *)
+(*  GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS         *)
+(*  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER  *)
+(*  IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR       *)
+(*  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN   *)
+(*  IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                         *)
+(*========================================================================*)
+
+open finite_mapTheory finite_mapLib
+open HolKernel Parse boolLib bossLib;
+open pred_setSimps pred_setTheory
+open finite_mapTheory
+open set_relationTheory
+open integerTheory intReduce quantHeuristicsLib;
+open wordsTheory
+
+val _ = numLib.prefer_num();
+
+(* From BasicProvers, for compatibility with older versions of HOL *)
+fun subgoal q = Q.SUBGOAL_THEN q STRIP_ASSUME_TAC
+
+val _ = new_theory "lem"
+
+val failwith_def = Define `failwith (s:'a) = (ARB:'b)`;
+
+val set_CASE_def = zDefine `
+  set_CASE s c_emp c_sing c_else =
+    (if s = {} then c_emp else (
+     if (FINITE s /\ (CARD s = 1)) then c_sing (CHOICE s) else
+     c_else))`
+
+val set_CASE_emp = prove ( 
+``!c_emp c_sing c_else. set_CASE {} c_emp c_sing c_else = c_emp``,
+  SIMP_TAC std_ss [set_CASE_def])
+
+
+
+val set_CASE_sing = prove (
+``!x c_emp c_sing c_else. set_CASE {x} c_emp c_sing c_else = c_sing x``,
+  SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def])
+
+
+val set_CASE_infinite = prove (``~(FINITE s) ==> (set_CASE s c_emp c_sing c_else = c_else)``,
+REPEAT STRIP_TAC THEN
+`~ (s = {})` by METIS_TAC [FINITE_EMPTY] THEN
+ASM_SIMP_TAC (std_ss++PRED_SET_ss) [set_CASE_def])
+
+val set_CASE_else_two_elems = store_thm ("set_CASE_else_two_elems",
+``(x1 IN s /\ x2 IN s /\ ~(x1 = x2)) ==>
+  (set_CASE s c_emp c_sing c_else = c_else)``,
+
+REPEAT STRIP_TAC THEN
+Tactical.REVERSE (Cases_on `FINITE s`) THEN1 (
+  ASM_SIMP_TAC std_ss [set_CASE_infinite]
+) THEN
+
+`~(s = {})` by (PROVE_TAC [MEMBER_NOT_EMPTY]) THEN
+
+subgoal `2 <= CARD s` THEN1 (
+  `CARD {x1; x2} = 2` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN
+  `{x1; x2} SUBSET s` by ASM_SIMP_TAC (std_ss++PRED_SET_ss) [] THEN
+  PROVE_TAC [CARD_SUBSET]
+) THEN
+
+ASM_SIMP_TAC arith_ss [set_CASE_def]);
+
+
+val set_CASE_else_1 = prove (``~(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = c_else)``,
+REPEAT STRIP_TAC THEN
+MATCH_MP_TAC set_CASE_else_two_elems THEN
+ASM_SIMP_TAC (std_ss++PRED_SET_ss) [])
+
+
+val set_CASE_else_2 = prove (``(x1 = x2) ==> (set_CASE (x1 INSERT (x2 INSERT s)) c_emp c_sing c_else = set_CASE (x2 INSERT s) c_emp c_sing c_else)``,
+SIMP_TAC (std_ss++PRED_SET_ss) [])
+
+
+val set_CASE_REWRITES = save_thm ("set_CASE_REWRITES",
+  LIST_CONJ (map GEN_ALL [set_CASE_emp, set_CASE_sing, set_CASE_else_1, set_CASE_else_2, set_CASE_infinite]));
+
+val _ = export_rewrites ["set_CASE_REWRITES"]
+
+
+val set_CASE_compute = store_thm ("set_CASE_compute", ``
+   (!c_sing c_emp c_else. set_CASE {} c_emp c_sing c_else = c_emp) /\
+   (!x c_sing c_emp c_else.
+      set_CASE {x} c_emp c_sing c_else = c_sing x) /\
+   (!x2 x1 s c_sing c_emp c_else.
+      x1 <> x2 ==>
+      (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else =
+       c_else)) /\
+   (!x2 x1 s c_sing c_emp c_else.
+      (set_CASE (x1 INSERT x2 INSERT s) c_emp c_sing c_else =
+       if (x1 = x2) then set_CASE (x2 INSERT s) c_emp c_sing c_else else c_else))``,
+METIS_TAC[set_CASE_REWRITES]);
+
+
+val SET_FILTER_def = zDefine `
+ (SET_FILTER P s = ({e | e | (e IN s) /\ P e}))`;
+
+val SET_FILTER_REWRITES = store_thm ("SET_FILTER_REWRITES",``
+  (!P. (SET_FILTER P {} = {})) /\
+  (!P x s. P x ==> (SET_FILTER P (x INSERT s) = x INSERT (SET_FILTER P s))) /\
+  (!P x s. (~(P x) ==> (SET_FILTER P (x INSERT s) = SET_FILTER P s)))``,
+
+SIMP_TAC (std_ss++PRED_SET_ss) [SET_FILTER_def, EXTENSION] THEN
+METIS_TAC[])
+
+val _ = export_rewrites ["SET_FILTER_REWRITES"]
+
+
+val SET_FILTER_compute = store_thm ("SET_FILTER_compute",``
+  (!P. (SET_FILTER P {} = {})) /\
+  (!P x s. (SET_FILTER P (x INSERT s) = if P x then 
+        x INSERT (SET_FILTER P s) else (SET_FILTER P s)))``,
+METIS_TAC [SET_FILTER_REWRITES])
+
+
+val _ = computeLib.add_persistent_funs ["set_CASE_compute", "SET_FILTER_compute"]
+
+
+val SET_SIGMA_def = zDefine 
+  `SET_SIGMA P Q = { (x, y) | x IN P /\ y IN Q x }`;
+
+val SET_SIGMA_EMPTY = store_thm(
+  "SET_SIGMA_EMPTY",
+  ``!Q. SET_SIGMA {} Q = {}``,
+  SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION]);
+val _ = export_rewrites ["SET_SIGMA_EMPTY"]
+val _ = computeLib.add_persistent_funs ["SET_SIGMA_EMPTY"]
+
+val SET_SIGMA_INSERT_LEFT = store_thm(
+  "SET_SIGMA_INSERT_LEFT",
+  ``!P Q x. SET_SIGMA (x INSERT P) Q = 
+     (IMAGE (\y. (x, y)) (Q x)) UNION (SET_SIGMA P Q)``,
+  SIMP_TAC (std_ss++PRED_SET_ss) [SET_SIGMA_def, EXTENSION] THEN
+  METIS_TAC[])
+val _ = export_rewrites ["SET_SIGMA_INSERT_LEFT"]
+val _ = computeLib.add_persistent_funs ["SET_SIGMA_INSERT_LEFT"]
+
+
+val _ = computeLib.add_persistent_funs ["list.LIST_TO_SET"]
+
+
+val FMAP_TO_SET_def = zDefine 
+  `FMAP_TO_SET m = IMAGE (\k. (k, FAPPLY m k)) (FDOM m)`;
+
+val FMAP_TO_SET_FEMPTY = store_thm ("FMAP_TO_SET_FEMPTY",
+  ``FMAP_TO_SET FEMPTY = {}``,
+SIMP_TAC std_ss [FMAP_TO_SET_def, FDOM_FEMPTY, IMAGE_EMPTY]);
+val _ = export_rewrites ["FMAP_TO_SET_FEMPTY"]
+val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FEMPTY"]
+
+val FMAP_TO_SET_FUPDATE = store_thm ("FMAP_TO_SET_FUPDATE",
+  ``FMAP_TO_SET (FUPDATE m (k, v)) = (k, v) INSERT (FMAP_TO_SET (m \\ k))``,
+SIMP_TAC (std_ss ++ PRED_SET_ss) [FMAP_TO_SET_def, FDOM_FUPDATE, FAPPLY_FUPDATE_THM, EXTENSION,
+  FDOM_DOMSUB, DOMSUB_FAPPLY_THM] THEN
+METIS_TAC[]);
+val _ = export_rewrites ["FMAP_TO_SET_FUPDATE"]
+val _ = computeLib.add_persistent_funs ["FMAP_TO_SET_FUPDATE"]
+
+
+val IN_FMAP_TO_SET = store_thm ("IN_FMAP_TO_SET",
+  ``(k, v) IN FMAP_TO_SET m = (FLOOKUP m k = SOME v)``,
+SIMP_TAC (std_ss++PRED_SET_ss) [FMAP_TO_SET_def, FLOOKUP_DEF] THEN
+METIS_TAC[optionTheory.option_CLAUSES])
+
+val FUPDATE_NEQ_FEMPTY = store_thm ("FUPDATE_NEQ_FEMPTY", ``(FUPDATE m (k, v) = FEMPTY) = F``,
+  SIMP_TAC (std_ss++PRED_SET_ss) [fmap_EXT, FDOM_FUPDATE, FDOM_FEMPTY])
+val _ = export_rewrites ["FUPDATE_NEQ_FEMPTY"]
+val _ = computeLib.add_persistent_funs ["FUPDATE_NEQ_FEMPTY"]
+
+val FUPDATE_EQ_FUPDATE = store_thm ("FUPDATE_EQ_FUPDATE", 
+  ``(FUPDATE m (k, v) = FUPDATE m' (k', v')) = 
+    (k IN FDOM (FUPDATE m' (k', v')) /\
+     (FUPDATE m' (k', v') ' k = v) /\
+     (m \\ k = (FUPDATE m' (k', v') \\ k))) ``,
+
+  EQ_TAC THEN STRIP_TAC THEN1 (
+     POP_ASSUM (ASSUME_TAC o GSYM) THEN
+     ASM_REWRITE_TAC [] THEN
+     SIMP_TAC std_ss [FDOM_FUPDATE, IN_INSERT, FAPPLY_FUPDATE, DOMSUB_FUPDATE]
+  ) THEN
+  FULL_SIMP_TAC std_ss [fmap_EXT, EXTENSION, FDOM_DOMSUB, IN_DELETE, FDOM_FUPDATE, IN_INSERT,
+     DOMSUB_FAPPLY_THM, FAPPLY_FUPDATE_THM] THEN
+  METIS_TAC[]
+)
+
+val _ = export_rewrites ["FUPDATE_EQ_FUPDATE"]
+val _ = computeLib.add_persistent_funs ["FUPDATE_EQ_FUPDATE"]
+
+
+val FEVERY_FUPDATE_DOMSUB = store_thm ("FEVERY_FUPDATE_DOMSUB",
+  ``(FEVERY P (FUPDATE m (k, v))) = (P (k, v) /\ FEVERY P (m \\ k))``,
+SIMP_TAC std_ss [FEVERY_FUPDATE, fmap_domsub]);
+
+val _ = computeLib.add_persistent_funs ["finite_map.FRANGE_FEMPTY", "finite_map.FRANGE_FUPDATE_DOMSUB", 
+  "finite_map.FEVERY_FEMPTY", "FEVERY_FUPDATE_DOMSUB"]
+
+val _ = computeLib.add_persistent_funs ["finite_map.o_f_FUPDATE", "finite_map.o_f_FEMPTY", 
+   "finite_map.FCARD_FEMPTY", "finite_map.FCARD_FUPDATE"]
+
+
+
+
+
+val rcomp_empty_1 = store_thm ("rcomp_empty_1",
+  ``({} OO r) = {}``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION])
+
+val rcomp_empty_2 = store_thm ("rcomp_empty_2",
+  ``(r OO {}) = {}``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss) [rcomp_def, EXTENSION])
+
+val rcomp_insert_compute = store_thm ("rcomp_insert_compute",
+  ``(r1 OO ((x, y) INSERT r2)) = ((r1 OO r2) UNION (IMAGE (\ xy'. (FST xy', y)) (SET_FILTER (\ xy'. SND xy' = x) r1)))``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rcomp_def, EXTENSION, SET_FILTER_def] THEN
+METIS_TAC[])
+
+val _ = computeLib.add_persistent_funs ["rcomp_insert_compute", "rcomp_empty_1", "rcomp_empty_2"]
+
+
+val rrestrict_eval = store_thm ("rrestrict_eval",
+  ``rrestrict r s = SET_FILTER (\ (x, y). x IN s /\ y IN s) r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++quantHeuristicsLib.QUANT_INST_ss [std_qp]) [rrestrict_def, EXTENSION, SET_FILTER_def])
+
+val domain_eval = store_thm ("domain_eval",
+  ``domain r = IMAGE FST r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [domain_def, EXTENSION])
+
+val range_eval = store_thm ("range_eval",
+  ``range r = IMAGE SND r``,
+SIMP_TAC (std_ss++pred_setSimps.PRED_SET_ss++QUANT_INST_ss [std_qp]) [range_def, EXTENSION])
+
+val _ = computeLib.add_persistent_funs ["rrestrict_eval", "domain_eval", "range_eval"]
+
+val w2int_def = Define `w2int (w : 'a word) = 
+  let i1 = (w2n w) in
+  let i2 = (INT_MAX (:'a)) in
+  if i1 > i2 then (int_of_num i1 - (int_of_num (UINT_MAX (:'a)))) - 1 else int_of_num i1`
+
+val w2ui_def = Define `w2ui (w : 'a word) = int_of_num (w2n w)`
+
+val _ = Define `MAP_TO_LIST m = SET_TO_LIST (\(x, y). FAPPLY m x = y)`
+
+val _ = export_theory()
diff --git a/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml
new file mode 100644
index 00000000..7ef74237
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_assert_extraScript.sml
@@ -0,0 +1,46 @@
+(*Generated by Lem from assert_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open stringTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_assert_extra"
+
+
+(*open import {ocaml} `Xstring`*)
+(*open import {hol} `stringTheory` `lemTheory`*)
+(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ------------------------------------ *)
+(* failing with a proper error message  *)
+(* ------------------------------------ *)
+
+(*val failwith: forall 'a. string -> 'a*)
+
+(* ------------------------------------ *)
+(* failing without an error message     *)
+(* ------------------------------------ *)
+
+(*val fail : forall 'a. 'a*)
+val _ = Define `
+ ((fail:'a)=  (failwith "fail"))`;
+
+
+(* ------------------------------------- *)
+(* assertions                            *)
+(* ------------------------------------- *)
+
+(*val ensure : bool -> string -> unit*)
+val _ = Define `
+ ((ensure:bool -> string -> unit) test msg=  
+ (if test then
+    () 
+  else
+    failwith msg))`;
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml
new file mode 100644
index 00000000..eba5f169
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_basic_classesScript.sml
@@ -0,0 +1,504 @@
+(*Generated by Lem from basic_classes.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_basic_classes"
+
+(******************************************************************************)
+(* Basic Type Classes                                                         *)
+(******************************************************************************)
+
+(*open import Bool*) 
+
+(*open import {coq} `Coq.Strings.Ascii`*)
+
+(* ========================================================================== *)
+(* Equality                                                                   *)
+(* ========================================================================== *)
+
+(* Lem`s default equality (=) is defined by the following type-class Eq.
+   This typeclass should define equality on an abstract datatype 'a. It should
+   always coincide with the default equality of Coq, HOL and Isabelle.
+   For OCaml, it might be different, since abstract datatypes like sets
+   might have fancy equalities. *)
+
+(*class ( Eq 'a ) 
+  val = [isEqual] : 'a -> 'a -> bool
+  val <> [isInequal] : 'a -> 'a -> bool
+end*)
+
+
+(* (=) should for all instances be an equivalence relation 
+   The isEquivalence predicate of relations could be used here.
+   However, this would lead to a cyclic dependency. *)
+
+(* TODO: add later, once lemmata can be assigned to classes 
+lemma eq_equiv: ((forall x. (x = x)) &&
+                 (forall x y. (x = y) <-> (y = x)) &&
+                 (forall x y z. ((x = y) && (y = z)) --> (x = z)))
+*)
+
+(* Structural equality *)
+
+(* Sometimes, it is also handy to be able to use structural equality.
+   This equality is mapped to the build-in equality of backends. This equality
+   differs significantly for each backend. For example, OCaml can`t check equality
+   of function types, whereas HOL can.  When using structural equality, one should 
+   know what one is doing. The only guarentee is that is behaves like 
+   the native backend equality.
+
+   A lengthy name for structural equality is used to discourage its direct use.
+   It also ensures that users realise it is unsafe (e.g. OCaml can`t check two functions
+   for equality *)
+(*val unsafe_structural_equality : forall 'a. 'a -> 'a -> bool*)
+
+(*val unsafe_structural_inequality : forall 'a. 'a -> 'a -> bool*)
+(*let unsafe_structural_inequality x y=  not (unsafe_structural_equality x y)*)
+
+
+(* ========================================================================== *)
+(* Orderings                                                                  *)
+(* ========================================================================== *)
+
+(* The type-class Ord represents total orders (also called linear orders) *)
+val _ = Hol_datatype `
+ ordering = LT | EQ | GT`;
+
+
+val _ = Define `
+ ((orderingIsLess:ordering -> bool) LT=        T)
+/\ ((orderingIsLess:ordering -> bool) _=        F)`;
+
+val _ = Define `
+ ((orderingIsGreater:ordering -> bool) GT=     T)
+/\ ((orderingIsGreater:ordering -> bool) _=     F)`;
+
+val _ = Define `
+ ((orderingIsEqual:ordering -> bool) EQ=       T)
+/\ ((orderingIsEqual:ordering -> bool) _=       F)`;
+
+
+val _ = Define `
+ ((ordering_cases:ordering -> 'a -> 'a -> 'a -> 'a) r lt eq gt=  
+ (if orderingIsLess r then lt else
+  if orderingIsEqual r then eq else gt))`;
+
+
+
+(*val orderingEqual : ordering -> ordering -> bool*)
+
+val _ = Hol_datatype `
+(*  'a *) Ord_class= <| 
+  compare_method                 : 'a -> 'a -> ordering;
+  isLess_method         : 'a -> 'a -> bool;
+  isLessEqual_method    : 'a -> 'a -> bool;
+  isGreater_method      : 'a -> 'a -> bool;
+  isGreaterEqual_method : 'a -> 'a -> bool 
+|>`;
+
+
+
+(* Ocaml provides default, polymorphic compare functions. Let's use them
+   as the default. However, because used perhaps in a typeclass they must be 
+   defined for all targets. So, explicitly declare them as undefined for
+   all other targets. If explictly declare undefined, the type-checker won't complain and
+   an error will only be raised when trying to actually output the function for a certain
+   target. *)
+(*val defaultCompare   : forall 'a. 'a -> 'a -> ordering*)
+(*val defaultLess      : forall 'a. 'a -> 'a -> bool*)
+(*val defaultLessEq    : forall 'a. 'a -> 'a -> bool*)
+(*val defaultGreater   : forall 'a. 'a -> 'a -> bool*)
+(*val defaultGreaterEq : forall 'a. 'a -> 'a -> bool*) 
+
+
+val _ = Define `
+ ((genericCompare:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a -> 'a -> ordering) (less: 'a -> 'a -> bool) (equal: 'a -> 'a -> bool) (x : 'a) (y : 'a)=  
+ (if less x y then
+    LT
+  else if equal x y then
+    EQ
+  else
+    GT))`;
+
+
+
+(*
+(* compare should really be a total order *)
+lemma ord_OK_1: (
+  (forall x y. (compare x y = EQ) <-> (compare y x = EQ)) &&
+  (forall x y. (compare x y = LT) <-> (compare y x = GT)))
+
+lemma ord_OK_2: (
+  (forall x y z. (x <= y) && (y <= z) --> (x <= z)) &&
+  (forall x y. (x <= y) || (y <= x))
+)
+*)
+
+(* let's derive a compare function from the Ord type-class *)
+(*val ordCompare : forall 'a. Eq 'a, Ord 'a => 'a -> 'a -> ordering*)
+val _ = Define `
+ ((ordCompare:'a Ord_class -> 'a -> 'a -> ordering)dict_Basic_classes_Ord_a x y=  
+ (if ( dict_Basic_classes_Ord_a.isLess_method x y) then LT else
+  if (x = y) then EQ else GT))`;
+
+
+val _ = Hol_datatype `
+(*  'a *) OrdMaxMin_class= <| 
+  max_method : 'a -> 'a -> 'a;
+  min_method : 'a -> 'a -> 'a
+|>`;
+
+
+(*val minByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((minByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y=  (if (le x y) then x else y))`;
+
+
+(*val maxByLessEqual : forall 'a. ('a -> 'a -> bool) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((maxByLessEqual:('a -> 'a -> bool) -> 'a -> 'a -> 'a) le x y=  (if (le y x) then x else y))`;
+
+
+(*val defaultMax : forall 'a. Ord 'a => 'a -> 'a -> 'a*)
+
+(*val defaultMin : forall 'a. Ord 'a => 'a -> 'a -> 'a*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_var_dict:'a Ord_class -> 'a OrdMaxMin_class)dict_Basic_classes_Ord_a= (<|
+
+  max_method := (maxByLessEqual  
+  dict_Basic_classes_Ord_a.isLessEqual_method);
+
+  min_method := (minByLessEqual  
+  dict_Basic_classes_Ord_a.isLessEqual_method)|>))`;
+
+
+
+(* ========================================================================== *)
+(* SetTypes                                                                   *)
+(* ========================================================================== *)
+
+(* Set implementations use often an order on the elements. This allows the OCaml implementation
+   to use trees for implementing them. At least, one needs to be able to check equality on sets.
+   One could use the Ord type-class for sets. However, defining a special typeclass is cleaner
+   and allows more flexibility. One can make e.g. sure, that this type-class is ignored for
+   backends like HOL or Isabelle, which don't need it. Moreover, one is not forced to also instantiate
+   the functions "<", "<=" ... *)
+
+(*class ( SetType 'a ) 
+  val {ocaml;coq} setElemCompare : 'a -> 'a -> ordering
+end*)
+
+val _ = Define `
+ ((boolCompare:bool -> bool -> ordering) T T=  EQ)
+/\ ((boolCompare:bool -> bool -> ordering) T F=  GT)
+/\ ((boolCompare:bool -> bool -> ordering) F T=  LT)
+/\ ((boolCompare:bool -> bool -> ordering) F F=  EQ)`;
+
+
+(* strings *)
+
+(*val charEqual : char -> char -> bool*)
+
+(*val stringEquality : string -> string -> bool*)
+
+(* pairs *)
+
+(*val pairEqual : forall 'a 'b. Eq 'a, Eq 'b => ('a * 'b) -> ('a * 'b) -> bool*)
+(*let pairEqual (a1, b1) (a2, b2)=  (a1 = a2) && (b1 = b2)*)
+
+(*val pairEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> ('a * 'b) -> ('a * 'b) -> bool*)
+
+(*val pairCompare : forall 'a 'b. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('a * 'b) -> ('a * 'b) -> ordering*)
+val _ = Define `
+ ((pairCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) -> 'a#'b -> 'a#'b -> ordering) cmpa cmpb (a1, b1) (a2, b2)=  
+ ((case cmpa a1 a2 of
+      LT => LT
+    | GT => GT
+    | EQ => cmpb b1 b2
+  )))`;
+
+
+val _ = Define `
+ ((pairLess:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)=  (( 
+  dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLess_method x2 y2))))`;
+
+val _ = Define `
+ ((pairLessEq:'a Ord_class -> 'b Ord_class -> 'b#'a -> 'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b (x1, x2) (y1, y2)=  (( 
+  dict_Basic_classes_Ord_b.isLess_method x1 y1) \/ (( dict_Basic_classes_Ord_b.isLessEqual_method x1 y1) /\ ( dict_Basic_classes_Ord_a.isLessEqual_method x2 y2))))`;
+
+
+val _ = Define `
+ ((pairGreater:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12=  (pairLess 
+  dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`;
+
+val _ = Define `
+ ((pairGreaterEq:'a Ord_class -> 'b Ord_class -> 'a#'b -> 'a#'b -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b x12 y12=  (pairLessEq 
+  dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12 x12))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup2_dict:'a Ord_class -> 'b Ord_class ->('a#'b)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b= (<|
+
+  compare_method := (pairCompare  
+  dict_Basic_classes_Ord_a.compare_method  dict_Basic_classes_Ord_b.compare_method);
+
+  isLess_method := 
+  (pairLess dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+  isLessEqual_method := 
+  (pairLessEq dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+  isGreater_method := 
+  (pairGreater dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b);
+
+  isGreaterEqual_method := 
+  (pairGreaterEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b)|>))`;
+
+
+
+(* triples *)
+
+(*val tripleEqual : forall 'a 'b 'c. Eq 'a, Eq 'b, Eq 'c => ('a * 'b * 'c) -> ('a * 'b * 'c) -> bool*)
+(*let tripleEqual (x1, x2, x3) (y1, y2, y3)=  ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, x3)) (y1, (y2, y3)))*)
+
+(*val tripleCompare : forall 'a 'b 'c. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) -> ('a * 'b * 'c) -> ('a * 'b * 'c) -> ordering*)
+val _ = Define `
+ ((tripleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) -> 'a#'b#'c -> 'a#'b#'c -> ordering) cmpa cmpb cmpc (a1, b1, c1) (a2, b2, c2)=  
+ (pairCompare cmpa (pairCompare cmpb cmpc) (a1, (b1, c1)) (a2, (b2, c2))))`;
+
+
+val _ = Define `
+ ((tripleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)=  (pairLess 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`;
+
+val _ = Define `
+ ((tripleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'a#'b#'c -> 'a#'b#'c -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c (x1, x2, x3) (y1, y2, y3)=  (pairLessEq 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c) dict_Basic_classes_Ord_a (x1, (x2, x3)) (y1, (y2, y3))))`;
+
+
+val _ = Define `
+ ((tripleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123=  (tripleLess 
+  dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`;
+
+val _ = Define `
+ ((tripleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'c#'b#'a -> 'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c x123 y123=  (tripleLessEq 
+  dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123 x123))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup3_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class ->('a#'b#'c)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c= (<|
+
+  compare_method := (tripleCompare  
+  dict_Basic_classes_Ord_a.compare_method  dict_Basic_classes_Ord_b.compare_method  dict_Basic_classes_Ord_c.compare_method);
+
+  isLess_method := 
+  (tripleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c);
+
+  isLessEqual_method := 
+  (tripleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c);
+
+  isGreater_method := 
+  (tripleGreater dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_a);
+
+  isGreaterEqual_method := 
+  (tripleGreaterEq dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_a)|>))`;
+
+
+(* quadruples *)
+
+(*val quadrupleEqual : forall 'a 'b 'c 'd. Eq 'a, Eq 'b, Eq 'c, Eq 'd => ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> bool*)
+(*let quadrupleEqual (x1, x2, x3, x4) (y1, y2, y3, y4)=  ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4))))*)
+
+(*val quadrupleCompare : forall 'a 'b 'c 'd. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+                                              ('d -> 'd -> ordering) -> ('a * 'b * 'c * 'd) -> ('a * 'b * 'c * 'd) -> ordering*)
+val _ = Define `
+ ((quadrupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> ordering) cmpa cmpb cmpc cmpd (a1, b1, c1, d1) (a2, b2, c2, d2)=  
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc cmpd)) (a1, (b1, (c1, d1))) (a2, (b2, (c2, d2)))))`;
+
+
+val _ = Define `
+ ((quadrupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)=  (pairLess 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`;
+
+val _ = Define `
+ ((quadrupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'a#'b#'c#'d -> 'a#'b#'c#'d -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d (x1, x2, x3, x4) (y1, y2, y3, y4)=  (pairLessEq 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        dict_Basic_classes_Ord_d)) dict_Basic_classes_Ord_a (x1, (x2, (x3, x4))) (y1, (y2, (y3, y4)))))`;
+
+
+val _ = Define `
+ ((quadrupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234=  (quadrupleLess 
+  dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`;
+
+val _ = Define `
+ ((quadrupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'd#'c#'b#'a -> 'd#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d x1234 y1234=  (quadrupleLessEq 
+  dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y1234 x1234))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup4_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class ->('a#'b#'c#'d)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d= (<|
+
+  compare_method := (quadrupleCompare  
+  dict_Basic_classes_Ord_a.compare_method  dict_Basic_classes_Ord_b.compare_method  dict_Basic_classes_Ord_c.compare_method  dict_Basic_classes_Ord_d.compare_method);
+
+  isLess_method := 
+  (quadrupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d);
+
+  isLessEqual_method := 
+  (quadrupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d);
+
+  isGreater_method := 
+  (quadrupleGreater dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+     dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+  isGreaterEqual_method := 
+  (quadrupleGreaterEq dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+     dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`;
+
+
+(* quintuples *)
+
+(*val quintupleEqual : forall 'a 'b 'c 'd 'e. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e => ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> bool*)
+(*let quintupleEqual (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)=  ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5)))))*)
+
+(*val quintupleCompare : forall 'a 'b 'c 'd 'e. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+                                              ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('a * 'b * 'c * 'd * 'e) -> ('a * 'b * 'c * 'd * 'e) -> ordering*)
+val _ = Define `
+ ((quintupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> ordering) cmpa cmpb cmpc cmpd cmpe (a1, b1, c1, d1, e1) (a2, b2, c2, d2, e2)=  
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd cmpe))) (a1, (b1, (c1, (d1, e1)))) (a2, (b2, (c2, (d2, e2))))))`;
+
+
+val _ = Define `
+ ((quintupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)=  (pairLess 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+           dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`;
+
+val _ = Define `
+ ((quintupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'a#'b#'c#'d#'e -> 'a#'b#'c#'d#'e -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e (x1, x2, x3, x4, x5) (y1, y2, y3, y4, y5)=  (pairLessEq 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+           dict_Basic_classes_Ord_e))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, x5)))) (y1, (y2, (y3, (y4, y5))))))`;
+
+
+val _ = Define `
+ ((quintupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345=  (quintupleLess 
+  dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`;
+
+val _ = Define `
+ ((quintupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'e#'d#'c#'b#'a -> 'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e x12345 y12345=  (quintupleLessEq 
+  dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y12345 x12345))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup5_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class ->('a#'b#'c#'d#'e)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e= (<|
+
+  compare_method := (quintupleCompare  
+  dict_Basic_classes_Ord_a.compare_method  dict_Basic_classes_Ord_b.compare_method  dict_Basic_classes_Ord_c.compare_method  dict_Basic_classes_Ord_d.compare_method  dict_Basic_classes_Ord_e.compare_method);
+
+  isLess_method := 
+  (quintupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_e);
+
+  isLessEqual_method := 
+  (quintupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_e);
+
+  isGreater_method := 
+  (quintupleGreater dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_a);
+
+  isGreaterEqual_method := 
+  (quintupleGreaterEq dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_a)|>))`;
+
+
+(* sextuples *)
+
+(*val sextupleEqual : forall 'a 'b 'c 'd 'e 'f. Eq 'a, Eq 'b, Eq 'c, Eq 'd, Eq 'e, Eq 'f => ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> bool*)
+(*let sextupleEqual (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)=  ((Instance_Basic_classes_Eq_tup2.=) (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6))))))*)
+
+(*val sextupleCompare : forall 'a 'b 'c 'd 'e 'f. ('a -> 'a -> ordering) -> ('b -> 'b -> ordering) -> ('c -> 'c -> ordering) ->
+                                              ('d -> 'd -> ordering) -> ('e -> 'e -> ordering) -> ('f -> 'f -> ordering) ->
+                                              ('a * 'b * 'c * 'd * 'e * 'f) -> ('a * 'b * 'c * 'd * 'e * 'f) -> ordering*)
+val _ = Define `
+ ((sextupleCompare:('a -> 'a -> ordering) ->('b -> 'b -> ordering) ->('c -> 'c -> ordering) ->('d -> 'd -> ordering) ->('e -> 'e -> ordering) ->('f -> 'f -> ordering) -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> ordering) cmpa cmpb cmpc cmpd cmpe cmpf (a1, b1, c1, d1, e1, f1) (a2, b2, c2, d2, e2, f2)=  
+ (pairCompare cmpa (pairCompare cmpb (pairCompare cmpc (pairCompare cmpd (pairCompare cmpe cmpf)))) (a1, (b1, (c1, (d1, (e1, f1))))) (a2, (b2, (c2, (d2, (e2, f2)))))))`;
+
+
+val _ = Define `
+ ((sextupleLess:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)=  (pairLess 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+           (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+              dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`;
+
+val _ = Define `
+ ((sextupleLessEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'a#'b#'c#'d#'e#'f -> 'a#'b#'c#'d#'e#'f -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f (x1, x2, x3, x4, x5, x6) (y1, y2, y3, y4, y5, y6)=  (pairLessEq 
+  (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_b
+     (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_c
+        (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_d
+           (instance_Basic_classes_Ord_tup2_dict dict_Basic_classes_Ord_e
+              dict_Basic_classes_Ord_f)))) dict_Basic_classes_Ord_a (x1, (x2, (x3, (x4, (x5, x6))))) (y1, (y2, (y3, (y4, (y5, y6)))))))`;
+
+
+val _ = Define `
+ ((sextupleGreater:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456=  (sextupleLess 
+  dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`;
+
+val _ = Define `
+ ((sextupleGreaterEq:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class -> 'f#'e#'d#'c#'b#'a -> 'f#'e#'d#'c#'b#'a -> bool)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f x123456 y123456=  (sextupleLessEq 
+  dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a y123456 x123456))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_tup6_dict:'a Ord_class -> 'b Ord_class -> 'c Ord_class -> 'd Ord_class -> 'e Ord_class -> 'f Ord_class ->('a#'b#'c#'d#'e#'f)Ord_class)dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f= (<|
+
+  compare_method := (sextupleCompare  
+  dict_Basic_classes_Ord_a.compare_method  dict_Basic_classes_Ord_b.compare_method  dict_Basic_classes_Ord_c.compare_method  dict_Basic_classes_Ord_d.compare_method  dict_Basic_classes_Ord_e.compare_method  dict_Basic_classes_Ord_f.compare_method);
+
+  isLess_method := 
+  (sextupleLess dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f);
+
+  isLessEqual_method := 
+  (sextupleLessEq dict_Basic_classes_Ord_a dict_Basic_classes_Ord_b
+     dict_Basic_classes_Ord_c dict_Basic_classes_Ord_d
+     dict_Basic_classes_Ord_e dict_Basic_classes_Ord_f);
+
+  isGreater_method := 
+  (sextupleGreater dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+     dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+     dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a);
+
+  isGreaterEqual_method := 
+  (sextupleGreaterEq dict_Basic_classes_Ord_f dict_Basic_classes_Ord_e
+     dict_Basic_classes_Ord_d dict_Basic_classes_Ord_c
+     dict_Basic_classes_Ord_b dict_Basic_classes_Ord_a)|>))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_boolScript.sml b/snapshots/hol4/lem/hol-lib/lem_boolScript.sml
new file mode 100644
index 00000000..5e6aa09f
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_boolScript.sml
@@ -0,0 +1,75 @@
+(*Generated by Lem from bool.lem.*)
+open HolKernel Parse boolLib bossLib;
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_bool"
+
+ 
+
+(* The type bool is hard-coded, so are true and false *)
+
+(* ----------------------- *)
+(* not                     *)
+(* ----------------------- *)
+
+(*val not : bool -> bool*)
+(*let not b=  match b with
+  | true -> false
+  | false -> true
+end*)
+
+(* ----------------------- *)
+(* and                     *)
+(* ----------------------- *)
+
+(*val && [and] : bool -> bool -> bool*)
+(*let && b1 b2=  match (b1, b2) with
+  | (true, true) -> true
+  | _ -> false
+end*)
+
+
+(* ----------------------- *)
+(* or                      *)
+(* ----------------------- *)
+
+(*val || [or] : bool -> bool -> bool*)
+(*let || b1 b2=  match (b1, b2) with
+  | (false, false) -> false
+  | _ -> true
+end*)
+
+
+(* ----------------------- *)
+(* implication             *)
+(* ----------------------- *)
+
+(*val --> [imp] : bool -> bool -> bool*)
+(*let --> b1 b2=  match (b1, b2) with
+  | (true, false) -> false
+  | _ -> true
+end*)
+
+
+(* ----------------------- *)
+(* equivalence             *)
+(* ----------------------- *)
+
+(*val <-> [equiv] : bool -> bool -> bool*)
+(*let <-> b1 b2=  match (b1, b2) with
+  | (true, true) -> true
+  | (false, false) -> true
+  | _ -> false
+end*)
+
+
+(* ----------------------- *)
+(* xor                     *)
+(* ----------------------- *)
+
+(*val xor : bool -> bool -> bool*)
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml
new file mode 100644
index 00000000..15437410
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_eitherScript.sml
@@ -0,0 +1,83 @@
+(*Generated by Lem from either.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_listTheory lem_tupleTheory sumTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_either"
+
+ 
+
+(*open import Bool Basic_classes List Tuple*)
+(*open import {hol} `sumTheory`*)
+(*open import {ocaml} `Either`*)
+
+(*type either 'a 'b
+  = Left  of 'a
+  | Right of 'b*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Equality.                                                                  *)
+(* -------------------------------------------------------------------------- *)
+
+(*val eitherEqual : forall 'a 'b. Eq 'a, Eq 'b => (either 'a 'b) -> (either 'a 'b) -> bool*)
+(*val eitherEqualBy : forall 'a 'b. ('a -> 'a -> bool) -> ('b -> 'b -> bool) -> (either 'a 'b) -> (either 'a 'b) -> bool*)
+
+val _ = Define `
+ ((eitherEqualBy:('a -> 'a -> bool) ->('b -> 'b -> bool) ->('a,'b)sum ->('a,'b)sum -> bool) eql eqr (left: ('a, 'b) sum) (right: ('a, 'b) sum)=  
+ ((case (left, right) of
+      (INL l, INL l') => eql l l'
+    | (INR r, INR r') => eqr r r'
+    | _ => F
+  )))`;
+
+(*let eitherEqual=  eitherEqualBy (=) (=)*)
+
+val _ = Define `
+ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL x') (INL y')=  (cmpa x' y'))
+/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR x') (INR y')=  (cmpb x' y'))
+/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INL _) (INR _)=  LT)
+/\ ((either_setElemCompare:('d -> 'b -> lem_basic_classes$ordering) ->('c -> 'a -> lem_basic_classes$ordering) ->('d,'c)sum ->('b,'a)sum -> lem_basic_classes$ordering) cmpa cmpb (INR _) (INL _)=  GT)`;
+
+                           
+
+(* -------------------------------------------------------------------------- *)
+(* Utility functions.                                                         *)
+(* -------------------------------------------------------------------------- *)
+
+(*val isLeft : forall 'a 'b. either 'a 'b -> bool*)
+
+(*val isRight : forall 'a 'b. either 'a 'b -> bool*)
+
+
+(*val either : forall 'a 'b 'c. ('a -> 'c) -> ('b -> 'c) -> either 'a 'b -> 'c*)
+(*let either fa fb x=  match x with
+  | Left a -> fa a
+  | Right b -> fb b
+end*)
+
+
+(*val partitionEither : forall 'a 'b. list (either 'a 'b) -> (list 'a * list 'b)*)
+ val _ = Define `
+ ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) ([])=  ([], []))
+/\ ((SUM_PARTITION:(('a,'b)sum)list -> 'a list#'b list) (x :: xs)=  ((
+      let (ll, rl) = (SUM_PARTITION xs) in
+      (case x of 
+          INL l => ((l::ll), rl)
+        | INR r => (ll, (r::rl))
+      )
+    )))`;
+
+
+
+(*val lefts : forall 'a 'b. list (either 'a 'b) -> list 'a*)
+
+
+(*val rights : forall 'a 'b. list (either 'a 'b) -> list 'b*)
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_functionScript.sml b/snapshots/hol4/lem/hol-lib/lem_functionScript.sml
new file mode 100644
index 00000000..2f6f52b8
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_functionScript.sml
@@ -0,0 +1,72 @@
+(*Generated by Lem from function.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_function"
+
+(******************************************************************************)
+(* A library for common operations on functions                               *)
+(******************************************************************************)
+
+(*open import Bool Basic_classes*)
+
+(*open import {coq} `Program.Basics`*)
+
+(* ----------------------- *)
+(* identity function       *)
+(* ----------------------- *)
+
+(*val id : forall 'a. 'a -> 'a*)
+(*let id x=  x*)
+
+
+(* ----------------------- *)
+(* constant function       *)
+(* ----------------------- *)
+
+(*val const : forall 'a 'b. 'a -> 'b -> 'a*)
+
+
+(* ----------------------- *)
+(* function composition    *)
+(* ----------------------- *)
+
+(*val comb : forall 'a 'b 'c. ('b -> 'c) -> ('a -> 'b) -> ('a -> 'c)*)
+(*let comb f g=  (fun x -> f (g x))*)
+
+
+(* ----------------------- *)
+(* function application    *)
+(* ----------------------- *)
+
+(*val $ [apply] : forall 'a 'b. ('a -> 'b) -> ('a -> 'b)*)
+(*let $ f=  (fun x -> f x)*)
+
+(*val $> [rev_apply] : forall 'a 'b. 'a -> ('a -> 'b) -> 'b*)
+(*let $> x f=  f x*)
+
+(* ----------------------- *)
+(* flipping argument order *)
+(* ----------------------- *)
+
+(*val flip : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('b -> 'a -> 'c)*)
+(*let flip f=  (fun x y -> f y x)*)
+
+
+(* currying / uncurrying *)
+
+(*val curry : forall 'a 'b 'c. (('a * 'b) -> 'c) -> 'a -> 'b -> 'c*)
+val _ = Define `
+ ((curry:('a#'b -> 'c) -> 'a -> 'b -> 'c) f=  (\ a b .  f (a, b)))`;
+
+
+(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*)
+val _ = Define `
+ ((uncurry:('a -> 'b -> 'c) -> 'a#'b -> 'c) f (a,b)=  (f a b))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml
new file mode 100644
index 00000000..6543ef87
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_function_extraScript.sml
@@ -0,0 +1,25 @@
+(*Generated by Lem from function_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_maybeTheory lem_boolTheory lem_basic_classesTheory lem_numTheory lem_functionTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_function_extra"
+
+
+
+(*open import Maybe Bool Basic_classes Num Function*)
+
+(*open import {hol} `lemTheory`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ----------------------- *)
+(* getting a unique value  *)
+(* ----------------------- *)
+
+(*val THE : forall 'a. ('a -> bool) -> Maybe.maybe 'a*)
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_listScript.sml b/snapshots/hol4/lem/hol-lib/lem_listScript.sml
new file mode 100644
index 00000000..f2ba75d6
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_listScript.sml
@@ -0,0 +1,776 @@
+(*Generated by Lem from list.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_functionTheory lem_tupleTheory lem_numTheory lemTheory listTheory rich_listTheory sortingTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_list"
+
+ 
+
+(*open import Bool Maybe Basic_classes Function Tuple Num*)
+
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+(*open import {hol} `lemTheory` `listTheory` `rich_listTheory` `sortingTheory`*)
+
+(* ========================================================================== *)
+(* Basic list functions                                                       *)
+(* ========================================================================== *)
+
+(* The type of lists as well as list literals like [], [1;2], ... are hardcoded. 
+   Thus, we can directly dive into derived definitions. *)
+
+
+(* ----------------------- *)
+(* cons                    *)
+(* ----------------------- *)
+
+(*val :: : forall 'a. 'a -> list 'a -> list 'a*)
+
+
+(* ----------------------- *)
+(* Emptyness check         *)
+(* ----------------------- *)
+
+(*val null : forall 'a. list 'a -> bool*)
+(*let null l=  match l with [] -> true | _ -> false end*)
+
+(* ----------------------- *)
+(* Length                  *)
+(* ----------------------- *)
+
+(*val length : forall 'a. list 'a -> nat*)
+(*let rec length l= 
+  match l with
+    | [] -> 0
+    | x :: xs -> (Instance_Num_NumAdd_nat.+) (length xs) 1
+  end*)
+
+(* ----------------------- *)
+(* Equality                *)
+(* ----------------------- *)
+
+(*val listEqual : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*val listEqualBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+
+ val _ = Define `
+ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) ([])=  T)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) (_::_)=  F)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (_::_) ([])=  F)
+/\ ((listEqualBy:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x::xs) (y :: ys)=  (eq x y /\ listEqualBy eq xs ys))`;
+
+
+
+(* ----------------------- *)
+(* compare                 *)
+(* ----------------------- *)
+
+(*val lexicographicCompare : forall 'a. Ord 'a => list 'a -> list 'a -> Basic_classes.ordering*)
+(*val lexicographicCompareBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a -> Basic_classes.ordering*)
+
+ val _ = Define `
+ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) ([])=  EQ)
+/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp ([]) (_::_)=  LT)
+/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (_::_) ([])=  GT)
+/\ ((lexicographic_compare:('a -> 'a -> lem_basic_classes$ordering) -> 'a list -> 'a list -> lem_basic_classes$ordering) cmp (x::xs) (y::ys)=  ((
+      (case cmp x y of 
+          LT => LT
+        | GT => GT
+        | EQ => lexicographic_compare cmp xs ys
+      )
+    )))`;
+
+
+(*val lexicographicLess : forall 'a. Ord 'a => list 'a -> list 'a -> bool*)
+(*val lexicographicLessBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+ val _ = Define `
+ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])=  F)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)=  T)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])=  F)
+/\ ((lexicographic_less:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)=  ((less x y) \/ ((less_eq x y) /\ (lexicographic_less less less_eq xs ys))))`;
+
+
+(*val lexicographicLessEq : forall 'a. Ord 'a => list 'a -> list 'a -> bool*)
+(*val lexicographicLessEqBy : forall 'a. ('a -> 'a -> bool) -> ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+ val _ = Define `
+ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) ([])=  T)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq ([]) (_::_)=  T)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (_::_) ([])=  F)
+/\ ((lexicographic_less_eq:('a -> 'a -> bool) ->('a -> 'a -> bool) -> 'a list -> 'a list -> bool) less less_eq (x::xs) (y::ys)=  (less x y \/ (less_eq x y /\ lexicographic_less_eq less less_eq xs ys)))`;
+
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_list_dict:'a lem_basic_classes$Ord_class ->('a list)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<|
+
+  compare_method := (lexicographic_compare  
+  dict_Basic_classes_Ord_a.compare_method);
+
+  isLess_method := (lexicographic_less  
+  dict_Basic_classes_Ord_a.isLess_method  dict_Basic_classes_Ord_a.isLessEqual_method);
+
+  isLessEqual_method := (lexicographic_less_eq  
+  dict_Basic_classes_Ord_a.isLess_method  dict_Basic_classes_Ord_a.isLessEqual_method);
+
+  isGreater_method := (\ x y. (lexicographic_less  
+  dict_Basic_classes_Ord_a.isLess_method  dict_Basic_classes_Ord_a.isLessEqual_method y x));
+
+  isGreaterEqual_method := (\ x y. (lexicographic_less_eq  
+  dict_Basic_classes_Ord_a.isLess_method  dict_Basic_classes_Ord_a.isLessEqual_method y x))|>))`;
+
+
+
+(* ----------------------- *)
+(* Append                  *)
+(* ----------------------- *)
+
+(*val ++ : forall 'a. list 'a -> list 'a -> list 'a*) (* originally append *)
+(*let rec ++ xs ys=  match xs with
+                     | [] -> ys
+                     | x :: xs' -> x :: (xs' ++ ys)
+                   end*)
+
+(* ----------------------- *)
+(* snoc                    *)
+(* ----------------------- *)
+
+(*val snoc : forall 'a. 'a -> list 'a -> list 'a*)
+(*let snoc e l=  l ++ [e]*)
+
+
+(* ----------------------- *)
+(* Reverse                 *)
+(* ----------------------- *)
+
+(* First lets define the function [reverse_append], which is
+   closely related to reverse. [reverse_append l1 l2] appends the list [l2] to the reverse of [l1].
+   This can be implemented more efficienctly than appending and is
+   used to implement reverse. *)
+
+(*val reverseAppend : forall 'a. list 'a -> list 'a -> list 'a*) (* originally named rev_append *)
+(*let rec reverseAppend l1 l2=  match l1 with 
+                                | [] -> l2
+                                | x :: xs -> reverseAppend xs (x :: l2)
+                               end*)
+
+(* Reversing a list *)
+(*val reverse : forall 'a. list 'a -> list 'a*) (* originally named rev *)
+(*let reverse l=  reverseAppend l []*)
+
+(* ----------------------- *)
+(* Map                     *)
+(* ----------------------- *)
+
+(*val map_tr : forall 'a 'b. list 'b -> ('a -> 'b) -> list 'a -> list 'b*)
+ val map_tr_defn = Defn.Hol_multi_defns `
+ ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f ([])=  (REVERSE rev_acc))
+/\ ((map_tr:'b list ->('a -> 'b) -> 'a list -> 'b list) rev_acc f (x :: xs)=  (map_tr ((f x) :: rev_acc) f xs))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) map_tr_defn;
+
+(* taken from: https://blogs.janestreet.com/optimizing-list-map/ *)
+(*val count_map : forall 'a 'b. ('a -> 'b) -> list 'a -> nat -> list 'b*)
+ val count_map_defn = Defn.Hol_multi_defns `
+ ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f ([]) ctr=  ([]))
+/\ ((count_map:('a -> 'b) -> 'a list -> num -> 'b list) f (hd :: tl) ctr=  (f hd :: 
+    (if ctr <( 5000 : num) then count_map f tl (ctr +( 1 : num)) 
+    else map_tr [] f tl)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) count_map_defn;
+ 
+(*val map : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*)
+(*let map f l=  count_map f l 0*)
+
+(* ----------------------- *)
+(* Reverse Map             *)
+(* ----------------------- *)
+
+(*val reverseMap : forall 'a 'b. ('a -> 'b) -> list 'a -> list 'b*)
+
+
+(* ========================================================================== *)
+(* Folding                                                                    *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* fold left               *)
+(* ----------------------- *)
+
+(*val foldl : forall 'a 'b. ('a -> 'b -> 'a) -> 'a -> list 'b -> 'a*) (* originally foldl *)
+
+(*let rec foldl f b l=  match l with
+  | []      -> b
+  | x :: xs -> foldl f (f b x) xs
+end*)
+
+
+(* ----------------------- *)
+(* fold right              *)
+(* ----------------------- *)
+
+(*val foldr : forall 'a 'b. ('a -> 'b -> 'b) -> 'b -> list 'a -> 'b*) (* originally foldr with different argument order *)
+(*let rec foldr f b l=  match l with
+  | []      -> b
+  | x :: xs -> f x (foldr f b xs)
+end*)
+
+
+(* ----------------------- *)
+(* concatenating lists     *)
+(* ----------------------- *)
+
+(*val concat : forall 'a. list (list 'a) -> list 'a*) (* before also called "flatten" *)
+(*let concat=  foldr (++) []*)
+
+
+(* -------------------------- *)
+(* concatenating with mapping *)
+(* -------------------------- *)
+
+(*val concatMap : forall 'a 'b. ('a -> list 'b) -> list 'a -> list 'b*)
+
+
+(* ------------------------- *)
+(* universal qualification   *)
+(* ------------------------- *)
+
+(*val all : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally for_all *)
+(*let all P l=  foldl (fun r e -> P e && r) true l*)
+
+
+
+(* ------------------------- *)
+(* existential qualification *)
+(* ------------------------- *)
+
+(*val any : forall 'a. ('a -> bool) -> list 'a -> bool*) (* originally exist *)
+(*let any P l=  foldl (fun r e -> P e || r) false l*)
+
+
+(* ------------------------- *)
+(* dest_init                 *)
+(* ------------------------- *)
+
+(* get the initial part and the last element of the list in a safe way *)
+
+(*val dest_init : forall 'a. list 'a -> Maybe.maybe (list 'a * 'a)*) 
+
+ val _ = Define `
+ ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen ([])=  (REVERSE rev_init, last_elem_seen))
+/\ ((dest_init_aux:'a list -> 'a -> 'a list -> 'a list#'a) rev_init last_elem_seen (x::xs)=  (dest_init_aux (last_elem_seen::rev_init) x xs))`;
+
+
+val _ = Define `
+ ((dest_init:'a list ->('a list#'a)option) ([])=  NONE)
+/\ ((dest_init:'a list ->('a list#'a)option) (x::xs)=  (SOME (dest_init_aux [] x xs)))`;
+
+
+
+(* ========================================================================== *)
+(* Indexing lists                                                             *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* index / nth with maybe   *)
+(* ------------------------- *)
+
+(*val index : forall 'a. list 'a -> nat -> Maybe.maybe 'a*)
+
+ val _ = Define `
+ ((list_index:'a list -> num -> 'a option) ([]) n=  NONE)
+/\ ((list_index:'a list -> num -> 'a option) (x :: xs) n=  (if n =( 0 : num) then SOME x else list_index xs (n -( 1 : num))))`;
+
+
+(* ------------------------- *)
+(* findIndices               *)
+(* ------------------------- *)
+
+(* [findIndices P l] returns the indices of all elements of list [l] that satisfy predicate [P]. 
+   Counting starts with 0, the result list is sorted ascendingly *)
+(*val findIndices : forall 'a. ('a -> bool) -> list 'a -> list nat*)
+
+ val _ = Define `
+ ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P ([])=  ([]))
+/\ ((find_indices_aux:num ->('a -> bool) -> 'a list ->(num)list) (i:num) P (x :: xs)=  (if P x then i :: find_indices_aux (i +( 1 : num)) P xs else find_indices_aux (i +( 1 : num)) P xs))`;
+
+val _ = Define `
+ ((find_indices:('a -> bool) -> 'a list ->(num)list) P l=  (find_indices_aux(( 0 : num)) P l))`;
+
+
+
+
+(* ------------------------- *)
+(* findIndex                 *)
+(* ------------------------- *)
+
+(* findIndex returns the first index of a list that satisfies a given predicate. *)
+(*val findIndex : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe nat*)
+val _ = Define `
+ ((find_index:('a -> bool) -> 'a list ->(num)option) P l=  ((case find_indices P l of
+    [] => NONE
+  | x :: _ => SOME x
+)))`;
+
+
+(* ------------------------- *)
+(* elemIndices               *)
+(* ------------------------- *)
+
+(*val elemIndices : forall 'a. Eq 'a => 'a -> list 'a -> list nat*)
+
+(* ------------------------- *)
+(* elemIndex                 *)
+(* ------------------------- *)
+
+(*val elemIndex : forall 'a. Eq 'a => 'a -> list 'a -> Maybe.maybe nat*)
+
+
+(* ========================================================================== *)
+(* Creating lists                                                             *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* genlist                   *)
+(* ------------------------- *)
+
+(* [genlist f n] generates the list [f 0; f 1; ... (f (n-1))] *)
+(*val genlist : forall 'a. (nat -> 'a) -> nat -> list 'a*)
+
+
+(*let rec genlist f n= 
+  match n with
+    | 0 -> []
+    | n' + 1 -> snoc (f n') (genlist f n')
+  end*)
+
+
+(* ------------------------- *)
+(* replicate                 *)
+(* ------------------------- *)
+
+(*val replicate : forall 'a. nat -> 'a -> list 'a*)
+(*let rec replicate n x= 
+  match n with
+    | 0 -> []
+    | n' + 1 -> x :: replicate n' x
+  end*)
+
+
+(* ========================================================================== *)
+(* Sublists                                                                   *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* splitAt                   *)
+(* ------------------------- *)
+
+(* [splitAt n xs] returns a tuple (xs1, xs2), with "append xs1 xs2 = xs" and 
+   "length xs1 = n". If there are not enough elements 
+   in [xs], the original list and the empty one are returned. *)
+(*val splitAtAcc : forall 'a. list 'a -> nat -> list 'a -> (list 'a * list 'a)*)
+ val splitAtAcc_defn = Hol_defn "splitAtAcc" `
+ ((splitAtAcc:'a list -> num -> 'a list -> 'a list#'a list) revAcc n l=  
+  ((case l of
+      []    => (REVERSE revAcc, [])
+    | x::xs => if n <=( 0 : num) then (REVERSE revAcc, l) else splitAtAcc (x::revAcc) (n -( 1 : num)) xs
+  )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn splitAtAcc_defn;
+
+(*val splitAt : forall 'a. nat -> list 'a -> (list 'a * list 'a)*)
+(*let rec splitAt n l=  
+   splitAtAcc [] n l*)
+
+
+(* ------------------------- *)
+(* take                      *)
+(* ------------------------- *)
+
+(* take n xs returns the prefix of xs of length n, or xs itself if n > length xs *)
+(*val take : forall 'a. nat -> list 'a -> list 'a*)
+(*let take n l=  fst (splitAt n l)*)
+
+(* ------------------------- *)
+(* drop                      *)
+(* ------------------------- *)
+
+(* [drop n xs] drops the first [n] elements of [xs]. It returns the empty list, if [n] > [length xs]. *)
+(*val drop : forall 'a. nat -> list 'a -> list 'a*)
+(*let drop n l=  snd (splitAt n l)*)
+
+(* ------------------------------------ *)
+(* splitWhile, takeWhile, and dropWhile *)
+(* ------------------------------------ *)
+
+(*val splitWhile_tr : forall 'a. ('a -> bool) -> list 'a -> list 'a -> (list 'a * list 'a)*)
+ val _ = Define `
+ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p ([]) acc= 
+    (REVERSE acc, []))
+/\ ((splitWhile_tr:('a -> bool) -> 'a list -> 'a list -> 'a list#'a list) p (x::xs) acc=    
+ (if p x then
+      splitWhile_tr p xs (x::acc)
+    else
+      (REVERSE acc, (x::xs))))`;
+
+
+(*val splitWhile : forall 'a. ('a -> bool) -> list 'a -> (list 'a * list 'a)*)
+val _ = Define `
+ ((splitWhile:('a -> bool) -> 'a list -> 'a list#'a list) p xs=  (splitWhile_tr p xs []))`;
+
+
+(* [takeWhile p xs] takes the first elements of [xs] that satisfy [p]. *)
+(*val takeWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+val _ = Define `
+ ((takeWhile:('a -> bool) -> 'a list -> 'a list) p l=  (FST (splitWhile p l)))`;
+
+
+(* [dropWhile p xs] drops the first elements of [xs] that satisfy [p]. *)
+(*val dropWhile : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+val _ = Define `
+ ((dropWhile:('a -> bool) -> 'a list -> 'a list) p l=  (SND (splitWhile p l)))`;
+
+
+(* ------------------------- *)
+(* isPrefixOf                *)
+(* ------------------------- *)
+
+(*val isPrefixOf : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*let rec isPrefixOf l1 l2=  match (l1, l2) with
+  | ([], _) -> true
+  | (_::_, []) -> false
+  | (x::xs, y::ys) -> (x = y) && isPrefixOf xs ys
+end*)
+
+(* ------------------------- *)
+(* update                    *)
+(* ------------------------- *)
+(*val update : forall 'a. list 'a -> nat -> 'a -> list 'a*)
+(*let rec update l n e=  
+  match l with
+    | []      -> []
+    | x :: xs -> if (Instance_Basic_classes_Eq_nat.=) n 0 then e :: xs else x :: (update xs ((Instance_Num_NumMinus_nat.-) n 1) e)
+end*)
+
+
+
+(* ========================================================================== *)
+(* Searching lists                                                            *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* Membership test           *)
+(* ------------------------- *)
+
+(* The membership test, one of the basic list functions, is actually tricky for
+   Lem, because it is tricky, which equality to use. From Lem`s point of 
+   perspective, we want to use the equality provided by the equality type - class.
+   This allows for example to check whether a set is in a list of sets.
+
+   However, in order to use the equality type class, elem essentially becomes
+   existential quantification over lists. For types, which implement semantic
+   equality (=) with syntactic equality, this is overly complicated. In
+   our theorem prover backend, we would end up with overly complicated, harder
+   to read definitions and some of the automation would be harder to apply.
+   Moreover, nearly all the old Lem generated code would change and require 
+   (hopefully minor) adaptions of proofs.
+
+   For now, we ignore this problem and just demand, that all instances of
+   the equality type class do the right thing for the theorem prover backends.   
+*)
+
+(*val elem : forall 'a. Eq 'a => 'a -> list 'a -> bool*)
+(*val elemBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> bool*)
+
+val _ = Define `
+ ((elemBy:('a -> 'a -> bool) -> 'a -> 'a list -> bool) eq e l=  (EXISTS (eq e) l))`;
+
+(*let elem=  elemBy (=)*)
+
+(* ------------------------- *)
+(* Find                      *)
+(* ------------------------- *)
+(*val find : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe 'a*) (* previously not of maybe type *)
+ val _ = Define `
+ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P ([])=  NONE)
+/\ ((list_find_opt:('a -> bool) -> 'a list -> 'a option) P (x :: xs)=  (if P x then SOME x else list_find_opt P xs))`;
+
+
+
+(* ----------------------------- *)
+(* Lookup in an associative list *)
+(* ----------------------------- *)
+(*val lookup   : forall 'a 'b. Eq 'a              => 'a -> list ('a * 'b) -> Maybe.maybe 'b*)
+(*val lookupBy : forall 'a 'b. ('a -> 'a -> bool) -> 'a -> list ('a * 'b) -> Maybe.maybe 'b*)
+
+(* DPM: eta-expansion for Coq backend type-inference. *)
+val _ = Define `
+ ((lookupBy:('a -> 'a -> bool) -> 'a ->('a#'b)list -> 'b option) eq k m=  (OPTION_MAP (\ x .  SND x) (list_find_opt (\p .  
+  (case (p ) of ( (k', _) ) => eq k k' )) m)))`;
+
+
+(* ------------------------- *)
+(* filter                    *)
+(* ------------------------- *)
+(*val filter : forall 'a. ('a -> bool) -> list 'a -> list 'a*)
+(*let rec filter P l=  match l with
+                       | [] -> []
+                       | x :: xs -> if (P x) then x :: (filter P xs) else filter P xs
+                     end*)
+
+
+(* ------------------------- *)
+(* partition                 *)
+(* ------------------------- *)
+(*val partition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*)
+(*let partition P l=  (filter P l, filter (fun x -> not (P x)) l)*)
+
+(*val reversePartition : forall 'a. ('a -> bool) -> list 'a -> list 'a * list 'a*)
+(*let reversePartition P l=  partition P (reverse l)*)
+
+
+(* ------------------------- *)
+(* delete first element      *)
+(* with certain property     *)
+(* ------------------------- *)
+
+(*val deleteFirst : forall 'a. ('a -> bool) -> list 'a -> Maybe.maybe (list 'a)*) 
+ val _ = Define `
+ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P ([])=  NONE)
+/\ ((list_delete_first:('a -> bool) -> 'a list ->('a list)option) P (x :: xs)=  (if (P x) then SOME xs else OPTION_MAP (\ xs' .  x :: xs') (list_delete_first P xs)))`;
+
+
+
+(*val delete : forall 'a. Eq 'a => 'a -> list 'a -> list 'a*)
+(*val deleteBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*)
+
+val _ = Define `
+ ((list_delete:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) eq x l=  (option_CASE (list_delete_first (eq x) l) l I))`;
+
+
+
+(* ========================================================================== *)
+(* Zipping and unzipping lists                                                *)
+(* ========================================================================== *)
+
+(* ------------------------- *)
+(* zip                       *)
+(* ------------------------- *)
+
+(* zip takes two lists and returns a list of corresponding pairs. If one input list is short, excess elements of the longer list are discarded. *)
+(*val zip : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) (* before combine *)
+ val _ = Define `
+ ((list_combine:'a list -> 'b list ->('a#'b)list) l1 l2=  ((case (l1, l2) of
+    (x :: xs, y :: ys) => (x, y) :: list_combine xs ys
+  | _ => []
+)))`;
+
+
+(* ------------------------- *)
+(* unzip                     *)
+(* ------------------------- *)
+
+(*val unzip: forall 'a 'b. list ('a * 'b) -> (list 'a * list 'b)*)
+(*let rec unzip l=  match l with
+  | [] -> ([], [])
+  | (x, y) :: xys -> let (xs, ys) = unzip xys in (x :: xs, y :: ys)
+end*)
+
+(* ------------------------- *)
+(* distinct elements         *)
+(* ------------------------- *)
+
+(*val allDistinct : forall 'a. Eq 'a => list 'a -> bool*)
+(*let rec allDistinct l=  
+  match l with
+    | [] -> true
+    | (x::l') -> not (elem x l') && allDistinct l'
+  end*)
+
+(* some more useful functions *)
+(*val mapMaybe : forall 'a 'b. ('a -> Maybe.maybe 'b) -> list 'a -> list 'b*)
+ val mapMaybe_defn = Defn.Hol_multi_defns `
+ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f ([])=  ([]))
+/\ ((mapMaybe:('a -> 'b option) -> 'a list -> 'b list) f (x::xs)=      
+ ((case f x of
+        NONE => mapMaybe f xs
+      | SOME y => y :: (mapMaybe f xs)
+      )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapMaybe_defn;
+
+(*val mapi : forall 'a 'b. (nat -> 'a -> 'b) -> list 'a -> list 'b*)
+ val mapiAux_defn = Defn.Hol_multi_defns `
+ ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) ([])=  ([]))
+/\ ((mapiAux:(num -> 'b -> 'a) -> num -> 'b list -> 'a list) f (n : num) (x :: xs)=  ((f n x) :: mapiAux f (n +( 1 : num)) xs))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) mapiAux_defn;
+val _ = Define `
+ ((mapi:(num -> 'a -> 'b) -> 'a list -> 'b list) f l=  (mapiAux f(( 0 : num)) l))`;
+
+
+(*val deletes: forall 'a. Eq 'a => list 'a -> list 'a -> list 'a*)
+val _ = Define `
+ ((deletes:'a list -> 'a list -> 'a list) xs ys=  
+ (FOLDL (combin$C (list_delete (=))) xs ys))`;
+
+
+(* ========================================================================== *)
+(* Comments (not clean yet, please ignore the rest of the file)               *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* skipped from Haskell Lib*)
+(* ----------------------- 
+
+intersperse :: a -> [a] -> [a]
+intercalate :: [a] -> [[a]] -> [a]
+transpose :: [[a]] -> [[a]]
+subsequences :: [a] -> [[a]]
+permutations :: [a] -> [[a]]
+foldl` :: (a -> b -> a) -> a -> [b] -> aSource
+foldl1` :: (a -> a -> a) -> [a] -> aSource
+
+and
+or
+sum
+product
+maximum
+minimum
+scanl
+scanr
+scanl1
+scanr1
+Accumulating maps
+
+mapAccumL :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+mapAccumR :: (acc -> x -> (acc, y)) -> acc -> [x] -> (acc, [y])Source
+
+iterate :: (a -> a) -> a -> [a]
+repeat :: a -> [a]
+cycle :: [a] -> [a]
+unfoldr
+
+
+takeWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhile :: (a -> Bool) -> [a] -> [a]Source
+dropWhileEnd :: (a -> Bool) -> [a] -> [a]Source
+span :: (a -> Bool) -> [a] -> ([a], [a])Source
+break :: (a -> Bool) -> [a] -> ([a], [a])Source
+break p is equivalent to span (not . p).
+stripPrefix :: Eq a => [a] -> [a] -> Maybe [a]Source
+group :: Eq a => [a] -> [[a]]Source
+inits :: [a] -> [[a]]Source
+tails :: [a] -> [[a]]Source
+
+
+isPrefixOf :: Eq a => [a] -> [a] -> BoolSource
+isSuffixOf :: Eq a => [a] -> [a] -> BoolSource
+isInfixOf :: Eq a => [a] -> [a] -> BoolSource
+
+
+
+notElem :: Eq a => a -> [a] -> BoolSource
+
+zip3 :: [a] -> [b] -> [c] -> [(a, b, c)]Source
+zip4 :: [a] -> [b] -> [c] -> [d] -> [(a, b, c, d)]Source
+zip5 :: [a] -> [b] -> [c] -> [d] -> [e] -> [(a, b, c, d, e)]Source
+zip6 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [(a, b, c, d, e, f)]Source
+zip7 :: [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [(a, b, c, d, e, f, g)]Source
+
+zipWith :: (a -> b -> c) -> [a] -> [b] -> [c]Source
+zipWith3 :: (a -> b -> c -> d) -> [a] -> [b] -> [c] -> [d]Source
+zipWith4 :: (a -> b -> c -> d -> e) -> [a] -> [b] -> [c] -> [d] -> [e]Source
+zipWith5 :: (a -> b -> c -> d -> e -> f) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f]Source
+zipWith6 :: (a -> b -> c -> d -> e -> f -> g) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g]Source
+zipWith7 :: (a -> b -> c -> d -> e -> f -> g -> h) -> [a] -> [b] -> [c] -> [d] -> [e] -> [f] -> [g] -> [h]Source
+
+
+unzip3 :: [(a, b, c)] -> ([a], [b], [c])Source
+unzip4 :: [(a, b, c, d)] -> ([a], [b], [c], [d])Source
+unzip5 :: [(a, b, c, d, e)] -> ([a], [b], [c], [d], [e])Source
+unzip6 :: [(a, b, c, d, e, f)] -> ([a], [b], [c], [d], [e], [f])Source
+unzip7 :: [(a, b, c, d, e, f, g)] -> ([a], [b], [c], [d], [e], [f], [g])Source
+
+
+lines :: String -> [String]Source
+words :: String -> [String]Source
+unlines :: [String] -> StringSource
+unwords :: [String] -> StringSource
+nub :: Eq a => [a] -> [a]Source
+delete :: Eq a => a -> [a] -> [a]Source
+
+(\\) :: Eq a => [a] -> [a] -> [a]Source
+union :: Eq a => [a] -> [a] -> [a]Source
+intersect :: Eq a => [a] -> [a] -> [a]Source
+sort :: Ord a => [a] -> [a]Source
+insert :: Ord a => a -> [a] -> [a]Source
+
+
+nubBy :: (a -> a -> Bool) -> [a] -> [a]Source
+deleteBy :: (a -> a -> Bool) -> a -> [a] -> [a]Source
+deleteFirstsBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+unionBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+intersectBy :: (a -> a -> Bool) -> [a] -> [a] -> [a]Source
+groupBy :: (a -> a -> Bool) -> [a] -> [[a]]Source
+sortBy :: (a -> a -> Ordering) -> [a] -> [a]Source
+insertBy :: (a -> a -> Ordering) -> a -> [a] -> [a]Source
+maximumBy :: (a -> a -> Ordering) -> [a] -> aSource
+minimumBy :: (a -> a -> Ordering) -> [a] -> aSource
+genericLength :: Num i => [b] -> iSource
+genericTake :: Integral i => i -> [a] -> [a]Source
+genericDrop :: Integral i => i -> [a] -> [a]Source
+genericSplitAt :: Integral i => i -> [b] -> ([b], [b])Source
+genericIndex :: Integral a => [b] -> a -> bSource
+genericReplicate :: Integral i => i -> a -> [a]Source
+
+
+*)
+
+
+(* ----------------------- *)
+(* skipped from Lem Lib    *)
+(* ----------------------- 
+
+
+val for_all2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val exists2 : forall 'a 'b. ('a -> 'b -> bool) -> list 'a -> list 'b -> bool
+val map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c 
+val rev_map2 : forall 'a 'b 'c. ('a -> 'b -> 'c) -> list 'a -> list 'b -> list 'c
+val fold_left2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'a) -> 'a -> list 'b -> list 'c -> 'a
+val fold_right2 : forall 'a 'b 'c. ('a -> 'b -> 'c -> 'c) -> list 'a -> list 'b -> 'c -> 'c
+
+
+(* now maybe result and called lookup *)
+val assoc : forall 'a 'b. 'a -> list ('a * 'b) -> 'b
+let inline {ocaml} assoc = Ocaml.List.assoc
+
+
+val mem_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> bool
+val remove_assoc : forall 'a 'b. 'a -> list ('a * 'b) -> list ('a * 'b)
+
+
+
+val stable_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+val fast_sort : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a
+
+val merge : forall 'a. ('a -> 'a -> num) -> list 'a -> list 'a -> list 'a
+val intersect : forall 'a. list 'a -> list 'a -> list 'a
+
+
+*)
+
+(*val     catMaybes : forall 'a. list (Maybe.maybe 'a) -> list 'a*)
+ val catMaybes_defn = Defn.Hol_multi_defns `
+ ((catMaybes:('a option)list -> 'a list) ([])=        
+ ([]))
+/\ ((catMaybes:('a option)list -> 'a list) (NONE :: xs')=        
+ (catMaybes xs'))
+/\ ((catMaybes:('a option)list -> 'a list) (SOME x :: xs')=        
+ (x :: catMaybes xs'))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) catMaybes_defn;
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml
new file mode 100644
index 00000000..b8e452d3
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_list_extraScript.sml
@@ -0,0 +1,110 @@
+(*Generated by Lem from list_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_basic_classesTheory lem_tupleTheory lem_numTheory lem_listTheory lem_assert_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_list_extra"
+
+
+
+(*open import Bool Maybe Basic_classes Tuple Num List Assert_extra*)
+
+(* ------------------------- *)
+(* head of non-empty list    *)
+(* ------------------------- *)
+(*val head : forall 'a. list 'a -> 'a*)
+(*let head l=  match l with | x::xs -> x | [] -> failwith "List_extra.head of empty list" end*)
+
+
+(* ------------------------- *)
+(* tail of non-empty list    *)
+(* ------------------------- *)
+(*val tail : forall 'a. list 'a -> list 'a*)
+(*let tail l=  match l with | x::xs -> xs | [] -> failwith "List_extra.tail of empty list" end*)
+
+
+(* ------------------------- *)
+(* last                      *)
+(* ------------------------- *)
+(*val last : forall 'a. list 'a -> 'a*)
+(*let rec last l=  match l with | [x] -> x | x1::x2::xs -> last (x2 :: xs) | [] -> failwith "List_extra.last of empty list" end*)
+
+
+(* ------------------------- *)
+(* init                      *)
+(* ------------------------- *)
+
+(* All elements of a non-empty list except the last one. *)
+(*val init : forall 'a. list 'a -> list 'a*)
+(*let rec init l=  match l with | [x] -> [] | x1::x2::xs -> x1::(init (x2::xs)) | [] -> failwith "List_extra.init of empty list" end*)
+
+
+(* ------------------------- *)
+(* foldl1 / foldr1           *)
+(* ------------------------- *)
+
+(* folding functions for non-empty lists,
+    which don`t take the base case *)
+(*val foldl1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*)
+val _ = Define `
+ ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)=  (FOLDL f x xs))
+/\ ((foldl1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])=  (failwith "List_extra.foldl1 of empty list"))`;
+
+
+(*val foldr1 : forall 'a. ('a -> 'a -> 'a) -> list 'a -> 'a*)
+val _ = Define `
+ ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f (x :: xs)=  (FOLDR f x xs))
+/\ ((foldr1:('a -> 'a -> 'a) -> 'a list -> 'a) f ([])=  (failwith "List_extra.foldr1 of empty list"))`;
+
+
+  
+(* ------------------------- *)
+(* nth element               *)
+(* ------------------------- *)
+
+(* get the nth element of a list *)
+(*val nth : forall 'a. list 'a -> nat -> 'a*)
+(*let nth l n=  match index l n with Just e -> e | Nothing -> failwith "List_extra.nth" end*)
+
+
+(* ------------------------- *)
+(* Find_non_pure             *)
+(* ------------------------- *)
+(*val findNonPure : forall 'a. ('a -> bool) -> list 'a -> 'a*) 
+val _ = Define `
+ ((findNonPure:('a -> bool) -> 'a list -> 'a) P l=  ((case (list_find_opt P l) of 
+    SOME e      => e
+  | NONE     => failwith "List_extra.findNonPure"
+)))`;
+
+
+
+(* ------------------------- *)
+(* zip same length           *)
+(* ------------------------- *)
+
+(*val zipSameLength : forall 'a 'b. list 'a -> list 'b -> list ('a * 'b)*) 
+(*let rec zipSameLength l1 l2=  match (l1, l2) with
+  | (x :: xs, y :: ys) -> (x, y) :: zipSameLength xs ys
+  | ([], []) -> []
+  | _ -> failwith "List_extra.zipSameLength of different length lists"
+
+end*)
+
+(*val     unfoldr: forall 'a 'b. ('a -> Maybe.maybe ('b * 'a)) -> 'a -> list 'b*)
+ val unfoldr_defn = Hol_defn "unfoldr" `
+ ((unfoldr:('a ->('b#'a)option) -> 'a -> 'b list) f x=  
+ ((case f x of
+      SOME (y, x') =>
+        y :: unfoldr f x'
+    | NONE =>
+        []
+  )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn unfoldr_defn;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml
new file mode 100644
index 00000000..c169e9a8
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_machine_wordScript.sml
@@ -0,0 +1,433 @@
+(*Generated by Lem from machine_word.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_numTheory lem_basic_classesTheory lem_showTheory lem_functionTheory wordsTheory wordsLib bitstringTheory integer_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_machine_word"
+
+
+
+(*open import Bool Num Basic_classes Show Function*)
+
+(*open import {isabelle} `~~/src/HOL/Word/Word`*)
+(*open import {hol} `wordsTheory` `wordsLib` `bitstringTheory` `integer_wordTheory`*)
+
+(*type mword 'a*)
+
+(*class (Size 'a)
+  val size : nat
+end*)
+
+(*val native_size : forall 'a. nat*)
+
+(*val ocaml_inject : forall 'a. nat * Num.natural -> mword 'a*)
+
+(* A singleton type family that can be used to carry a size as the type parameter *)
+
+(*type itself 'a*)
+
+(*val the_value : forall 'a. itself 'a*)
+
+(*val size_itself : forall 'a. Size 'a => itself 'a -> nat*)
+val _ = Define `
+ ((size_itself:'a itself -> num) x=  (dimindex (the_value : 'a itself)))`;
+
+
+(*******************************************************************)
+(* Fixed bitwidths extracted from Anthony's models.                *)
+(*                                                                 *)
+(* If you need a size N that is not included here, put the lines   *)
+(*                                                                 *)
+(* type tyN                                                        *)
+(* instance (Size tyN) let size = N end                            *)
+(* declare isabelle target_rep type tyN = `N`                      *)
+(* declare hol target_rep type tyN = `N`                           *)
+(*                                                                 *)
+(* in your project, replacing N in each line.                      *)
+(*******************************************************************)
+
+(*type ty1*)
+(*type ty2*)
+(*type ty3*)
+(*type ty4*)
+(*type ty5*)
+(*type ty6*)
+(*type ty7*)
+(*type ty8*)
+(*type ty9*)
+(*type ty10*)
+(*type ty11*)
+(*type ty12*)
+(*type ty13*)
+(*type ty14*)
+(*type ty15*)
+(*type ty16*)
+(*type ty17*)
+(*type ty18*)
+(*type ty19*)
+(*type ty20*)
+(*type ty21*)
+(*type ty22*)
+(*type ty23*)
+(*type ty24*)
+(*type ty25*)
+(*type ty26*)
+(*type ty27*)
+(*type ty28*)
+(*type ty29*)
+(*type ty30*)
+(*type ty31*)
+(*type ty32*)
+(*type ty33*)
+(*type ty34*)
+(*type ty35*)
+(*type ty36*)
+(*type ty37*)
+(*type ty38*)
+(*type ty39*)
+(*type ty40*)
+(*type ty41*)
+(*type ty42*)
+(*type ty43*)
+(*type ty44*)
+(*type ty45*)
+(*type ty46*)
+(*type ty47*)
+(*type ty48*)
+(*type ty49*)
+(*type ty50*)
+(*type ty51*)
+(*type ty52*)
+(*type ty53*)
+(*type ty54*)
+(*type ty55*)
+(*type ty56*)
+(*type ty57*)
+(*type ty58*)
+(*type ty59*)
+(*type ty60*)
+(*type ty61*)
+(*type ty62*)
+(*type ty63*)
+(*type ty64*)
+(*type ty65*)
+(*type ty66*)
+(*type ty67*)
+(*type ty68*)
+(*type ty69*)
+(*type ty70*)
+(*type ty71*)
+(*type ty72*)
+(*type ty73*)
+(*type ty74*)
+(*type ty75*)
+(*type ty76*)
+(*type ty77*)
+(*type ty78*)
+(*type ty79*)
+(*type ty80*)
+(*type ty81*)
+(*type ty82*)
+(*type ty83*)
+(*type ty84*)
+(*type ty85*)
+(*type ty86*)
+(*type ty87*)
+(*type ty88*)
+(*type ty89*)
+(*type ty90*)
+(*type ty91*)
+(*type ty92*)
+(*type ty93*)
+(*type ty94*)
+(*type ty95*)
+(*type ty96*)
+(*type ty97*)
+(*type ty98*)
+(*type ty99*)
+(*type ty100*)
+(*type ty101*)
+(*type ty102*)
+(*type ty103*)
+(*type ty104*)
+(*type ty105*)
+(*type ty106*)
+(*type ty107*)
+(*type ty108*)
+(*type ty109*)
+(*type ty110*)
+(*type ty111*)
+(*type ty112*)
+(*type ty113*)
+(*type ty114*)
+(*type ty115*)
+(*type ty116*)
+(*type ty117*)
+(*type ty118*)
+(*type ty119*)
+(*type ty120*)
+(*type ty121*)
+(*type ty122*)
+(*type ty123*)
+(*type ty124*)
+(*type ty125*)
+(*type ty126*)
+(*type ty127*)
+(*type ty128*)
+(*type ty129*)
+(*type ty130*)
+(*type ty131*)
+(*type ty132*)
+(*type ty133*)
+(*type ty134*)
+(*type ty135*)
+(*type ty136*)
+(*type ty137*)
+(*type ty138*)
+(*type ty139*)
+(*type ty140*)
+(*type ty141*)
+(*type ty142*)
+(*type ty143*)
+(*type ty144*)
+(*type ty145*)
+(*type ty146*)
+(*type ty147*)
+(*type ty148*)
+(*type ty149*)
+(*type ty150*)
+(*type ty151*)
+(*type ty152*)
+(*type ty153*)
+(*type ty154*)
+(*type ty155*)
+(*type ty156*)
+(*type ty157*)
+(*type ty158*)
+(*type ty159*)
+(*type ty160*)
+(*type ty161*)
+(*type ty162*)
+(*type ty163*)
+(*type ty164*)
+(*type ty165*)
+(*type ty166*)
+(*type ty167*)
+(*type ty168*)
+(*type ty169*)
+(*type ty170*)
+(*type ty171*)
+(*type ty172*)
+(*type ty173*)
+(*type ty174*)
+(*type ty175*)
+(*type ty176*)
+(*type ty177*)
+(*type ty178*)
+(*type ty179*)
+(*type ty180*)
+(*type ty181*)
+(*type ty182*)
+(*type ty183*)
+(*type ty184*)
+(*type ty185*)
+(*type ty186*)
+(*type ty187*)
+(*type ty188*)
+(*type ty189*)
+(*type ty190*)
+(*type ty191*)
+(*type ty192*)
+(*type ty193*)
+(*type ty194*)
+(*type ty195*)
+(*type ty196*)
+(*type ty197*)
+(*type ty198*)
+(*type ty199*)
+(*type ty200*)
+(*type ty201*)
+(*type ty202*)
+(*type ty203*)
+(*type ty204*)
+(*type ty205*)
+(*type ty206*)
+(*type ty207*)
+(*type ty208*)
+(*type ty209*)
+(*type ty210*)
+(*type ty211*)
+(*type ty212*)
+(*type ty213*)
+(*type ty214*)
+(*type ty215*)
+(*type ty216*)
+(*type ty217*)
+(*type ty218*)
+(*type ty219*)
+(*type ty220*)
+(*type ty221*)
+(*type ty222*)
+(*type ty223*)
+(*type ty224*)
+(*type ty225*)
+(*type ty226*)
+(*type ty227*)
+(*type ty228*)
+(*type ty229*)
+(*type ty230*)
+(*type ty231*)
+(*type ty232*)
+(*type ty233*)
+(*type ty234*)
+(*type ty235*)
+(*type ty236*)
+(*type ty237*)
+(*type ty238*)
+(*type ty239*)
+(*type ty240*)
+(*type ty241*)
+(*type ty242*)
+(*type ty243*)
+(*type ty244*)
+(*type ty245*)
+(*type ty246*)
+(*type ty247*)
+(*type ty248*)
+(*type ty249*)
+(*type ty250*)
+(*type ty251*)
+(*type ty252*)
+(*type ty253*)
+(*type ty254*)
+(*type ty255*)
+(*type ty256*)
+(*type ty257*)
+
+(*val word_length : forall 'a. mword 'a -> nat*)
+
+(******************************************************************)
+(* Conversions                                                    *)
+(******************************************************************)
+
+(*val signedIntegerFromWord : forall 'a. mword 'a -> Num.integer*)
+
+(*val unsignedIntegerFromWord : forall 'a. mword 'a -> Num.integer*)
+
+(* Version without typeclass constraint so that we can derive operations
+   in Lem for one of the theorem provers without requiring it. *)
+(*val proverWordFromInteger : forall 'a. Num.integer -> mword 'a*)
+
+(*val wordFromInteger : forall 'a. Size 'a => Num.integer -> mword 'a*)
+(* The OCaml version is defined after the arithmetic operations, below. *)
+
+(*val naturalFromWord : forall 'a. mword 'a -> Num.natural*)
+
+(*val wordFromNatural : forall 'a. Size 'a => Num.natural -> mword 'a*)
+
+(*val wordToHex : forall 'a. mword 'a -> string*)
+
+val _ = Define `
+((instance_Show_Show_Machine_word_mword_dict:('a words$word)lem_show$Show_class)= (<|
+
+  show_method := words$word_to_hex_string|>))`;
+
+
+(*val wordFromBitlist : forall 'a. Size 'a => list bool -> mword 'a*)
+
+(*val bitlistFromWord : forall 'a. mword 'a -> list bool*)
+
+
+(*val size_test_fn : forall 'a. Size 'a => mword 'a -> nat*)
+val _ = Define `
+ ((size_test_fn:'a words$word -> num) _=  (dimindex (the_value : 'a itself)))`;
+
+
+(******************************************************************)
+(* Comparisons                                                    *)
+(******************************************************************)
+
+(*val mwordEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val signedLess : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val signedLessEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val unsignedLess : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(*val unsignedLessEq : forall 'a. mword 'a -> mword 'a -> bool*)
+
+(* Comparison tests are below, after the definition of wordFromInteger *)
+
+(******************************************************************)
+(* Appending, splitting and probing words                         *)
+(******************************************************************)
+
+(*val word_concat : forall 'a 'b 'c. mword 'a -> mword 'b -> mword 'c*)
+
+(* Note that we assume the result type has the correct size, especially
+   for Isabelle. *)
+(*val word_extract : forall 'a 'b. nat -> nat -> mword 'a -> mword 'b*)
+
+(*  Needs to be in the prover because we'd end up with unknown sizes in the
+   types in Lem.
+*)
+(*val word_update : forall 'a 'b. mword 'a -> nat -> nat -> mword 'b -> mword 'a*)
+
+(*val setBit : forall 'a. mword 'a -> nat -> bool -> mword 'a*)
+
+(*val getBit : forall 'a. mword 'a -> nat -> bool*)
+
+(*val msb : forall 'a. mword 'a -> bool*)
+
+(*val lsb : forall 'a. mword 'a -> bool*)
+
+(******************************************************************)
+(* Bitwise operations, shifts, etc.                               *)
+(******************************************************************)
+
+(*val shiftLeft  : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val shiftRight : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val arithShiftRight : forall 'a. mword 'a -> nat -> mword 'a*)
+
+(*val lAnd       : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lOr        : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lXor       : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val lNot       : forall 'a. mword 'a -> mword 'a*)
+
+(*val rotateRight : forall 'a. nat -> mword 'a -> mword 'a*)
+
+(*val rotateLeft : forall 'a. nat -> mword 'a -> mword 'a*)
+
+(*val zeroExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*)
+
+(*val signExtend : forall 'a 'b. Size 'b => mword 'a -> mword 'b*)
+
+(* Sign extension tests are below, after the definition of wordFromInteger *)
+
+(*****************************************************************)
+(* Arithmetic                                                    *)
+(*****************************************************************)
+
+(*val plus   : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val minus  : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val uminus : forall 'a. mword 'a -> mword 'a*)
+
+(*val times : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val unsignedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+(*val signedDivide : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+
+(*val modulo : forall 'a. mword 'a -> mword 'a -> mword 'a*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_mapScript.sml b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml
new file mode 100644
index 00000000..a85a9d67
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_mapScript.sml
@@ -0,0 +1,153 @@
+(*Generated by Lem from map.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_maybeTheory lem_listTheory lem_tupleTheory lem_setTheory lem_numTheory finite_mapTheory finite_mapLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_map"
+
+
+
+(*open import Bool Basic_classes Function Maybe List Tuple Set Num*)
+(*open import {hol} `finite_mapTheory` `finite_mapLib`*)
+
+(*type map 'k 'v*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* Map equality.                                                              *)
+(* -------------------------------------------------------------------------- *)
+
+(*val mapEqual : forall 'k 'v. Eq 'k, Eq 'v => map 'k 'v -> map 'k 'v -> bool*)
+(*val mapEqualBy : forall 'k 'v. ('k -> 'k -> bool) -> ('v -> 'v -> bool) -> map 'k 'v -> map 'k 'v -> bool*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Map type class                                                             *)
+(* -------------------------------------------------------------------------- *)
+
+(*class ( MapKeyType 'a )
+  val {ocaml;coq} mapKeyCompare : 'a -> 'a -> Basic_classes.ordering
+end*)
+
+(* -------------------------------------------------------------------------- *)
+(* Empty maps                                                                 *)
+(* -------------------------------------------------------------------------- *)
+
+(*val empty : forall 'k 'v. MapKeyType 'k => map 'k 'v*)
+(*val emptyBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Insertion                                                                  *)
+(* -------------------------------------------------------------------------- *)
+
+(*val insert    : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Singleton                                                                  *)
+(* -------------------------------------------------------------------------- *)
+
+(*val singleton : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* Emptyness check                                                            *)
+(* -------------------------------------------------------------------------- *)
+
+(*val null  : forall 'k 'v. MapKeyType 'k, Eq 'k, Eq 'v => map 'k 'v -> bool*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* lookup                                                                     *)
+(* -------------------------------------------------------------------------- *)
+
+(*val lookupBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> Maybe.maybe 'v*)
+
+(*val lookup          : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> Maybe.maybe 'v*)
+
+(* -------------------------------------------------------------------------- *)
+(* findWithDefault                                                            *)
+(* -------------------------------------------------------------------------- *)
+
+(*val findWithDefault : forall 'k 'v. MapKeyType 'k => 'k -> 'v -> map 'k 'v -> 'v*)
+
+(* -------------------------------------------------------------------------- *)
+(* from lists                                                                 *)
+(* -------------------------------------------------------------------------- *)
+
+(*val fromList  : forall 'k 'v. MapKeyType 'k => list ('k * 'v) -> map 'k 'v*)
+(*let fromList l=  foldl (fun m (k,v) -> insert k v m) empty l*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* to sets / domain / range                                                   *)
+(* -------------------------------------------------------------------------- *)
+
+(*val toSet : forall 'k 'v. MapKeyType 'k, SetType 'k, SetType 'v => map 'k 'v -> set ('k * 'v)*) 
+(*val toSetBy : forall 'k 'v. (('k * 'v) -> ('k * 'v) -> Basic_classes.ordering) -> map 'k 'v -> set ('k * 'v)*)
+
+
+(*val domainBy : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> map 'k 'v -> set 'k*)
+(*val domain : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> set 'k*)
+
+
+(*val range : forall 'k 'v. MapKeyType 'k, SetType 'v => map 'k 'v -> set 'v*)
+(*val rangeBy : forall 'k 'v. ('v -> 'v -> Basic_classes.ordering) -> map 'k 'v -> set 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* member                                                                     *)
+(* -------------------------------------------------------------------------- *)
+
+(*val member          : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*)
+
+(*val notMember       : forall 'k 'v. MapKeyType 'k, SetType 'k, Eq 'k => 'k -> map 'k 'v -> bool*)
+
+(* -------------------------------------------------------------------------- *)
+(* Quantification                                                             *)
+(* -------------------------------------------------------------------------- *)
+
+(*val any : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) 
+(*val all : forall 'k 'v. MapKeyType 'k, Eq 'v => ('k -> 'v -> bool) -> map 'k 'v -> bool*) 
+
+(*let all P m=  (forall k v. (P k v && ((Instance_Basic_classes_Eq_Maybe_maybe.=) (lookup k m) (Just v))))*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Set-like operations.                                                       *)
+(* -------------------------------------------------------------------------- *)
+(*val deleteBy         : forall 'k 'v. ('k -> 'k -> Basic_classes.ordering) -> 'k -> map 'k 'v -> map 'k 'v*)
+(*val delete           : forall 'k 'v. MapKeyType 'k => 'k -> map 'k 'v -> map 'k 'v*)
+(*val deleteSwap      : forall 'k 'v. MapKeyType 'k => map 'k 'v -> 'k -> map 'k 'v*)
+
+(*val union          : forall 'k 'v. MapKeyType 'k => map 'k 'v -> map 'k 'v -> map 'k 'v*)
+
+(*val unions           : forall 'k 'v. MapKeyType 'k => list (map 'k 'v) -> map 'k 'v*)
+
+
+(* -------------------------------------------------------------------------- *)
+(* Maps (in the functor sense).                                               *)
+(* -------------------------------------------------------------------------- *)
+
+(*val map             : forall 'k 'v 'w. MapKeyType 'k => ('v -> 'w) -> map 'k 'v -> map 'k 'w*)
+
+(*val mapi : forall 'k 'v 'w. MapKeyType 'k => ('k -> 'v -> 'w) -> map 'k 'v -> map 'k 'w*)
+
+(* -------------------------------------------------------------------------- *)
+(* Cardinality                                                                *)
+(* -------------------------------------------------------------------------- *)
+(*val size  : forall 'k 'v. MapKeyType 'k, SetType 'k => map 'k 'v -> nat*)
+
+(* instance of SetType *)
+val _ = Define `
+ ((map_setElemCompare:(('d#'c)set ->('b#'a)set -> 'e) ->('d,'c)fmap ->('b,'a)fmap -> 'e) cmp x y=  
+ (cmp (FMAP_TO_SET x) (FMAP_TO_SET y)))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml
new file mode 100644
index 00000000..57a258f8
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_map_extraScript.sml
@@ -0,0 +1,72 @@
+(*Generated by Lem from map_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory lem_assert_extraTheory lem_maybeTheory lem_listTheory lem_numTheory lem_setTheory lem_mapTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_map_extra"
+
+
+
+(*open import Bool Basic_classes Function Assert_extra Maybe List Num Set Map*)
+
+(* -------------------------------------------------------------------------- *)
+(* find                                                                       *)
+(* -------------------------------------------------------------------------- *)
+
+(*val find : forall 'k 'v. MapKeyType 'k => 'k -> Map.map 'k 'v -> 'v*)
+(*let find k m=  match (lookup k m) with Just x -> x | Nothing -> failwith "Map_extra.find" end*)
+
+
+
+(* -------------------------------------------------------------------------- *)
+(* from sets / domain / range                                                 *)
+(* -------------------------------------------------------------------------- *)
+
+
+(*val fromSet : forall 'k 'v. MapKeyType 'k => ('k -> 'v) -> set 'k -> Map.map 'k 'v*)
+(*let fromSet f s=  Set_helpers.fold (fun k m -> Map.insert k (f k) m) s Map.empty*)
+
+(*
+assert fromSet_0: (fromSet succ (Set.empty : set nat) = Map.empty)
+assert fromSet_1: (fromSet succ {(2:nat); 3; 4}) = Map.fromList [(2,3); (3, 4); (4, 5)]
+*)
+
+(* -------------------------------------------------------------------------- *)
+(* fold                                                                       *)
+(* -------------------------------------------------------------------------- *)
+
+(*val fold : forall 'k 'v 'r. MapKeyType 'k, SetType 'k, SetType 'v => ('k -> 'v -> 'r -> 'r) -> Map.map 'k 'v -> 'r -> 'r*)
+val _ = Define `
+ ((fold:('k -> 'v -> 'r -> 'r) ->('k,'v)fmap -> 'r -> 'r) f m v=  (ITSET (\ (k, v) r .  f k v r) (FMAP_TO_SET m) v))`;
+
+
+(*
+assert fold_1: (fold (fun k v a -> (a+k)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 9)
+assert fold_2: (fold (fun k v a -> (a+v)) (Map.fromList [((2:nat),(3:nat)); (3, 4); (4, 5)]) 0 = 12)
+*)
+
+(*val toList: forall 'k 'v. MapKeyType 'k => Map.map 'k 'v -> list ('k * 'v)*)
+(* declare compile_message toList = "Map_extra.toList is only defined for the ocaml, isabelle and coq backend" *)
+
+(* more 'map' functions *)
+
+(* TODO: this function is in map_extra rather than map just for implementation reasons *)
+(*val mapMaybe : forall 'a 'b 'c. MapKeyType 'a => ('a -> 'b -> Maybe.maybe 'c) -> Map.map 'a 'b -> Map.map 'a 'c*)
+(* OLD: TODO: mapMaybe depends on toList that is not defined for hol and isabelle *)
+val _ = Define `
+ ((option_map:('a -> 'b -> 'c option) ->('a,'b)fmap ->('a,'c)fmap) f m=  
+ (FOLDL
+    (\ m' (k, v) . 
+      (case f k v of
+          NONE => m'
+        | SOME v' =>m' |+ (k, v')
+      ))
+    FEMPTY
+    (MAP_TO_LIST m)))`;
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml
new file mode 100644
index 00000000..29562d66
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_maybeScript.sml
@@ -0,0 +1,112 @@
+(*Generated by Lem from maybe.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_functionTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_maybe"
+
+ 
+
+(*open import Bool Basic_classes Function*)
+
+(* ========================================================================== *)
+(* Basic stuff                                                                *)
+(* ========================================================================== *)
+
+(*type maybe 'a = 
+  | Nothing
+  | Just of 'a*)
+
+
+(*val maybeEqual : forall 'a. Eq 'a => maybe 'a -> maybe 'a -> bool*)
+(*val maybeEqualBy : forall 'a. ('a -> 'a -> bool) -> maybe 'a -> maybe 'a -> bool*)
+
+val _ = Define `
+ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE NONE=  T)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq NONE (SOME _)=  F)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME _) NONE=  F)
+/\ ((maybeEqualBy:('a -> 'a -> bool) -> 'a option -> 'a option -> bool) eq (SOME x') (SOME y')=  (eq x' y'))`;
+  
+
+
+val _ = Define `
+ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE NONE=  EQ)
+/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp NONE (SOME _)=  LT)
+/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME _) NONE=  GT)
+/\ ((maybeCompare:('b -> 'a -> lem_basic_classes$ordering) -> 'b option -> 'a option -> lem_basic_classes$ordering) cmp (SOME x') (SOME y')=  (cmp x' y'))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Maybe_maybe_dict:'a lem_basic_classes$Ord_class ->('a option)lem_basic_classes$Ord_class)dict_Basic_classes_Ord_a= (<|
+
+  compare_method := (maybeCompare  
+  dict_Basic_classes_Ord_a.compare_method);
+
+  isLess_method := (\ m1 .  (\ m2 .  maybeCompare  
+  dict_Basic_classes_Ord_a.compare_method m1 m2 = LT));
+
+  isLessEqual_method := (\ m1 .  (\ m2 .  (let r = (maybeCompare  
+  dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = LT) \/ (r = EQ))));
+
+  isGreater_method := (\ m1 .  (\ m2 .  maybeCompare  
+  dict_Basic_classes_Ord_a.compare_method m1 m2 = GT));
+
+  isGreaterEqual_method := (\ m1 .  (\ m2 .  (let r = (maybeCompare  
+  dict_Basic_classes_Ord_a.compare_method m1 m2) in (r = GT) \/ (r = EQ))))|>))`;
+
+
+(* ----------------------- *)
+(* maybe                   *)
+(* ----------------------- *)
+
+(*val maybe : forall 'a 'b. 'b -> ('a -> 'b) -> maybe 'a -> 'b*)
+(*let maybe d f mb=  match mb with 
+  | Just a -> f a
+  | Nothing -> d
+end*)
+
+(* ----------------------- *)
+(* isJust / isNothing      *)
+(* ----------------------- *)
+
+(*val isJust : forall 'a. maybe 'a -> bool*)
+(*let isJust mb=  match mb with 
+  | Just _ -> true
+  | Nothing -> false
+end*)
+
+(*val isNothing : forall 'a. maybe 'a -> bool*)
+(*let isNothing mb=  match mb with 
+  | Just _ -> false
+  | Nothing -> true
+end*)
+
+(* ----------------------- *)
+(* fromMaybe               *)
+(* ----------------------- *)
+
+(*val fromMaybe : forall 'a. 'a -> maybe 'a -> 'a*)
+(*let fromMaybe d mb=  match mb with
+   | Just v  -> v
+   | Nothing -> d
+end*)
+
+(* ----------------------- *)
+(* map                     *)
+(* ----------------------- *)
+
+(*val map : forall 'a 'b. ('a -> 'b) -> maybe 'a -> maybe 'b*) 
+(*let map f=  maybe Nothing (fun v -> Just (f v))*)
+
+
+(* ----------------------- *)
+(* bind                    *)
+(* ----------------------- *)
+
+(*val bind : forall 'a 'b. maybe 'a -> ('a -> maybe 'b) -> maybe 'b*) 
+(*let bind mb f=  maybe Nothing f mb*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml
new file mode 100644
index 00000000..6b04d291
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_maybe_extraScript.sml
@@ -0,0 +1,23 @@
+(*Generated by Lem from maybe_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_basic_classesTheory lem_maybeTheory lem_assert_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_maybe_extra"
+
+ 
+
+(*open import Basic_classes Maybe Assert_extra*)
+
+(* ----------------------- *)
+(* fromJust                *)
+(* ----------------------- *)
+
+(*val fromJust : forall 'a. Maybe.maybe 'a -> 'a*)
+(*let fromJust op=  match op with | Just v -> v | Nothing -> failwith "fromJust of Nothing" end*)
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_numScript.sml b/snapshots/hol4/lem/hol-lib/lem_numScript.sml
new file mode 100644
index 00000000..9dcd0554
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_numScript.sml
@@ -0,0 +1,1317 @@
+(*Generated by Lem from num.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory integerTheory intReduce wordsTheory wordsLib ratTheory realTheory intrealTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_num"
+
+
+
+(*open import Bool Basic_classes*)
+(*open import {isabelle} `~~/src/HOL/Word/Word` `Real` `~~/src/HOL/NthRoot`*)
+(*open import {hol} `integerTheory` `intReduce` `wordsTheory` `wordsLib` `ratTheory` `realTheory` `intrealTheory`*)
+(*open import {coq} `Coq.Numbers.BinNums` `Coq.ZArith.BinInt` `Coq.ZArith.Zpower` `Coq.ZArith.Zdiv` `Coq.ZArith.Zmax` `Coq.Numbers.Natural.Peano.NPeano` `Coq.QArith.Qabs` `Coq.QArith.Qminmax` `Coq.Reals.ROrderedType` `Coq.Reals.Rbase` `Coq.Reals.Rfunctions`*) 
+
+(*class inline ( Numeral 'a ) 
+  val fromNumeral : numeral -> 'a 
+end*)
+
+(* ========================================================================== *)
+(* Syntactic type-classes for common operations                               *)
+(* ========================================================================== *)
+
+(* Typeclasses can be used as a mean to overload constants like "+", "-", etc *)
+
+val _ = Hol_datatype `
+(*  'a *) NumNegate_class= <| 
+  numNegate_method : 'a -> 'a 
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumAbs_class= <| 
+  abs_method : 'a -> 'a 
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumAdd_class= <| 
+  numAdd_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumMinus_class= <| 
+  numMinus_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumMult_class= <| 
+  numMult_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumPow_class= <| 
+  numPow_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumDivision_class= <| 
+  numDivision_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumIntegerDivision_class= <| 
+  div_method : 'a -> 'a -> 'a
+|>`;
+
+
+
+val _ = Hol_datatype `
+(*  'a *) NumRemainder_class= <| 
+  mod_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumSucc_class= <| 
+  succ_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) NumPred_class= <| 
+  pred_method : 'a -> 'a
+|>`;
+ 
+
+
+(* ----------------------- *)
+(* natural                 *)
+(* ----------------------- *)
+
+(* unbounded size natural numbers *)
+(*type natural*)
+
+
+(* ----------------------- *)
+(* int                     *)
+(* ----------------------- *)
+
+(* bounded size integers with uncertain length *)
+
+(*type int*)
+
+
+(* ----------------------- *)
+(* integer                 *)
+(* ----------------------- *)
+
+(* unbounded size integers *)
+
+(*type integer*)
+
+(* ----------------------- *)
+(* bint                    *)
+(* ----------------------- *)
+
+(* TODO the bounded ints are only partially implemented, use with care. *)
+
+(* 32 bit integers *)
+(*type int32*) 
+
+(* 64 bit integers *)
+(*type int64*) 
+
+
+(* ----------------------- *)
+(* rational                *)
+(* ----------------------- *)
+
+(* unbounded size and precision rational numbers *)
+
+(*type rational*) (* ???: better type for this in HOL? *)
+
+
+(* ----------------------- *)
+(* real                    *)
+(* ----------------------- *)
+
+(* real numbers *)
+(* Note that for OCaml, this is mapped to floats with 64 bits. *)
+
+(*type real*) (* ???: better type for this in HOL? *)
+
+
+(* ----------------------- *)
+(* double                  *)
+(* ----------------------- *)
+
+(* double precision floating point (64 bits) *)
+
+(*type float64*) (* ???: better type for this in HOL? *)
+
+(*type float32*) (* ???: better type for this in HOL? *)
+
+
+(* ========================================================================== *)
+(* Binding the standard operations for the number types                       *)
+(* ========================================================================== *)
+
+
+(* ----------------------- *)
+(* nat                     *)
+(* ----------------------- *)
+
+(*val natFromNumeral : numeral -> nat*)
+
+(*val natEq : nat -> nat -> bool*)
+
+(*val natLess : nat -> nat -> bool*)
+(*val natLessEqual : nat -> nat -> bool*)
+(*val natGreater : nat -> nat -> bool*)
+(*val natGreaterEqual : nat -> nat -> bool*)
+
+(*val natCompare : nat -> nat -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_nat_dict:(num)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val natAdd : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumAdd_nat_dict:(num)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val natMinus : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumMinus_nat_dict:(num)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val natSucc : nat -> nat*)
+(*let natSucc n=  (Instance_Num_NumAdd_nat.+) n 1*)
+val _ = Define `
+((instance_Num_NumSucc_nat_dict:(num)NumSucc_class)= (<|
+
+  succ_method := SUC|>))`;
+
+
+(*val natPred : nat -> nat*)
+val _ = Define `
+((instance_Num_NumPred_nat_dict:(num)NumPred_class)= (<|
+
+  pred_method := PRE|>))`;
+
+
+(*val natMult : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumMult_nat_dict:(num)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+(*val natDiv : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_nat_dict:(num)NumIntegerDivision_class)= (<|
+
+  div_method := (DIV)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_nat_dict:(num)NumDivision_class)= (<|
+
+  numDivision_method := (DIV)|>))`;
+
+
+(*val natMod : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumRemainder_nat_dict:(num)NumRemainder_class)= (<|
+
+  mod_method := (MOD)|>))`;
+
+
+
+(*val gen_pow_aux : forall 'a. ('a -> 'a -> 'a) -> 'a -> 'a -> nat -> 'a*)
+ val _ = Define `
+ ((gen_pow_aux:('a -> 'a -> 'a) -> 'a -> 'a -> num -> 'a) (mul : 'a -> 'a -> 'a) (a : 'a) (b : 'a) (e : num)=   
+ ((case e of
+       0 => a (* cannot happen, call discipline guarentees e >= 1 *)
+     | (SUC 0) => mul a b
+     | (  (SUC(SUC e'))) => let e'' = (e DIV( 2 : num)) in
+                   let a' = (if (e MOD( 2 : num)) =( 0 : num) then a else mul a b) in
+                   gen_pow_aux mul a' (mul b b) e''
+   )))`;
+
+       
+val _ = Define `
+ ((gen_pow:'a ->('a -> 'a -> 'a) -> 'a -> num -> 'a) (one1 : 'a) (mul : 'a -> 'a -> 'a) (b : 'a) (e : num) : 'a=  
+  (if e <( 0 : num) then one1 else 
+  if (e =( 0 : num)) then one1 else gen_pow_aux mul one1 b e))`;
+
+
+(*val natPow : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Num_NumPow_nat_dict:(num)NumPow_class)= (<|
+
+  numPow_method := ( ** )|>))`;
+
+
+(*val natMin : nat -> nat -> nat*)
+
+(*val natMax : nat -> nat -> nat*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_nat_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := MAX;
+
+  min_method := MIN|>))`;
+
+
+
+(* ----------------------- *)
+(* natural                 *)
+(* ----------------------- *)
+
+(*val naturalFromNumeral : numeral -> natural*)
+
+(*val naturalEq : natural -> natural -> bool*)
+
+(*val naturalLess : natural -> natural -> bool*)
+(*val naturalLessEqual : natural -> natural -> bool*)
+(*val naturalGreater : natural -> natural -> bool*)
+(*val naturalGreaterEqual : natural -> natural -> bool*)
+
+(*val naturalCompare : natural -> natural -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_natural_dict:(num)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val naturalAdd : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_natural_dict:(num)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val naturalMinus : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_natural_dict:(num)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val naturalSucc : natural -> natural*)
+(*let naturalSucc n=  (Instance_Num_NumAdd_Num_natural.+) n 1*)
+val _ = Define `
+((instance_Num_NumSucc_Num_natural_dict:(num)NumSucc_class)= (<|
+
+  succ_method := SUC|>))`;
+
+
+(*val naturalPred : natural -> natural*)
+val _ = Define `
+((instance_Num_NumPred_Num_natural_dict:(num)NumPred_class)= (<|
+
+  pred_method := PRE|>))`;
+
+
+(*val naturalMult : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_natural_dict:(num)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+
+(*val naturalPow : natural -> nat -> natural*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_natural_dict:(num)NumPow_class)= (<|
+
+  numPow_method := ( ** )|>))`;
+
+
+(*val naturalDiv : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_natural_dict:(num)NumIntegerDivision_class)= (<|
+
+  div_method := (DIV)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_natural_dict:(num)NumDivision_class)= (<|
+
+  numDivision_method := (DIV)|>))`;
+
+
+(*val naturalMod : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_natural_dict:(num)NumRemainder_class)= (<|
+
+  mod_method := (MOD)|>))`;
+
+
+(*val naturalMin : natural -> natural -> natural*)
+
+(*val naturalMax : natural -> natural -> natural*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_natural_dict:(num)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := MAX;
+
+  min_method := MIN|>))`;
+
+
+
+(* ----------------------- *)
+(* int                     *)
+(* ----------------------- *)
+
+(*val intFromNumeral : numeral -> int*)
+
+(*val intEq : int -> int -> bool*)
+
+(*val intLess : int -> int -> bool*)
+(*val intLessEqual : int -> int -> bool*)
+(*val intGreater : int -> int -> bool*)
+(*val intGreaterEqual : int -> int -> bool*)
+
+(*val intCompare : int -> int -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int_dict:(int)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val intNegate : int -> int*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int_dict:(int)NumNegate_class)= (<|
+
+  numNegate_method := (\ i. ~ i)|>))`;
+
+
+(*val intAbs : int -> int*) (* TODO: check *)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int_dict:(int)NumAbs_class)= (<|
+
+  abs_method := ABS|>))`;
+
+
+(*val intAdd : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int_dict:(int)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val intMinus : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int_dict:(int)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val intSucc : int -> int*)
+val _ = Define `
+((instance_Num_NumSucc_Num_int_dict:(int)NumSucc_class)= (<|
+
+  succ_method := (\ n. n +( 1 : int))|>))`;
+
+
+(*val intPred : int -> int*)
+val _ = Define `
+((instance_Num_NumPred_Num_int_dict:(int)NumPred_class)= (<|
+
+  pred_method := (\ n. n -( 1 : int))|>))`;
+
+
+(*val intMult : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int_dict:(int)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+
+(*val intPow : int -> nat -> int*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_int_dict:(int)NumPow_class)= (<|
+
+  numPow_method := ( ** )|>))`;
+
+
+(*val intDiv : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int_dict:(int)NumIntegerDivision_class)= (<|
+
+  div_method := (/)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int_dict:(int)NumDivision_class)= (<|
+
+  numDivision_method := (/)|>))`;
+
+
+(*val intMod : int -> int -> int*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int_dict:(int)NumRemainder_class)= (<|
+
+  mod_method := (%)|>))`;
+
+
+(*val intMin : int -> int -> int*)
+
+(*val intMax : int -> int -> int*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := int_max;
+
+  min_method := int_min|>))`;
+
+
+(* ----------------------- *)
+(* int32                   *)
+(* ----------------------- *)
+(*val int32FromNumeral : numeral -> int32*)
+
+(*val int32Eq : int32 -> int32 -> bool*)
+
+(*val int32Less : int32 -> int32 -> bool*)
+(*val int32LessEqual : int32 -> int32 -> bool*)
+(*val int32Greater : int32 -> int32 -> bool*)
+(*val int32GreaterEqual : int32 -> int32 -> bool*)
+
+(*val int32Compare : int32 -> int32 -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int32_dict:(word32)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val int32Negate : int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int32_dict:(word32)NumNegate_class)= (<|
+
+  numNegate_method := (\ i. ((- i) : word32))|>))`;
+
+
+(*val int32Abs : int32 -> int32*)
+val _ = Define `
+ ((int32Abs:word32 -> word32) i=  (if((n2w 0) : word32) <= i then i else ((- i) : word32)))`;
+
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int32_dict:(word32)NumAbs_class)= (<|
+
+  abs_method := int32Abs|>))`;
+
+
+
+(*val int32Add : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int32_dict:(word32)NumAdd_class)= (<|
+
+  numAdd_method := (\ i1 i2. ((word_add i1 i2) : word32))|>))`;
+
+
+(*val int32Minus : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int32_dict:(word32)NumMinus_class)= (<|
+
+  numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word32))|>))`;
+
+
+(*val int32Succ : int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumSucc_Num_int32_dict:(word32)NumSucc_class)= (<|
+
+  succ_method := (\ n.  ((word_add n (((n2w 1) : word32))) : word32))|>))`;
+
+
+(*val int32Pred : int32 -> int32*)
+val _ = Define `
+((instance_Num_NumPred_Num_int32_dict:(word32)NumPred_class)= (<|
+
+  pred_method := (\ n.  ((word_sub n (((n2w 1) : word32))) : word32))|>))`;
+
+
+(*val int32Mult : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int32_dict:(word32)NumMult_class)= (<|
+
+  numMult_method := (\ i1 i2. ((word_mul i1 i2) : word32))|>))`;
+
+
+
+(*val int32Pow : int32 -> nat -> int32*)
+val _ = Define `
+ ((int32Pow:word32 -> num -> word32)=  (gen_pow(((n2w 1) : word32)) (\ i1 i2. ((word_mul i1 i2) : word32))))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_int32_dict:(word32)NumPow_class)= (<|
+
+  numPow_method := int32Pow|>))`;
+
+
+(*val int32Div : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int32_dict:(word32)NumIntegerDivision_class)= (<|
+
+  div_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int32_dict:(word32)NumDivision_class)= (<|
+
+  numDivision_method := (\ i1 i2. ((word_div i1 i2) : word32))|>))`;
+
+
+(*val int32Mod : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int32_dict:(word32)NumRemainder_class)= (<|
+
+  mod_method := (\ i1 i2. ((word_mod i1 i2) : word32))|>))`;
+
+
+(*val int32Min : int32 -> int32 -> int32*)
+
+(*val int32Max : int32 -> int32 -> int32*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int32_dict:(word32)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := word_smax;
+
+  min_method := word_smin|>))`;
+
+
+
+
+(* ----------------------- *)
+(* int64                   *)
+(* ----------------------- *)
+(*val int64FromNumeral : numeral -> int64*)
+
+(*val int64Eq : int64 -> int64 -> bool*)
+
+(*val int64Less : int64 -> int64 -> bool*)
+(*val int64LessEqual : int64 -> int64 -> bool*)
+(*val int64Greater : int64 -> int64 -> bool*)
+(*val int64GreaterEqual : int64 -> int64 -> bool*)
+
+(*val int64Compare : int64 -> int64 -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_int64_dict:(word64)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val int64Negate : int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_int64_dict:(word64)NumNegate_class)= (<|
+
+  numNegate_method := (\ i. ((- i) : word64))|>))`;
+
+
+(*val int64Abs : int64 -> int64*)
+val _ = Define `
+ ((int64Abs:word64 -> word64) i=  (if((n2w 0) : word64) <= i then i else ((- i) : word64)))`;
+
+
+val _ = Define `
+((instance_Num_NumAbs_Num_int64_dict:(word64)NumAbs_class)= (<|
+
+  abs_method := int64Abs|>))`;
+
+
+
+(*val int64Add : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_int64_dict:(word64)NumAdd_class)= (<|
+
+  numAdd_method := (\ i1 i2. ((word_add i1 i2) : word64))|>))`;
+
+
+(*val int64Minus : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_int64_dict:(word64)NumMinus_class)= (<|
+
+  numMinus_method := (\ i1 i2. ((word_sub i1 i2) : word64))|>))`;
+
+
+(*val int64Succ : int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumSucc_Num_int64_dict:(word64)NumSucc_class)= (<|
+
+  succ_method := (\ n.  ((word_add n (((n2w 1) : word64))) : word64))|>))`;
+
+
+(*val int64Pred : int64 -> int64*)
+val _ = Define `
+((instance_Num_NumPred_Num_int64_dict:(word64)NumPred_class)= (<|
+
+  pred_method := (\ n.  ((word_sub n (((n2w 1) : word64))) : word64))|>))`;
+
+
+(*val int64Mult : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_int64_dict:(word64)NumMult_class)= (<|
+
+  numMult_method := (\ i1 i2. ((word_mul i1 i2) : word64))|>))`;
+
+
+
+(*val int64Pow : int64 -> nat -> int64*)
+val _ = Define `
+ ((int64Pow:word64 -> num -> word64)=  (gen_pow(((n2w 1) : word64)) (\ i1 i2. ((word_mul i1 i2) : word64))))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_int64_dict:(word64)NumPow_class)= (<|
+
+  numPow_method := int64Pow|>))`;
+
+
+(*val int64Div : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_int64_dict:(word64)NumIntegerDivision_class)= (<|
+
+  div_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_int64_dict:(word64)NumDivision_class)= (<|
+
+  numDivision_method := (\ i1 i2. ((word_div i1 i2) : word64))|>))`;
+
+
+(*val int64Mod : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_int64_dict:(word64)NumRemainder_class)= (<|
+
+  mod_method := (\ i1 i2. ((word_mod i1 i2) : word64))|>))`;
+
+
+(*val int64Min : int64 -> int64 -> int64*)
+
+(*val int64Max : int64 -> int64 -> int64*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_int64_dict:(word64)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := word_smax;
+
+  min_method := word_smin|>))`;
+
+
+
+(* ----------------------- *)
+(* integer                 *)
+(* ----------------------- *)
+
+(*val integerFromNumeral : numeral -> integer*)
+
+(*val integerFromNat : nat -> integer*) (* TODO: check *)
+
+(*val integerEq : integer -> integer -> bool*)
+
+(*val integerLess : integer -> integer -> bool*)
+(*val integerLessEqual : integer -> integer -> bool*)
+(*val integerGreater : integer -> integer -> bool*)
+(*val integerGreaterEqual : integer -> integer -> bool*)
+
+(*val integerCompare : integer -> integer -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_integer_dict:(int)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val integerNegate : integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_integer_dict:(int)NumNegate_class)= (<|
+
+  numNegate_method := (\ i. ~ i)|>))`;
+
+
+(*val integerAbs : integer -> integer*) (* TODO: check *)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_integer_dict:(int)NumAbs_class)= (<|
+
+  abs_method := ABS|>))`;
+
+
+(*val integerAdd : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_integer_dict:(int)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val integerMinus : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_integer_dict:(int)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val integerSucc : integer -> integer*)
+val _ = Define `
+((instance_Num_NumSucc_Num_integer_dict:(int)NumSucc_class)= (<|
+
+  succ_method := (\ n. n +( 1 : int))|>))`;
+
+
+(*val integerPred : integer -> integer*)
+val _ = Define `
+((instance_Num_NumPred_Num_integer_dict:(int)NumPred_class)= (<|
+
+  pred_method := (\ n. n -( 1 : int))|>))`;
+
+
+(*val integerMult : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_integer_dict:(int)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+
+(*val integerPow : integer -> nat -> integer*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_integer_dict:(int)NumPow_class)= (<|
+
+  numPow_method := ( ** )|>))`;
+
+
+(*val integerDiv : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Num_integer_dict:(int)NumIntegerDivision_class)= (<|
+
+  div_method := (/)|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Num_integer_dict:(int)NumDivision_class)= (<|
+
+  numDivision_method := (/)|>))`;
+
+
+(*val integerMod : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Num_NumRemainder_Num_integer_dict:(int)NumRemainder_class)= (<|
+
+  mod_method := (%)|>))`;
+
+
+(*val integerMin : integer -> integer -> integer*)
+
+(*val integerMax : integer -> integer -> integer*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_integer_dict:(int)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := int_max;
+
+  min_method := int_min|>))`;
+
+
+
+
+(* ----------------------- *)
+(* rational                *)
+(* ----------------------- *)
+
+(*val rationalFromNumeral : numeral -> rational*)
+
+(*val rationalFromInt : int -> rational*)
+
+(*val rationalEq : rational -> rational -> bool*)
+
+(*val rationalLess : rational -> rational -> bool*)
+(*val rationalLessEqual : rational -> rational -> bool*)
+(*val rationalGreater : rational -> rational -> bool*)
+(*val rationalGreaterEqual : rational -> rational -> bool*)
+
+(*val rationalCompare : rational -> rational -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_rational_dict:(rat)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val rationalAdd : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_rational_dict:(rat)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val rationalMinus : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_rational_dict:(rat)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val rationalNegate : rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_rational_dict:(rat)NumNegate_class)= (<|
+
+  numNegate_method := (\ n. ( 0 : rat) - n)|>))`;
+
+
+(*val rationalAbs : rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_rational_dict:(rat)NumAbs_class)= (<|
+
+  abs_method := (\ n. (if n >( 0 : rat) then n else( 0 : rat) - n))|>))`;
+
+
+(*val rationalSucc : rational -> rational*)
+val _ = Define `
+((instance_Num_NumSucc_Num_rational_dict:(rat)NumSucc_class)= (<|
+
+  succ_method := (\ n. n +( 1 : rat))|>))`;
+
+
+(*val rationalPred : rational -> rational*)
+val _ = Define `
+((instance_Num_NumPred_Num_rational_dict:(rat)NumPred_class)= (<|
+
+  pred_method := (\ n. n -( 1 : rat))|>))`;
+
+
+(*val rationalMult : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_rational_dict:(rat)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+(*val rationalDiv : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Num_NumDivision_Num_rational_dict:(rat)NumDivision_class)= (<|
+
+  numDivision_method := (/)|>))`;
+
+
+(*val rationalFromFrac : int -> int -> rational*)
+(*let rationalFromFrac n d=  (Instance_Num_NumDivision_Num_rational./) (rationalFromInt n) (rationalFromInt d)*)
+
+(*val rationalPowInteger : rational -> integer -> rational*)
+ val rationalPowInteger_defn = Hol_defn "rationalPowInteger" `
+ ((rationalPowInteger:rat -> int -> rat) b e=  
+ (if e =( 0 : int) then( 1 : rat) else
+  if e >( 0 : int) then rationalPowInteger b (e -( 1 : int)) * b else
+  rationalPowInteger b (e +( 1 : int)) / b))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn rationalPowInteger_defn;
+
+(*val rationalPowNat : rational -> nat -> rational*)
+val _ = Define `
+ ((rationalPowNat:rat -> num -> rat) r e=  (rationalPowInteger r (int_of_num e)))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Num_rational_dict:(rat)NumPow_class)= (<|
+
+  numPow_method := rationalPowNat|>))`;
+
+
+(*val rationalMin : rational -> rational -> rational*)
+
+(*val rationalMax : rational -> rational -> rational*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_rational_dict:(rat)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := (maxByLessEqual (<=));
+
+  min_method := (minByLessEqual (<=))|>))`;
+
+
+
+
+(* ----------------------- *)
+(* real                    *)
+(* ----------------------- *)
+
+(*val realFromNumeral : numeral -> real*)
+
+(*val realFromInteger : integer -> real*)
+
+(*val realEq : real -> real -> bool*)
+
+(*val realLess : real -> real -> bool*)
+(*val realLessEqual : real -> real -> bool*)
+(*val realGreater : real -> real -> bool*)
+(*val realGreaterEqual : real -> real -> bool*)
+
+(*val realCompare : real -> real -> Basic_classes.ordering*)
+
+val _ = Define `
+((instance_Basic_classes_Ord_Num_real_dict:(real)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (genericCompare (<) (=));
+
+  isLess_method := (<);
+
+  isLessEqual_method := (<=);
+
+  isGreater_method := (>);
+
+  isGreaterEqual_method := (>=)|>))`;
+
+
+(*val realAdd : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumAdd_Num_real_dict:(real)NumAdd_class)= (<|
+
+  numAdd_method := (+)|>))`;
+
+
+(*val realMinus : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumMinus_Num_real_dict:(real)NumMinus_class)= (<|
+
+  numMinus_method := (-)|>))`;
+
+
+(*val realNegate : real -> real*)
+
+val _ = Define `
+((instance_Num_NumNegate_Num_real_dict:(real)NumNegate_class)= (<|
+
+  numNegate_method := (\ n. (real_of_num 0) - n)|>))`;
+
+
+(*val realAbs : real -> real*)
+
+val _ = Define `
+((instance_Num_NumAbs_Num_real_dict:(real)NumAbs_class)= (<|
+
+  abs_method := (\ n. (if n >(real_of_num 0) then n else(real_of_num 0) - n))|>))`;
+
+
+(*val realSucc : real -> real*)
+val _ = Define `
+((instance_Num_NumSucc_Num_real_dict:(real)NumSucc_class)= (<|
+
+  succ_method := (\ n. n +(real_of_num 1))|>))`;
+
+
+(*val realPred : real -> real*)
+val _ = Define `
+((instance_Num_NumPred_Num_real_dict:(real)NumPred_class)= (<|
+
+  pred_method := (\ n. n -(real_of_num 1))|>))`;
+
+
+(*val realMult : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumMult_Num_real_dict:(real)NumMult_class)= (<|
+
+  numMult_method := ( * )|>))`;
+
+
+(*val realDiv : real -> real -> real*)
+
+val _ = Define `
+((instance_Num_NumDivision_Num_real_dict:(real)NumDivision_class)= (<|
+
+  numDivision_method := (/)|>))`;
+
+
+(*val realFromFrac : integer -> integer -> real*)
+val _ = Define `
+ ((realFromFrac:int -> int -> real) n d=  (((real_of_int n)) / ((real_of_int d))))`;
+
+
+(*val realPowInteger : real -> integer -> real*)
+ val realPowInteger_defn = Hol_defn "realPowInteger" `
+ ((realPowInteger:real -> int -> real) b e=  
+ (if e =( 0 : int) then(real_of_num 1) else
+  if e >( 0 : int) then realPowInteger b (e -( 1 : int)) * b else
+  realPowInteger b (e +( 1 : int)) / b))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn realPowInteger_defn;
+
+(*val realPowNat : real -> nat -> real*)
+(*let realPowNat r e=  realPowInteger r (integerFromNat e)*)
+
+val _ = Define `
+((instance_Num_NumPow_Num_real_dict:(real)NumPow_class)= (<|
+
+  numPow_method := (pow)|>))`;
+
+
+(*val realSqrt : real -> real*)
+
+(*val realMin : real -> real -> real*)
+
+(*val realMax : real -> real -> real*)
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Num_real_dict:(real)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := max;
+
+  min_method := min|>))`;
+
+
+(*val realCeiling : real -> integer*)
+
+(*val realFloor : real -> integer*)
+
+(* ========================================================================== *)
+(* Translation between number types                                           *)
+(* ========================================================================== *)
+
+(******************)
+(* integerFrom... *)
+(******************)
+
+(*val integerFromInt : int -> integer*)
+
+(*val integerFromNatural : natural -> integer*)
+
+
+(*val integerFromInt32 : int32 -> integer*)
+
+
+(*val integerFromInt64 : int64 -> integer*)
+
+
+(******************)
+(* naturalFrom... *)
+(******************)
+
+(*val naturalFromNat : nat -> natural*)
+
+(*val naturalFromInteger : integer -> natural*)
+
+
+(******************)
+(* intFrom ...    *)
+(******************)
+
+(*val intFromInteger : integer -> int*)
+
+(*val intFromNat : nat -> int*)
+
+
+(******************)
+(* natFrom ...    *)
+(******************)
+
+(*val natFromNatural : natural -> nat*)
+
+(*val natFromInt : int -> nat*)
+
+
+(******************)
+(* int32From ...  *)
+(******************)
+
+(*val int32FromNat : nat -> int32*)
+
+(*val int32FromNatural : natural -> int32*)
+
+(*val int32FromInteger : integer -> int32*)
+val _ = Define `
+ ((int32FromInteger:int -> word32) i=  (
+  let abs_int32 = (((n2w (Num (ABS i))) : word32)) in
+  if (i <( 0 : int)) then (((- abs_int32) : word32)) else abs_int32 
+))`;
+
+
+(*val int32FromInt : int -> int32*)
+val _ = Define `
+ ((int32FromInt:int -> word32) i=  (int32FromInteger ( i)))`;
+
+
+
+(*val int32FromInt64 : int64 -> int32*)
+(*let int32FromInt64 i=  int32FromInteger (integerFromInt64 i)*)
+
+
+
+
+(******************)
+(* int64From ...  *)
+(******************)
+
+(*val int64FromNat : nat -> int64*)
+
+(*val int64FromNatural : natural -> int64*)
+
+(*val int64FromInteger : integer -> int64*)
+val _ = Define `
+ ((int64FromInteger:int -> word64) i=  (
+  let abs_int64 = (((n2w (Num (ABS i))) : word64)) in
+  if (i <( 0 : int)) then (((- abs_int64) : word64)) else abs_int64 
+))`;
+
+
+(*val int64FromInt : int -> int64*)
+val _ = Define `
+ ((int64FromInt:int -> word64) i=  (int64FromInteger ( i)))`;
+
+
+
+(*val int64FromInt32 : int32 -> int64*)
+(*let int64FromInt32 i=  int64FromInteger (integerFromInt32 i)*)
+
+
+(******************)
+(* what's missing *)
+(******************)
+
+(*val naturalFromInt : int -> natural*)
+(*val naturalFromInt32 : int32 -> natural*)
+(*val naturalFromInt64 : int64 -> natural*)
+
+
+(*val intFromNatural : natural -> int*)
+(*val intFromInt32 : int32 -> int*)
+(*val intFromInt64 : int64 -> int*)
+
+(*val natFromInteger : integer -> nat*)
+(*val natFromInt32 : int32 -> nat*)
+(*val natFromInt64 : int64 -> nat*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml
new file mode 100644
index 00000000..69644f94
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_num_extraScript.sml
@@ -0,0 +1,34 @@
+(*Generated by Lem from num_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_numTheory lem_stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_num_extra"
+
+(* **************************************************** *)
+(*                                                      *)
+(* A library of additional functions on numbers         *)
+(*                                                      *)
+(* **************************************************** *)
+
+(*open import Num*)
+(*open import String*)
+
+(*val naturalOfString : string -> Num.natural*)
+
+(*val integerOfString : string -> Num.integer*)
+
+
+(* Truncation integer division (round toward zero) *)
+(*val integerDiv_t: Num.integer -> Num.integer -> Num.integer*)
+
+(* Truncation modulo *)
+(*val integerRem_t: Num.integer -> Num.integer -> Num.integer*)
+
+(* Flooring modulo *)
+(*val integerRem_f: Num.integer -> Num.integer -> Num.integer*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml b/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml
new file mode 100644
index 00000000..34c8b4ae
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_pervasivesScript.sml
@@ -0,0 +1,18 @@
+(*Generated by Lem from pervasives.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_basic_classesTheory lem_boolTheory lem_tupleTheory lem_maybeTheory lem_eitherTheory lem_functionTheory lem_numTheory lem_mapTheory lem_setTheory lem_listTheory lem_stringTheory lem_wordTheory lem_showTheory lem_sortingTheory lem_relationTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_pervasives"
+
+ 
+
+(*include import Basic_classes Bool Tuple Maybe Either Function Num Map Set List String Word Show*)
+
+(*import Sorting Relation*)
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml
new file mode 100644
index 00000000..33ccd627
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_pervasives_extraScript.sml
@@ -0,0 +1,16 @@
+(*Generated by Lem from pervasives_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_function_extraTheory lem_maybe_extraTheory lem_map_extraTheory lem_num_extraTheory lem_set_extraTheory lem_set_helpersTheory lem_list_extraTheory lem_string_extraTheory lem_assert_extraTheory lem_show_extraTheory lem_machine_wordTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_pervasives_extra"
+
+ 
+
+(*include import Pervasives*) 
+(*include import Function_extra Maybe_extra Map_extra Num_extra Set_extra Set_helpers List_extra String_extra Assert_extra Show_extra Machine_word*)
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_relationScript.sml b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml
new file mode 100644
index 00000000..e73b66ce
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_relationScript.sml
@@ -0,0 +1,448 @@
+(*Generated by Lem from relation.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_tupleTheory lem_setTheory lem_numTheory set_relationTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_relation"
+
+
+
+(*open import Bool Basic_classes Tuple Set Num*)
+(*open import {hol} `set_relationTheory`*)
+
+(* ========================================================================== *)
+(* The type of relations                                                      *)
+(* ========================================================================== *)
+
+val _ = type_abbrev((* ( 'a, 'b) *) "rel_pred" , ``: 'a -> 'b -> bool``);
+val _ = type_abbrev((* ( 'a, 'b) *) "rel_set" , ``: ('a # 'b) set``);
+
+(* Binary relations are usually represented as either
+   sets of pairs (rel_set) or as curried functions (rel_pred). 
+   
+   The choice depends on taste and the backend. Lem should not take a 
+   decision, but supports both representations. There is an abstract type
+   pred, which can be converted to both representations. The representation
+   of pred itself then depends on the backend. However, for the time beeing,
+   let's implement relations as sets to get them working more quickly. *)
+
+val _ = type_abbrev((* ( 'a, 'b) *) "rel" , ``: ('a, 'b) rel_set``);
+
+(*val relToSet : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel_set 'a 'b*)
+(*val relFromSet : forall 'a 'b. SetType 'a, SetType 'b => rel_set 'a 'b -> rel 'a 'b*)
+
+(*val relEq : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> bool*)
+val _ = Define `
+ ((relEq:('a#'b)set ->('a#'b)set -> bool) r1 r2=  (r1 = r2))`;
+
+
+(*val relToPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel_pred 'a 'b*)
+(*val relFromPred : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => set 'a -> set 'b -> rel_pred 'a 'b -> rel 'a 'b*)
+
+(*let relToPred r=  (fun x y -> (x, y) IN relToSet r)*)
+val _ = Define `
+ ((relFromPred:'a set -> 'b set ->('a -> 'b -> bool) ->('a#'b)set) xs ys p=  (SET_FILTER (\ (x,y) .  p x y) (xs CROSS ys)))`;
+
+
+ 
+(* ========================================================================== *)
+(* Basic Operations                                                           *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* membership test         *)
+(* ----------------------- *)
+
+(*val inRel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => 'a -> 'b -> rel 'a 'b -> bool*)
+
+
+(* ----------------------- *)
+(* empty relation          *)
+(* ----------------------- *)
+
+(*val relEmpty : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b*)
+
+(* ----------------------- *)
+(* Insertion               *)
+(* ----------------------- *)
+
+(*val relAdd : forall 'a 'b. SetType 'a, SetType 'b => 'a -> 'b -> rel 'a 'b -> rel 'a 'b*)
+
+
+(* ----------------------- *)
+(* Identity relation       *)
+(* ----------------------- *)
+
+(*val relIdOn : forall 'a. SetType 'a, Eq 'a => set 'a -> rel 'a 'a*)
+val _ = Define `
+ ((relIdOn:'a set ->('a#'a)set) s=  (relFromPred s s (=)))`;
+
+
+(*val relId : forall 'a. SetType 'a, Eq 'a => rel 'a 'a*)
+val _ = Define `
+ ((relId:('a#'a)set)=  ({(x, x) |  x | T}))`;
+
+
+(* ----------------------- *)
+(* relation union          *)
+(* ----------------------- *)
+
+(*val relUnion : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) 
+
+(* ----------------------- *)
+(* relation intersection   *)
+(* ----------------------- *)
+
+(*val relIntersection : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> rel 'a 'b*) 
+
+(* ----------------------- *)
+(* Relation Composition    *)
+(* ----------------------- *)
+
+(*val relComp : forall 'a 'b 'c. SetType 'a, SetType 'b, SetType 'c, Eq 'a, Eq 'b => rel 'a 'b -> rel 'b 'c -> rel 'a 'c*)
+(*let relComp r1 r2=  relFromSet {(e1, e3) | forall ((e1,e2) IN (relToSet r1)) ((e2',e3) IN (relToSet r2)) | e2 = e2'}*)
+
+(* ----------------------- *)
+(* restrict                *)
+(* ----------------------- *)
+
+(*val relRestrict : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*)
+(*let relRestrict r s=  relFromSet ({ (a, b) | forall (a IN s) (b IN s) | inRel a b r })*)
+
+
+(* ----------------------- *)
+(* Converse                *)
+(* ----------------------- *)
+
+(*val relConverse : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> rel 'b 'a*)
+val _ = Define `
+ ((lem_converse:('a#'b)set ->('b#'a)set) r=  (IMAGE SWAP (r)))`;
+
+
+
+(* ----------------------- *)
+(* domain                  *)
+(* ----------------------- *)
+
+(*val relDomain : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'a*)
+(*let relDomain r=  Set.map (fun x -> fst x) (relToSet r)*)
+
+(* ----------------------- *)
+(* range                   *)
+(* ----------------------- *)
+
+(*val relRange : forall 'a 'b. SetType 'a, SetType 'b => rel 'a 'b -> set 'b*)
+(*let relRange r=  Set.map (fun x -> snd x) (relToSet r)*)
+
+
+(* ----------------------- *)
+(* field / definedOn       *)
+(*                         *)
+(* avoid the keyword field *)
+(* ----------------------- *)
+
+(*val relDefinedOn : forall 'a. SetType 'a => rel 'a 'a -> set 'a*)
+
+(* ----------------------- *)
+(* relOver                 *)
+(*                         *)
+(* avoid the keyword field *)
+(* ----------------------- *)
+
+(*val relOver : forall 'a. SetType 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((rel_over:('a#'a)set -> 'a set -> bool) r s=  ((((domain r) UNION (range r))) SUBSET s))`;
+
+
+
+(* ----------------------- *)
+(* apply a relation        *)
+(* ----------------------- *)
+
+(* Given a relation r and a set s, relApply r s applies s to r, i.e.
+   it returns the set of all value reachable via r from a value in s.
+   This operation can be seen as a generalisation of function application. *)
+   
+(*val relApply : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a => rel 'a 'b -> set 'a -> set 'b*)
+val _ = Define `
+ ((rapply:('a#'b)set -> 'a set -> 'b set) r s= 
+  ({ y | x, y | ((x, y) IN (r)) /\ (x IN s) }))`;
+
+
+
+(* ========================================================================== *)
+(* Properties                                                                 *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* subrel                  *)
+(* ----------------------- *)
+
+(*val isSubrel : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> rel 'a 'b -> bool*)
+
+(* ----------------------- *)
+(* reflexivity             *)
+(* ----------------------- *)
+
+(*val isReflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_reflexive_on:('a#'a)set -> 'a set -> bool) r s=  (! (e :: s). (e, e) IN r))`;
+
+
+(*val isReflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_reflexive:('a#'a)set -> bool) r=  (! e. (e, e) IN r))`;
+
+
+
+(* ----------------------- *)
+(* irreflexivity           *)
+(* ----------------------- *)
+
+(*val isIrreflexiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+(*let isIrreflexiveOn r s=  (forall (e IN s). not (inRel e e r))*)
+
+(*val isIrreflexive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_irreflexive:('a#'a)set -> bool) r=  (! ((e1, e2) :: (r)). ~ (e1 = e2)))`;
+
+
+
+(* ----------------------- *)
+(* symmetry                *)
+(* ----------------------- *)
+
+(*val isSymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_symmetric_on:('a#'a)set -> 'a set -> bool) r s=  (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> ((e2, e1) IN r)))`;
+
+
+(*val isSymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_symmetric:('a#'a)set -> bool) r=  (! ((e1, e2) :: r). (e2, e1) IN r))`;
+
+
+
+(* ----------------------- *)
+(* antisymmetry            *)
+(* ----------------------- *)
+
+(*val isAntisymmetricOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_antisymmetric_on:('a#'a)set -> 'a set -> bool) r s=  (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) ==> (((e2, e1) IN r) ==> (e1 = e2))))`;
+
+
+(*val isAntisymmetric : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let isAntisymmetric r=  (forall ((e1, e2) IN relToSet r). (inRel e2 e1 r) --> (e1 = e2))*)
+
+
+(* ----------------------- *)
+(* transitivity            *)
+(* ----------------------- *)
+
+(*val isTransitiveOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_transitive_on:('a#'a)set -> 'a set -> bool) r s=  (! (e1 :: s) (e2 :: s) (e3 :: s). ((e1, e2) IN r) ==> (((e2, e3) IN r) ==> ((e1, e3) IN r))))`;
+
+
+(*val isTransitive : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let isTransitive r=  (forall ((e1, e2) IN relToSet r) (e3 IN relApply r {e2}). inRel e1 e3 r)*)
+
+(* ----------------------- *)
+(* total                   *)
+(* ----------------------- *)
+
+(*val isTotalOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_on:('a#'a)set -> 'a set -> bool) r s=  (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e2, e1) IN r)))`;
+
+
+
+(*val isTotal : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_total:('a#'a)set -> bool) r=  (! e1 e2. ((e1, e2) IN r) \/ ((e2, e1) IN r)))`;
+
+
+(*val isTrichotomousOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_trichotomous_on:('a#'a)set -> 'a set -> bool) r s=  (! (e1 :: s) (e2 :: s). ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`;
+
+
+(*val isTrichotomous : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_trichotomous:('a#'a)set -> bool) r=  (! e1 e2. ((e1, e2) IN r) \/ ((e1 = e2) \/ ((e2, e1) IN r))))`;
+
+
+
+(* ----------------------- *)
+(* is_single_valued        *)
+(* ----------------------- *)
+
+(*val isSingleValued : forall 'a 'b. SetType 'a, SetType 'b, Eq 'a, Eq 'b => rel 'a 'b -> bool*)
+val _ = Define `
+ ((lem_is_single_valued:('a#'b)set -> bool) r=  (! ((e1, e2a) :: r) (e2b :: rapply r {e1}). e2a = e2b))`;
+
+
+
+(* ----------------------- *)
+(* equivalence relation    *)
+(* ----------------------- *)
+
+(*val isEquivalenceOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_equivalence_on:('a#'a)set -> 'a set -> bool) r s=  (lem_is_reflexive_on r s /\ lem_is_symmetric_on r s /\ lem_transitive_on r s))`;
+
+
+
+(*val isEquivalence : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_equivalence:('a#'a)set -> bool) r=  (lem_is_reflexive r /\ lem_is_symmetric r /\ transitive r))`;
+
+
+
+(* ----------------------- *)
+(* well founded            *)
+(* ----------------------- *)
+
+(*val isWellFounded : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+(*let ~{ocaml;coq} isWellFounded r=  (forall P. (forall x. (forall y. inRel y x r --> P x) --> P x) --> (forall x. P x))*)
+
+
+(* ========================================================================== *)
+(* Orders                                                                     *)
+(* ========================================================================== *)
+
+
+(* ----------------------- *)
+(* pre- or quasiorders     *)
+(* ----------------------- *)
+
+(*val isPreorderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_preorder_on:('a#'a)set -> 'a set -> bool) r s=  (lem_is_reflexive_on r s /\ lem_transitive_on r s))`;
+
+
+(*val isPreorder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_preorder:('a#'a)set -> bool) r=  (lem_is_reflexive r /\ transitive r))`;
+
+
+
+(* ----------------------- *)
+(* partial orders          *)
+(* ----------------------- *)
+
+(*val isPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_partial_order_on:('a#'a)set -> 'a set -> bool) r s=  (lem_is_reflexive_on r s /\ lem_transitive_on r s /\ lem_is_antisymmetric_on r s))`;
+
+
+
+(*val isStrictPartialOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_partial_order_on:('a#'a)set -> 'a set -> bool) r s=  (irreflexive r s /\ lem_transitive_on r s))`;
+
+
+
+(*val isStrictPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_partial_order:('a#'a)set -> bool) r=  (lem_is_irreflexive r /\ transitive r))`;
+
+
+(*val isPartialOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_partial_order:('a#'a)set -> bool) r=  (lem_is_reflexive r /\ transitive r /\ antisym r))`;
+
+
+(* ----------------------- *)
+(* total / linear orders   *)
+(* ----------------------- *)
+
+(*val isTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_order_on:('a#'a)set -> 'a set -> bool) r s=  (lem_is_partial_order_on r s /\ lem_is_total_on r s))`;
+
+
+(*val isStrictTotalOrderOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_total_order_on:('a#'a)set -> 'a set -> bool) r s=  (lem_is_strict_partial_order_on r s /\ lem_is_trichotomous_on r s))`;
+
+
+(*val isTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_total_order:('a#'a)set -> bool) r=  (lem_is_partial_order r /\ lem_is_total r))`;
+
+
+(*val isStrictTotalOrder : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> bool*)
+val _ = Define `
+ ((lem_is_strict_total_order:('a#'a)set -> bool) r=  (lem_is_strict_partial_order r /\ lem_is_trichotomous r))`;
+
+
+
+
+(* ========================================================================== *)
+(* closures                                                                   *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* transitive closure      *)
+(* ----------------------- *)
+
+(*val transitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+(*val transitiveClosureByEq  : forall 'a. ('a -> 'a -> bool) -> rel 'a 'a -> rel 'a 'a*)
+(*val transitiveClosureByCmp : forall 'a. ('a * 'a -> 'a * 'a -> Basic_classes.ordering) -> rel 'a 'a -> rel 'a 'a*)
+
+
+(* ----------------------- *)
+(* transitive closure step *)
+(* ----------------------- *)
+
+(*val transitiveClosureAdd : forall 'a. SetType 'a, Eq 'a => 'a -> 'a -> rel 'a 'a -> rel 'a 'a*)
+
+val _ = Define `
+ ((tc_insert:'a -> 'a ->('a#'a)set ->('a#'a)set) x y r=  
+  ((((((x,y) INSERT (r)))) UNION ((((({(x, z) | z | 
+  (z IN range r) /\ ((y, z) IN r)})) UNION (({(z, y) | z | 
+  (z IN domain r) /\ ((z, x) IN r)}))))))))`;
+
+
+
+(* ========================================================================== *)
+(* reflexive closure                                                          *)
+(* ========================================================================== *)
+
+(*val reflexiveTransitiveClosureOn : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> set 'a -> rel 'a 'a*)
+val _ = Define `
+ ((reflexive_transitive_closure_on:('a#'a)set -> 'a set ->('a#'a)set) r s=  (tc (((r) UNION ((relIdOn s))))))`;
+
+
+
+(*val reflexiveTransitiveClosure : forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+val _ = Define `
+ ((reflexiveTransitiveClosure:('a#'a)set ->('a#'a)set) r=  (tc (((r) UNION (relId)))))`;
+
+
+
+
+(* ========================================================================== *)
+(* inverse of closures                                                        *)
+(* ========================================================================== *)
+
+(* ----------------------- *)
+(* without transitve edges *)
+(* ----------------------- *)
+
+(*val withoutTransitiveEdges: forall 'a. SetType 'a, Eq 'a => rel 'a 'a -> rel 'a 'a*)
+val _ = Define `
+ ((withoutTransitiveEdges:('a#'a)set ->('a#'a)set) r=  
+ (let tc1 = (tc r) in
+  {(a, c) | a, c 
+  | ((a, c) IN r) /\
+   (! (b :: range r).
+      ((a <> b) /\ (b <> c)) ==> ~ (((a, b) IN tc1) /\ ((b, c) IN tc1)))}))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_setScript.sml b/snapshots/hol4/lem/hol-lib/lem_setScript.sml
new file mode 100644
index 00000000..7f553a68
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_setScript.sml
@@ -0,0 +1,317 @@
+(*Generated by Lem from set.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_set_helpersTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set"
+
+(******************************************************************************)
+(* A library for sets                                                         *)
+(*                                                                            *)
+(* It mainly follows the Haskell Set-library                                  *)
+(******************************************************************************)
+
+(* Sets in Lem are a bit tricky. On the one hand, we want efficiently executable sets.
+   OCaml and Haskell both represent sets by some kind of balancing trees. This means
+   that sets are finite and an order on the element type is required. 
+   Such sets are constructed by simple, executable operations like inserting or
+   deleting elements, union, intersection, filtering etc.
+
+   On the other hand, we want to use sets for specifications. This leads often
+   infinite sets, which are specificied in complicated, perhaps even undecidable
+   ways.
+
+   The set library in this file, chooses the first approach. It describes 
+   *finite* sets with an underlying order. Infinite sets should in the medium
+   run be represented by a separate type. Since this would require some significant
+   changes to Lem, for the moment also infinite sets are represented using this
+   class. However, a run-time exception might occour when using these sets. 
+   This problem needs adressing in the future. *)
+   
+
+(* ========================================================================== *)
+(* Header                                                                     *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num List Set_helpers*)
+
+(* DPM: sets currently implemented as lists due to mismatch between Coq type
+ * class hierarchy and the hierarchy implemented in Lem.
+ *)
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {hol} `lemTheory`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ----------------------- *)
+(* Equality check          *)
+(* ----------------------- *)
+
+(*val setEqualBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*)
+
+(*val setEqual : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+
+(* ----------------------- *)
+(* Empty set               *)
+(* ----------------------- *)
+
+(*val empty : forall 'a. SetType 'a => set 'a*) 
+(*val emptyBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a*)
+
+(* ----------------------- *)
+(* any / all               *)
+(* ----------------------- *)
+
+(*val any : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*)
+
+(*val all : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> bool*)
+
+
+(* ----------------------- *)
+(* (IN)                    *)
+(* ----------------------- *)
+
+(*val IN [member] : forall 'a. SetType 'a => 'a -> set 'a -> bool*) 
+(*val memberBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a -> bool*)
+
+(* ----------------------- *)
+(* not (IN)                *)
+(* ----------------------- *)
+
+(*val NIN [notMember] : forall 'a. SetType 'a => 'a -> set 'a -> bool*)
+
+
+
+(* ----------------------- *)
+(* Emptyness check         *)
+(* ----------------------- *)
+
+(*val null : forall 'a. SetType 'a => set 'a -> bool*)
+
+
+(* ------------------------ *)
+(* singleton                *)
+(* ------------------------ *)
+
+(*val singletonBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> set 'a*)
+(*val singleton : forall 'a. SetType 'a => 'a -> set 'a*)
+
+
+(* ----------------------- *)
+(* size                    *)
+(* ----------------------- *)
+
+(*val size : forall 'a. SetType 'a => set 'a -> nat*)
+
+
+(* ----------------------------*)
+(* setting up pattern matching *)
+(* --------------------------- *)
+
+(*val set_case : forall 'a 'b. SetType 'a => set 'a -> 'b -> ('a -> 'b) -> 'b -> 'b*)
+
+
+(* ------------------------ *)
+(* union                    *)
+(* ------------------------ *)
+
+(*val unionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*)
+(*val union : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+
+(* ----------------------- *)
+(* insert                  *)
+(* ----------------------- *)
+
+(*val insert : forall 'a. SetType 'a => 'a -> set 'a -> set 'a*)
+
+(* ----------------------- *)
+(* filter                  *)
+(* ----------------------- *)
+
+(*val filter : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a*) 
+(*let filter P s=  {e | forall (e IN s) | P e}*)
+
+
+(* ----------------------- *)
+(* partition               *)
+(* ----------------------- *)
+
+(*val partition : forall 'a. SetType 'a => ('a -> bool) -> set 'a -> set 'a * set 'a*)
+val _ = Define `
+ ((SET_PARTITION:('a -> bool) -> 'a set -> 'a set#'a set) P s=  (SET_FILTER P s, SET_FILTER (\ e .  ~ (P e)) s))`;
+
+
+
+(* ----------------------- *)
+(* split                   *)
+(* ----------------------- *)
+
+(*val split : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * set 'a*)
+val _ = Define `
+ ((SET_SPLIT:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#'a set)dict_Basic_classes_Ord_a p s=  (SET_FILTER (
+  dict_Basic_classes_Ord_a.isGreater_method p) s, SET_FILTER (dict_Basic_classes_Ord_a.isLess_method p) s))`;
+
+
+(*val splitMember : forall 'a. SetType 'a, Ord 'a => 'a -> set 'a -> set 'a * bool * set 'a*)
+val _ = Define `
+ ((splitMember:'a lem_basic_classes$Ord_class -> 'a -> 'a set -> 'a set#bool#'a set)dict_Basic_classes_Ord_a p s=  (SET_FILTER (
+  dict_Basic_classes_Ord_a.isLess_method p) s, (p IN s), SET_FILTER (
+  dict_Basic_classes_Ord_a.isGreater_method p) s))`;
+
+
+(* ------------------------ *)
+(* subset and proper subset *)
+(* ------------------------ *)
+
+(*val isSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*)
+(*val isProperSubsetOfBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> bool*)
+
+(*val isSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+(*val isProperSubsetOf : forall 'a. SetType 'a => set 'a -> set 'a -> bool*)
+
+
+(* ------------------------ *)
+(* delete                   *)
+(* ------------------------ *)
+
+(*val delete : forall 'a. SetType 'a, Eq 'a => 'a -> set 'a -> set 'a*)
+(*val deleteBy : forall 'a. SetType 'a => ('a -> 'a -> bool) -> 'a -> set 'a -> set 'a*)
+
+
+(* ------------------------ *)
+(* bigunion                 *)
+(* ------------------------ *)
+
+(*val bigunion : forall 'a. SetType 'a => set (set 'a) -> set 'a*)
+(*val bigunionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set (set 'a) -> set 'a*)
+
+(*let bigunion bs=  {x | forall (s IN bs) (x IN s) | true}*)
+
+(* ------------------------ *)
+(* big intersection         *)
+(* ------------------------ *)
+
+(* Shaked's addition, for which he is now forever responsible as a de facto
+ * Lem maintainer...
+ *)
+(*val bigintersection : forall 'a. SetType 'a => set (set 'a) -> set 'a*)
+val _ = Define `
+ ((bigintersection:('a set)set -> 'a set) bs= 
+  ({x | x | (x IN (BIGUNION bs)) /\ (! (s :: bs). x IN s)}))`;
+
+
+(* ------------------------ *)
+(* difference               *)
+(* ------------------------ *)
+
+(*val differenceBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*)
+(*val difference : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+
+(* ------------------------ *)
+(* intersection             *)
+(* ------------------------ *)
+
+(*val intersection : forall 'a. SetType 'a => set 'a -> set 'a -> set 'a*)
+(*val intersectionBy : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> set 'a*)
+
+
+(* ------------------------ *)
+(* map                      *)
+(* ------------------------ *)
+
+(*val map : forall 'a 'b. SetType 'a, SetType 'b => ('a -> 'b) -> set 'a -> set 'b*) (* before image *)
+(*let map f s=  { f e | forall (e IN s) | true }*)
+
+(*val mapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> 'b) -> set 'a -> set 'b*) 
+
+
+(* ------------------------ *)
+(* bigunionMap              *)
+(* ------------------------ *)
+
+(* In order to avoid providing an comparison function for sets of sets,
+   it might be better to combine bigunion and map sometimes into a single operation. *)
+
+(*val bigunionMap : forall 'a 'b. SetType 'a, SetType 'b => ('a -> set 'b) -> set 'a -> set 'b*)
+(*val bigunionMapBy : forall 'a 'b. ('b -> 'b -> Basic_classes.ordering) -> ('a -> set 'b) -> set 'a -> set 'b*)
+
+(* ------------------------ *)
+(* mapMaybe and fromMaybe   *)
+(* ------------------------ *)
+
+(* If the mapping function returns Just x, x is added to the result
+   set. If it returns Nothing, no element is added. *)
+
+(*val mapMaybe : forall 'a 'b. SetType 'a, SetType 'b => ('a -> Maybe.maybe 'b) -> set 'a -> set 'b*)
+val _ = Define `
+ ((setMapMaybe:('a -> 'b option) -> 'a set -> 'b set) f s=  
+  (BIGUNION (IMAGE (\ x .  (case f x of 
+                          SOME y  => {y} 
+                        | NONE => EMPTY
+                        )) s)))`;
+
+
+(*val removeMaybe : forall 'a. SetType 'a => set (Maybe.maybe 'a) -> set 'a*)
+val _ = Define `
+ ((removeMaybe:('a option)set -> 'a set) s=  (setMapMaybe (\ x .  x) s))`;
+
+
+(* ------------------------ *)
+(* min and max              *)
+(* ------------------------ *)
+
+(*val findMin : forall 'a.  SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*) 
+(*val findMax : forall 'a.  SetType 'a, Eq 'a => set 'a -> Maybe.maybe 'a*)
+
+(* ------------------------ *)
+(* fromList                 *)
+(* ------------------------ *)
+
+(*val fromList : forall 'a.  SetType 'a => list 'a -> set 'a*) (* before from_list *)
+(*val fromListBy : forall 'a.  ('a -> 'a -> Basic_classes.ordering) -> list 'a -> set 'a*) 
+
+
+(* ------------------------ *)
+(* Sigma                    *)
+(* ------------------------ *)
+
+(*val sigma : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> ('a -> set 'b) -> set ('a * 'b)*)
+(*val sigmaBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> ('a -> set 'b) -> set ('a * 'b)*)
+
+(*let sigma sa sb=  { (a, b) | forall (a IN sa) (b IN sb a) | true }*)
+
+
+(* ------------------------ *)
+(* cross product            *)
+(* ------------------------ *)
+
+(*val cross : forall 'a 'b. SetType 'a, SetType 'b => set 'a -> set 'b -> set ('a * 'b)*)
+(*val crossBy : forall 'a 'b. (('a * 'b) -> ('a * 'b) -> Basic_classes.ordering) -> set 'a -> set 'b -> set ('a * 'b)*)
+
+(*let cross s1 s2=  { (e1, e2) | forall (e1 IN s1) (e2 IN s2) | true }*)
+
+
+(* ------------------------ *)
+(* finite                   *)
+(* ------------------------ *)
+
+(*val finite : forall 'a. SetType 'a => set 'a -> bool*)
+
+
+(* ----------------------------*)
+(* fixed point                 *)
+(* --------------------------- *)
+
+(*val leastFixedPoint : forall 'a. SetType 'a 
+  => nat -> (set 'a -> set 'a) -> set 'a -> set 'a*)
+ val leastFixedPoint_defn = Defn.Hol_multi_defns `
+ ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) 0 f x=  x)
+/\ ((leastFixedPoint:num ->('a set -> 'a set) -> 'a set -> 'a set) ((SUC bound')) f x=  (let fx = (f x) in
+                  if fx SUBSET x then x
+                  else leastFixedPoint bound' f (fx UNION x)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) leastFixedPoint_defn; 
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml
new file mode 100644
index 00000000..5409a408
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_set_extraScript.sml
@@ -0,0 +1,118 @@
+(*Generated by Lem from set_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory lem_listTheory lem_sortingTheory lem_setTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set_extra"
+
+(******************************************************************************)
+(* A library for sets                                                         *)
+(*                                                                            *)
+(* It mainly follows the Haskell Set-library                                  *)
+(******************************************************************************)
+
+(* ========================================================================== *)
+(* Header                                                                     *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num List Sorting Set*)
+
+
+(* ----------------------------*)
+(* set choose (be careful !)   *)
+(* --------------------------- *)
+
+(*val choose : forall 'a. SetType 'a => set 'a -> 'a*)
+
+(* ------------------------ *)
+(* chooseAndSplit           *)
+(* ------------------------ *)
+(* The idea here is to provide a simple primitive that Lem code can use
+ * to perform its own custom searches within the set -- likely using a
+ * search criterion related to the element ordering, but not necessarily).
+ * For example, sometimes we don't necessarily want to search for a specific
+ * element, but want to search for elements greater than or less than some other.
+ * Someties we'd like to use "split" but don't know a good value to "split" at.
+ * This function lets the set implementation decide that value.
+ *
+ * The contract of chooseAndSplit is simply to select an element nondeterministically
+ * and return that element, together with the subsets of elements less than and
+ * greater than it. In this way, we can recursively traverse the set with any
+ * search criterion, and we avoid baking in the tree representation (although that
+ * is the obvious choice).
+ *)
+(*val chooseAndSplit : forall 'a. SetType 'a, Ord 'a => set 'a -> Maybe.maybe (set 'a * 'a * set 'a)*)
+val _ = Define `
+ ((chooseAndSplit:'a lem_basic_classes$Ord_class -> 'a set ->('a set#'a#'a set)option)dict_Basic_classes_Ord_a s=  
+ (if s = EMPTY then
+    NONE
+  else
+    let element1  = (CHOICE s) in
+    let (lt, gt) = (lem_set$SET_SPLIT 
+  dict_Basic_classes_Ord_a element1 s) in
+      SOME (lt, element1, gt)))`;
+
+
+(* ----------------------------*)
+(* universal set               *)
+(* --------------------------- *)
+
+(*val universal : forall 'a. SetType 'a => set 'a*)
+
+
+(* ----------------------------*)
+(* toList                      *)
+(* --------------------------- *)
+
+(*val toList        : forall 'a. SetType 'a => set 'a -> list 'a*)
+
+
+(* ----------------------------*)
+(* toOrderedList               *)
+(* --------------------------- *)
+
+(* "toOrderedList" returns a sorted list. Therefore the result is (given a suitable order) deterministic.
+   Therefore, it is much preferred to "toList". However, it still is only defined for finite sets. So, please
+   use carefully and consider using set-operations instead of translating sets to lists, performing list manipulations
+   and then transforming back to sets. *)
+
+(*val toOrderedListBy : forall 'a. ('a -> 'a -> bool) -> set 'a -> list 'a*)
+
+(*val toOrderedList : forall 'a. SetType 'a, Ord 'a => set 'a -> list 'a*)
+
+(* ----------------------- *)
+(* compare                 *)
+(* ----------------------- *)
+
+(*val setCompareBy: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> set 'a -> set 'a -> Basic_classes.ordering*)
+val _ = Define `
+ ((setCompareBy:('a -> 'a -> lem_basic_classes$ordering) -> 'a set -> 'a set -> lem_basic_classes$ordering) cmp ss ts=  
+ (let ss' = (ARB (\ x y .  cmp x y = LT) ss) in
+  let ts' = (ARB (\ x y .  cmp x y = LT) ts) in
+    lexicographic_compare cmp ss' ts'))`;
+
+
+(*val setCompare : forall 'a. SetType 'a, Ord 'a => set 'a -> set 'a -> Basic_classes.ordering*)
+val _ = Define `
+ ((setCompare:'a lem_basic_classes$Ord_class -> 'a set -> 'a set -> lem_basic_classes$ordering)dict_Basic_classes_Ord_a=  (setCompareBy  
+  dict_Basic_classes_Ord_a.compare_method))`;
+
+
+(* ----------------------------*)
+(* unbounded fixed point       *)
+(* --------------------------- *)
+
+(* Is NOT supported by the coq backend! *)
+(*val leastFixedPointUnbounded : forall 'a. SetType 'a => (set 'a -> set 'a) -> set 'a -> set 'a*)
+ val leastFixedPointUnbounded_defn = Hol_defn "leastFixedPointUnbounded" `
+ ((leastFixedPointUnbounded:('a set -> 'a set) -> 'a set -> 'a set) f x=   
+ (let fx = (f x) in
+   if fx SUBSET x then x
+   else leastFixedPointUnbounded f (fx UNION x)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn leastFixedPointUnbounded_defn;
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml b/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml
new file mode 100644
index 00000000..5ce9f938
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_set_helpersScript.sml
@@ -0,0 +1,47 @@
+(*Generated by Lem from set_helpers.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_functionTheory lem_numTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_set_helpers"
+
+(******************************************************************************)
+(* Helper functions for sets                                                  *)
+(******************************************************************************)
+
+(* Usually there is a something.lem file containing the main definitions and a 
+   something_extra.lem one containing functions that might cause problems for
+   some backends or are just seldomly used.
+
+   For sets the situation is different. folding is not well defined, since it
+   is only sensibly defined for finite sets and the traversal 
+   order is underspecified. *) 
+
+(* ========================================================================== *)
+(* Header                                                                     *)
+(* ========================================================================== *)
+
+(*open import Bool Basic_classes Maybe Function Num*) 
+
+(*open import {coq} `Coq.Lists.List`*)
+
+(* ------------------------ *)
+(* fold                     *)
+(* ------------------------ *)
+
+(* fold is suspicious, because if given a function, for which
+   the order, in which the arguments are given, matters, its
+   results are undefined. On the other hand, it is very handy to
+   define other - non suspicious functions. 
+
+   Moreover, fold is central for OCaml, since it is used to
+   compile set comprehensions *)
+
+(*val fold : forall 'a 'b. ('a -> 'b -> 'b) -> set 'a -> 'b -> 'b*)
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_showScript.sml b/snapshots/hol4/lem/hol-lib/lem_showScript.sml
new file mode 100644
index 00000000..1852c219
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_showScript.sml
@@ -0,0 +1,85 @@
+(*Generated by Lem from show.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lemTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_show"
+
+
+
+(*open import String Maybe Num Basic_classes*)
+
+(*open import {hol} `lemTheory`*)
+
+val _ = Hol_datatype `
+(*  'a *) Show_class= <|
+  show_method: 'a -> string
+|>`;
+
+
+val _ = Define `
+((instance_Show_Show_string_dict:(string)Show_class)= (<|
+
+  show_method := (\ s.  STRCAT"\""  (STRCAT s "\""))|>))`;
+
+
+(*val stringFromMaybe : forall 'a. ('a -> string) -> Maybe.maybe 'a -> string*)
+val _ = Define `
+ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX (SOME x)=   (STRCAT"Just ("  (STRCAT(showX x) ")")))
+/\ ((stringFromMaybe:('a -> string) -> 'a option -> string) showX NONE=  "Nothing")`;
+
+
+val _ = Define `
+((instance_Show_Show_Maybe_maybe_dict:'a Show_class ->('a option)Show_class)dict_Show_Show_a= (<|
+
+  show_method := (\ x_opt. stringFromMaybe  
+  dict_Show_Show_a.show_method x_opt)|>))`;
+
+
+(*val stringFromListAux : forall 'a. ('a -> string) -> list 'a -> string*)
+ val stringFromListAux_defn = Defn.Hol_multi_defns `
+ ((stringFromListAux:('a -> string) -> 'a list -> string) showX ([])=  "")
+/\ ((stringFromListAux:('a -> string) -> 'a list -> string) showX (x::xs')=      
+ ((case xs' of
+        [] => showX x
+      | _ =>  STRCAT(showX x)  (STRCAT"; " (stringFromListAux showX xs'))
+      )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) stringFromListAux_defn;
+
+(*val stringFromList : forall 'a. ('a -> string) -> list 'a -> string*)
+val _ = Define `
+ ((stringFromList:('a -> string) -> 'a list -> string) showX xs=   
+ (STRCAT"["  (STRCAT(stringFromListAux showX xs) "]")))`;
+
+
+val _ = Define `
+((instance_Show_Show_list_dict:'a Show_class ->('a list)Show_class)dict_Show_Show_a= (<|
+
+  show_method := (\ xs. stringFromList  
+  dict_Show_Show_a.show_method xs)|>))`;
+
+
+(*val stringFromPair : forall 'a 'b. ('a -> string) -> ('b -> string) -> ('a * 'b) -> string*)
+val _ = Define `
+ ((stringFromPair:('a -> string) ->('b -> string) -> 'a#'b -> string) showX showY (x,y)=   
+ (STRCAT"("  (STRCAT(showX x)  (STRCAT", "  (STRCAT(showY y) ")")))))`;
+
+
+val _ = Define `
+((instance_Show_Show_tup2_dict:'a Show_class -> 'b Show_class ->('a#'b)Show_class)dict_Show_Show_a dict_Show_Show_b= (<|
+
+  show_method := (stringFromPair  
+  dict_Show_Show_a.show_method  dict_Show_Show_b.show_method)|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_bool_dict:(bool)Show_class)= (<|
+
+  show_method := (\ b. if b then "true" else "false")|>))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml
new file mode 100644
index 00000000..d8e50e16
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_show_extraScript.sml
@@ -0,0 +1,67 @@
+(*Generated by Lem from show_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_stringTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_setTheory lem_relationTheory lem_showTheory lem_set_extraTheory lem_string_extraTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_show_extra"
+
+
+
+(*open import String Maybe Num Basic_classes Set Relation Show*) 
+(*import Set_extra String_extra*)
+
+val _ = Define `
+((instance_Show_Show_nat_dict:(num)lem_show$Show_class)= (<|
+
+  show_method := num_to_dec_string|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_natural_dict:(num)lem_show$Show_class)= (<|
+
+  show_method := num_to_dec_string|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_int_dict:(int)lem_show$Show_class)= (<|
+
+  show_method := lem_string_extra$stringFromInt|>))`;
+
+
+val _ = Define `
+((instance_Show_Show_Num_integer_dict:(int)lem_show$Show_class)= (<|
+
+  show_method := lem_string_extra$stringFromInteger|>))`;
+
+
+val _ = Define `
+ ((stringFromSet:('a -> string) -> 'a set -> string) showX xs=   
+ (STRCAT"{"  (STRCAT(lem_show$stringFromListAux showX (SET_TO_LIST xs)) "}")))`;
+
+
+(* Abbreviates the representation if the relation is transitive. *)
+val _ = Define `
+ ((stringFromRelation:('a#'a -> string) ->('a#'a)set -> string) showX rel=  
+ (if transitive rel then
+    let pruned_rel = (withoutTransitiveEdges rel) in
+    if (! (e :: rel). (e IN pruned_rel)) then
+      (* The relations are the same (there are no transitive edges),
+         so we can just as well print the original one. *)
+      stringFromSet showX rel
+    else
+       STRCAT"trancl of " (stringFromSet showX pruned_rel)
+  else
+    stringFromSet showX rel))`;
+
+
+val _ = Define `
+((instance_Show_Show_set_dict:'a lem_show$Show_class ->('a set)lem_show$Show_class)dict_Show_Show_a= (<|
+
+  show_method := (\ xs. stringFromSet  
+  dict_Show_Show_a.show_method xs)|>))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml
new file mode 100644
index 00000000..30f66e5e
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_sortingScript.sml
@@ -0,0 +1,107 @@
+(*Generated by Lem from sorting.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_maybeTheory lem_listTheory lem_numTheory sortingTheory permLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_sorting"
+
+
+
+(*open import Bool Basic_classes Maybe List Num*)
+
+(*open import {isabelle} `~~/src/HOL/Library/Permutation`*)
+(*open import {coq} `Coq.Lists.List`*)
+(*open import {hol} `sortingTheory` `permLib`*)
+(*open import {isabelle} `$LIB_DIR/Lem`*)
+
+(* ------------------------- *)
+(* permutations              *)
+(* ------------------------- *)
+
+(*val isPermutation : forall 'a. Eq 'a => list 'a -> list 'a -> bool*)
+(*val isPermutationBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a -> bool*)
+
+ val _ = Define `
+ ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq ([]) l2=  (NULL l2))
+/\ ((PERM_BY:('a -> 'a -> bool) -> 'a list -> 'a list -> bool) eq (x :: xs) l2=  ((
+      (case list_delete_first (eq x) l2 of
+          NONE => F
+        | SOME ys => PERM_BY eq xs ys
+      )
+    )))`;
+
+
+
+
+(* ------------------------- *)
+(* isSorted                  *)
+(* ------------------------- *)
+
+(* isSortedBy R l 
+   checks, whether the list l is sorted by ordering R. 
+   R should represent an order, i.e. it should be transitive.
+   Different backends defined "isSorted" slightly differently. However,
+   the definitions coincide for transitive R. Therefore there is the
+   following restriction:
+
+   WARNING: Use isSorted and isSortedBy only with transitive relations!
+*)
+
+(*val isSorted : forall 'a. Ord 'a => list 'a -> bool*)
+(*val isSortedBy : forall 'a. ('a -> 'a -> bool) -> list 'a -> bool*)
+
+(* DPM: rejigged the definition with a nested match to get past Coq's termination checker. *)
+(*let rec isSortedBy cmp l=  match l with
+  | [] -> true
+  | x1 :: xs ->
+    match xs with
+      | [] -> true
+      | x2 :: _ -> (cmp x1 x2 && isSortedBy cmp xs)
+    end
+end*)
+
+
+(* ----------------------- *)
+(* insertion sort          *)
+(* ----------------------- *) 
+
+(*val insert : forall 'a. Ord 'a => 'a -> list 'a -> list 'a*)
+(*val insertBy : forall 'a. ('a -> 'a -> bool) -> 'a -> list 'a -> list 'a*)
+
+(*val insertSort: forall 'a. Ord 'a => list 'a -> list 'a*)
+(*val insertSortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*)
+
+ val _ = Define `
+ ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e ([])=  ([e]))
+/\ ((INSERT_SORT_INSERT:('a -> 'a -> bool) -> 'a -> 'a list -> 'a list) cmp e (x :: xs)=  (if cmp x e then x :: (INSERT_SORT_INSERT cmp e xs) else (e :: (x :: xs))))`;
+
+
+val _ = Define `
+ ((INSERT_SORT:('a -> 'a -> bool) -> 'a list -> 'a list) cmp l=  (FOLDL (\ l e .  INSERT_SORT_INSERT cmp e l) [] l))`;
+
+
+
+(* ----------------------- *)
+(* general sorting         *)
+(* ----------------------- *) 
+
+(*val sort: forall 'a. Ord 'a => list 'a -> list 'a*)
+(*val sortBy: forall 'a. ('a -> 'a -> bool) -> list 'a -> list 'a*)
+(*val sortByOrd: forall 'a. ('a -> 'a -> Basic_classes.ordering) -> list 'a -> list 'a*)
+
+(*val predicate_of_ord : forall 'a. ('a -> 'a -> Basic_classes.ordering) -> 'a -> 'a -> bool*)
+val _ = Define `
+ ((predicate_of_ord:('a -> 'a -> lem_basic_classes$ordering) -> 'a -> 'a -> bool) f x y=  
+ ((case f x y of
+      LT => T
+    | EQ => T
+    | GT => F
+  )))`;
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_stringScript.sml b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml
new file mode 100644
index 00000000..9dd53778
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_stringScript.sml
@@ -0,0 +1,74 @@
+(*Generated by Lem from string.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory lem_listTheory lemTheory stringTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_string"
+
+
+
+(*open import Bool Basic_classes List*)
+(*open import {ocaml} `Xstring`*)
+(*open import {hol} `lemTheory` `stringTheory`*)
+(*open import {coq} `Coq.Strings.Ascii` `Coq.Strings.String`*)
+
+(* ------------------------------------------- *)
+(* translations between strings and char lists *)
+(* ------------------------------------------- *)
+
+(*val toCharList : string -> list char*)
+
+(*val toString : list char -> string*)
+
+
+(* ----------------------- *)
+(* generating strings      *)
+(* ----------------------- *)
+
+(*val makeString : nat -> char -> string*)
+(*let makeString len c=  toString (replicate len c)*)
+
+(* ----------------------- *)
+(* length                  *)
+(* ----------------------- *)
+
+(*val stringLength : string -> nat*)
+
+(* ----------------------- *)
+(* string concatenation    *)
+(* ----------------------- *)
+
+(*val ^ [stringAppend] : string -> string -> string*)
+
+
+(* ----------------------------*)
+(* setting up pattern matching *)
+(* --------------------------- *)
+
+(*val string_case : forall 'a. string -> 'a -> (char -> string -> 'a) -> 'a*)
+
+(*let string_case s c_empty c_cons= 
+  match (toCharList s) with
+    | [] -> c_empty
+    | c :: cs -> c_cons c (toString cs)
+  end*)
+
+(*val empty_string : string*)
+
+(*val cons_string : char -> string -> string*)
+
+(*val concat : string -> list string -> string*)
+ val concat_defn = Defn.Hol_multi_defns `
+ ((concat:string ->(string)list -> string) sep ([])=  "")
+/\ ((concat:string ->(string)list -> string) sep (s :: ss')=      
+ ((case ss' of
+        [] => s
+      | _ =>  STRCAT s  (STRCAT sep (concat sep ss'))
+      )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) (List.map Defn.save_defn) concat_defn;
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml
new file mode 100644
index 00000000..0801601a
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_string_extraScript.sml
@@ -0,0 +1,124 @@
+(*Generated by Lem from string_extra.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_numTheory lem_listTheory lem_basic_classesTheory lem_stringTheory lem_list_extraTheory ASCIInumbersTheory stringLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_string_extra"
+
+(******************************************************************************)
+(* String functions                                                           *)
+(******************************************************************************)
+
+(*open import Basic_classes*)
+(*open import Num*)
+(*open import List*)
+(*open import String*)
+(*open import List_extra*)
+(*open import {hol} `stringLib`*)
+(*open import {hol} `ASCIInumbersTheory`*)
+
+
+(******************************************************************************)
+(* Character's to numbers                                                     *)
+(******************************************************************************)
+
+(*val ord : char -> nat*)
+
+(*val chr : nat -> char*)
+
+(******************************************************************************)
+(* Converting to strings                                                      *)
+(******************************************************************************)
+
+(*val stringFromNatHelper : nat -> list char -> list char*)
+ val stringFromNatHelper_defn = Hol_defn "stringFromNatHelper" `
+ ((stringFromNatHelper:num ->(char)list ->(char)list) n acc=  
+ (if n =( 0 : num) then
+    acc
+  else
+    stringFromNatHelper (n DIV( 10 : num)) (CHR ((n MOD( 10 : num)) +( 48 : num)) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNatHelper_defn;
+
+(*val stringFromNat : nat -> string*)
+
+(*val stringFromNaturalHelper : Num.natural -> list char -> list char*)
+ val stringFromNaturalHelper_defn = Hol_defn "stringFromNaturalHelper" `
+ ((stringFromNaturalHelper:num ->(char)list ->(char)list) n acc=  
+ (if n =( 0:num) then
+    acc
+  else
+    stringFromNaturalHelper (n DIV( 10:num)) (CHR ((((n MOD( 10:num)) +( 48:num)):num)) :: acc)))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn stringFromNaturalHelper_defn;
+
+(*val stringFromNatural : Num.natural -> string*)
+
+(*val stringFromInt : Num.int -> string*)
+val _ = Define `
+ ((stringFromInt:int -> string) i=  
+  (if i <( 0 : int) then 
+     STRCAT"-" (num_to_dec_string (Num (ABS i)))
+  else
+    num_to_dec_string (Num (ABS i))))`;
+
+
+(*val stringFromInteger : Num.integer -> string*)
+val _ = Define `
+ ((stringFromInteger:int -> string) i=  
+  (if i <( 0 : int) then 
+     STRCAT"-" (num_to_dec_string (Num (ABS i)))
+  else
+    num_to_dec_string (Num (ABS i))))`;
+
+
+
+(******************************************************************************)
+(* List-like operations                                                       *)
+(******************************************************************************)
+
+(*val nth : string -> nat -> char*)
+(*let nth s n=  List_extra.nth (toCharList s) n*)
+
+(*val stringConcat : list string -> string*)
+(*let stringConcat s= 
+  List.foldr (^) "" s*)
+
+(******************************************************************************)
+(* String comparison                                                          *)
+(******************************************************************************)
+
+(*val stringCompare : string -> string -> Basic_classes.ordering*)
+
+val _ = Define `
+ ((stringLess:string -> string -> bool) x y=  (orderingIsLess (EQ)))`;
+
+val _ = Define `
+ ((stringLessEq:string -> string -> bool) x y=  (~ (orderingIsGreater (EQ))))`;
+
+val _ = Define `
+ ((stringGreater:string -> string -> bool) x y=  (stringLess y x))`;
+
+val _ = Define `
+ ((stringGreaterEq:string -> string -> bool) x y=  (stringLessEq y x))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_string_dict:(string)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := (\ x y. EQ);
+
+  isLess_method := stringLess;
+
+  isLessEqual_method := stringLessEq;
+
+  isGreater_method := stringGreater;
+
+  isGreaterEqual_method := stringGreaterEq|>))`;
+
+ 
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml b/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml
new file mode 100644
index 00000000..7ee21f63
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_tupleScript.sml
@@ -0,0 +1,51 @@
+(*Generated by Lem from tuple.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_basic_classesTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_tuple"
+
+ 
+
+(*open import Bool Basic_classes*)
+
+(* ----------------------- *)
+(* fst                     *)
+(* ----------------------- *)
+
+(*val fst : forall 'a 'b. 'a * 'b -> 'a*)
+(*let fst (v1, v2)=  v1*)
+
+(* ----------------------- *)
+(* snd                     *)
+(* ----------------------- *)
+
+(*val snd : forall 'a 'b. 'a * 'b -> 'b*)
+(*let snd (v1, v2)=  v2*)
+
+
+(* ----------------------- *)
+(* curry                   *)
+(* ----------------------- *)
+
+(*val curry : forall 'a 'b 'c. ('a * 'b -> 'c) -> ('a -> 'b -> 'c)*)
+
+(* ----------------------- *)
+(* uncurry                 *)
+(* ----------------------- *)
+
+(*val uncurry : forall 'a 'b 'c. ('a -> 'b -> 'c) -> ('a * 'b -> 'c)*)
+
+
+(* ----------------------- *)
+(* swap                    *)
+(* ----------------------- *)
+
+(*val swap : forall 'a 'b. ('a * 'b) -> ('b * 'a)*) 
+(*let swap (v1, v2)=  (v2, v1)*)
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/lem/hol-lib/lem_wordScript.sml b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml
new file mode 100644
index 00000000..690909a0
--- /dev/null
+++ b/snapshots/hol4/lem/hol-lib/lem_wordScript.sml
@@ -0,0 +1,1021 @@
+(*Generated by Lem from word.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_boolTheory lem_maybeTheory lem_numTheory lem_basic_classesTheory lem_listTheory wordsTheory wordsLib;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "lem_word"
+
+
+
+(*open import Bool Maybe Num Basic_classes List*)
+
+(*open import {isabelle} `~~/src/HOL/Word/Word`*)
+(*open import {hol} `wordsTheory` `wordsLib`*)
+
+
+(* ========================================================================== *)
+(* Define general purpose word, i.e. sequences of bits of arbitrary length    *)
+(* ========================================================================== *)
+
+val _ = Hol_datatype `
+ bitSequence = BitSeq of 
+    num option  => (* length of the sequence, Nothing means infinite length *)
+   bool => bool       (* sign of the word, used to fill up after concrete value is exhausted *)
+   list`;
+    (* the initial part of the sequence, least significant bit first *)
+
+(*val bitSeqEq : bitSequence -> bitSequence -> bool*)
+
+(*val boolListFrombitSeq : nat -> bitSequence -> list bool*)
+
+ val _ = Define `
+ ((boolListFrombitSeqAux:num -> 'a -> 'a list -> 'a list) n s bl=  
+ (if n =( 0 : num) then [] else
+  (case bl of
+      []       => REPLICATE n s
+    | b :: bl' => b :: (boolListFrombitSeqAux (n -( 1 : num)) s bl')
+  )))`;
+
+
+val _ = Define `
+ ((boolListFrombitSeq:num -> bitSequence ->(bool)list) n (BitSeq _ s bl)=  (boolListFrombitSeqAux n s bl))`;
+
+
+
+(*val bitSeqFromBoolList : list bool -> Maybe.maybe bitSequence*)
+val _ = Define `
+ ((bitSeqFromBoolList:(bool)list ->(bitSequence)option) bl=  
+ ((case dest_init bl of
+      NONE => NONE
+    | SOME (bl', s) => SOME (BitSeq (SOME (LENGTH bl)) s bl')
+  )))`;
+
+
+
+(* cleans up the representation of a bitSequence without changing its semantics *)
+(*val cleanBitSeq : bitSequence -> bitSequence*)
+val _ = Define `
+ ((cleanBitSeq:bitSequence -> bitSequence) (BitSeq len s bl)=  ((case len of
+    NONE => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE bl))))
+  | SOME n  => (BitSeq len s (REVERSE (dropWhile ((<=>) s) (REVERSE (TAKE (n -( 1 : num)) bl)))))
+)))`;
+
+
+
+(*val bitSeqTestBit : bitSequence -> nat -> Maybe.maybe bool*)
+val _ = Define `
+ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq NONE s bl) pos=  (if pos < LENGTH bl then list_index bl pos else SOME s))
+/\ ((bitSeqTestBit:bitSequence -> num ->(bool)option) (BitSeq(SOME l) s bl) pos=  (if (pos >= l) then NONE else
+                if ((pos = (l -( 1 : num))) \/ (pos >= LENGTH bl)) then SOME s else
+                list_index bl pos))`;
+
+
+(*val bitSeqSetBit : bitSequence -> nat -> bool -> bitSequence*)
+val _ = Define `
+ ((bitSeqSetBit:bitSequence -> num -> bool -> bitSequence) (BitSeq len s bl) pos v=  
+ (let bl' = (if (pos < LENGTH bl) then bl else bl ++ REPLICATE pos s) in
+  let bl'' = (LUPDATE v pos bl') in
+  let bs' = (BitSeq len s bl'') in
+  cleanBitSeq bs'))`;
+
+
+
+(*val resizeBitSeq : Maybe.maybe nat -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((resizeBitSeq:(num)option -> bitSequence -> bitSequence) new_len bs= 
+  ((case cleanBitSeq bs of
+       (BitSeq len s bl) =>
+   let shorten_opt = ((case (new_len, len) of
+                            (NONE, _) => NONE
+                        | (SOME l1, NONE) => SOME l1
+                        | (SOME l1, SOME l2) =>
+                      if (l1 < l2) then SOME l1 else NONE
+                      )) in
+   (case shorten_opt of
+         NONE => BitSeq new_len s bl
+     | SOME l1 => (
+                  let bl' = (TAKE l1 (bl ++ [s])) in
+                  (case dest_init bl' of
+                        NONE => (BitSeq len s bl) (* do nothing if size 0 is requested *)
+                    | SOME (bl'', s') => cleanBitSeq (BitSeq new_len s' bl'')
+                  ))
+   )
+   )))`;
+ 
+
+(*val bitSeqNot : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqNot:bitSequence -> bitSequence) (BitSeq len s bl)=  (BitSeq len (~ s) (MAP (\ x. ~ x) bl)))`;
+
+
+(*val bitSeqBinop : (bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence*)
+
+(*val bitSeqBinopAux : (bool -> bool -> bool) -> bool -> list bool -> bool -> list bool -> list bool*)
+ val _ = Define `
+ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 ([])=  ([]))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 ([])=  ((binop b1 s2) :: bitSeqBinopAux binop s1 bl1' s2 []))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 ([]) s2 (b2 :: bl2')=  ((binop s1 b2) :: bitSeqBinopAux binop s1 []   s2 bl2'))
+/\ ((bitSeqBinopAux:(bool -> bool -> bool) -> bool ->(bool)list -> bool ->(bool)list ->(bool)list) binop s1 (b1 :: bl1') s2 (b2 :: bl2')=  ((binop b1 b2) :: bitSeqBinopAux binop s1 bl1' s2 bl2'))`;
+
+
+val _ = Define `
+ ((bitSeqBinop:(bool -> bool -> bool) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2=  ( 
+  (case cleanBitSeq bs1 of
+      (BitSeq len1 s1 bl1) =>
+  (case cleanBitSeq bs2 of
+      (BitSeq len2 s2 bl2) =>
+  let len = ((case (len1, len2) of
+                   (SOME l1, SOME l2) => SOME (MAX l1 l2)
+               | _ => NONE
+             )) in
+  let s = (binop s1 s2) in
+  let bl = (bitSeqBinopAux binop s1 bl1 s2 bl2) in
+  cleanBitSeq (BitSeq len s bl)
+  )
+  )
+))`;
+
+
+val _ = Define `
+ ((bitSeqAnd:bitSequence -> bitSequence -> bitSequence)=  (bitSeqBinop (/\)))`;
+
+val _ = Define `
+ ((bitSeqOr:bitSequence -> bitSequence -> bitSequence)=  (bitSeqBinop (\/)))`;
+
+val _ = Define `
+ ((bitSeqXor:bitSequence -> bitSequence -> bitSequence)=  (bitSeqBinop (\ b1 b2. ~ (b1 <=> b2))))`;
+
+
+(*val bitSeqShiftLeft : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqShiftLeft:bitSequence -> num -> bitSequence) (BitSeq len s bl) n=  (cleanBitSeq (BitSeq len s (REPLICATE n F ++ bl))))`;
+
+
+(*val bitSeqArithmeticShiftRight : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithmeticShiftRight:bitSequence -> num -> bitSequence) bs n= 
+  ((case cleanBitSeq bs of
+       (BitSeq len s bl) =>
+   cleanBitSeq (BitSeq len s (DROP n bl))
+   )))`;
+
+
+(*val bitSeqLogicalShiftRight : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqLogicalShiftRight:bitSequence -> num -> bitSequence) bs n=  
+  (if (n =( 0 : num)) then cleanBitSeq bs else  
+  (case cleanBitSeq bs of
+      (BitSeq len s bl) =>
+  (case len of
+        NONE => cleanBitSeq (BitSeq len s (DROP n bl))
+    | SOME l => cleanBitSeq (BitSeq len F ((DROP n bl) ++ REPLICATE l s))
+  )
+  )))`;
+
+
+
+(* integerFromBoolList sign bl creates an integer from a list of bits
+   (least significant bit first) and an explicitly given sign bit.
+   It uses two's complement encoding. *)
+(*val integerFromBoolList : (bool * list bool) -> Num.integer*)
+
+ val _ = Define `
+ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) (([]) : bool list)=  acc)
+/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((T :: bl') : bool list)=  (integerFromBoolListAux ((acc *( 2 : int)) +( 1 : int)) bl'))
+/\ ((integerFromBoolListAux:int ->(bool)list -> int) (acc : int) ((F :: bl') : bool list)=  (integerFromBoolListAux (acc *( 2 : int)) bl'))`;
+
+
+val _ = Define `
+ ((integerFromBoolList:bool#(bool)list -> int) (sign, bl)=   
+  (if sign then 
+     ~ (integerFromBoolListAux(( 0 : int)) (REVERSE (MAP (\ x. ~ x) bl)) +( 1 : int))
+   else integerFromBoolListAux(( 0 : int)) (REVERSE bl)))`;
+
+
+(* [boolListFromInteger i] creates a sign bit and a list of booleans from an integer. The len_opt tells it when to stop.*)
+(*val boolListFromInteger :    Num.integer -> bool * list bool*)
+
+ val _ = Define `
+ ((boolListFromNatural:(bool)list -> num ->(bool)list) acc (remainder : num)= 
+ (if (remainder >( 0:num)) then 
+   (boolListFromNatural (((remainder MOD( 2:num)) =( 1:num)) :: acc) 
+      (remainder DIV( 2:num)))
+ else
+   REVERSE acc))`;
+
+
+val _ = Define `
+ ((boolListFromInteger:int -> bool#(bool)list) (i : int)=  
+  (if (i <( 0 : int)) then
+    (T, MAP (\ x. ~ x) (boolListFromNatural [] (Num (ABS (~ (i +( 1 : int)))))))
+  else
+    (F, boolListFromNatural [] (Num (ABS i)))))`;
+
+
+
+(* [bitSeqFromInteger len_opt i] encodes [i] as a bitsequence with [len_opt] bits. If there are not enough
+   bits, truncation happens *)
+(*val bitSeqFromInteger : Maybe.maybe nat -> Num.integer -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromInteger:(num)option -> int -> bitSequence) len_opt i=  
+ (let (s, bl) = (boolListFromInteger i) in
+  resizeBitSeq len_opt (BitSeq NONE s bl)))`;
+
+
+
+(*val integerFromBitSeq : bitSequence -> Num.integer*)
+val _ = Define `
+ ((integerFromBitSeq:bitSequence -> int) bs= 
+  ((case cleanBitSeq bs of (BitSeq len s bl) => integerFromBoolList (s, bl) )))`;
+
+
+
+(* Now we can via translation to integers map arithmetic operations to bitSequences *)
+
+(*val bitSeqArithUnaryOp : (Num.integer -> Num.integer) -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithUnaryOp:(int -> int) -> bitSequence -> bitSequence) uop bs= 
+  ((case bs of
+       (BitSeq len _ _) =>
+   bitSeqFromInteger len (uop (integerFromBitSeq bs))
+   )))`;
+
+
+(*val bitSeqArithBinOp : (Num.integer -> Num.integer -> Num.integer) -> bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqArithBinOp:(int -> int -> int) -> bitSequence -> bitSequence -> bitSequence) binop bs1 bs2= 
+  ((case bs1 of
+       (BitSeq len1 _ _) =>
+   (case bs2 of
+       (BitSeq len2 _ _) =>
+   let len = ((case (len1, len2) of
+                    (SOME l1, SOME l2) => SOME (MAX l1 l2)
+                | _ => NONE
+              )) in
+   bitSeqFromInteger len
+     (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2))
+   )
+   )))`;
+
+
+(*val bitSeqArithBinTest : forall 'a. (Num.integer -> Num.integer -> 'a) -> bitSequence -> bitSequence -> 'a*)
+val _ = Define `
+ ((bitSeqArithBinTest:(int -> int -> 'a) -> bitSequence -> bitSequence -> 'a) binop bs1 bs2=  (binop (integerFromBitSeq bs1) (integerFromBitSeq bs2)))`;
+
+
+
+(* now instantiate the number interface for bit-sequences *)
+
+(*val bitSeqFromNumeral : numeral -> bitSequence*)
+
+(*val bitSeqLess : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqLess:bitSequence -> bitSequence -> bool) bs1 bs2=  (bitSeqArithBinTest (<) bs1 bs2))`;
+
+
+(*val bitSeqLessEqual : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqLessEqual:bitSequence -> bitSequence -> bool) bs1 bs2=  (bitSeqArithBinTest (<=) bs1 bs2))`;
+
+
+(*val bitSeqGreater : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqGreater:bitSequence -> bitSequence -> bool) bs1 bs2=  (bitSeqArithBinTest (>) bs1 bs2))`;
+
+
+(*val bitSeqGreaterEqual : bitSequence -> bitSequence -> bool*)
+val _ = Define `
+ ((bitSeqGreaterEqual:bitSequence -> bitSequence -> bool) bs1 bs2=  (bitSeqArithBinTest (>=) bs1 bs2))`;
+
+
+(*val bitSeqCompare : bitSequence -> bitSequence -> Basic_classes.ordering*)
+val _ = Define `
+ ((bitSeqCompare:bitSequence -> bitSequence -> lem_basic_classes$ordering) bs1 bs2=  (bitSeqArithBinTest (genericCompare (<) (=)) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Basic_classes_Ord_Word_bitSequence_dict:(bitSequence)lem_basic_classes$Ord_class)= (<|
+
+  compare_method := bitSeqCompare;
+
+  isLess_method := bitSeqLess;
+
+  isLessEqual_method := bitSeqLessEqual;
+
+  isGreater_method := bitSeqGreater;
+
+  isGreaterEqual_method := bitSeqGreaterEqual|>))`;
+
+
+(* arithmetic negation, don't mix up with bitwise negation *)
+(*val bitSeqNegate : bitSequence -> bitSequence*) 
+val _ = Define `
+ ((bitSeqNegate:bitSequence -> bitSequence) bs=  (bitSeqArithUnaryOp (\ i. ~ i) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumNegate_Word_bitSequence_dict:(bitSequence)lem_num$NumNegate_class)= (<|
+
+  numNegate_method := bitSeqNegate|>))`;
+
+
+
+(*val bitSeqAdd : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqAdd:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp (+) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumAdd_Word_bitSequence_dict:(bitSequence)lem_num$NumAdd_class)= (<|
+
+  numAdd_method := bitSeqAdd|>))`;
+
+
+(*val bitSeqMinus : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMinus:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp (-) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumMinus_Word_bitSequence_dict:(bitSequence)lem_num$NumMinus_class)= (<|
+
+  numMinus_method := bitSeqMinus|>))`;
+
+
+(*val bitSeqSucc : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqSucc:bitSequence -> bitSequence) bs=  (bitSeqArithUnaryOp (\ n. n +( 1 : int)) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumSucc_Word_bitSequence_dict:(bitSequence)lem_num$NumSucc_class)= (<|
+
+  succ_method := bitSeqSucc|>))`;
+
+
+(*val bitSeqPred : bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqPred:bitSequence -> bitSequence) bs=  (bitSeqArithUnaryOp (\ n. n -( 1 : int)) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumPred_Word_bitSequence_dict:(bitSequence)lem_num$NumPred_class)= (<|
+
+  pred_method := bitSeqPred|>))`;
+
+
+(*val bitSeqMult : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMult:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp ( * ) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumMult_Word_bitSequence_dict:(bitSequence)lem_num$NumMult_class)= (<|
+
+  numMult_method := bitSeqMult|>))`;
+
+
+
+(*val bitSeqPow : bitSequence -> nat -> bitSequence*)
+val _ = Define `
+ ((bitSeqPow:bitSequence -> num -> bitSequence) bs n=  (bitSeqArithUnaryOp (\ i .  i ** n) bs))`;
+
+
+val _ = Define `
+((instance_Num_NumPow_Word_bitSequence_dict:(bitSequence)lem_num$NumPow_class)= (<|
+
+  numPow_method := bitSeqPow|>))`;
+
+
+(*val bitSeqDiv : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqDiv:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp (/) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumIntegerDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumIntegerDivision_class)= (<|
+
+  div_method := bitSeqDiv|>))`;
+
+
+val _ = Define `
+((instance_Num_NumDivision_Word_bitSequence_dict:(bitSequence)lem_num$NumDivision_class)= (<|
+
+  numDivision_method := bitSeqDiv|>))`;
+
+
+(*val bitSeqMod : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMod:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp (%) bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Num_NumRemainder_Word_bitSequence_dict:(bitSequence)lem_num$NumRemainder_class)= (<|
+
+  mod_method := bitSeqMod|>))`;
+
+
+(*val bitSeqMin : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMin:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp int_min bs1 bs2))`;
+
+
+(*val bitSeqMax : bitSequence -> bitSequence -> bitSequence*)
+val _ = Define `
+ ((bitSeqMax:bitSequence -> bitSequence -> bitSequence) bs1 bs2=  (bitSeqArithBinOp int_max bs1 bs2))`;
+
+
+val _ = Define `
+((instance_Basic_classes_OrdMaxMin_Word_bitSequence_dict:(bitSequence)lem_basic_classes$OrdMaxMin_class)= (<|
+
+  max_method := bitSeqMax;
+
+  min_method := bitSeqMin|>))`;
+
+
+
+
+
+(* ========================================================================== *)
+(* Interface for bitoperations                                                *)
+(* ========================================================================== *)
+
+val _ = Hol_datatype `
+(*  'a *) WordNot_class= <|
+  lnot_method : 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) WordAnd_class= <|
+  land_method  : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) WordOr_class= <|
+  lor_method : 'a -> 'a -> 'a
+|>`;
+
+
+
+val _ = Hol_datatype `
+(*  'a *) WordXor_class= <|
+  lxor_method : 'a -> 'a -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) WordLsl_class= <|
+  lsl_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) WordLsr_class= <|
+  lsr_method : 'a -> num -> 'a
+|>`;
+
+
+val _ = Hol_datatype `
+(*  'a *) WordAsr_class= <|
+  asr_method : 'a -> num -> 'a
+|>`;
+
+
+(* ----------------------- *)
+(* bitSequence             *)
+(* ----------------------- *)
+
+val _ = Define `
+((instance_Word_WordNot_Word_bitSequence_dict:(bitSequence)WordNot_class)= (<|
+
+  lnot_method := bitSeqNot|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Word_bitSequence_dict:(bitSequence)WordAnd_class)= (<|
+
+  land_method := bitSeqAnd|>))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Word_bitSequence_dict:(bitSequence)WordOr_class)= (<|
+
+  lor_method := bitSeqOr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Word_bitSequence_dict:(bitSequence)WordXor_class)= (<|
+
+  lxor_method := bitSeqXor|>))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Word_bitSequence_dict:(bitSequence)WordLsl_class)= (<|
+
+  lsl_method := bitSeqShiftLeft|>))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Word_bitSequence_dict:(bitSequence)WordLsr_class)= (<|
+
+  lsr_method := bitSeqLogicalShiftRight|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Word_bitSequence_dict:(bitSequence)WordAsr_class)= (<|
+
+  asr_method := bitSeqArithmeticShiftRight|>))`;
+
+
+
+(* ----------------------- *)
+(* int32                   *)
+(* ----------------------- *)
+
+(*val int32Lnot : Num.int32 -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordNot_Num_int32_dict:(word32)WordNot_class)= (<|
+
+  lnot_method := (\ w. (~ w))|>))`;
+
+
+
+(*val int32Lor  : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordOr_Num_int32_dict:(word32)WordOr_class)= (<|
+
+  lor_method := word_or|>))`;
+
+
+(*val int32Lxor : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordXor_Num_int32_dict:(word32)WordXor_class)= (<|
+
+  lxor_method := word_xor|>))`;
+
+
+(*val int32Land : Num.int32 -> Num.int32 -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int32_dict:(word32)WordAnd_class)= (<|
+
+  land_method := word_and|>))`;
+
+
+(*val int32Lsl  : Num.int32 -> nat -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int32_dict:(word32)WordLsl_class)= (<|
+
+  lsl_method := word_lsl|>))`;
+
+
+(*val int32Lsr  : Num.int32 -> nat -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsr_Num_int32_dict:(word32)WordLsr_class)= (<|
+
+  lsr_method := word_lsr|>))`;
+
+
+
+(*val int32Asr  : Num.int32 -> nat -> Num.int32*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int32_dict:(word32)WordAsr_class)= (<|
+
+  asr_method := word_asr|>))`;
+
+
+
+(* ----------------------- *)
+(* int64                   *)
+(* ----------------------- *)
+
+(*val int64Lnot : Num.int64 -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordNot_Num_int64_dict:(word64)WordNot_class)= (<|
+
+  lnot_method := (\ w. (~ w))|>))`;
+
+
+(*val int64Lor  : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordOr_Num_int64_dict:(word64)WordOr_class)= (<|
+
+  lor_method := word_or|>))`;
+
+
+(*val int64Lxor : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordXor_Num_int64_dict:(word64)WordXor_class)= (<|
+
+  lxor_method := word_xor|>))`;
+
+
+(*val int64Land : Num.int64 -> Num.int64 -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int64_dict:(word64)WordAnd_class)= (<|
+
+  land_method := word_and|>))`;
+
+
+(*val int64Lsl  : Num.int64 -> nat -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int64_dict:(word64)WordLsl_class)= (<|
+
+  lsl_method := word_lsl|>))`;
+
+
+(*val int64Lsr  : Num.int64 -> nat -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordLsr_Num_int64_dict:(word64)WordLsr_class)= (<|
+
+  lsr_method := word_lsr|>))`;
+
+
+(*val int64Asr  : Num.int64 -> nat -> Num.int64*) (* XXX: fix *)
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int64_dict:(word64)WordAsr_class)= (<|
+
+  asr_method := word_asr|>))`;
+
+
+
+(* ----------------------- *)
+(* Words via bit sequences *)
+(* ----------------------- *)
+
+(*val defaultLnot : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a*) 
+val _ = Define `
+ ((defaultLnot:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a) fromBitSeq toBitSeq x=  (fromBitSeq (bitSeqNegate (toBitSeq x))))`;
+
+
+(*val defaultLand : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLand:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2=  (fromBitSeq (bitSeqAnd (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2=  (fromBitSeq (bitSeqOr (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLxor : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> 'a -> 'a*)
+val _ = Define `
+ ((defaultLxor:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> 'a -> 'a) fromBitSeq toBitSeq x1 x2=  (fromBitSeq (bitSeqXor (toBitSeq x1) (toBitSeq x2))))`;
+
+
+(*val defaultLsl : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultLsl:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n=  (fromBitSeq (bitSeqShiftLeft (toBitSeq x) n)))`;
+
+
+(*val defaultLsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultLsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n=  (fromBitSeq (bitSeqLogicalShiftRight (toBitSeq x) n)))`;
+
+
+(*val defaultAsr : forall 'a. (bitSequence -> 'a) -> ('a -> bitSequence) -> 'a -> nat -> 'a*)
+val _ = Define `
+ ((defaultAsr:(bitSequence -> 'a) ->('a -> bitSequence) -> 'a -> num -> 'a) fromBitSeq toBitSeq x n=  (fromBitSeq (bitSeqArithmeticShiftRight (toBitSeq x) n)))`;
+
+
+(* ----------------------- *)
+(* integer                 *)
+(* ----------------------- *)
+
+(*val integerLnot : Num.integer -> Num.integer*)
+val _ = Define `
+ ((integerLnot:int -> int) i=  (~ (i +( 1 : int))))`;
+
+
+val _ = Define `
+((instance_Word_WordNot_Num_integer_dict:(int)WordNot_class)= (<|
+
+  lnot_method := integerLnot|>))`;
+
+
+
+(*val integerLor  : Num.integer -> Num.integer -> Num.integer*)
+val _ = Define `
+ ((integerLor:int -> int -> int) i1 i2=  (defaultLor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_integer_dict:(int)WordOr_class)= (<|
+
+  lor_method := integerLor|>))`;
+
+
+(*val integerLxor : Num.integer -> Num.integer -> Num.integer*)
+val _ = Define `
+ ((integerLxor:int -> int -> int) i1 i2=  (defaultLxor integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_integer_dict:(int)WordXor_class)= (<|
+
+  lxor_method := integerLxor|>))`;
+
+
+(*val integerLand : Num.integer -> Num.integer -> Num.integer*)
+val _ = Define `
+ ((integerLand:int -> int -> int) i1 i2=  (defaultLand integerFromBitSeq (bitSeqFromInteger NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_integer_dict:(int)WordAnd_class)= (<|
+
+  land_method := integerLand|>))`;
+
+
+(*val integerLsl  : Num.integer -> nat -> Num.integer*)
+val _ = Define `
+ ((integerLsl:int -> num -> int) i n=  (defaultLsl integerFromBitSeq (bitSeqFromInteger NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_integer_dict:(int)WordLsl_class)= (<|
+
+  lsl_method := integerLsl|>))`;
+
+
+(*val integerAsr  : Num.integer -> nat -> Num.integer*)
+val _ = Define `
+ ((integerAsr:int -> num -> int) i n=  (defaultAsr integerFromBitSeq (bitSeqFromInteger NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Num_integer_dict:(int)WordLsr_class)= (<|
+
+  lsr_method := integerAsr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_integer_dict:(int)WordAsr_class)= (<|
+
+  asr_method := integerAsr|>))`;
+
+
+
+(* ----------------------- *)
+(* int                     *)
+(* ----------------------- *)
+
+(* sometimes it is convenient to be able to perform bit-operations on ints.
+   However, since int is not well-defined (it has different size on different systems),
+   it should be used very carefully and only for operations that don't depend on the
+   bitwidth of int *)
+
+(*val intFromBitSeq : bitSequence -> Num.int*)
+val _ = Define `
+ ((intFromBitSeq:bitSequence -> int) bs=  (I (integerFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs))))`;
+
+
+
+(*val bitSeqFromInt : Num.int -> bitSequence*) 
+val _ = Define `
+ ((bitSeqFromInt:int -> bitSequence) i=  (bitSeqFromInteger (SOME(( 31 : num))) ( i)))`;
+
+
+
+(*val intLnot : Num.int -> Num.int*)
+val _ = Define `
+ ((intLnot:int -> int) i=  (~ (i +( 1 : int))))`;
+
+
+val _ = Define `
+((instance_Word_WordNot_Num_int_dict:(int)WordNot_class)= (<|
+
+  lnot_method := intLnot|>))`;
+
+
+(*val intLor  : Num.int -> Num.int -> Num.int*)
+val _ = Define `
+ ((intLor:int -> int -> int) i1 i2=  (defaultLor intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_int_dict:(int)WordOr_class)= (<|
+
+  lor_method := intLor|>))`;
+
+
+(*val intLxor : Num.int -> Num.int -> Num.int*)
+val _ = Define `
+ ((intLxor:int -> int -> int) i1 i2=  (defaultLxor intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_int_dict:(int)WordXor_class)= (<|
+
+  lxor_method := intLxor|>))`;
+
+
+(*val intLand : Num.int -> Num.int -> Num.int*)
+val _ = Define `
+ ((intLand:int -> int -> int) i1 i2=  (defaultLand intFromBitSeq bitSeqFromInt i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_int_dict:(int)WordAnd_class)= (<|
+
+  land_method := intLand|>))`;
+
+
+(*val intLsl  : Num.int -> nat -> Num.int*)
+val _ = Define `
+ ((intLsl:int -> num -> int) i n=  (defaultLsl intFromBitSeq bitSeqFromInt i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_int_dict:(int)WordLsl_class)= (<|
+
+  lsl_method := intLsl|>))`;
+
+
+(*val intAsr  : Num.int -> nat -> Num.int*)
+val _ = Define `
+ ((intAsr:int -> num -> int) i n=  (defaultAsr intFromBitSeq bitSeqFromInt i n))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_int_dict:(int)WordAsr_class)= (<|
+
+  asr_method := intAsr|>))`;
+
+
+
+
+(* ----------------------- *)
+(* natural                 *)
+(* ----------------------- *)
+
+(* some operations work also on positive numbers *)
+
+(*val naturalFromBitSeq : bitSequence -> Num.natural*)
+val _ = Define `
+ ((naturalFromBitSeq:bitSequence -> num) bs=  (Num (ABS (integerFromBitSeq bs))))`;
+
+
+(*val bitSeqFromNatural : Maybe.maybe nat -> Num.natural -> bitSequence*)
+val _ = Define `
+ ((bitSeqFromNatural:(num)option -> num -> bitSequence) len n=  (bitSeqFromInteger len (int_of_num n)))`;
+
+
+(*val naturalLor  : Num.natural -> Num.natural -> Num.natural*)
+val _ = Define `
+ ((naturalLor:num -> num -> num) i1 i2=  (defaultLor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_Num_natural_dict:(num)WordOr_class)= (<|
+
+  lor_method := naturalLor|>))`;
+
+
+(*val naturalLxor : Num.natural -> Num.natural -> Num.natural*)
+val _ = Define `
+ ((naturalLxor:num -> num -> num) i1 i2=  (defaultLxor naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_Num_natural_dict:(num)WordXor_class)= (<|
+
+  lxor_method := naturalLxor|>))`;
+
+
+(*val naturalLand : Num.natural -> Num.natural -> Num.natural*)
+val _ = Define `
+ ((naturalLand:num -> num -> num) i1 i2=  (defaultLand naturalFromBitSeq (bitSeqFromNatural NONE) i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_Num_natural_dict:(num)WordAnd_class)= (<|
+
+  land_method := naturalLand|>))`;
+
+
+(*val naturalLsl  : Num.natural -> nat -> Num.natural*)
+val _ = Define `
+ ((naturalLsl:num -> num -> num) i n=  (defaultLsl naturalFromBitSeq (bitSeqFromNatural NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_Num_natural_dict:(num)WordLsl_class)= (<|
+
+  lsl_method := naturalLsl|>))`;
+
+
+(*val naturalAsr  : Num.natural -> nat -> Num.natural*)
+val _ = Define `
+ ((naturalAsr:num -> num -> num) i n=  (defaultAsr naturalFromBitSeq (bitSeqFromNatural NONE) i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsr_Num_natural_dict:(num)WordLsr_class)= (<|
+
+  lsr_method := naturalAsr|>))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_Num_natural_dict:(num)WordAsr_class)= (<|
+
+  asr_method := naturalAsr|>))`;
+
+
+
+(* ----------------------- *)
+(* nat                     *)
+(* ----------------------- *)
+
+(* sometimes it is convenient to be able to perform bit-operations on nats.
+   However, since nat is not well-defined (it has different size on different systems),
+   it should be used very carefully and only for operations that don't depend on the
+   bitwidth of nat *)
+
+(*val natFromBitSeq : bitSequence -> nat*)
+val _ = Define `
+ ((natFromBitSeq:bitSequence -> num) bs=  (((naturalFromBitSeq (resizeBitSeq (SOME(( 31 : num))) bs)):num)))`;
+
+
+
+(*val bitSeqFromNat : nat -> bitSequence*) 
+val _ = Define `
+ ((bitSeqFromNat:num -> bitSequence) i=  (bitSeqFromNatural (SOME(( 31 : num))) (( i:num))))`;
+
+
+
+(*val natLor  : nat -> nat -> nat*)
+val _ = Define `
+ ((natLor:num -> num -> num) i1 i2=  (defaultLor natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordOr_nat_dict:(num)WordOr_class)= (<|
+
+  lor_method := natLor|>))`;
+
+
+(*val natLxor : nat -> nat -> nat*)
+val _ = Define `
+ ((natLxor:num -> num -> num) i1 i2=  (defaultLxor natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordXor_nat_dict:(num)WordXor_class)= (<|
+
+  lxor_method := natLxor|>))`;
+
+
+(*val natLand : nat -> nat -> nat*)
+val _ = Define `
+ ((natLand:num -> num -> num) i1 i2=  (defaultLand natFromBitSeq bitSeqFromNat i1 i2))`;
+
+
+val _ = Define `
+((instance_Word_WordAnd_nat_dict:(num)WordAnd_class)= (<|
+
+  land_method := natLand|>))`;
+
+
+(*val natLsl  : nat -> nat -> nat*)
+val _ = Define `
+ ((natLsl:num -> num -> num) i n=  (defaultLsl natFromBitSeq bitSeqFromNat i n))`;
+
+
+val _ = Define `
+((instance_Word_WordLsl_nat_dict:(num)WordLsl_class)= (<|
+
+  lsl_method := natLsl|>))`;
+
+
+(*val natAsr  : nat -> nat -> nat*)
+val _ = Define `
+ ((natAsr:num -> num -> num) i n=  (defaultAsr natFromBitSeq bitSeqFromNat i n))`;
+
+
+val _ = Define `
+((instance_Word_WordAsr_nat_dict:(num)WordAsr_class)= (<|
+
+  asr_method := natAsr|>))`;
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/cheri/Holmakefile b/snapshots/hol4/sail/cheri/Holmakefile
new file mode 100644
index 00000000..604555b5
--- /dev/null
+++ b/snapshots/hol4/sail/cheri/Holmakefile
@@ -0,0 +1,11 @@
+LEMDIR=../../lem/hol-lib
+
+INCLUDES = $(LEMDIR) ../lib/hol
+
+all: cheri_sequentialTheory.uo
+.PHONY: all
+
+ifdef POLY
+BASE_HEAP = ../lib/hol/sail-heap
+
+endif
diff --git a/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml b/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml
new file mode 100644
index 00000000..3bc5ad50
--- /dev/null
+++ b/snapshots/hol4/sail/cheri/cheri_sequentialScript.sml
@@ -0,0 +1,9255 @@
+(*Generated by Lem from cheri_sequential.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory cheri_sequential_typesTheory mips_extras_sequentialTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "cheri_sequential"
+
+(*Generated by Sail from cheri_sequential.*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators_mwords*)
+(*open import State_monad*)
+(*open import State*)
+(*open import Cheri_sequential_types*)
+(*open import Mips_extras_sequential*)
+
+val _ = Define `
+ ((cap_size:int)=  ((( 32 : int):sail_values$ii)))`;
+
+
+(*val undefined_option : forall 'a. 'a -> Cheri_sequential_types.M (Maybe.maybe 'a)*)
+
+val _ = Define `
+ ((undefined_option:'a ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('a option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) typ_a=  (seqS (undefined_unit () ) (internal_pick [NONE;SOME typ_a])))`;
+
+
+
+
+
+
+
+
+(*val neq_bool : bool -> bool -> bool*)
+
+val _ = Define `
+ ((neq_bool:bool -> bool -> bool) x y=  (~ (((x = y)))))`;
+
+
+
+
+
+
+(*val builtin_and_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*)
+
+
+
+(*val builtin_or_vec : forall 'n. Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n -> Cheri_sequential_types.bits 'n*)
+
+
+
+(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b=   
+ ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | B1 => (vec_of_bits [B1]  :  1 words$word) )))`;
+
+
+(*val DecStr : Sail_values.ii -> string*)
+
+(*val HexStr : Sail_values.ii -> string*)
+
+(*val __MIPS_write : forall  'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((MIPS_write:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width data=   
+ (write_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       :  64 words$word) addr data))`;
+
+
+(*val __MIPS_read : forall  'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MIPS_read:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((read_ram instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii) width
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        :  64 words$word) addr
+     : ( 'p8_times_n_ words$word) cheri_sequential_types$M)))`;
+
+
+
+
+(*val undefined_exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.exception*)
+
+val _ = Define `
+ ((undefined_exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS (seqS   
+(undefined_unit () )   
+(undefined_string () )) (\ (w__0 : string) .  seqS (seqS (seqS   
+(undefined_unit () )   
+(undefined_unit () ))   
+(undefined_unit () ))   
+(internal_pick
+     [ISAException () ;Error_not_implemented w__0;Error_misaligned_access () ;Error_EBREAK () ;Error_internal_error () ]))))`;
+
+
+(*val sign_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+(*val zero_extend : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((sign_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((sign_extend0 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :  'm words$word)))`;
+
+
+val _ = Define `
+ ((zero_extend1:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((zero_extend0 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict v m__tv  :  'm words$word)))`;
+
+
+(*val zeros : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((zeros:int -> unit -> 'n words$word) (n__tv : int) () =  ((replicate_bits (vec_of_bits [B0]  :  1 words$word) n__tv  :  'n words$word)))`;
+
+
+(*val ones : forall 'n . Size 'n => Num.integer -> unit -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((ones:int -> unit -> 'n words$word) (n__tv : int) () =  ((replicate_bits (vec_of_bits [B1]  :  1 words$word) n__tv  :  'n words$word)))`;
+
+
+
+
+
+
+
+
+
+
+(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((bool_to_bits:bool ->(1)words$word) x=  (if x then (vec_of_bits [B1]  :  1 words$word) else (vec_of_bits [B0]  :  1 words$word)))`;
+
+
+(*val bit_to_bool : Sail_values.bitU -> bool*)
+
+val _ = Define `
+ ((bit_to_bool:sail_values$bitU -> bool) b=  ((case b of   B1 => T | B0 => F )))`;
+
+
+(*val bits_to_bool : Machine_word.mword Machine_word.ty1 -> bool*)
+
+val _ = Define `
+ ((bits_to_bool:(1)words$word -> bool) x=  (bit_to_bool ((access_vec_dec x (( 0 : int):sail_values$ii)))))`;
+
+
+(*val to_bits : forall 'l. Size 'l => Machine_word.itself 'l -> Sail_values.ii -> Machine_word.mword 'l*)
+
+val _ = Define `
+ ((to_bits:'l itself -> int -> 'l words$word) l n=   
+ (let l = (size_itself_int l) in
+   (get_slice_int instance_Sail_values_Bitvector_Machine_word_mword_dict l n (( 0 : int):sail_values$ii)  :  'l words$word)))`;
+
+
+(*val mask : forall 'm 'n . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'm -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((mask:int -> 'm words$word -> 'n words$word) (n__tv : int) bs=   
+ ((subrange_vec_dec bs ((n__tv - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii)  :  'n words$word)))`;
+
+
+(*val extzv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((extzv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((extz_vec m__tv v  :  'm words$word)))`;
+
+
+(*val extsv : forall 'n 'm. Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((extsv:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((exts_vec m__tv v  :  'm words$word)))`;
+
+
+(*val slice_mask : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((slice_mask:int -> int -> int -> 'n words$word) (n__tv : int) i l=   
+ (let (one1 : 'n cheri_sequential_types$bits) = ((extzv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftl ((sub_vec ((shiftl one1 l  :  'n words$word)) one1  :  'n words$word)) i  :  'n words$word)))`;
+
+
+(*val is_zero_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*)
+
+val _ = Define `
+ ((is_zero_subrange:'n words$word -> int -> int -> bool) xs i j= 
+   (((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) = ((extzv ((int_of_num (words$word_len xs))) (vec_of_bits [B0]  :  1 words$word)  :  'n words$word))))`;
+
+
+(*val is_ones_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*)
+
+val _ = Define `
+ ((is_ones_subrange:'n words$word -> int -> int -> bool) xs i j=   
+ (let (m : 'n cheri_sequential_types$bits) = ((slice_mask ((int_of_num (words$word_len xs))) j ((j - i))  :  'n words$word)) in
+   (((and_vec xs m  :  'n words$word)) = m)))`;
+
+
+(*val slice_slice_concat : forall 'n 'm 'r . Size 'm, Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'r*)
+
+val _ = Define `
+ ((slice_slice_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 'r words$word) (r__tv : int) xs i l ys i' l'=   
+ (let xs =     
+((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   let ys =     
+((shiftr ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) i' l'  :  'm words$word))  :  'm words$word)) i'
+       :  'm words$word)) in
+   (or_vec ((shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)) ((extzv r__tv ys  :  'r words$word))
+     :  'r words$word)))`;
+
+
+(*val slice_zeros_concat : forall 'n   'r . Size 'n, Size 'r => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Num.integer -> Num.integer -> Machine_word.mword 'r*)
+
+val _ = Define `
+ ((slice_zeros_concat:int -> 'n words$word -> int -> int -> int -> 'r words$word) (r__tv : int) xs i l l'=   
+ (let xs =     
+((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv r__tv xs  :  'r words$word)) l'  :  'r words$word)))`;
+
+
+(*val subrange_subrange_eq : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> bool*)
+
+val _ = Define `
+ ((subrange_subrange_eq:'n words$word -> int -> int -> 'n words$word -> int -> int -> bool) xs i j ys i' j'=   
+ (let xs =     
+((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =     
+((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len xs))) j' ((i' - j'))  :  'n words$word))  :  'n words$word))
+        j'
+       :  'n words$word)) in
+   (xs = ys)))`;
+
+
+(*val subrange_subrange_concat : forall 'n   'm   's . Size 'm, Size 'n, Size 's => Num.integer -> Machine_word.mword 'n -> Num.integer -> Num.integer -> Machine_word.mword 'm -> Num.integer -> Num.integer -> Machine_word.mword 's*)
+
+val _ = Define `
+ ((subrange_subrange_concat:int -> 'n words$word -> int -> int -> 'm words$word -> int -> int -> 's words$word) (s__tv : int) xs i j ys i' j'=   
+ (let xs =     
+((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   let ys =     
+((shiftr
+        ((and_vec ys ((slice_mask ((int_of_num (words$word_len ys))) j' ((i' - j'))  :  'm words$word))  :  'm words$word))
+        j'
+       :  'm words$word)) in
+   (or_vec
+      ((sub_vec_int ((shiftl ((extzv s__tv xs  :  's words$word)) i'  :  's words$word))
+          ((j' - (( 1 : int):sail_values$ii)))
+         :  's words$word)) ((extzv s__tv ys  :  's words$word))
+     :  's words$word)))`;
+
+
+(*val place_subrange : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((place_subrange:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i j shift=   
+ (let xs =     
+((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) j
+       :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val place_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((place_slice:int -> 'n words$word -> int -> int -> int -> 'm words$word) (m__tv : int) xs i l shift=   
+ (let xs =     
+((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (shiftl ((extzv m__tv xs  :  'm words$word)) shift  :  'm words$word)))`;
+
+
+(*val zext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((zext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=   
+ (let xs =     
+((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   (extzv m__tv xs  :  'm words$word)))`;
+
+
+(*val sext_slice : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((sext_slice:int -> 'n words$word -> int -> int -> 'm words$word) (m__tv : int) xs i l=   
+ (let xs =     
+((arith_shiftr
+        ((shiftl ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word))
+            ((((((int_of_num (words$word_len xs))) - i)) - l))
+           :  'n words$word)) ((((int_of_num (words$word_len xs))) - l))
+       :  'n words$word)) in
+   (extsv m__tv xs  :  'm words$word)))`;
+
+
+(*val unsigned_slice : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*)
+
+val _ = Define `
+ ((unsigned_slice:'n words$word -> int -> int -> int) xs i l=   
+ (let xs =     
+((shiftr ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) i l  :  'n words$word))  :  'n words$word)) i  :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val unsigned_subrange : forall 'n . Size 'n => Machine_word.mword 'n -> Sail_values.ii -> Sail_values.ii -> Sail_values.ii*)
+
+val _ = Define `
+ ((unsigned_subrange:'n words$word -> int -> int -> int) xs i j=   
+ (let xs =     
+((shiftr
+        ((and_vec xs ((slice_mask ((int_of_num (words$word_len xs))) j ((i - j))  :  'n words$word))  :  'n words$word)) i
+       :  'n words$word)) in
+   lem$w2ui xs))`;
+
+
+(*val zext_ones : forall 'n . Size 'n => Num.integer -> Sail_values.ii -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((zext_ones:int -> int -> 'n words$word) (n__tv : int) m=   
+ (let (v : 'n cheri_sequential_types$bits) = ((extsv n__tv (vec_of_bits [B1]  :  1 words$word)  :  'n words$word)) in
+   (shiftr v ((((int_of_num (words$word_len v))) - m))  :  'n words$word)))`;
+
+
+(*val undefined_CauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((undefined_CauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 :  32 words$word) . 
+   internal_pick [Mk_CauseReg w__0])))`;
+
+
+(*val _get_CauseReg : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32*)
+
+val _ = Define `
+ ((get_CauseReg:cheri_sequential_types$CauseReg ->(32)words$word) (Mk_CauseReg (v))=  v)`;
+
+
+(*val _set_CauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_CauseReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_CapCauseReg : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16*)
+
+(*val _set_CapCauseReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+(*val _get_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_BD : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_BD:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_BD : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_BD:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_CauseReg_CE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_CE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_CE : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_CE:cheri_sequential_types$CauseReg ->(2)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 28 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_IV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_IV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_IV : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_IV:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_CauseReg_WP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_WP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_WP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_WP:cheri_sequential_types$CauseReg ->(1)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_CauseReg_IP : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_IP:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_IP : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_IP:cheri_sequential_types$CauseReg ->(8)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5*)
+
+val _ = Define `
+ ((get_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word) (Mk_CauseReg (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)))`;
+
+
+(*val _set_CauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CauseReg))sail_values$register_ref ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CauseReg) . 
+   let r = ((get_CauseReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_CauseReg r))))`;
+
+
+(*val _update_CauseReg_ExcCode : Cheri_sequential_types.CauseReg -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CauseReg*)
+
+val _ = Define `
+ ((update_CauseReg_ExcCode:cheri_sequential_types$CauseReg ->(5)words$word -> cheri_sequential_types$CauseReg) (Mk_CauseReg (v)) x=   
+ (Mk_CauseReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _update_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*)
+
+(*val _get_CapCauseReg_ExcCode : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*)
+
+(*val _set_CapCauseReg_ExcCode : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+(*val undefined_TLBEntryLoReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((undefined_TLBEntryLoReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryLoReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   internal_pick [Mk_TLBEntryLoReg w__0])))`;
+
+
+(*val _get_TLBEntryLoReg : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg:cheri_sequential_types$TLBEntryLoReg ->(64)words$word) (Mk_TLBEntryLoReg (v))=  v)`;
+
+
+(*val _set_TLBEntryLoReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_TLBEntryLoReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=   
+ ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_CapS : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_CapS:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_CapS : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_CapS:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=   
+ ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_CapL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_CapL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_CapL : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_CapL:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word) (Mk_TLBEntryLoReg (v))=   
+ ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_PFN : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_PFN:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_PFN : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_PFN:cheri_sequential_types$TLBEntryLoReg ->(24)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_C : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_C:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_C : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_C:cheri_sequential_types$TLBEntryLoReg ->(3)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_D : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_D:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_D : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_D:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_V : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_V:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_V : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_V:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word) (Mk_TLBEntryLoReg (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntryLoReg_G : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryLoReg_G:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryLoReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryLoReg) . 
+   let r = ((get_TLBEntryLoReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryLoReg r))))`;
+
+
+(*val _update_TLBEntryLoReg_G : Cheri_sequential_types.TLBEntryLoReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntryLoReg*)
+
+val _ = Define `
+ ((update_TLBEntryLoReg_G:cheri_sequential_types$TLBEntryLoReg ->(1)words$word -> cheri_sequential_types$TLBEntryLoReg) (Mk_TLBEntryLoReg (v)) x=   
+ (Mk_TLBEntryLoReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val undefined_TLBEntryHiReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntryHiReg*)
+
+val _ = Define `
+ ((undefined_TLBEntryHiReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntryHiReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   internal_pick [Mk_TLBEntryHiReg w__0])))`;
+
+
+(*val _get_TLBEntryHiReg : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg:cheri_sequential_types$TLBEntryHiReg ->(64)words$word) (Mk_TLBEntryHiReg (v))=  v)`;
+
+
+(*val _set_TLBEntryHiReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_TLBEntryHiReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word) (Mk_TLBEntryHiReg (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_R : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_R:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . 
+   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+
+
+(*val _update_TLBEntryHiReg_R : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_R:cheri_sequential_types$TLBEntryHiReg ->(2)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=   
+ (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word) (Mk_TLBEntryHiReg (v))=   
+ ((subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  27 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_VPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_VPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . 
+   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+
+
+(*val _update_TLBEntryHiReg_VPN2 : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_VPN2:cheri_sequential_types$TLBEntryHiReg ->(27)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=   
+ (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word) (Mk_TLBEntryHiReg (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_TLBEntryHiReg_ASID : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntryHiReg_ASID:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntryHiReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . 
+   let r = ((get_TLBEntryHiReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_TLBEntryHiReg r))))`;
+
+
+(*val _update_TLBEntryHiReg_ASID : Cheri_sequential_types.TLBEntryHiReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntryHiReg*)
+
+val _ = Define `
+ ((update_TLBEntryHiReg_ASID:cheri_sequential_types$TLBEntryHiReg ->(8)words$word -> cheri_sequential_types$TLBEntryHiReg) (Mk_TLBEntryHiReg (v)) x=   
+ (Mk_TLBEntryHiReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val undefined_ContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.ContextReg*)
+
+val _ = Define `
+ ((undefined_ContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   internal_pick [Mk_ContextReg w__0])))`;
+
+
+(*val _get_ContextReg : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_ContextReg:cheri_sequential_types$ContextReg ->(64)words$word) (Mk_ContextReg (v))=  v)`;
+
+
+(*val _set_ContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_ContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_ContextReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41*)
+
+val _ = Define `
+ ((get_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word) (Mk_ContextReg (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii)  :  41 words$word)))`;
+
+
+(*val _set_ContextReg_PTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_ContextReg_PTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(41)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . 
+   let r = ((get_ContextReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_ContextReg r))))`;
+
+
+(*val _update_ContextReg_PTEBase : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty41 -> Cheri_sequential_types.ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_PTEBase:cheri_sequential_types$ContextReg ->(41)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x=   
+ (Mk_ContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 23 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19*)
+
+val _ = Define `
+ ((get_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word) (Mk_ContextReg (v))=  ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  19 words$word)))`;
+
+
+(*val _set_ContextReg_BadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_ContextReg_BadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$ContextReg))sail_values$register_ref ->(19)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$ContextReg) . 
+   let r = ((get_ContextReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_ContextReg r))))`;
+
+
+(*val _update_ContextReg_BadVPN2 : Cheri_sequential_types.ContextReg -> Machine_word.mword Machine_word.ty19 -> Cheri_sequential_types.ContextReg*)
+
+val _ = Define `
+ ((update_ContextReg_BadVPN2:cheri_sequential_types$ContextReg ->(19)words$word -> cheri_sequential_types$ContextReg) (Mk_ContextReg (v)) x=   
+ (Mk_ContextReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val undefined_XContextReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.XContextReg*)
+
+val _ = Define `
+ ((undefined_XContextReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$XContextReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   internal_pick [Mk_XContextReg w__0])))`;
+
+
+(*val _get_XContextReg : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_XContextReg:cheri_sequential_types$XContextReg ->(64)words$word) (Mk_XContextReg (v))=  v)`;
+
+
+(*val _set_XContextReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_XContextReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_XContextReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31*)
+
+val _ = Define `
+ ((get_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word) (Mk_XContextReg (v))=   
+ ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii)  :  31 words$word)))`;
+
+
+(*val _set_XContextReg_XPTEBase : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XPTEBase:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(31)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . 
+   let r = ((get_XContextReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_XContextReg r))))`;
+
+
+(*val _update_XContextReg_XPTEBase : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XPTEBase:cheri_sequential_types$XContextReg ->(31)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x=   
+ (Mk_XContextReg ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 33 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word) (Mk_XContextReg (v))=  ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_XContextReg_XR : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XR:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . 
+   let r = ((get_XContextReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_XContextReg r))))`;
+
+
+(*val _update_XContextReg_XR : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XR:cheri_sequential_types$XContextReg ->(2)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x=   
+ (Mk_XContextReg ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 31 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27*)
+
+val _ = Define `
+ ((get_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word) (Mk_XContextReg (v))=   
+ ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  27 words$word)))`;
+
+
+(*val _set_XContextReg_XBadVPN2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_XContextReg_XBadVPN2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$XContextReg))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$XContextReg) . 
+   let r = ((get_XContextReg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_XContextReg r))))`;
+
+
+(*val _update_XContextReg_XBadVPN2 : Cheri_sequential_types.XContextReg -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.XContextReg*)
+
+val _ = Define `
+ ((update_XContextReg_XBadVPN2:cheri_sequential_types$XContextReg ->(27)words$word -> cheri_sequential_types$XContextReg) (Mk_XContextReg (v)) x=   
+ (Mk_XContextReg ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((TLBNumEntries:int)=  ((( 64 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+((TLBIndexMax:(6)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word)))`;
+
+
+(*val MAX : Num.integer -> Num.integer*)
+
+val _ = Define `
+ ((MAX0:int -> int) n=  (((pow2 n)) - (( 1 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((MAX_U64:int)=  (MAX0 (( 64 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((MAX_VA:int)=  (MAX0 (( 40 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((MAX_PA:int)=  (MAX0 (( 36 : int):sail_values$ii)))`;
+
+
+(*val undefined_TLBEntry : unit -> Cheri_sequential_types.M Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((undefined_TLBEntry:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$TLBEntry),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 117 : int):sail_values$ii)  : ( 117 words$word) cheri_sequential_types$M) (\ (w__0 :  117 words$word) . 
+   internal_pick [Mk_TLBEntry w__0])))`;
+
+
+(*val _get_TLBEntry : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117*)
+
+val _ = Define `
+ ((get_TLBEntry:cheri_sequential_types$TLBEntry ->(117)words$word) (Mk_TLBEntry (v))=  v)`;
+
+
+(*val _set_TLBEntry : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty117 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(117)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_TLBEntry v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16*)
+
+val _ = Define `
+ ((get_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii)  :  16 words$word)))`;
+
+
+(*val _set_TLBEntry_pagemask : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pagemask:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_pagemask : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pagemask:cheri_sequential_types$TLBEntry ->(16)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 116 : int):sail_values$ii) (( 101 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_TLBEntry_r : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_r:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_r : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_r:cheri_sequential_types$TLBEntry ->(2)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 100 : int):sail_values$ii) (( 99 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27*)
+
+val _ = Define `
+ ((get_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii)  :  27 words$word)))`;
+
+
+(*val _set_TLBEntry_vpn2 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_vpn2:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(27)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_vpn2 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty27 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_vpn2:cheri_sequential_types$TLBEntry ->(27)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 98 : int):sail_values$ii) (( 72 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_TLBEntry_asid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_asid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_asid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_asid:cheri_sequential_types$TLBEntry ->(8)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 71 : int):sail_values$ii) (( 64 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_g : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_g:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_g : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_g:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_valid : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_valid:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_valid : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_valid:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 62 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_caps1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_caps1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_caps1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_caps1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 61 : int):sail_values$ii) (( 61 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_capl1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_capl1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_capl1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_capl1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 60 : int):sail_values$ii) (( 60 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*)
+
+val _ = Define `
+ ((get_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntry_pfn1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pfn1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_pfn1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pfn1:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 36 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*)
+
+val _ = Define `
+ ((get_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntry_c1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_c1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_c1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_c1:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 33 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_d1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_d1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_d1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_d1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 32 : int):sail_values$ii) (( 32 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_v1 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_v1:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_v1 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_v1:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 31 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_caps0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_caps0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_caps0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_caps0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 30 : int):sail_values$ii) (( 30 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_capl0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_capl0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_capl0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_capl0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 29 : int):sail_values$ii) (( 29 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24*)
+
+val _ = Define `
+ ((get_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  24 words$word)))`;
+
+
+(*val _set_TLBEntry_pfn0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_pfn0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(24)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_pfn0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty24 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_pfn0:cheri_sequential_types$TLBEntry ->(24)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 28 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3*)
+
+val _ = Define `
+ ((get_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)))`;
+
+
+(*val _set_TLBEntry_c0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_c0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(3)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_c0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty3 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_c0:cheri_sequential_types$TLBEntry ->(3)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_d0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_d0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_d0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_d0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+(*val _get_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word) (Mk_TLBEntry (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_TLBEntry_v0 : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_TLBEntry_v0:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$TLBEntry) . 
+   let r = ((get_TLBEntry w__0  :  117 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  117 words$word)) in
+   write_regS r_ref (Mk_TLBEntry r))))`;
+
+
+(*val _update_TLBEntry_v0 : Cheri_sequential_types.TLBEntry -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.TLBEntry*)
+
+val _ = Define `
+ ((update_TLBEntry_v0:cheri_sequential_types$TLBEntry ->(1)words$word -> cheri_sequential_types$TLBEntry) (Mk_TLBEntry (v)) x=   
+ (Mk_TLBEntry ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  117 words$word))))`;
+
+
+val _ = Define `
+((TLBEntries:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$TLBEntry))sail_values$register_ref)list)=  
+ ([TLBEntry63_ref;TLBEntry62_ref;TLBEntry61_ref;TLBEntry60_ref;TLBEntry59_ref;TLBEntry58_ref;TLBEntry57_ref;TLBEntry56_ref;TLBEntry55_ref;TLBEntry54_ref;TLBEntry53_ref;TLBEntry52_ref;TLBEntry51_ref;TLBEntry50_ref;TLBEntry49_ref;TLBEntry48_ref;TLBEntry47_ref;TLBEntry46_ref;TLBEntry45_ref;TLBEntry44_ref;TLBEntry43_ref;
+   TLBEntry42_ref;TLBEntry41_ref;TLBEntry40_ref;TLBEntry39_ref;TLBEntry38_ref;TLBEntry37_ref;TLBEntry36_ref;TLBEntry35_ref;TLBEntry34_ref;TLBEntry33_ref;TLBEntry32_ref;TLBEntry31_ref;TLBEntry30_ref;TLBEntry29_ref;TLBEntry28_ref;TLBEntry27_ref;TLBEntry26_ref;TLBEntry25_ref;TLBEntry24_ref;TLBEntry23_ref;TLBEntry22_ref;
+   TLBEntry21_ref;TLBEntry20_ref;TLBEntry19_ref;TLBEntry18_ref;TLBEntry17_ref;TLBEntry16_ref;TLBEntry15_ref;TLBEntry14_ref;TLBEntry13_ref;TLBEntry12_ref;TLBEntry11_ref;TLBEntry10_ref;TLBEntry09_ref;TLBEntry08_ref;TLBEntry07_ref;TLBEntry06_ref;TLBEntry05_ref;TLBEntry04_ref;TLBEntry03_ref;TLBEntry02_ref;TLBEntry01_ref;
+   TLBEntry00_ref]))`;
+
+
+(*val undefined_StatusReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((undefined_StatusReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$StatusReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 :  32 words$word) . 
+   internal_pick [Mk_StatusReg w__0])))`;
+
+
+(*val _get_StatusReg : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32*)
+
+val _ = Define `
+ ((get_StatusReg:cheri_sequential_types$StatusReg ->(32)words$word) (Mk_StatusReg (v))=  v)`;
+
+
+(*val _set_StatusReg : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty32 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(32)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_StatusReg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4*)
+
+val _ = Define `
+ ((get_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii)  :  4 words$word)))`;
+
+
+(*val _set_StatusReg_CU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_CU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(4)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_CU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty4 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_CU:cheri_sequential_types$StatusReg ->(4)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_BEV : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_BEV:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_BEV : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_BEV:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_StatusReg_IM : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_IM:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_IM : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_IM:cheri_sequential_types$StatusReg ->(8)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_KX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_KX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_KX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_KX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_SX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_SX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_SX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_SX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_UX : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_UX:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_UX : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_UX:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_StatusReg_KSU : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_KSU:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(2)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_KSU : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty2 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_KSU:cheri_sequential_types$StatusReg ->(2)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_ERL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_ERL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_ERL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_ERL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_EXL : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_EXL:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_EXL : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_EXL:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val _get_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word) (Mk_StatusReg (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_StatusReg_IE : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_StatusReg_IE:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$StatusReg))sail_values$register_ref ->(1)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let r = ((get_StatusReg w__0  :  32 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  32 words$word)) in
+   write_regS r_ref (Mk_StatusReg r))))`;
+
+
+(*val _update_StatusReg_IE : Cheri_sequential_types.StatusReg -> Machine_word.mword Machine_word.ty1 -> Cheri_sequential_types.StatusReg*)
+
+val _ = Define `
+ ((update_StatusReg_IE:cheri_sequential_types$StatusReg ->(1)words$word -> cheri_sequential_types$StatusReg) (Mk_StatusReg (v)) x=   
+ (Mk_StatusReg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  32 words$word))))`;
+
+
+(*val execute_branch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_branch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) pc=  (seqS   
+(write_regS delayedPC_ref pc) (write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
+
+
+(*val NotWordVal : Machine_word.mword Machine_word.ty64 -> bool*)
+
+val _ = Define `
+ ((NotWordVal:(64)words$word -> bool) word= 
+   (((replicate_bits ((cast_unit_vec0 ((access_vec_dec word (( 31 : int):sail_values$ii)))  :  1 words$word)) (( 32 : int):sail_values$ii)
+        :  32 words$word)) <> ((subrange_vec_dec word (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))))`;
+
+
+(*val rGPR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((rGPR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx=   
+ (let i = (lem$w2ui idx) in
+   if (((i = (( 0 : int):sail_values$ii)))) then
+     returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0]
+               :  64 words$word)
+   else bindS     
+(read_regS GPR_ref) (\ (w__0 : ( 64 cheri_sequential_types$bits) list) . 
+     returnS ((access_list_dec w__0 i  :  64 words$word)))))`;
+
+
+(*val wGPR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((wGPR:(5)words$word ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx v=   
+ (let i = (lem$w2ui idx) in
+   if (((i = (( 0 : int):sail_values$ii)))) then returnS () 
+   else bindS     
+(read_regS GPR_ref) (\ (w__0 : ( 64 words$word) list) . 
+     write_regS GPR_ref ((update_list_dec w__0 i v  : ( 64 words$word) list)))))`;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+(*val Exception_of_num : Num.integer -> Cheri_sequential_types.Exception*)
+
+val _ = Define `
+ ((Exception_of_num:int -> cheri_sequential_types$Exception) arg_=   
+ (let l__81 = arg_ in
+   if (((l__81 = (( 0 : int):sail_values$ii)))) then Interrupt
+   else if (((l__81 = (( 1 : int):sail_values$ii)))) then TLBMod
+   else if (((l__81 = (( 2 : int):sail_values$ii)))) then TLBL
+   else if (((l__81 = (( 3 : int):sail_values$ii)))) then TLBS
+   else if (((l__81 = (( 4 : int):sail_values$ii)))) then AdEL
+   else if (((l__81 = (( 5 : int):sail_values$ii)))) then AdES
+   else if (((l__81 = (( 6 : int):sail_values$ii)))) then Sys
+   else if (((l__81 = (( 7 : int):sail_values$ii)))) then Bp
+   else if (((l__81 = (( 8 : int):sail_values$ii)))) then ResI
+   else if (((l__81 = (( 9 : int):sail_values$ii)))) then CpU
+   else if (((l__81 = (( 10 : int):sail_values$ii)))) then Ov
+   else if (((l__81 = (( 11 : int):sail_values$ii)))) then Tr
+   else if (((l__81 = (( 12 : int):sail_values$ii)))) then C2E
+   else if (((l__81 = (( 13 : int):sail_values$ii)))) then C2Trap
+   else if (((l__81 = (( 14 : int):sail_values$ii)))) then XTLBRefillL
+   else if (((l__81 = (( 15 : int):sail_values$ii)))) then XTLBRefillS
+   else if (((l__81 = (( 16 : int):sail_values$ii)))) then XTLBInvL
+   else if (((l__81 = (( 17 : int):sail_values$ii)))) then XTLBInvS
+   else MCheck))`;
+
+
+(*val num_of_Exception : Cheri_sequential_types.Exception -> Num.integer*)
+
+val _ = Define `
+ ((num_of_Exception:cheri_sequential_types$Exception -> int) arg_=   
+ ((case arg_ of
+     Interrupt => (( 0 : int):sail_values$ii)
+   | TLBMod => (( 1 : int):sail_values$ii)
+   | TLBL => (( 2 : int):sail_values$ii)
+   | TLBS => (( 3 : int):sail_values$ii)
+   | AdEL => (( 4 : int):sail_values$ii)
+   | AdES => (( 5 : int):sail_values$ii)
+   | Sys => (( 6 : int):sail_values$ii)
+   | Bp => (( 7 : int):sail_values$ii)
+   | ResI => (( 8 : int):sail_values$ii)
+   | CpU => (( 9 : int):sail_values$ii)
+   | Ov => (( 10 : int):sail_values$ii)
+   | Tr => (( 11 : int):sail_values$ii)
+   | C2E => (( 12 : int):sail_values$ii)
+   | C2Trap => (( 13 : int):sail_values$ii)
+   | XTLBRefillL => (( 14 : int):sail_values$ii)
+   | XTLBRefillS => (( 15 : int):sail_values$ii)
+   | XTLBInvL => (( 16 : int):sail_values$ii)
+   | XTLBInvS => (( 17 : int):sail_values$ii)
+   | MCheck => (( 18 : int):sail_values$ii)
+   )))`;
+
+
+(*val undefined_Exception : unit -> Cheri_sequential_types.M Cheri_sequential_types.Exception*)
+
+val _ = Define `
+ ((undefined_Exception:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Exception),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =   
+ (internal_pick
+     [Interrupt;TLBMod;TLBL;TLBS;AdEL;AdES;Sys;Bp;ResI;CpU;Ov;Tr;C2E;C2Trap;XTLBRefillL;XTLBRefillS;XTLBInvL;XTLBInvS;MCheck]))`;
+
+
+(*val ExceptionCode : Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty5*)
+
+val _ = Define `
+ ((ExceptionCode:cheri_sequential_types$Exception ->(5)words$word) ex=   
+ (let (x : 8 cheri_sequential_types$bits) =     
+((case ex of
+       Interrupt => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+     | TLBMod => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  :  8 words$word)
+     | TLBL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | TLBS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | AdEL => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0]  :  8 words$word)
+     | AdES => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1]  :  8 words$word)
+     | Sys => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0]  :  8 words$word)
+     | Bp => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1]  :  8 words$word)
+     | ResI => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0]  :  8 words$word)
+     | CpU => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B1]  :  8 words$word)
+     | Ov => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B0]  :  8 words$word)
+     | Tr => (vec_of_bits [B0;B0;B0;B0;B1;B1;B0;B1]  :  8 words$word)
+     | C2E => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  :  8 words$word)
+     | C2Trap => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBRefillL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBRefillS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | XTLBInvL => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+     | XTLBInvS => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+     | MCheck => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0]  :  8 words$word)
+     )) in
+   (subrange_vec_dec x (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word)))`;
+
+
+(*val SignalExceptionMIPS : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*)
+
+val _ = Define `
+ ((SignalExceptionMIPS:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex kccBase=  (bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) .  bindS (seqS
+   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then bindS
+      (read_regS inBranchDelay_ref  : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) . 
+      if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then bindS
+        (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) .  seqS        
+(write_regS CP0EPC_ref ((sub_vec_int w__2 (( 4 : int):sail_values$ii)  :  64 words$word)))        
+(set_CauseReg_BD CP0Cause_ref (vec_of_bits [B1]  :  1 words$word)))
+      else bindS
+        (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) .  seqS        
+(write_regS CP0EPC_ref w__3) (set_CauseReg_BD CP0Cause_ref (vec_of_bits [B0]  :  1 words$word))))
+    else returnS () )   
+(read_regS CP0Status_ref)) (\ (w__4 : cheri_sequential_types$StatusReg) . 
+   let vectorOffset =     
+(if ((bits_to_bool ((get_StatusReg_EXL w__4  :  1 words$word)))) then
+       (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else if ((((((ex = XTLBRefillL))) \/ (((ex = XTLBRefillS)))))) then
+       (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else if (((ex = C2Trap))) then (vec_of_bits [B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+     else (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)) in bindS   
+(read_regS CP0Status_ref) (\ (w__5 : cheri_sequential_types$StatusReg) . 
+   let (vectorBase : 64 cheri_sequential_types$bits) =     
+(if ((bits_to_bool ((get_StatusReg_BEV w__5  :  1 words$word)))) then
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         :  64 words$word)
+     else
+       (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                     B0]
+         :  64 words$word)) in seqS (seqS (seqS   
+(write_regS
+     nextPC_ref
+     ((sub_vec
+         ((add_vec vectorBase ((sign_extend1 (( 64 : int):sail_values$ii) vectorOffset  :  64 words$word))  :  64 words$word))
+         kccBase
+        :  64 words$word)))   
+(set_CauseReg_ExcCode CP0Cause_ref ((ExceptionCode ex  :  5 words$word))))   
+(set_StatusReg_EXL CP0Status_ref (vec_of_bits [B1]  :  1 words$word))) (throwS (ISAException () )))))))`;
+
+
+(*val SignalException : forall 'o. Cheri_sequential_types.Exception -> Cheri_sequential_types.M 'o*)
+
+(*val SignalExceptionBadAddr : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*)
+
+(*val capRegToCapStruct : Machine_word.mword Machine_word.ty257 -> Cheri_sequential_types.CapStruct*)
+
+val _ = Define `
+ ((capRegToCapStruct:(257)words$word -> cheri_sequential_types$CapStruct) capReg=   
+ (<| CapStruct_tag := ((bit_to_bool ((access_vec_dec capReg (( 256 : int):sail_values$ii))))); 
+      CapStruct_padding := ((subrange_vec_dec capReg (( 255 : int):sail_values$ii) (( 248 : int):sail_values$ii)  :  8 words$word)); 
+      CapStruct_otype := ((subrange_vec_dec capReg (( 247 : int):sail_values$ii) (( 224 : int):sail_values$ii)  :  24 words$word)); 
+      CapStruct_uperms := ((subrange_vec_dec capReg (( 223 : int):sail_values$ii) (( 208 : int):sail_values$ii)  :  16 words$word)); 
+      CapStruct_perm_reserved11_14 := ((subrange_vec_dec capReg (( 207 : int):sail_values$ii) (( 204 : int):sail_values$ii)  :  4 words$word)); 
+      CapStruct_access_system_regs := ((bit_to_bool ((access_vec_dec capReg (( 203 : int):sail_values$ii))))); 
+      CapStruct_permit_unseal := ((bit_to_bool ((access_vec_dec capReg (( 202 : int):sail_values$ii))))); 
+      CapStruct_permit_ccall := ((bit_to_bool ((access_vec_dec capReg (( 201 : int):sail_values$ii))))); 
+      CapStruct_permit_seal := ((bit_to_bool ((access_vec_dec capReg (( 200 : int):sail_values$ii))))); 
+      CapStruct_permit_store_local_cap := ((bit_to_bool ((access_vec_dec capReg (( 199 : int):sail_values$ii))))); 
+      CapStruct_permit_store_cap := ((bit_to_bool ((access_vec_dec capReg (( 198 : int):sail_values$ii))))); 
+      CapStruct_permit_load_cap := ((bit_to_bool ((access_vec_dec capReg (( 197 : int):sail_values$ii))))); 
+      CapStruct_permit_store := ((bit_to_bool ((access_vec_dec capReg (( 196 : int):sail_values$ii))))); 
+      CapStruct_permit_load := ((bit_to_bool ((access_vec_dec capReg (( 195 : int):sail_values$ii))))); 
+      CapStruct_permit_execute := ((bit_to_bool ((access_vec_dec capReg (( 194 : int):sail_values$ii))))); 
+      CapStruct_global := ((bit_to_bool ((access_vec_dec capReg (( 193 : int):sail_values$ii))))); 
+      CapStruct_sealed := ((bit_to_bool ((access_vec_dec capReg (( 192 : int):sail_values$ii))))); 
+      CapStruct_address := ((subrange_vec_dec capReg (( 191 : int):sail_values$ii) (( 128 : int):sail_values$ii)  :  64 words$word)); 
+      CapStruct_base := ((subrange_vec_dec capReg (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii)  :  64 words$word)); 
+      CapStruct_length := ((subrange_vec_dec capReg (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)) |>))`;
+
+
+(*val getCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31*)
+
+val _ = Define `
+ ((getCapPerms:cheri_sequential_types$CapStruct ->(31)words$word) cap=   
+ ((concat_vec cap.CapStruct_uperms
+      ((concat_vec cap.CapStruct_perm_reserved11_14
+          ((concat_vec ((bool_to_bits cap.CapStruct_access_system_regs  :  1 words$word))
+              ((concat_vec ((bool_to_bits cap.CapStruct_permit_unseal  :  1 words$word))
+                  ((concat_vec ((bool_to_bits cap.CapStruct_permit_ccall  :  1 words$word))
+                      ((concat_vec ((bool_to_bits cap.CapStruct_permit_seal  :  1 words$word))
+                          ((concat_vec
+                              ((bool_to_bits cap.CapStruct_permit_store_local_cap  :  1 words$word))
+                              ((concat_vec
+                                  ((bool_to_bits cap.CapStruct_permit_store_cap  :  1 words$word))
+                                  ((concat_vec
+                                      ((bool_to_bits cap.CapStruct_permit_load_cap  :  1 words$word))
+                                      ((concat_vec
+                                          ((bool_to_bits cap.CapStruct_permit_store  :  1 words$word))
+                                          ((concat_vec
+                                              ((bool_to_bits cap.CapStruct_permit_load  :  1 words$word))
+                                              ((concat_vec
+                                                  ((bool_to_bits cap.CapStruct_permit_execute
+                                                     :  1 words$word))
+                                                  ((bool_to_bits cap.CapStruct_global  :  1 words$word))
+                                                 :  2 words$word))
+                                             :  3 words$word))
+                                         :  4 words$word))
+                                     :  5 words$word))
+                                 :  6 words$word))
+                             :  7 words$word))
+                         :  8 words$word))
+                     :  9 words$word))
+                 :  10 words$word))
+             :  11 words$word))
+         :  15 words$word))
+     :  31 words$word)))`;
+
+
+(*val capStructToMemBits256 : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*)
+
+val _ = Define `
+ ((capStructToMemBits256:cheri_sequential_types$CapStruct ->(256)words$word) cap=   
+ ((concat_vec cap.CapStruct_padding
+      ((concat_vec cap.CapStruct_otype
+          ((concat_vec ((getCapPerms cap  :  31 words$word))
+              ((concat_vec ((bool_to_bits cap.CapStruct_sealed  :  1 words$word))
+                  ((concat_vec cap.CapStruct_address
+                      ((concat_vec cap.CapStruct_base cap.CapStruct_length  :  128 words$word))
+                     :  192 words$word))
+                 :  193 words$word))
+             :  224 words$word))
+         :  248 words$word))
+     :  256 words$word)))`;
+
+
+(*val capStructToCapReg : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty257*)
+
+val _ = Define `
+ ((capStructToCapReg:cheri_sequential_types$CapStruct ->(257)words$word) cap=   
+ ((concat_vec ((bool_to_bits cap.CapStruct_tag  :  1 words$word))
+      ((capStructToMemBits256 cap  :  256 words$word))
+     :  257 words$word)))`;
+
+
+(*val getCapBase : Cheri_sequential_types.CapStruct -> Num.integer*)
+
+val _ = Define `
+ ((getCapBase:cheri_sequential_types$CapStruct -> int) c=  (lem$w2ui c.CapStruct_base))`;
+
+
+val _ = Define `
+((null_cap:cheri_sequential_types$CapStruct)=  
+ (<| CapStruct_tag := F; 
+     CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) ()   :  8 words$word)); 
+     CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) ()   :  24 words$word)); 
+     CapStruct_uperms := ((zeros (( 16 : int):sail_values$ii) ()   :  16 words$word)); 
+     CapStruct_perm_reserved11_14 := ((zeros (( 4 : int):sail_values$ii) ()   :  4 words$word)); 
+     CapStruct_access_system_regs := F; 
+     CapStruct_permit_unseal := F; 
+     CapStruct_permit_ccall := F; 
+     CapStruct_permit_seal := F; 
+     CapStruct_permit_store_local_cap := F; 
+     CapStruct_permit_store_cap := F; 
+     CapStruct_permit_load_cap := F; 
+     CapStruct_permit_store := F; 
+     CapStruct_permit_load := F; 
+     CapStruct_permit_execute := F; 
+     CapStruct_global := F; 
+     CapStruct_sealed := F; 
+     CapStruct_address := ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)); 
+     CapStruct_base := ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)); 
+     CapStruct_length :=       
+((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1]
+         :  64 words$word)) |>))`;
+
+
+(*val int_to_cap : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.CapStruct*)
+
+val _ = Define `
+ ((int_to_cap:(64)words$word -> cheri_sequential_types$CapStruct) address=  ((null_cap with<| CapStruct_address := address|>)))`;
+
+
+(*val setCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*)
+
+val _ = Define `
+ ((setCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c offset= 
+   (T, (c with<| CapStruct_address := ((add_vec c.CapStruct_base offset  :  64 words$word))|>)))`;
+
+
+val _ = Define `
+ ((SignalException:cheri_sequential_types$Exception ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex=  (bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) .  bindS (seqS
+   (if ((~ ((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))))) then bindS
+      (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ pc .  bindS
+      (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 :  257 words$word) . 
+      let pcc = (capRegToCapStruct w__1) in
+      let (success, epcc) = (setCapOffset pcc pc) in
+      if success then write_regS C31_ref ((capStructToCapReg epcc  :  257 words$word))
+      else
+        write_regS
+          C31_ref
+          ((capStructToCapReg
+              ((int_to_cap
+                  ((add_vec_int
+                      ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase pcc))
+                         :  64 words$word)) ((lem$w2ui pc))
+                     :  64 words$word))))
+             :  257 words$word))))
+    else returnS () )
+   (read_regS C29_ref  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__2 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS nextPCC_ref w__2)
+   (read_regS C29_ref  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS delayedPCC_ref w__3)
+   (read_regS C29_ref  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__4 :  257 words$word) . 
+   let base = (getCapBase ((capRegToCapStruct w__4))) in
+   SignalExceptionMIPS ex ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) base  :  64 words$word))))))))`;
+
+
+val _ = Define `
+ ((SignalExceptionBadAddr:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr=  (seqS (write_regS CP0BadVAddr_ref badAddr) (SignalException ex)))`;
+
+
+(*val SignalExceptionTLB : forall 'o. Cheri_sequential_types.Exception -> Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M 'o*)
+
+val _ = Define `
+ ((SignalExceptionTLB:cheri_sequential_types$Exception ->(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) ex badAddr=  (seqS (seqS (seqS (seqS (seqS (seqS   
+(write_regS CP0BadVAddr_ref badAddr)   
+(set_ContextReg_BadVPN2 TLBContext_ref ((subrange_vec_dec badAddr (( 31 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  19 words$word))))   
+(set_XContextReg_XBadVPN2 TLBXContext_ref
+     ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  27 words$word))))   
+(set_XContextReg_XR TLBXContext_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word))))   
+(set_TLBEntryHiReg_R TLBEntryHi_ref ((subrange_vec_dec badAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word))))   
+(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((subrange_vec_dec badAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  27 words$word))))   
+(SignalException ex)))`;
+
+
+(*val MemAccessType_of_num : Num.integer -> Cheri_sequential_types.MemAccessType*)
+
+val _ = Define `
+ ((MemAccessType_of_num:int -> cheri_sequential_types$MemAccessType) arg_=   
+ (let l__79 = arg_ in
+   if (((l__79 = (( 0 : int):sail_values$ii)))) then Instruction
+   else if (((l__79 = (( 1 : int):sail_values$ii)))) then LoadData
+   else StoreData))`;
+
+
+(*val num_of_MemAccessType : Cheri_sequential_types.MemAccessType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_MemAccessType:cheri_sequential_types$MemAccessType -> int) arg_=   
+ ((case arg_ of   Instruction => (( 0 : int):sail_values$ii) | LoadData => (( 1 : int):sail_values$ii) | StoreData => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val undefined_MemAccessType : unit -> Cheri_sequential_types.M Cheri_sequential_types.MemAccessType*)
+
+val _ = Define `
+ ((undefined_MemAccessType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$MemAccessType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [Instruction;LoadData;StoreData]))`;
+
+
+(*val AccessLevel_of_num : Num.integer -> Cheri_sequential_types.AccessLevel*)
+
+val _ = Define `
+ ((AccessLevel_of_num:int -> cheri_sequential_types$AccessLevel) arg_=   
+ (let l__77 = arg_ in
+   if (((l__77 = (( 0 : int):sail_values$ii)))) then User
+   else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor
+   else Kernel))`;
+
+
+(*val num_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Num.integer*)
+
+val _ = Define `
+ ((num_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) arg_=   
+ ((case arg_ of   User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val undefined_AccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*)
+
+val _ = Define `
+ ((undefined_AccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [User;Supervisor;Kernel]))`;
+
+
+(*val int_of_AccessLevel : Cheri_sequential_types.AccessLevel -> Sail_values.ii*)
+
+val _ = Define `
+ ((int_of_AccessLevel:cheri_sequential_types$AccessLevel -> int) level=   
+ ((case level of   User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Kernel => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val grantsAccess : Cheri_sequential_types.AccessLevel -> Cheri_sequential_types.AccessLevel -> bool*)
+
+val _ = Define `
+ ((grantsAccess:cheri_sequential_types$AccessLevel -> cheri_sequential_types$AccessLevel -> bool) currentLevel requiredLevel=   
+ (((int_of_AccessLevel currentLevel)) >= ((int_of_AccessLevel requiredLevel))))`;
+
+
+(*val getAccessLevel : unit -> Cheri_sequential_types.M Cheri_sequential_types.AccessLevel*)
+
+val _ = Define `
+ ((getAccessLevel:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$AccessLevel),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) .  bindS   
+(read_regS CP0Status_ref) (\ (w__1 : cheri_sequential_types$StatusReg) . 
+   if (((((bits_to_bool ((get_StatusReg_EXL w__0  :  1 words$word)))) \/ ((bits_to_bool ((get_StatusReg_ERL w__1  :  1 words$word))))))) then
+     returnS Kernel
+   else bindS     
+(read_regS CP0Status_ref) (\ (w__2 : cheri_sequential_types$StatusReg) . 
+     let p__132 = ((get_StatusReg_KSU w__2  :  2 words$word)) in
+     let b__0 = p__132 in
+     returnS (if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Kernel
+              else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Supervisor
+              else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then User
+              else User))))))`;
+
+
+(*val checkCP0Access : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((checkCP0Access:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(getAccessLevel () ) (\ accessLevel .  bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   if ((((((accessLevel <> Kernel))) /\ ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):sail_values$ii))))))))))
+   then seqS     
+(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B0;B0]  :  2 words$word)) (SignalException CpU)
+   else returnS () ))))`;
+
+
+(*val incrementCP0Count : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((incrementCP0Count:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS TLBRandom_ref  : ( 6 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$TLBIndexT) .  bindS
+   (read_regS TLBWired_ref  : ( 6 words$word) cheri_sequential_types$M) (\ (w__1 :  6 words$word) .  bindS
+   (if (((w__0 = w__1))) then returnS TLBIndexMax
+    else bindS
+      (read_regS TLBRandom_ref  : ( 6 words$word) cheri_sequential_types$M) (\ (w__2 :  6 words$word) . 
+      returnS ((sub_vec_int w__2 (( 1 : int):sail_values$ii)  :  6 words$word)))) (\ (w__3 :  6 words$word) .  bindS (seqS   
+(write_regS TLBRandom_ref w__3)
+   (read_regS CP0Count_ref  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__4 :  32 words$word) .  bindS (seqS   
+(write_regS CP0Count_ref ((add_vec_int w__4 (( 1 : int):sail_values$ii)  :  32 words$word)))
+   (read_regS CP0Count_ref  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__5 : 32 cheri_sequential_types$bits) .  bindS
+   (read_regS CP0Compare_ref  : ( 32 words$word) cheri_sequential_types$M) (\ (w__6 :  32 words$word) .  bindS (seqS
+   (if (((w__5 = w__6))) then bindS      
+(read_regS CP0Cause_ref) (\ (w__7 : cheri_sequential_types$CauseReg) . 
+      set_CauseReg_IP CP0Cause_ref
+        ((or_vec ((get_CauseReg_IP w__7  :  8 words$word))
+            (vec_of_bits [B1;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+           :  8 words$word)))
+    else returnS () )   
+(read_regS CP0Status_ref)) (\ (w__8 : cheri_sequential_types$StatusReg) . 
+   let ims = ((get_StatusReg_IM w__8  :  8 words$word)) in bindS   
+(read_regS CP0Cause_ref) (\ (w__9 : cheri_sequential_types$CauseReg) . 
+   let ips = ((get_CauseReg_IP w__9  :  8 words$word)) in bindS   
+(read_regS CP0Status_ref) (\ (w__10 : cheri_sequential_types$StatusReg) . 
+   let ie = ((get_StatusReg_IE w__10  :  1 words$word)) in bindS   
+(read_regS CP0Status_ref) (\ (w__11 : cheri_sequential_types$StatusReg) . 
+   let exl = ((get_StatusReg_EXL w__11  :  1 words$word)) in bindS   
+(read_regS CP0Status_ref) (\ (w__12 : cheri_sequential_types$StatusReg) . 
+   let erl = ((get_StatusReg_ERL w__12  :  1 words$word)) in
+   if (((((~ ((bits_to_bool exl)))) /\ (((((~ ((bits_to_bool erl)))) /\ (((((bits_to_bool ie)) /\ (((((and_vec ips ims  :  8 words$word)) <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))))))))) then
+     SignalException Interrupt
+   else returnS () )))))))))))))`;
+
+
+(*val decode_failure_of_num : Num.integer -> Cheri_sequential_types.decode_failure*)
+
+val _ = Define `
+ ((decode_failure_of_num:int -> cheri_sequential_types$decode_failure) arg_=   
+ (let l__74 = arg_ in
+   if (((l__74 = (( 0 : int):sail_values$ii)))) then No_matching_pattern
+   else if (((l__74 = (( 1 : int):sail_values$ii)))) then Unsupported_instruction
+   else if (((l__74 = (( 2 : int):sail_values$ii)))) then Illegal_instruction
+   else Internal_error))`;
+
+
+(*val num_of_decode_failure : Cheri_sequential_types.decode_failure -> Num.integer*)
+
+val _ = Define `
+ ((num_of_decode_failure:cheri_sequential_types$decode_failure -> int) arg_= 
+  ((case arg_ of   no_matching_pattern => (( 0 : int): sail_values$ii) )))`;
+
+
+(*val undefined_decode_failure : unit -> Cheri_sequential_types.M Cheri_sequential_types.decode_failure*)
+
+val _ = Define `
+ ((undefined_decode_failure:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$decode_failure),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =   
+ (internal_pick [No_matching_pattern;Unsupported_instruction;Illegal_instruction;Internal_error]))`;
+
+
+(*val Comparison_of_num : Num.integer -> Cheri_sequential_types.Comparison*)
+
+val _ = Define `
+ ((Comparison_of_num:int -> cheri_sequential_types$Comparison) arg_=   
+ (let l__67 = arg_ in
+   if (((l__67 = (( 0 : int):sail_values$ii)))) then EQ'
+   else if (((l__67 = (( 1 : int):sail_values$ii)))) then NE
+   else if (((l__67 = (( 2 : int):sail_values$ii)))) then GE
+   else if (((l__67 = (( 3 : int):sail_values$ii)))) then GEU
+   else if (((l__67 = (( 4 : int):sail_values$ii)))) then GT'
+   else if (((l__67 = (( 5 : int):sail_values$ii)))) then LE
+   else if (((l__67 = (( 6 : int):sail_values$ii)))) then LT'
+   else LTU))`;
+
+
+(*val num_of_Comparison : Cheri_sequential_types.Comparison -> Num.integer*)
+
+val _ = Define `
+ ((num_of_Comparison:cheri_sequential_types$Comparison -> int) arg_=   
+ ((case arg_ of
+     EQ' => (( 0 : int):sail_values$ii)
+   | NE => (( 1 : int):sail_values$ii)
+   | GE => (( 2 : int):sail_values$ii)
+   | GEU => (( 3 : int):sail_values$ii)
+   | GT' => (( 4 : int):sail_values$ii)
+   | LE => (( 5 : int):sail_values$ii)
+   | LT' => (( 6 : int):sail_values$ii)
+   | LTU => (( 7 : int):sail_values$ii)
+   )))`;
+
+
+(*val undefined_Comparison : unit -> Cheri_sequential_types.M Cheri_sequential_types.Comparison*)
+
+val _ = Define `
+ ((undefined_Comparison:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$Comparison),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [EQ';NE;GE;GEU;GT';LE;LT';LTU]))`;
+
+
+(*val compare : Cheri_sequential_types.Comparison -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> bool*)
+
+val _ = Define `
+ ((compare:cheri_sequential_types$Comparison ->(64)words$word ->(64)words$word -> bool) cmp valA valB=   
+ ((case cmp of
+     EQ' => (valA = valB)
+   | NE => (valA <> valB)
+   | GE => ((integer_word$w2i valA) >= (integer_word$w2i valB))
+   | GEU => ((lem$w2ui valA) >= (lem$w2ui valB))
+   | GT' => ((integer_word$w2i valB) < (integer_word$w2i valA))
+   | LE => ((integer_word$w2i valB) >= (integer_word$w2i valA))
+   | LT' => ((integer_word$w2i valA) < (integer_word$w2i valB))
+   | LTU => ((lem$w2ui valA) < (lem$w2ui valB))
+   )))`;
+
+
+(*val WordType_of_num : Num.integer -> Cheri_sequential_types.WordType*)
+
+val _ = Define `
+ ((WordType_of_num:int -> cheri_sequential_types$WordType) arg_=   
+ (let l__64 = arg_ in
+   if (((l__64 = (( 0 : int):sail_values$ii)))) then B
+   else if (((l__64 = (( 1 : int):sail_values$ii)))) then H
+   else if (((l__64 = (( 2 : int):sail_values$ii)))) then W0
+   else D))`;
+
+
+(*val num_of_WordType : Cheri_sequential_types.WordType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_WordType:cheri_sequential_types$WordType -> int) arg_=   
+ ((case arg_ of   B => (( 0 : int):sail_values$ii) | H => (( 1 : int):sail_values$ii) | W0 => (( 2 : int):sail_values$ii) | D => (( 3 : int):sail_values$ii) )))`;
+
+
+(*val undefined_WordType : unit -> Cheri_sequential_types.M Cheri_sequential_types.WordType*)
+
+val _ = Define `
+ ((undefined_WordType:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$WordType),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [B;H;W0;D]))`;
+
+
+(*val wordWidthBytes : Cheri_sequential_types.WordType -> Num.integer*)
+
+val _ = Define `
+ ((wordWidthBytes:cheri_sequential_types$WordType -> int) w=  ((case w of   B => (( 1 : int):sail_values$ii) | H => (( 2 : int):sail_values$ii) | W0 => (( 4 : int):sail_values$ii) | D => (( 8 : int):sail_values$ii) )))`;
+
+
+val _ = Define `
+ ((alignment_width:int)=  ((( 16 : int):sail_values$ii)))`;
+
+
+(*val isAddressAligned : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.WordType -> bool*)
+
+val _ = Define `
+ ((isAddressAligned:(64)words$word -> cheri_sequential_types$WordType -> bool) addr wordType=   
+ (let a = (lem$w2ui addr) in
+   (((a / alignment_width)) = ((((((a + ((wordWidthBytes wordType)))) - (( 1 : int):sail_values$ii))) /
+         alignment_width)))))`;
+
+
+(*val MEMr_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MEMr_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1=  (bindS
+   (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . 
+   returnS ((reverse_endianness w__0  :  'p8_times_n_ words$word)))))`;
+
+
+(*val MEMr_reserve_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Cheri_sequential_types.M (Machine_word.mword 'p8_times_n_)*)
+
+val _ = Define `
+ ((MEMr_reserve_wrapper:(64)words$word -> int ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((('p8_times_n_ words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1=  (bindS
+   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1  : ( 'p8_times_n_ words$word) cheri_sequential_types$M) (\ w__0 . 
+   returnS ((reverse_endianness w__0  :  'p8_times_n_ words$word)))))`;
+
+
+(*val init_cp0_state : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((init_cp0_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (set_StatusReg_BEV CP0Status_ref ((cast_unit_vec0 B1  :  1 words$word))))`;
+
+
+(*val init_cp2_state : unit -> Cheri_sequential_types.M unit*)
+
+(*val cp2_next_pc : unit -> Cheri_sequential_types.M unit*)
+
+(*val dump_cp2_state : unit -> Cheri_sequential_types.M unit*)
+
+(*val tlbEntryMatch : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty27 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.TLBEntry -> bool*)
+
+val _ = Define `
+ ((tlbEntryMatch:(2)words$word ->(27)words$word ->(8)words$word -> cheri_sequential_types$TLBEntry -> bool) r vpn2 asid entry=   
+ (let entryValid = ((get_TLBEntry_valid entry  :  1 words$word)) in
+   let entryR = ((get_TLBEntry_r entry  :  2 words$word)) in
+   let entryMask = ((get_TLBEntry_pagemask entry  :  16 words$word)) in
+   let entryVPN = ((get_TLBEntry_vpn2 entry  :  27 words$word)) in
+   let entryASID = ((get_TLBEntry_asid entry  :  8 words$word)) in
+   let entryG = ((get_TLBEntry_g entry  :  1 words$word)) in
+   let (vpnMask : 27 cheri_sequential_types$bits) =     
+((not_vec ((zero_extend1 (( 27 : int):sail_values$ii) entryMask  :  27 words$word))  :  27 words$word)) in
+   (((bits_to_bool entryValid)) /\ ((((((r = entryR))) /\ ((((((((and_vec vpn2 vpnMask  :  27 words$word)) = ((and_vec entryVPN vpnMask  :  27 words$word))))) /\ ((((((asid = entryASID))) \/ ((bits_to_bool entryG))))))))))))))`;
+
+
+(*val tlbSearch : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Maybe.maybe (Machine_word.mword Machine_word.ty6))*)
+
+val _ = Define `
+ ((tlbSearch:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((((6)words$word)option),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) VAddr=   
+ (catch_early_returnS
+     (let r = ((subrange_vec_dec VAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word)) in
+     let vpn2 = ((subrange_vec_dec VAddr (( 39 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  27 words$word)) in bindS     
+(liftRS (read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) . 
+     let asid = ((get_TLBEntryHiReg_ASID w__0  :  8 words$word)) in seqS
+     (foreachS (index_list (( 0 : int):sail_values$ii) (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () 
+       (\ idx unit_var .  bindS         
+(liftRS (read_regS ((access_list_dec TLBEntries idx)))) (\ (w__1 : cheri_sequential_types$TLBEntry) . 
+         if ((tlbEntryMatch r vpn2 asid w__1)) then
+           (early_returnS (SOME ((to_bits ((make_the_value (( 6 : int):sail_values$ii)  :  6 itself)) idx  :  6 words$word))) : (unit, ( ( 6 words$word)option))
+             cheri_sequential_types$MR)
+         else returnS () )))     
+(returnS NONE)))))`;
+
+
+(*val TLBTranslate2 : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*)
+
+val _ = Define `
+ ((TLBTranslate2:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType=  (bindS
+   (tlbSearch vAddr  : ( ( 6 words$word)option) cheri_sequential_types$M) (\ idx . 
+   (case idx of
+     SOME (idx) =>
+      let i = (lem$w2ui idx) in bindS      
+(read_regS ((access_list_dec TLBEntries i))) (\ entry . 
+      let entryMask = ((get_TLBEntry_pagemask entry  :  16 words$word)) in
+      let b__0 = entryMask in bindS
+      (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
+         returnS (( 12 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 14 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 16 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 18 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 20 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 22 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 24 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 26 : int):sail_values$ii)
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word))))
+       then
+         returnS (( 28 : int):sail_values$ii)
+       else undefined_range (( 12 : int):sail_values$ii) (( 28 : int):sail_values$ii)) (\ (evenOddBit : int) . 
+      let isOdd = (access_vec_dec vAddr evenOddBit) in
+      let ((caps : 1 cheri_sequential_types$bits), (capl : 1 cheri_sequential_types$bits), (pfn : 24 cheri_sequential_types$bits), (d : 1 cheri_sequential_types$bits), (v : 1 cheri_sequential_types$bits)) =        
+(if ((bit_to_bool isOdd)) then
+          ((get_TLBEntry_caps1 entry  :  1 words$word),
+           (get_TLBEntry_capl1 entry  :  1 words$word),
+           (get_TLBEntry_pfn1 entry  :  24 words$word),
+           (get_TLBEntry_d1 entry  :  1 words$word),
+           (get_TLBEntry_v1 entry  :  1 words$word))
+        else
+          ((get_TLBEntry_caps0 entry  :  1 words$word),
+           (get_TLBEntry_capl0 entry  :  1 words$word),
+           (get_TLBEntry_pfn0 entry  :  24 words$word),
+           (get_TLBEntry_d0 entry  :  1 words$word),
+           (get_TLBEntry_v0 entry  :  1 words$word))) in
+      if ((~ ((bits_to_bool v)))) then
+        (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBInvS else XTLBInvL) vAddr
+          : (( 64 words$word # bool)) cheri_sequential_types$M)
+      else if ((((((accessType = StoreData))) /\ ((~ ((bits_to_bool d))))))) then
+        (SignalExceptionTLB TLBMod vAddr  : (( 64 words$word # bool)) cheri_sequential_types$M)
+      else
+        let (res : 64 cheri_sequential_types$bits) =          
+((zero_extend1 (( 64 : int):sail_values$ii)
+             ((subrange_subrange_concat
+                 (((((((( 23 : int):sail_values$ii) -
+                             ((((evenOddBit - (( 12 : int):sail_values$ii))) - (( 1 : int):sail_values$ii)))))
+                         +
+                         ((evenOddBit - (( 1 : int):sail_values$ii)))))
+                     - (((( 0 : int):sail_values$ii) - (( 1 : int):sail_values$ii))))) pfn
+                 (( 23 : int):sail_values$ii) ((evenOddBit - (( 12 : int):sail_values$ii))) vAddr
+                 ((evenOddBit - (( 1 : int):sail_values$ii))) (( 0 : int):sail_values$ii)
+                :  36 words$word))
+            :  64 words$word)) in
+        returnS (res, bits_to_bool (if (((accessType = StoreData))) then caps else capl))))
+   | NONE =>
+      (SignalExceptionTLB (if (((accessType = StoreData))) then XTLBRefillS else XTLBRefillL) vAddr
+        : (( 64 words$word # bool)) cheri_sequential_types$M)
+   ))))`;
+
+
+(*val TLBTranslateC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64 * bool)*)
+
+val _ = Define `
+ ((TLBTranslateC:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word#bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType=  (bindS   
+(getAccessLevel () ) (\ currentAccessLevel . 
+   let compat32 =
+     (((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 31 : int):sail_values$ii)  :  31 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
+         :  31 words$word)) in
+   let b__0 = ((subrange_vec_dec vAddr (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word)) in
+   let ((requiredLevel : cheri_sequential_types$AccessLevel), (addr :  ( 64 cheri_sequential_types$bits)option)) =     
+(if (((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) then
+       (case (compat32, (subrange_vec_dec vAddr (( 30 : int):sail_values$ii) (( 29 : int):sail_values$ii)  :  2 words$word)) of
+         (T, b__1) =>
+          if (((b__1 = (vec_of_bits [B1;B1]  :  2 words$word)))) then (Kernel, NONE)
+          else if (((b__1 = (vec_of_bits [B1;B0]  :  2 words$word)))) then (Supervisor, NONE)
+          else if (((b__1 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+            (Kernel,
+             SOME ((concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        :  32 words$word)
+                      ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                          ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  29 words$word))
+                         :  32 words$word))
+                     :  64 words$word)))
+          else
+            (Kernel,
+             SOME ((concat_vec
+                      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                        :  32 words$word)
+                      ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word)
+                          ((subrange_vec_dec vAddr (( 28 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  29 words$word))
+                         :  32 words$word))
+                     :  64 words$word)))
+       | (g__130, g__131) => (Kernel, NONE)
+       )
+     else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (Kernel,
+        SOME ((concat_vec (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)
+                 ((subrange_vec_dec vAddr (( 58 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  59 words$word))
+                :  64 words$word)))
+     else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then (Supervisor, NONE)
+     else (User, NONE)) in
+   if ((~ ((grantsAccess currentAccessLevel requiredLevel)))) then
+     (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+       : (( 64 words$word # bool)) cheri_sequential_types$M)
+   else bindS
+     (case addr of
+       SOME (a) => returnS (a, F)
+     | NONE =>
+        if (((((~ compat32)) /\ ((((lem$w2ui ((subrange_vec_dec vAddr (( 61 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  62 words$word)))) > MAX_VA))))) then
+          (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+            : (( 64 words$word # bool)) cheri_sequential_types$M)
+        else (TLBTranslate2 vAddr accessType  : (( 64 words$word # bool)) cheri_sequential_types$M)
+     ) (\ varstup .  let ((pa : 64 cheri_sequential_types$bits), (c : bool)) = varstup in
+     if ((((lem$w2ui pa)) > MAX_PA)) then
+       (SignalExceptionBadAddr (if (((accessType = StoreData))) then AdES else AdEL) vAddr
+         : (( 64 words$word # bool)) cheri_sequential_types$M)
+     else returnS (pa, c)))))`;
+
+
+(*val TLBTranslate : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((TLBTranslate:(64)words$word -> cheri_sequential_types$MemAccessType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr accessType=  (bindS
+   (TLBTranslateC vAddr accessType  : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup .  let (addr, c) = varstup in
+   returnS addr)))`;
+
+
+(*val CPtrCmpOp_of_num : Num.integer -> Cheri_sequential_types.CPtrCmpOp*)
+
+val _ = Define `
+ ((CPtrCmpOp_of_num:int -> cheri_sequential_types$CPtrCmpOp) arg_=   
+ (let l__57 = arg_ in
+   if (((l__57 = (( 0 : int):sail_values$ii)))) then CEQ
+   else if (((l__57 = (( 1 : int):sail_values$ii)))) then CNE
+   else if (((l__57 = (( 2 : int):sail_values$ii)))) then CLT
+   else if (((l__57 = (( 3 : int):sail_values$ii)))) then CLE
+   else if (((l__57 = (( 4 : int):sail_values$ii)))) then CLTU
+   else if (((l__57 = (( 5 : int):sail_values$ii)))) then CLEU
+   else if (((l__57 = (( 6 : int):sail_values$ii)))) then CEXEQ
+   else CNEXEQ))`;
+
+
+(*val num_of_CPtrCmpOp : Cheri_sequential_types.CPtrCmpOp -> Num.integer*)
+
+val _ = Define `
+ ((num_of_CPtrCmpOp:cheri_sequential_types$CPtrCmpOp -> int) arg_=   
+ ((case arg_ of
+     CEQ => (( 0 : int):sail_values$ii)
+   | CNE => (( 1 : int):sail_values$ii)
+   | CLT => (( 2 : int):sail_values$ii)
+   | CLE => (( 3 : int):sail_values$ii)
+   | CLTU => (( 4 : int):sail_values$ii)
+   | CLEU => (( 5 : int):sail_values$ii)
+   | CEXEQ => (( 6 : int):sail_values$ii)
+   | CNEXEQ => (( 7 : int):sail_values$ii)
+   )))`;
+
+
+(*val undefined_CPtrCmpOp : unit -> Cheri_sequential_types.M Cheri_sequential_types.CPtrCmpOp*)
+
+val _ = Define `
+ ((undefined_CPtrCmpOp:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CPtrCmpOp),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [CEQ;CNE;CLT;CLE;CLTU;CLEU;CEXEQ;CNEXEQ]))`;
+
+
+(*val ClearRegSet_of_num : Num.integer -> Cheri_sequential_types.ClearRegSet*)
+
+val _ = Define `
+ ((ClearRegSet_of_num:int -> cheri_sequential_types$ClearRegSet) arg_=   
+ (let l__54 = arg_ in
+   if (((l__54 = (( 0 : int):sail_values$ii)))) then GPLo
+   else if (((l__54 = (( 1 : int):sail_values$ii)))) then GPHi
+   else if (((l__54 = (( 2 : int):sail_values$ii)))) then CLo
+   else CHi))`;
+
+
+(*val num_of_ClearRegSet : Cheri_sequential_types.ClearRegSet -> Num.integer*)
+
+val _ = Define `
+ ((num_of_ClearRegSet:cheri_sequential_types$ClearRegSet -> int) arg_=   
+ ((case arg_ of   GPLo => (( 0 : int):sail_values$ii) | GPHi => (( 1 : int):sail_values$ii) | CLo => (( 2 : int):sail_values$ii) | CHi => (( 3 : int):sail_values$ii) )))`;
+
+
+(*val undefined_ClearRegSet : unit -> Cheri_sequential_types.M Cheri_sequential_types.ClearRegSet*)
+
+val _ = Define `
+ ((undefined_ClearRegSet:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ClearRegSet),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (internal_pick [GPLo;GPHi;CLo;CHi]))`;
+
+
+(*val undefined_CapStruct : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*)
+
+val _ = Define `
+ ((undefined_CapStruct:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(undefined_bool0 () ) (\ (w__0 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 : 8 cheri_sequential_types$bits) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 24 : int):sail_values$ii)  : ( 24 words$word) cheri_sequential_types$M) (\ (w__2 : 24 cheri_sequential_types$bits) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 : 16 cheri_sequential_types$bits) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 4 : int):sail_values$ii)  : ( 4 words$word) cheri_sequential_types$M) (\ (w__4 : 4 cheri_sequential_types$bits) .  bindS   
+(undefined_bool0 () ) (\ (w__5 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__6 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__7 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__8 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__9 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__10 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__11 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__12 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__13 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__14 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__15 : bool) .  bindS   
+(undefined_bool0 () ) (\ (w__16 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__17 : 64 cheri_sequential_types$bits) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__18 : 64 cheri_sequential_types$bits) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__19 : 64 cheri_sequential_types$bits) . 
+   returnS (<| CapStruct_tag := w__0; 
+               CapStruct_padding := w__1; 
+               CapStruct_otype := w__2; 
+               CapStruct_uperms := w__3; 
+               CapStruct_perm_reserved11_14 := w__4; 
+               CapStruct_access_system_regs := w__5; 
+               CapStruct_permit_unseal := w__6; 
+               CapStruct_permit_ccall := w__7; 
+               CapStruct_permit_seal := w__8; 
+               CapStruct_permit_store_local_cap := w__9; 
+               CapStruct_permit_store_cap := w__10; 
+               CapStruct_permit_load_cap := w__11; 
+               CapStruct_permit_store := w__12; 
+               CapStruct_permit_load := w__13; 
+               CapStruct_permit_execute := w__14; 
+               CapStruct_global := w__15; 
+               CapStruct_sealed := w__16; 
+               CapStruct_address := w__17; 
+               CapStruct_base := w__18; 
+               CapStruct_length := w__19 |>)))))))))))))))))))))))`;
+
+
+val _ = Define `
+((default_cap:cheri_sequential_types$CapStruct)=  
+ (<| CapStruct_tag := T; 
+     CapStruct_padding := ((zeros (( 8 : int):sail_values$ii) ()   :  8 words$word)); 
+     CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) ()   :  24 words$word)); 
+     CapStruct_uperms := ((ones (( 16 : int):sail_values$ii) ()   :  16 words$word)); 
+     CapStruct_perm_reserved11_14 := ((ones (( 4 : int):sail_values$ii) ()   :  4 words$word)); 
+     CapStruct_access_system_regs := T; 
+     CapStruct_permit_unseal := T; 
+     CapStruct_permit_ccall := T; 
+     CapStruct_permit_seal := T; 
+     CapStruct_permit_store_local_cap := T; 
+     CapStruct_permit_store_cap := T; 
+     CapStruct_permit_load_cap := T; 
+     CapStruct_permit_store := T; 
+     CapStruct_permit_load := T; 
+     CapStruct_permit_execute := T; 
+     CapStruct_global := T; 
+     CapStruct_sealed := F; 
+     CapStruct_address := ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)); 
+     CapStruct_base := ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)); 
+     CapStruct_length :=       
+((vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                     B1]
+         :  64 words$word)) |>))`;
+
+
+val _ = Define `
+((null_cap_bits:(256)words$word)=  ((capStructToMemBits256 null_cap  :  256 words$word)))`;
+
+
+(*val capStructToMemBits : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty256*)
+
+val _ = Define `
+ ((capStructToMemBits:cheri_sequential_types$CapStruct ->(256)words$word) cap=   
+ ((xor_vec ((capStructToMemBits256 cap  :  256 words$word)) null_cap_bits  :  256 words$word)))`;
+
+
+(*val memBitsToCapBits : bool -> Machine_word.mword Machine_word.ty256 -> Machine_word.mword Machine_word.ty257*)
+
+val _ = Define `
+ ((memBitsToCapBits:bool ->(256)words$word ->(257)words$word) tag b=   
+ ((concat_vec ((bool_to_bits tag  :  1 words$word)) ((xor_vec b null_cap_bits  :  256 words$word))
+     :  257 words$word)))`;
+
+
+(*val setCapPerms : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty31 -> Cheri_sequential_types.CapStruct*)
+
+val _ = Define `
+ ((setCapPerms:cheri_sequential_types$CapStruct ->(31)words$word -> cheri_sequential_types$CapStruct) cap perms=   
+ ((cap with<|
+     CapStruct_uperms := ((subrange_vec_dec perms (( 30 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  16 words$word)); CapStruct_perm_reserved11_14 :=
+       ((subrange_vec_dec perms (( 14 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  4 words$word)); CapStruct_access_system_regs :=
+       ((bit_to_bool ((access_vec_dec perms (( 10 : int):sail_values$ii))))); CapStruct_permit_unseal :=
+       ((bit_to_bool ((access_vec_dec perms (( 9 : int):sail_values$ii))))); CapStruct_permit_ccall :=
+       ((bit_to_bool ((access_vec_dec perms (( 8 : int):sail_values$ii))))); CapStruct_permit_seal :=
+       ((bit_to_bool ((access_vec_dec perms (( 7 : int):sail_values$ii))))); CapStruct_permit_store_local_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 6 : int):sail_values$ii))))); CapStruct_permit_store_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 5 : int):sail_values$ii))))); CapStruct_permit_load_cap :=
+       ((bit_to_bool ((access_vec_dec perms (( 4 : int):sail_values$ii))))); CapStruct_permit_store :=
+       ((bit_to_bool ((access_vec_dec perms (( 3 : int):sail_values$ii))))); CapStruct_permit_load :=
+       ((bit_to_bool ((access_vec_dec perms (( 2 : int):sail_values$ii))))); CapStruct_permit_execute :=
+       ((bit_to_bool ((access_vec_dec perms (( 1 : int):sail_values$ii))))); CapStruct_global :=
+       ((bit_to_bool ((access_vec_dec perms (( 0 : int):sail_values$ii)))))|>)))`;
+
+
+(*val sealCap : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty24 -> (bool * Cheri_sequential_types.CapStruct)*)
+
+val _ = Define `
+ ((sealCap:cheri_sequential_types$CapStruct ->(24)words$word -> bool#cheri_sequential_types$CapStruct) cap otype=  (T, (cap with<| CapStruct_sealed := T; CapStruct_otype := otype|>)))`;
+
+
+(*val getCapTop : Cheri_sequential_types.CapStruct -> Num.integer*)
+
+val _ = Define `
+ ((getCapTop:cheri_sequential_types$CapStruct -> int) c=  (((lem$w2ui c.CapStruct_base)) + ((lem$w2ui c.CapStruct_length))))`;
+
+
+(*val getCapOffset : Cheri_sequential_types.CapStruct -> Num.integer*)
+
+val _ = Define `
+ ((getCapOffset:cheri_sequential_types$CapStruct -> int) c=   
+ (hardware_mod ((((lem$w2ui c.CapStruct_address)) - ((lem$w2ui c.CapStruct_base))))
+     ((pow2 (( 64 : int):sail_values$ii)))))`;
+
+
+(*val getCapLength : Cheri_sequential_types.CapStruct -> Num.integer*)
+
+val _ = Define `
+ ((getCapLength:cheri_sequential_types$CapStruct -> int) c=  (lem$w2ui c.CapStruct_length))`;
+
+
+(*val getCapCursor : Cheri_sequential_types.CapStruct -> Num.integer*)
+
+val _ = Define `
+ ((getCapCursor:cheri_sequential_types$CapStruct -> int) c=  (lem$w2ui c.CapStruct_address))`;
+
+
+(*val incCapOffset : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> (bool * Cheri_sequential_types.CapStruct)*)
+
+val _ = Define `
+ ((incCapOffset:cheri_sequential_types$CapStruct ->(64)words$word -> bool#cheri_sequential_types$CapStruct) c delta=   
+ (let (newAddr : 64 cheri_sequential_types$bits) = ((add_vec c.CapStruct_address delta  :  64 words$word)) in
+   (T, (c with<| CapStruct_address := newAddr|>))))`;
+
+
+(*val setCapBounds : Cheri_sequential_types.CapStruct -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty65 -> (bool * Cheri_sequential_types.CapStruct)*)
+
+val _ = Define `
+ ((setCapBounds:cheri_sequential_types$CapStruct ->(64)words$word ->(65)words$word -> bool#cheri_sequential_types$CapStruct) cap base top=   
+ (let (length : 65 cheri_sequential_types$bits) =     
+((sub_vec top ((concat_vec (vec_of_bits [B0]  :  1 words$word) base  :  65 words$word))  :  65 words$word)) in
+   (T,
+    (cap with<|
+      CapStruct_base := base; CapStruct_length :=
+        ((subrange_vec_dec length (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)); CapStruct_address := base|>))))`;
+
+
+(*val undefined_ast : unit -> Cheri_sequential_types.M Cheri_sequential_types.ast*)
+
+val _ = Define `
+ ((undefined_ast:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$ast),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__0 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__1 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__3 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__4 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__5 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__6 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__7 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__8 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__9 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__10 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__11 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__12 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__13 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__14 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__15 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__16 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__17 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__18 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__19 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__20 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__21 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__22 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__23 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__24 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__25 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__26 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__27 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__28 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__29 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__30 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__31 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__32 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__33 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__34 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__35 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__36 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__37 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__38 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__39 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__40 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__41 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__42 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__43 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__44 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__45 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__46 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__47 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__48 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__49 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__50 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__51 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__52 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__53 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__54 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__55 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__56 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__57 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__58 :  16 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__59 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__60 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__61 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__62 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__63 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__64 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__65 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__66 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__67 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__68 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__69 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__70 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__71 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__72 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__73 :  5 words$word) .  bindS
+   (undefined_bitvector 
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+   (undefined_bitvector 
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+   (undefined_bitvector 
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+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__297 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__298 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__299 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__300 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__301 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__302 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__303 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__304 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__305 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__306 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__307 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__308 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__309 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__310 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__311 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__312 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__313 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__314 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__315 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii)  : ( 11 words$word) cheri_sequential_types$M) (\ (w__316 :  11 words$word) .  bindS (seqS   
+(undefined_unit () )
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M)) (\ (w__317 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__318 :  16 words$word) .  bindS   
+(undefined_bool0 () ) (\ (w__319 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__320 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__321 :  16 words$word) .  bindS   
+(undefined_bool0 () ) (\ (w__322 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__323 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__324 :  5 words$word) .  bindS   
+(undefined_bool0 () ) (\ (w__325 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__326 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__327 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__328 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__329 :  8 words$word) .  bindS   
+(undefined_bool0 () ) (\ (w__330 : bool) .  bindS   
+(undefined_WordType () ) (\ (w__331 : cheri_sequential_types$WordType) .  bindS   
+(undefined_bool0 () ) (\ (w__332 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__333 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__334 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__335 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__336 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__337 :  8 words$word) .  bindS   
+(undefined_WordType () ) (\ (w__338 : cheri_sequential_types$WordType) .  bindS   
+(undefined_bool0 () ) (\ (w__339 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__340 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__341 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__342 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__343 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii)  : ( 11 words$word) cheri_sequential_types$M) (\ (w__344 :  11 words$word) .  bindS   
+(undefined_bool0 () ) (\ (w__345 : bool) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__346 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__347 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__348 :  5 words$word) .  bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 11 : int):sail_values$ii)  : ( 11 words$word) cheri_sequential_types$M) (\ (w__349 :  11 words$word) .  bindS   
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+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 5 : int):sail_values$ii)  : ( 5 words$word) cheri_sequential_types$M) (\ (w__351 :  5 words$word) .  seqS   
+(undefined_unit () )   
+(internal_pick
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+
+
+(*val execute : Cheri_sequential_types.ast -> Cheri_sequential_types.M unit*)
+
+(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Cheri_sequential_types.ast*)
+
+val _ = Define `
+((DDC:(5)words$word)=  ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((IDC:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((KR1C:(5)words$word)=  ((vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((KR2C:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((KCC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((KDC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((EPCC:(5)words$word)=  ((vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((CapRegs:(((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapReg))sail_values$register_ref)list)=  
+ ([C31_ref;C30_ref;C29_ref;C28_ref;C27_ref;C26_ref;C25_ref;C24_ref;C23_ref;C22_ref;C21_ref;C20_ref;C19_ref;C18_ref;C17_ref;C16_ref;C15_ref;C14_ref;C13_ref;C12_ref;C11_ref;
+   C10_ref;C09_ref;C08_ref;C07_ref;C06_ref;C05_ref;C04_ref;C03_ref;C02_ref;C01_ref;C00_ref]))`;
+
+
+val _ = Define `
+ ((max_otype:int)=  (MAX0 (( 24 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((have_cp2:bool)=  T)`;
+
+
+(*val readCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M Cheri_sequential_types.CapStruct*)
+
+val _ = Define `
+ ((readCapReg:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapStruct),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n=   
+ (let i = (lem$w2ui n) in bindS
+   (read_regS ((access_list_dec CapRegs i  : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref))
+     : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 :  257 words$word) . 
+   returnS ((capRegToCapStruct w__0)))))`;
+
+
+(*val writeCapReg : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((writeCapReg:(5)words$word -> cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) n cap=   
+ (let i = (lem$w2ui n) in
+   write_regS
+     ((access_list_dec CapRegs i  : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref))
+     ((capStructToCapReg cap  :  257 words$word))))`;
+
+
+(*val CapEx_of_num : Num.integer -> Cheri_sequential_types.CapEx*)
+
+val _ = Define `
+ ((CapEx_of_num:int -> cheri_sequential_types$CapEx) arg_=   
+ (let l__32 = arg_ in
+   if (((l__32 = (( 0 : int):sail_values$ii)))) then CapEx_None
+   else if (((l__32 = (( 1 : int):sail_values$ii)))) then CapEx_LengthViolation
+   else if (((l__32 = (( 2 : int):sail_values$ii)))) then CapEx_TagViolation
+   else if (((l__32 = (( 3 : int):sail_values$ii)))) then CapEx_SealViolation
+   else if (((l__32 = (( 4 : int):sail_values$ii)))) then CapEx_TypeViolation
+   else if (((l__32 = (( 5 : int):sail_values$ii)))) then CapEx_CallTrap
+   else if (((l__32 = (( 6 : int):sail_values$ii)))) then CapEx_ReturnTrap
+   else if (((l__32 = (( 7 : int):sail_values$ii)))) then CapEx_TSSUnderFlow
+   else if (((l__32 = (( 8 : int):sail_values$ii)))) then CapEx_UserDefViolation
+   else if (((l__32 = (( 9 : int):sail_values$ii)))) then CapEx_TLBNoStoreCap
+   else if (((l__32 = (( 10 : int):sail_values$ii)))) then CapEx_InexactBounds
+   else if (((l__32 = (( 11 : int):sail_values$ii)))) then CapEx_GlobalViolation
+   else if (((l__32 = (( 12 : int):sail_values$ii)))) then CapEx_PermitExecuteViolation
+   else if (((l__32 = (( 13 : int):sail_values$ii)))) then CapEx_PermitLoadViolation
+   else if (((l__32 = (( 14 : int):sail_values$ii)))) then CapEx_PermitStoreViolation
+   else if (((l__32 = (( 15 : int):sail_values$ii)))) then CapEx_PermitLoadCapViolation
+   else if (((l__32 = (( 16 : int):sail_values$ii)))) then CapEx_PermitStoreCapViolation
+   else if (((l__32 = (( 17 : int):sail_values$ii)))) then CapEx_PermitStoreLocalCapViolation
+   else if (((l__32 = (( 18 : int):sail_values$ii)))) then CapEx_PermitSealViolation
+   else if (((l__32 = (( 19 : int):sail_values$ii)))) then CapEx_AccessSystemRegsViolation
+   else if (((l__32 = (( 20 : int):sail_values$ii)))) then CapEx_PermitCCallViolation
+   else if (((l__32 = (( 21 : int):sail_values$ii)))) then CapEx_AccessCCallIDCViolation
+   else CapEx_PermitUnsealViolation))`;
+
+
+(*val num_of_CapEx : Cheri_sequential_types.CapEx -> Num.integer*)
+
+val _ = Define `
+ ((num_of_CapEx:cheri_sequential_types$CapEx -> int) arg_=   
+ ((case arg_ of
+     CapEx_None => (( 0 : int):sail_values$ii)
+   | CapEx_LengthViolation => (( 1 : int):sail_values$ii)
+   | CapEx_TagViolation => (( 2 : int):sail_values$ii)
+   | CapEx_SealViolation => (( 3 : int):sail_values$ii)
+   | CapEx_TypeViolation => (( 4 : int):sail_values$ii)
+   | CapEx_CallTrap => (( 5 : int):sail_values$ii)
+   | CapEx_ReturnTrap => (( 6 : int):sail_values$ii)
+   | CapEx_TSSUnderFlow => (( 7 : int):sail_values$ii)
+   | CapEx_UserDefViolation => (( 8 : int):sail_values$ii)
+   | CapEx_TLBNoStoreCap => (( 9 : int):sail_values$ii)
+   | CapEx_InexactBounds => (( 10 : int):sail_values$ii)
+   | CapEx_GlobalViolation => (( 11 : int):sail_values$ii)
+   | CapEx_PermitExecuteViolation => (( 12 : int):sail_values$ii)
+   | CapEx_PermitLoadViolation => (( 13 : int):sail_values$ii)
+   | CapEx_PermitStoreViolation => (( 14 : int):sail_values$ii)
+   | CapEx_PermitLoadCapViolation => (( 15 : int):sail_values$ii)
+   | CapEx_PermitStoreCapViolation => (( 16 : int):sail_values$ii)
+   | CapEx_PermitStoreLocalCapViolation => (( 17 : int):sail_values$ii)
+   | CapEx_PermitSealViolation => (( 18 : int):sail_values$ii)
+   | CapEx_AccessSystemRegsViolation => (( 19 : int):sail_values$ii)
+   | CapEx_PermitCCallViolation => (( 20 : int):sail_values$ii)
+   | CapEx_AccessCCallIDCViolation => (( 21 : int):sail_values$ii)
+   | CapEx_PermitUnsealViolation => (( 22 : int):sail_values$ii)
+   )))`;
+
+
+(*val undefined_CapEx : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapEx*)
+
+val _ = Define `
+ ((undefined_CapEx:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapEx),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =   
+ (internal_pick
+     [CapEx_None;CapEx_LengthViolation;CapEx_TagViolation;CapEx_SealViolation;CapEx_TypeViolation;CapEx_CallTrap;CapEx_ReturnTrap;CapEx_TSSUnderFlow;CapEx_UserDefViolation;CapEx_TLBNoStoreCap;CapEx_InexactBounds;CapEx_GlobalViolation;CapEx_PermitExecuteViolation;CapEx_PermitLoadViolation;CapEx_PermitStoreViolation;CapEx_PermitLoadCapViolation;CapEx_PermitStoreCapViolation;CapEx_PermitStoreLocalCapViolation;CapEx_PermitSealViolation;CapEx_AccessSystemRegsViolation;CapEx_PermitCCallViolation;CapEx_AccessCCallIDCViolation;CapEx_PermitUnsealViolation]))`;
+
+
+(*val CapExCode : Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((CapExCode:cheri_sequential_types$CapEx ->(8)words$word) ex=   
+ ((case ex of
+     CapEx_None => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)
+   | CapEx_LengthViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1]  :  8 words$word)
+   | CapEx_TagViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0]  :  8 words$word)
+   | CapEx_SealViolation => (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1]  :  8 words$word)
+   | CapEx_TypeViolation => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0]  :  8 words$word)
+   | CapEx_CallTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1]  :  8 words$word)
+   | CapEx_ReturnTrap => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B0]  :  8 words$word)
+   | CapEx_TSSUnderFlow => (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1]  :  8 words$word)
+   | CapEx_UserDefViolation => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B0]  :  8 words$word)
+   | CapEx_TLBNoStoreCap => (vec_of_bits [B0;B0;B0;B0;B1;B0;B0;B1]  :  8 words$word)
+   | CapEx_InexactBounds => (vec_of_bits [B0;B0;B0;B0;B1;B0;B1;B0]  :  8 words$word)
+   | CapEx_GlobalViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0]  :  8 words$word)
+   | CapEx_PermitExecuteViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B1]  :  8 words$word)
+   | CapEx_PermitLoadViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B0]  :  8 words$word)
+   | CapEx_PermitStoreViolation => (vec_of_bits [B0;B0;B0;B1;B0;B0;B1;B1]  :  8 words$word)
+   | CapEx_PermitLoadCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0]  :  8 words$word)
+   | CapEx_PermitStoreCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B1]  :  8 words$word)
+   | CapEx_PermitStoreLocalCapViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B0]  :  8 words$word)
+   | CapEx_PermitSealViolation => (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1]  :  8 words$word)
+   | CapEx_AccessSystemRegsViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0]  :  8 words$word)
+   | CapEx_PermitCCallViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B1]  :  8 words$word)
+   | CapEx_AccessCCallIDCViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B0]  :  8 words$word)
+   | CapEx_PermitUnsealViolation => (vec_of_bits [B0;B0;B0;B1;B1;B0;B1;B1]  :  8 words$word)
+   )))`;
+
+
+(*val undefined_CapCauseReg : unit -> Cheri_sequential_types.M Cheri_sequential_types.CapCauseReg*)
+
+val _ = Define `
+ ((undefined_CapCauseReg:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((cheri_sequential_types$CapCauseReg),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__0 :  16 words$word) . 
+   internal_pick [Mk_CapCauseReg w__0])))`;
+
+
+val _ = Define `
+ ((get_CapCauseReg:cheri_sequential_types$CapCauseReg ->(16)words$word) (Mk_CapCauseReg (v))=  v)`;
+
+
+val _ = Define `
+ ((set_CapCauseReg:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ r . 
+   let r = (Mk_CapCauseReg v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))=  ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+val _ = Define `
+ ((set_CapCauseReg_ExcCode:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . 
+   let r = ((get_CapCauseReg w__0  :  16 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  16 words$word)) in
+   write_regS r_ref (Mk_CapCauseReg r))))`;
+
+
+val _ = Define `
+ ((update_CapCauseReg_ExcCode:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x=   
+ (Mk_CapCauseReg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  16 words$word))))`;
+
+
+(*val _get_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word) (Mk_CapCauseReg (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_CapCauseReg_RegNum : Sail_values.register_ref Cheri_sequential_types.regstate Cheri_sequential_types.register_value Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_CapCauseReg_RegNum:((cheri_sequential_types$regstate),(cheri_sequential_types$register_value),(cheri_sequential_types$CapCauseReg))sail_values$register_ref ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(read_regS r_ref) (\ (w__0 : cheri_sequential_types$CapCauseReg) . 
+   let r = ((get_CapCauseReg w__0  :  16 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  16 words$word)) in
+   write_regS r_ref (Mk_CapCauseReg r))))`;
+
+
+(*val _update_CapCauseReg_RegNum : Cheri_sequential_types.CapCauseReg -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.CapCauseReg*)
+
+val _ = Define `
+ ((update_CapCauseReg_RegNum:cheri_sequential_types$CapCauseReg ->(8)words$word -> cheri_sequential_types$CapCauseReg) (Mk_CapCauseReg (v)) x=   
+ (Mk_CapCauseReg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  16 words$word))))`;
+
+
+(*val execute_branch_pcc : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_branch_pcc:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) newPCC=  (seqS (seqS   
+(write_regS
+     delayedPC_ref
+     ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapOffset newPCC))  :  64 words$word)))   
+(write_regS delayedPCC_ref ((capStructToCapReg newPCC  :  257 words$word))))   
+(write_regS branchPending_ref (vec_of_bits [B1]  :  1 words$word))))`;
+
+
+(*val ERETHook : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((ERETHook:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS C31_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS nextPCC_ref w__0)
+   (read_regS C31_ref  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__1 : cheri_sequential_types$CapReg) .  write_regS delayedPCC_ref w__1))))`;
+
+
+(*val raise_c2_exception8 : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.M 'o*)
+
+val _ = Define `
+ ((raise_c2_exception8:cheri_sequential_types$CapEx ->(8)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum=  (seqS (seqS   
+(set_CapCauseReg_ExcCode CapCause_ref ((CapExCode capEx  :  8 words$word)))   
+(set_CapCauseReg_RegNum CapCause_ref regnum))   
+(let mipsEx =     
+(if ((((((capEx = CapEx_CallTrap))) \/ (((capEx = CapEx_ReturnTrap)))))) then C2Trap
+     else C2E) in
+   SignalException mipsEx)))`;
+
+
+(*val raise_c2_exception : forall 'o. Cheri_sequential_types.CapEx -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M 'o*)
+
+val _ = Define `
+ ((raise_c2_exception:cheri_sequential_types$CapEx ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx regnum=   
+ (let reg8 = ((concat_vec (vec_of_bits [B0;B0;B0]  :  3 words$word) regnum  :  8 words$word)) in
+   if ((((((capEx = CapEx_AccessSystemRegsViolation))) /\ (((regnum = IDC)))))) then
+     raise_c2_exception8 CapEx_AccessCCallIDCViolation reg8
+   else raise_c2_exception8 capEx reg8))`;
+
+
+(*val raise_c2_exception_noreg : forall 'o. Cheri_sequential_types.CapEx -> Cheri_sequential_types.M 'o*)
+
+val _ = Define `
+ ((raise_c2_exception_noreg:cheri_sequential_types$CapEx ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(('o,(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) capEx=   
+ (raise_c2_exception8 capEx (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1]  :  8 words$word)))`;
+
+
+(*val pcc_access_system_regs : unit -> Cheri_sequential_types.M bool*)
+
+val _ = Define `
+ ((pcc_access_system_regs:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 :  257 words$word) . 
+   let pcc = (capRegToCapStruct w__0) in
+   returnS pcc.CapStruct_access_system_regs)))`;
+
+
+(*val register_inaccessible : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M bool*)
+
+val _ = Define `
+ ((register_inaccessible:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) r=  (bindS
+   (read_regS inCCallDelay_ref  : ( 1 words$word) cheri_sequential_types$M) (\ (w__0 :  1 words$word) . 
+   if ((((((r = IDC))) /\ ((bits_to_bool w__0))))) then returnS T
+   else
+     let b__0 = r in
+     let (is_sys_reg : bool) =       
+(if (((b__0 = (vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))) then T
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))) then T
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))) then T
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))) then T
+       else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word)))) then T
+       else F) in
+     if is_sys_reg then bindS (pcc_access_system_regs () ) (\ (w__1 : bool) .  returnS ((~ w__1)))
+     else returnS F)))`;
+
+
+(*val MEMr_tagged : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*)
+
+val _ = Define `
+ ((MEMr_tagged:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr=  (bindS (seqS   
+(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "")   
+(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  bindS
+   (MEMr instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) cheri_sequential_types$M) (\ data . 
+   let ((cast_0 : bool), (cast_1 :  256 words$word)) = (tag, (reverse_endianness data  :  256 words$word)) in
+   returnS (cast_0, (words$w2w cast_1  :  256 words$word))))))`;
+
+
+(*val MEMr_tagged_reserve : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (bool * Machine_word.mword Machine_word.ty256)*)
+
+val _ = Define `
+ ((MEMr_tagged_reserve:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool#(256)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr=  (bindS (seqS   
+(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "")   
+(read_tag_bool instance_Sail_values_Bitvector_Machine_word_mword_dict addr)) (\ tag .  bindS
+   (MEMr_reserve instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size  : ( 256 words$word) cheri_sequential_types$M) (\ data . 
+   let ((cast_0 : bool), (cast_1 :  256 words$word)) = (tag, (reverse_endianness data  :  256 words$word)) in
+   returnS (cast_0, (words$w2w cast_1  :  256 words$word))))))`;
+
+
+(*val MEMw_tagged : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((MEMw_tagged:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data=  (seqS (seqS (seqS   
+(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "")   
+(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size))   
+(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (write_tag_bool 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag)))`;
+
+
+(*val MEMw_tagged_conditional : Machine_word.mword Machine_word.ty64 -> bool -> Machine_word.mword Machine_word.ty256 -> Cheri_sequential_types.M bool*)
+
+val _ = Define `
+ ((MEMw_tagged_conditional:(64)words$word -> bool ->(256)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr tag data=  (bindS (seqS (seqS   
+(assert_expS (((((hardware_mod ((lem$w2ui addr)) cap_size)) = (( 0 : int):sail_values$ii)))) "")   
+(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size))   
+(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr cap_size ((reverse_endianness data  :  256 words$word)))) (\ success .  seqS
+   (if success then write_tag_bool 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict addr tag else returnS () ) (returnS success))))`;
+
+
+val _ = Define `
+ ((cap_addr_mask:(64)words$word)=  
+ ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((((pow2 (( 64 : int):sail_values$ii))) - cap_size))
+    :  64 words$word)))`;
+
+
+(*val MEMw_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((MEMw_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data=   
+ (let ledata = ((reverse_endianness data  :  'p8_times_n_ words$word)) in
+   if (((addr = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0]
+            :  64 words$word)))) then seqS     
+(write_regS UART_WDATA_ref ((subrange_vec_dec ledata (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)))     
+(write_regS UART_WRITTEN_ref (vec_of_bits [B1]  :  1 words$word))
+   else seqS (seqS (seqS     
+(assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
+                         ((add_vec addr
+                             ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+                                 ((size1 - (( 1 : int):sail_values$ii)))
+                                :  64 words$word))
+                            :  64 words$word)) cap_addr_mask
+                        :  64 words$word))))) "")     
+(MEMea instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1))     
+(MEMval instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ledata)) (write_tag_bool 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F)))`;
+
+
+(*val MEMw_conditional_wrapper : forall   'p8_times_n_ . Size 'p8_times_n_ => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'p8_times_n_ -> Cheri_sequential_types.M bool*)
+
+val _ = Define `
+ ((MEMw_conditional_wrapper:(64)words$word -> int -> 'p8_times_n_ words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((bool),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr size1 data=  (bindS (seqS (seqS   
+(assert_expS (((((and_vec addr cap_addr_mask  :  64 words$word)) = ((and_vec
+                       ((add_vec addr
+                           ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+                               ((size1 - (( 1 : int):sail_values$ii)))
+                              :  64 words$word))
+                          :  64 words$word)) cap_addr_mask
+                      :  64 words$word))))) "")   
+(MEMea_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1))   
+(MEMval_conditional instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict addr size1 ((reverse_endianness data  :  'p8_times_n_ words$word)))) (\ success .  seqS
+   (if success then write_tag_bool 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict ((and_vec addr cap_addr_mask  :  64 words$word)) F
+    else returnS () )   
+(returnS success))))`;
+
+
+(*val addrWrapper : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.MemAccessType -> Cheri_sequential_types.WordType -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((addrWrapper:(64)words$word -> cheri_sequential_types$MemAccessType -> cheri_sequential_types$WordType ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) addr accessType width=   
+ (let capno = ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)) in bindS   
+(readCapReg capno) (\ cap .  seqS (seqS
+   (if ((~ cap.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation capno
+    else if cap.CapStruct_sealed then raise_c2_exception CapEx_SealViolation capno
+    else returnS () )
+   (case accessType of
+     Instruction =>
+      if ((~ cap.CapStruct_permit_execute)) then
+        raise_c2_exception CapEx_PermitExecuteViolation capno
+      else returnS () 
+   | LoadData =>
+      if ((~ cap.CapStruct_permit_load)) then raise_c2_exception CapEx_PermitLoadViolation capno
+      else returnS () 
+   | StoreData =>
+      if ((~ cap.CapStruct_permit_store)) then raise_c2_exception CapEx_PermitStoreViolation capno
+      else returnS () 
+   ))   
+(let cursor = (getCapCursor cap) in
+   let vAddr = (hardware_mod ((cursor + ((lem$w2ui addr)))) ((pow2 (( 64 : int):sail_values$ii)))) in
+   let size1 = (wordWidthBytes width) in
+   let base = (getCapBase cap) in
+   let top = (getCapTop cap) in
+   if ((((vAddr + size1)) > top)) then
+     (raise_c2_exception CapEx_LengthViolation capno  : ( 64 words$word) cheri_sequential_types$M)
+   else if ((vAddr < base)) then (raise_c2_exception CapEx_LengthViolation capno  : ( 64 words$word) cheri_sequential_types$M)
+   else returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word))))))`;
+
+
+(*val TranslatePC : Machine_word.mword Machine_word.ty64 -> Cheri_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((TranslatePC:(64)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) vAddr=  (bindS (seqS   
+(incrementCP0Count () )
+   (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__0 :  257 words$word) . 
+   let pcc = (capRegToCapStruct w__0) in
+   let base = (getCapBase pcc) in
+   let top = (getCapTop pcc) in
+   let absPC = (base + ((lem$w2ui vAddr))) in
+   if (((((absPC % (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then
+     (SignalExceptionBadAddr AdEL
+        ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) absPC  :  64 words$word))
+       : ( 64 words$word) cheri_sequential_types$M)
+   else if ((~ pcc.CapStruct_tag)) then
+     (raise_c2_exception_noreg CapEx_TagViolation  : ( 64 words$word) cheri_sequential_types$M)
+   else if ((((absPC + (( 4 : int):sail_values$ii))) > top)) then
+     (raise_c2_exception_noreg CapEx_LengthViolation  : ( 64 words$word) cheri_sequential_types$M)
+   else
+     (TLBTranslate ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) absPC  :  64 words$word))
+        Instruction
+       : ( 64 words$word) cheri_sequential_types$M))))`;
+
+
+(*val checkCP2usable : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((checkCP2usable:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   if ((~ ((bit_to_bool ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 2 : int):sail_values$ii))))))) then seqS     
+(set_CauseReg_CE CP0Cause_ref (vec_of_bits [B1;B0]  :  2 words$word)) (SignalException CpU)
+   else returnS () )))`;
+
+
+val _ = Define `
+ ((init_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =   
+ (let defaultBits = ((capStructToCapReg default_cap  :  257 words$word)) in seqS (seqS (seqS   
+(write_regS PCC_ref defaultBits)   
+(write_regS nextPCC_ref defaultBits))   
+(write_regS delayedPCC_ref defaultBits))
+   (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () 
+     (\ i unit_var . 
+       let idx = ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) i  :  5 words$word)) in
+       writeCapReg idx default_cap))))`;
+
+
+val _ = Define `
+ ((cp2_next_pc:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS nextPCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS PCC_ref w__0)
+   (read_regS inBranchDelay_ref  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__1 :  1 words$word) . 
+   if ((bits_to_bool w__1)) then bindS
+     (read_regS delayedPCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 : cheri_sequential_types$CapReg) . 
+     write_regS nextPCC_ref w__2)
+   else write_regS inCCallDelay_ref (vec_of_bits [B0]  :  1 words$word)))))`;
+
+
+(*val capToString : Cheri_sequential_types.CapStruct -> Cheri_sequential_types.M string*)
+
+val _ = Define `
+ ((capToString:cheri_sequential_types$CapStruct ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((string),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cap=  (seqS   
+(skip () )   
+(returnS ((STRCAT " t:"
+               ((STRCAT (if cap.CapStruct_tag then "1" else "0")
+                   ((STRCAT " s:"
+                       ((STRCAT (if cap.CapStruct_sealed then "1" else "0")
+                           ((STRCAT " perms:"
+                               ((STRCAT
+                                   ((string_of_bits 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                       ((concat_vec (vec_of_bits [B0]  :  1 words$word)
+                                           ((getCapPerms cap  :  31 words$word))
+                                          :  32 words$word))))
+                                   ((STRCAT " type:"
+                                       ((STRCAT ((string_of_bits 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict cap.CapStruct_otype))
+                                           ((STRCAT " offset:"
+                                               ((STRCAT
+                                                   ((string_of_bits 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                       ((to_bits
+                                                           ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+                                                           ((getCapOffset cap))
+                                                          :  64 words$word))))
+                                                   ((STRCAT " base:"
+                                                       ((STRCAT
+                                                           ((string_of_bits 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                               ((to_bits
+                                                                   ((make_the_value (( 64 : int):sail_values$ii)
+                                                                      :  64 itself))
+                                                                   ((getCapBase cap))
+                                                                  :  64 words$word))))
+                                                           ((STRCAT " length:"
+                                                               ((string_of_bits 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict
+                                                                   ((to_bits
+                                                                       ((make_the_value (( 64 : int):sail_values$ii)
+                                                                          :  64 itself))
+                                                                       ((int_min ((getCapLength cap))
+                                                                           ((MAX0 (( 64 : int):sail_values$ii)))))
+                                                                      :  64 words$word)))))))))))))))))))))))))))))))))`;
+
+
+val _ = Define `
+ ((dump_cp2_state:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__0 :  257 words$word) .  bindS   
+(capToString ((capRegToCapStruct w__0))) (\ (w__1 : string) . 
+   let (_ : unit) = (prerr_endline ((STRCAT "DEBUG CAP PCC" w__1))) in
+   (foreachS (index_list (( 0 : int):sail_values$ii) (( 31 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () 
+     (\ i unit_var .  bindS       
+(readCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) i  :  5 words$word))) (\ (w__2 :
+         cheri_sequential_types$CapStruct) .  bindS       
+(capToString w__2) (\ (w__3 : string) . 
+       returnS (let _ =         
+(prerr_endline ((STRCAT "DEBUG CAP REG " ((STRCAT ((string_of_int 
+  instance_Show_Show_Num_integer_dict i)) w__3))))) in
+       () )))))))))`;
+
+
+(*val extendLoad : forall 'sz . Size 'sz => Machine_word.mword 'sz -> bool -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((extendLoad:'sz words$word -> bool ->(64)words$word) memResult sign=   
+ (if sign then (sign_extend1 (( 64 : int):sail_values$ii) memResult  :  64 words$word)
+   else (zero_extend1 (( 64 : int):sail_values$ii) memResult  :  64 words$word)))`;
+
+
+(*val TLBWriteEntry : Machine_word.mword Machine_word.ty6 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((TLBWriteEntry:(6)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) idx=  (bindS
+   (read_regS TLBPageMask_ref  : ( 16 words$word) cheri_sequential_types$M) (\ pagemask . 
+   let b__0 = pagemask in seqS
+   (if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word))))
+    then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))) then
+      returnS () 
+    else SignalException MCheck)   
+(let i = (lem$w2ui idx) in
+   let entry = (access_list_dec TLBEntries i) in bindS (seqS   
+(set_TLBEntry_pagemask entry pagemask)   
+(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) .  bindS (seqS   
+(set_TLBEntry_r entry ((get_TLBEntryHiReg_R w__0  :  2 words$word)))   
+(read_regS TLBEntryHi_ref)) (\ (w__1 : cheri_sequential_types$TLBEntryHiReg) .  bindS (seqS   
+(set_TLBEntry_vpn2 entry ((get_TLBEntryHiReg_VPN2 w__1  :  27 words$word)))   
+(read_regS TLBEntryHi_ref)) (\ (w__2 : cheri_sequential_types$TLBEntryHiReg) .  bindS (seqS   
+(set_TLBEntry_asid entry ((get_TLBEntryHiReg_ASID w__2  :  8 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) .  bindS   
+(read_regS TLBEntryLo1_ref) (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS (seqS   
+(set_TLBEntry_g entry
+     ((bool_to_bits
+         (((((bits_to_bool ((get_TLBEntryLoReg_G w__3  :  1 words$word)))) /\ ((bits_to_bool ((get_TLBEntryLoReg_G w__4  :  1 words$word)))))))
+        :  1 words$word)))   
+(set_TLBEntry_valid entry ((cast_unit_vec0 B1  :  1 words$word))))   
+(read_regS TLBEntryLo0_ref)) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_caps0 entry ((get_TLBEntryLoReg_CapS w__5  :  1 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_capl0 entry ((get_TLBEntryLoReg_CapL w__6  :  1 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__7 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_pfn0 entry ((get_TLBEntryLoReg_PFN w__7  :  24 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__8 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_c0 entry ((get_TLBEntryLoReg_C w__8  :  3 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__9 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_d0 entry ((get_TLBEntryLoReg_D w__9  :  1 words$word)))   
+(read_regS TLBEntryLo0_ref)) (\ (w__10 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_v0 entry ((get_TLBEntryLoReg_V w__10  :  1 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__11 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_caps1 entry ((get_TLBEntryLoReg_CapS w__11  :  1 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__12 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_capl1 entry ((get_TLBEntryLoReg_CapL w__12  :  1 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__13 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_pfn1 entry ((get_TLBEntryLoReg_PFN w__13  :  24 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__14 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_c1 entry ((get_TLBEntryLoReg_C w__14  :  3 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__15 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(set_TLBEntry_d1 entry ((get_TLBEntryLoReg_D w__15  :  1 words$word)))   
+(read_regS TLBEntryLo1_ref)) (\ (w__16 : cheri_sequential_types$TLBEntryLoReg) . 
+   set_TLBEntry_v1 entry ((get_TLBEntryLoReg_V w__16  :  1 words$word)))))))))))))))))))))))`;
+
+
+val _ = Define `
+ ((decode:(32)words$word ->(cheri_sequential_types$ast)option) v__0=   
+ (if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (DADDIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DADDU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (DADDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DADD (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ADD (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ADDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ADDU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ADDIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSUBU (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSUB (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SUB0 (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SUBU (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AND (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ANDI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B0;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (OR (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ORI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (NOR (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (XOR (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (XORI (rs,rt,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (LUI (rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSLL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSLL32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSLLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B1]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRA (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRA32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRAV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : 5 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRL32 (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DSRLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SLL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SLLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SRA (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SRAV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sa : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SRL (rt,rd,sa))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SRLV (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SLT (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SLTI (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SLTU (rs,rt,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SLTIU (rs,rt,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MOVN (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MOVZ (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MFHI rd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MFLO rd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B1]
+                     :  21 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MTHI rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1;B1]
+                     :  21 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MTLO rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MUL (rs,rt,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MULT (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MULTU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DMULT (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DMULTU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MADD (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MADDU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MSUB (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MSUBU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIV0 (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIVU (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B0]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DDIV (rs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DDIVU (rs,rt))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word)))) then
+     let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  26 words$word)) in
+     SOME (J offset)
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word)))) then
+     let (offset : 26 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  26 words$word)) in
+     SOME (JAL offset)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  10 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  10 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (JR rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1]  :  6 words$word)))))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (JALR (rs,rd))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,F,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,F,T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,T,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BEQ (rs,rt,imm,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',T,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LT',T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,T,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GE,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GT',F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,GT',F,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (BCMPZ (rs,imm,LE,F,T))
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;
+                             B1;B1;B1;B1;B1;B0;B0;B1;B1;B0;B0]
+                 :  32 words$word)))) then
+     SOME (SYSCALL_THREAD_START () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word))))))) then
+     SOME (SYSCALL () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word))))))) then
+     SOME (BREAK () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (WAIT () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,GE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,GEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,LT'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,LTU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,EQ'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (TRAPREG (rs,rt,NE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,EQ'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,NE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,GE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,GEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,LT'))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (TRAPIMM (rs,imm,LTU))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (B,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (B,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (H,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B0;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (H,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (W0,T,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (W0,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (D,F,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (W0,T,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Load (D,F,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (B,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B0;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (H,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (W0,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (D,F,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (W0,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (Store (D,T,base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (LWL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (LWR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SWL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SWR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (LDL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (LDR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B0]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SDL (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B0;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (SDR (base,rt,offset))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (CACHE (base,op,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1]  :  6 words$word)))) then
+     let (base : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (op : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : cheri_sequential_types$imm16) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (PREF (base,op,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  21 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word))))))) then
+     SOME (SYNC () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (MFC0 (rt,rd,sel,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (MFC0 (rt,rd,sel,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     SOME (HCF () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B1;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))))))
+   then
+     SOME (HCF () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (MTC0 (rt,rd,sel,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : 3 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (MTC0 (rt,rd,sel,T))
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]
+                 :  32 words$word)))) then
+     SOME (TLBWI () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]
+                 :  32 words$word)))) then
+     SOME (TLBWR () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]
+                 :  32 words$word)))) then
+     SOME (TLBR () )
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (TLBP () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RDHWR (rt,rd))
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B1;B1;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (ERET () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetPerm (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetType (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetBase (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetLen (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetTag (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetSealed (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  16 words$word)))))))
+   then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetCause rd)
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                 :  32 words$word)))) then
+     SOME (CReturn () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetOffset (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  21 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                     :  21 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetCause rt)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CAndPerm (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CToPtr (rd,cb,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CNE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CLT))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CLE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CLTU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CLEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CEXEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,ct,CNEXEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CIncOffset (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetOffset (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetBounds (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CClearTag (cd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CFromPtr (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1]  :  11 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))))))))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCheckPerm (cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  11 words$word))))))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCheckType (cs,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSeal (cd,cs,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B1;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CUnseal (cd,cs,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B1;B1]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CJALR (cd,cb,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word))))))) then
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),cb,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetCause rd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetCause rs)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetPCC cd)
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  16 words$word)))))))
+   then
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CJALR ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),cb,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCheckPerm (cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCheckType (cs,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CClearTag (cd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CMOVX (cd,cs,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CJALR (cd,cb,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetPerm (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetType (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetBase (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetLen (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetTag (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetSealed (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetOffset (rd,cb))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetPCCSetOffset (cd,rs))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CReadHwr (cd,sel))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CWriteHwr (cb,sel))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (sel : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CGetAddr (cb,sel))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSeal (cd,cs,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CUnseal (cd,cs,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CAndPerm (cd,cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B1;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetOffset (cd,cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetBounds (cd,cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSetBoundsExact (cd,cs,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CIncOffset (cd,cb,rt))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CBuildCap (cd,cb,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCopyType (cd,cb,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CCSeal (cd,cs,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CToPtr (rd,cb,ct))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CFromPtr (cd,cb,rs))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B0]  :  6 words$word))))))) then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSub (rt,cb,cs))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CMOVX (cd,cs,rs,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B0]  :  6 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CMOVX (cd,cs,rs,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B0;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CNE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CLT))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CLE))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CLTU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CLEU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CEXEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CPtrCmp (rd,cb,cs,CNEXEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (ct : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CTestSubset (rd,cb,ct))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B0;B1]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (CBX (cd,imm,T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B0;B1;B0]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (CBX (cd,imm,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B1]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (CBZ (cd,imm,F))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B0]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (CBZ (cd,imm,T))
+   else if (((v__0 = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B1;B1;B1;B1;B1;B1;B1;B1;B1;B1;B1]
+                 :  32 words$word)))) then
+     SOME (CReturn () )
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B1]  :  11 words$word)))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (selector : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) in
+     SOME (CCall (cs,cb,selector))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B0]  :  16 words$word)))) then
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ClearRegs (GPLo,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B0;B1]  :  16 words$word)))) then
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ClearRegs (GPHi,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B0]  :  16 words$word)))) then
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ClearRegs (CLo,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B1;B1;B1;B1;B0;B0;B0;B1;B1]  :  16 words$word)))) then
+     let (imm : 16 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) in
+     SOME (ClearRegs (CHi,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B1;B1]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) in
+     SOME (CIncOffsetImmediate (cd,cb,imm))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B1;B0;B0]  :  11 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) in
+     SOME (CSetBoundsImmediate (cd,cb,imm))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,F,B,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,T,B,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,F,H,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,T,H,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,F,W0,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,T,W0,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CLoad (rd,cb,rt,offset,F,D,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),F,B,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),T,B,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),F,H,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B0;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),T,H,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),F,W0,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),T,W0,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B0;B1;B1]  :  11 words$word))))))) then
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLoad (rd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                      :  8 words$word),F,D,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,B,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,H,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,W0,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B0;B1;B0]  :  6 words$word)))) /\ (((((subrange_vec_dec v__0 (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 8 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  8 words$word)) in
+     SOME (CStore (rs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,D,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                          :  8 words$word),B,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                          :  8 words$word),H,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B0]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                          :  8 words$word),W0,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B1;B1]  :  6 words$word))))))) then
+     let (rs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CStore (rs,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                          :  8 words$word),D,T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B1;B1;B1;B0]  :  6 words$word)))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) in
+     SOME (CSC (cs,cb,rt,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),offset,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B1;B1;B1]  :  6 words$word))))))) then
+     let (cs : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSC (cs,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),rd,(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                       :  11 words$word),T))
+   else if (((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B0]  :  6 words$word)))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     let (offset : 11 cheri_sequential_types$bits) = ((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) in
+     SOME (CLC (cd,cb,rt,offset,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B1;B0;B0;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 10 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]  :  11 words$word))))))) then
+     let (cd : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     let (cb : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CLC (cd,cb,(vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word),(vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                                                    :  11 words$word),T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  11 words$word)) = (vec_of_bits [B0;B1;B0;B0;B1;B0;B0;B0;B1;B0;B0]  :  11 words$word)))) /\ (((((subrange_vec_dec v__0 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B0]  :  16 words$word)))))))
+   then
+     let (rt : cheri_sequential_types$regno) = ((subrange_vec_dec v__0 (( 20 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (C2Dump rt)
+   else SOME (RI () )))`;
+
+
+(*val execute_XORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_XORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((xor_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_XOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_XOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((xor_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_WAIT : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_WAIT:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__120=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) .  write_regS nextPC_ref w__0)))`;
+
+
+(*val execute_TRAPREG : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TRAPREG:(5)words$word ->(5)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt cmp=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . 
+   let condition = (compare cmp rs_val rt_val) in
+   if condition then SignalException Tr
+   else returnS () ))))`;
+
+
+(*val execute_TRAPIMM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TRAPIMM:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . 
+   let (imm_val : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word)) in
+   let condition = (compare cmp rs_val imm_val) in
+   if condition then SignalException Tr
+   else returnS () )))`;
+
+
+(*val execute_TLBWR : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TLBWR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__124=  (bindS (seqS   
+(checkCP0Access () )
+   (read_regS TLBRandom_ref  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+
+
+(*val execute_TLBWI : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TLBWI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__123=  (bindS (seqS   
+(checkCP0Access () )
+   (read_regS TLBIndex_ref  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 :  6 words$word) .  TLBWriteEntry w__0)))`;
+
+
+(*val execute_TLBR : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TLBR:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__125=  (bindS (seqS   
+(checkCP0Access () )
+   (read_regS TLBIndex_ref  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__0 : cheri_sequential_types$TLBIndexT) . 
+   let i = (lem$w2ui w__0) in bindS   
+(read_regS ((access_list_dec TLBEntries i))) (\ entry .  seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS (seqS   
+(write_regS TLBPageMask_ref ((get_TLBEntry_pagemask entry  :  16 words$word)))   
+(set_TLBEntryHiReg_R TLBEntryHi_ref ((get_TLBEntry_r entry  :  2 words$word))))   
+(set_TLBEntryHiReg_VPN2 TLBEntryHi_ref ((get_TLBEntry_vpn2 entry  :  27 words$word))))   
+(set_TLBEntryHiReg_ASID TLBEntryHi_ref ((get_TLBEntry_asid entry  :  8 words$word))))   
+(set_TLBEntryLoReg_CapS TLBEntryLo0_ref ((get_TLBEntry_caps0 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_CapL TLBEntryLo0_ref ((get_TLBEntry_capl0 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_PFN TLBEntryLo0_ref ((get_TLBEntry_pfn0 entry  :  24 words$word))))   
+(set_TLBEntryLoReg_C TLBEntryLo0_ref ((get_TLBEntry_c0 entry  :  3 words$word))))   
+(set_TLBEntryLoReg_D TLBEntryLo0_ref ((get_TLBEntry_d0 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_V TLBEntryLo0_ref ((get_TLBEntry_v0 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_G TLBEntryLo0_ref ((get_TLBEntry_g entry  :  1 words$word))))   
+(set_TLBEntryLoReg_CapS TLBEntryLo1_ref ((get_TLBEntry_caps1 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_CapL TLBEntryLo1_ref ((get_TLBEntry_capl1 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_PFN TLBEntryLo1_ref ((get_TLBEntry_pfn1 entry  :  24 words$word))))   
+(set_TLBEntryLoReg_C TLBEntryLo1_ref ((get_TLBEntry_c1 entry  :  3 words$word))))   
+(set_TLBEntryLoReg_D TLBEntryLo1_ref ((get_TLBEntry_d1 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_V TLBEntryLo1_ref ((get_TLBEntry_v1 entry  :  1 words$word))))   
+(set_TLBEntryLoReg_G TLBEntryLo1_ref ((get_TLBEntry_g entry  :  1 words$word)))))))`;
+
+
+(*val execute_TLBP : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_TLBP:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__126=  (bindS (seqS   
+(checkCP0Access () )   
+(read_regS TLBEntryHi_ref)) (\ (w__0 : cheri_sequential_types$TLBEntryHiReg) .  bindS
+   (tlbSearch ((get_TLBEntryHiReg w__0  :  64 words$word))  : ( ( 6 words$word)option) cheri_sequential_types$M) (\ result . 
+   (case result of
+     SOME (idx) => seqS      
+(write_regS TLBProbe_ref (vec_of_bits [B0]  :  1 words$word)) (write_regS TLBIndex_ref idx)
+   | NONE => seqS      
+(write_regS TLBProbe_ref (vec_of_bits [B1]  :  1 words$word))      
+(write_regS TLBIndex_ref (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word))
+   )))))`;
+
+
+(*val execute_Store : Cheri_sequential_types.WordType -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_Store:cheri_sequential_types$WordType -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width conditional base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      StoreData width
+     : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . 
+   if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdES vAddr
+   else bindS
+     (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . 
+     if conditional then bindS
+       (read_regS CP0LLBit_ref  : ( 1 words$word) cheri_sequential_types$M) (\ (w__1 : 1 cheri_sequential_types$bits) .  bindS
+       (if ((bit_to_bool ((access_vec_dec w__1 (( 0 : int):sail_values$ii))))) then
+          (case width of
+            B =>
+             MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii)
+               ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+          | H =>
+             MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii)
+               ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+          | W0 =>
+             MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii)
+               ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+          | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rt_val
+          )
+        else returnS F) (\ (success : bool) . 
+       wGPR rt ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+     else
+       (case width of
+         B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+       | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+       | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rt_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+       | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rt_val
+       )))))))`;
+
+
+(*val execute_SYSCALL_THREAD_START : unit -> unit*)
+
+val _ = Define `
+ ((execute_SYSCALL_THREAD_START:unit -> unit) g__116=  () )`;
+
+
+(*val execute_SYSCALL : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SYSCALL:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__118=  (SignalException Sys))`;
+
+
+(*val execute_SYNC : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SYNC:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__121=  (MEM_sync () ))`;
+
+
+(*val execute_SWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      StoreData W0
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr . 
+   let wordAddr =     
+((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  62 words$word))
+        (vec_of_bits [B0;B0]  :  2 words$word)
+       :  64 words$word)) in bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__12 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) in
+   if (((b__12 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+   else if (((b__12 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+   else if (((b__12 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+     MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+   else MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))))))))`;
+
+
+(*val execute_SWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      StoreData W0
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__8 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) in
+   if (((b__8 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+   else if (((b__8 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  24 words$word))
+   else if (((b__8 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+     MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word))
+   else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  8 words$word))))))))`;
+
+
+(*val execute_SUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ opA .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     wGPR rd
+       ((sign_extend1 (( 64 : int):sail_values$ii)
+           ((sub_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+               ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word))))))`;
+
+
+(*val execute_SUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ opA .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let (temp33 : 33 cheri_sequential_types$bits) =       
+((sub_vec
+          ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  33 words$word))
+          ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec temp33 (( 32 : int):sail_values$ii)))))
+            ((bit_to_bool ((access_vec_dec temp33 (( 31 : int):sail_values$ii))))))) then
+       SignalException Ov
+     else
+       wGPR rd
+         ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec temp33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            :  64 words$word))))))`;
+
+
+(*val execute_SRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word)) in
+   if ((NotWordVal temp)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+     (shift_bits_right 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp . 
+   if ((NotWordVal temp)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+     (shift_bits_right 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word)) in
+   if ((NotWordVal temp)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+     (shift_bits_right_arith 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 :  32 words$word) . 
+     wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp . 
+   if ((NotWordVal temp)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let rt32 = ((subrange_vec_dec temp (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+     (shift_bits_right_arith 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 :  32 words$word) . 
+     wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SLTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLTU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val . 
+   wGPR rd
+     ((zero_extend1 (( 64 : int):sail_values$ii)
+         (if ((((lem$w2ui rs_val) < (lem$w2ui rt_val)))) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word))))))`;
+
+
+(*val execute_SLTIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLTIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . 
+   let (immext : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word)) in
+   wGPR rt
+     ((zero_extend1 (( 64 : int):sail_values$ii)
+         (if ((((lem$w2ui rs_val) < (lem$w2ui immext)))) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_SLTI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLTI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=   
+ (let imm_val = (integer_word$w2i imm) in bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs_val = (integer_word$w2i w__0) in
+   wGPR rt
+     ((zero_extend1 (( 64 : int):sail_values$ii)
+         (if ((rs_val < imm_val)) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_SLT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLT:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd
+     ((zero_extend1 (( 64 : int):sail_values$ii)
+         (if ((((integer_word$w2i w__0) < (integer_word$w2i w__1)))) then (vec_of_bits [B1]  :  1 words$word)
+          else (vec_of_bits [B0]  :  1 words$word))
+        :  64 words$word))))))`;
+
+
+(*val execute_SLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word)) in bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rt32 = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 :  32 words$word) . 
+   wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__2  :  64 words$word)))))))`;
+
+
+(*val execute_SLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rt32 = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict rt32 sa  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 :  32 words$word) . 
+   wGPR rd ((sign_extend1 (( 64 : int):sail_values$ii) w__1  :  64 words$word))))))`;
+
+
+(*val execute_SDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      StoreData D
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let wordAddr =     
+((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  61 words$word))
+        (vec_of_bits [B0;B0;B0]  :  3 words$word)
+       :  64 words$word)) in
+   let b__40 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+   if (((b__40 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+   else if (((b__40 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  40 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  48 words$word))
+   else if (((b__40 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper wordAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  56 words$word))
+   else MEMw_wrapper wordAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word))))))))`;
+
+
+(*val execute_SDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_SDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word))
+      StoreData D
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__32 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+   if (((b__32 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 8 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 7 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  56 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 6 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  48 words$word))
+   else if (((b__32 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 5 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  40 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 3 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii)  :  24 words$word))
+   else if (((b__32 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+     MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii)  :  16 words$word))
+   else MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii)  :  8 words$word))))))))`;
+
+
+(*val execute_RI : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_RI:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__129=  (SignalException ResI))`;
+
+
+(*val execute_RDHWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_RDHWR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd=  (bindS   
+(getAccessLevel () ) (\ accessLevel . 
+   let (haveAccessLevel : bool) = (accessLevel = Kernel) in bindS   
+(read_regS CP0Status_ref) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   let (haveCU0 : bool) = (B1 = ((access_vec_dec ((get_StatusReg_CU w__0  :  4 words$word)) (( 0 : int):sail_values$ii)))) in
+   let rdi = (lem$w2ui rd) in bindS
+   (read_regS CP0HWREna_ref  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . 
+   let (haveHWREna : bool) = (B1 = ((access_vec_dec w__1 rdi))) in seqS
+   (if ((~ (((haveAccessLevel \/ (((haveCU0 \/ haveHWREna)))))))) then SignalException ResI
+    else returnS () )   
+(let b__146 = rd in bindS
+   (if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then
+      returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))) then
+      returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))) then bindS
+      (read_regS CP0Count_ref  : ( 32 words$word) cheri_sequential_types$M) (\ (w__2 : 32 cheri_sequential_types$bits) . 
+      returnS ((zero_extend1 (( 64 : int):sail_values$ii) w__2  :  64 words$word)))
+    else if (((b__146 = (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))) then
+      returnS ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B1]  :  1 words$word)  :  64 words$word))
+    else if (((b__146 = (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))) then
+      (read_regS CP0UserLocal_ref  : ( 64 words$word) cheri_sequential_types$M)
+    else (SignalException ResI  : ( 64 words$word) cheri_sequential_types$M)) (\ (temp : 64 cheri_sequential_types$bits) . 
+   wGPR rt temp)))))))`;
+
+
+(*val execute_PREF : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> unit*)
+
+val _ = Define `
+ ((execute_PREF:(5)words$word ->(5)words$word ->(16)words$word -> unit) base op imm=  () )`;
+
+
+(*val execute_ORI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ORI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((or_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_OR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_OR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((or_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_NOR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_NOR:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((not_vec ((or_vec w__0 w__1  :  64 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_MULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (result : 64 cheri_sequential_types$bits) .  seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))`;
+
+
+(*val execute_MULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (result : 64 cheri_sequential_types$bits) .  seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))`;
+
+
+(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal . 
+   let (result : 64 cheri_sequential_types$bits) =     
+((sign_extend1 (( 64 : int):sail_values$ii)
+        ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (w__1 :  64 words$word) . 
+   wGPR rd w__1)))))`;
+
+
+(*val execute_MTLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MTLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) .  write_regS LO_ref w__0)))`;
+
+
+(*val execute_MTHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MTHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) .  write_regS HI_ref w__0)))`;
+
+
+(*val execute_MTC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MTC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double=  (bindS (seqS   
+(checkCP0Access () )
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M)) (\ reg_val .  
+  (case (rd, sel) of
+        (b__108, b__109) =>
+  if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\
+          (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+    write_regS TLBIndex_ref
+      ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word)) else
+    if ((((((b__108 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\
+            (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+      returnS ()  else
+      if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\
+              (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+        set_TLBEntryLoReg TLBEntryLo0_ref reg_val else
+        if ((((((b__108 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\
+                (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+          set_TLBEntryLoReg TLBEntryLo1_ref reg_val else
+          if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
+                  /\ (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+            set_ContextReg_PTEBase TLBContext_ref
+              ((subrange_vec_dec reg_val (( 63 : int): sail_values$ii)
+                  (( 23 : int): sail_values$ii) : 41 words$word)) else
+            if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
+                    /\ (((b__109 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then
+              write_regS CP0UserLocal_ref reg_val else
+              if ((((((b__108 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word))))
+                      /\
+                      (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                write_regS TLBPageMask_ref
+                  ((subrange_vec_dec reg_val (( 28 : int): sail_values$ii)
+                      (( 13 : int): sail_values$ii) : 16 words$word)) else
+                if ((((((b__108 =
+                           (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word))))
+                        /\
+                        (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                  seqS
+                    (write_regS TLBWired_ref
+                       ((mask (( 6 : int): sail_values$ii) reg_val : 6 words$word)))
+                    (write_regS TLBRandom_ref TLBIndexMax) else
+                  if ((((((b__108 =
+                             (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word))))
+                          /\
+                          (((b__109 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                    write_regS CP0HWREna_ref
+                      ((concat_vec
+                          ((subrange_vec_dec reg_val
+                              (( 31 : int): sail_values$ii)
+                              (( 29 : int): sail_values$ii) : 3 words$word))
+                          ((concat_vec
+                              (vec_of_bits
+                                 [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0] : 25 words$word)
+                              ((subrange_vec_dec reg_val
+                                  (( 3 : int): sail_values$ii)
+                                  (( 0 : int): sail_values$ii) : 4 words$word))
+                           : 29 words$word)) : 32 words$word)) else
+                    if ((((((b__108 =
+                               (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
+                            /\
+                            (((b__109 =
+                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                      returnS ()  else
+                      if ((((((b__108 =
+                                 (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))
+                              /\
+                              (((b__109 =
+                                   (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                        write_regS CP0Count_ref
+                          ((subrange_vec_dec reg_val
+                              (( 31 : int): sail_values$ii)
+                              (( 0 : int): sail_values$ii) : 32 words$word))
+                      else
+                        if ((((((b__108 =
+                                   (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))
+                                /\
+                                (((b__109 =
+                                     (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                          seqS
+                            (seqS
+                               (set_TLBEntryHiReg_R TLBEntryHi_ref
+                                  ((subrange_vec_dec reg_val
+                                      (( 63 : int): sail_values$ii)
+                                      (( 62 : int): sail_values$ii) : 2 words$word)))
+                               (set_TLBEntryHiReg_VPN2 TLBEntryHi_ref
+                                  ((subrange_vec_dec reg_val
+                                      (( 39 : int): sail_values$ii)
+                                      (( 13 : int): sail_values$ii) : 27 words$word))))
+                            (set_TLBEntryHiReg_ASID TLBEntryHi_ref
+                               ((subrange_vec_dec reg_val
+                                   (( 7 : int): sail_values$ii)
+                                   (( 0 : int): sail_values$ii) : 8 words$word)))
+                        else
+                          if ((((((b__108 =
+                                     (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))
+                                  /\
+                                  (((b__109 =
+                                       (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                            bindS
+                              (seqS
+                                 (write_regS CP0Compare_ref
+                                    ((subrange_vec_dec reg_val
+                                        (( 31 : int): sail_values$ii)
+                                        (( 0 : int): sail_values$ii) : 32 words$word)))
+                                 (read_regS CP0Cause_ref))
+                              (\ (w__0 : cheri_sequential_types$CauseReg) . 
+                               set_CauseReg_IP CP0Cause_ref
+                                 ((and_vec
+                                     ((get_CauseReg_IP w__0 : 8 words$word))
+                                     (vec_of_bits [B0;B1;B1;B1;B1;B1;B1;B1] : 8 words$word)
+                                  : 8 words$word))) else
+                            if ((((((b__108 =
+                                       (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))
+                                    /\
+                                    (((b__109 =
+                                         (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                              seqS
+                                (seqS
+                                   (seqS
+                                      (seqS
+                                         (seqS
+                                            (seqS
+                                               (seqS
+                                                  (seqS
+                                                     (seqS
+                                                        (set_StatusReg_CU
+                                                           CP0Status_ref
+                                                           ((subrange_vec_dec
+                                                               reg_val
+                                                               (( 31 : int): sail_values$ii)
+                                                               (( 28 : int): sail_values$ii) : 4 words$word)))
+                                                        (set_StatusReg_BEV
+                                                           CP0Status_ref
+                                                           ((cast_unit_vec0
+                                                               ((access_vec_dec
+                                                                   reg_val
+                                                                   ((
+                                                                     22 : int): sail_values$ii))) : 1 words$word))))
+                                                     (set_StatusReg_IM
+                                                        CP0Status_ref
+                                                        ((subrange_vec_dec
+                                                            reg_val
+                                                            (( 15 : int): sail_values$ii)
+                                                            (( 8 : int): sail_values$ii) : 8 words$word))))
+                                                  (set_StatusReg_KX
+                                                     CP0Status_ref
+                                                     ((cast_unit_vec0
+                                                         ((access_vec_dec
+                                                             reg_val
+                                                             (( 7 : int): sail_values$ii))) : 1 words$word))))
+                                               (set_StatusReg_SX
+                                                  CP0Status_ref
+                                                  ((cast_unit_vec0
+                                                      ((access_vec_dec
+                                                          reg_val
+                                                          (( 6 : int): sail_values$ii))) : 1 words$word))))
+                                            (set_StatusReg_UX CP0Status_ref
+                                               ((cast_unit_vec0
+                                                   ((access_vec_dec reg_val
+                                                       (( 5 : int): sail_values$ii))) : 1 words$word))))
+                                         (set_StatusReg_KSU CP0Status_ref
+                                            ((subrange_vec_dec reg_val
+                                                (( 4 : int): sail_values$ii)
+                                                (( 3 : int): sail_values$ii) : 2 words$word))))
+                                      (set_StatusReg_ERL CP0Status_ref
+                                         ((cast_unit_vec0
+                                             ((access_vec_dec reg_val
+                                                 (( 2 : int): sail_values$ii))) : 1 words$word))))
+                                   (set_StatusReg_EXL CP0Status_ref
+                                      ((cast_unit_vec0
+                                          ((access_vec_dec reg_val
+                                              (( 1 : int): sail_values$ii))) : 1 words$word))))
+                                (set_StatusReg_IE CP0Status_ref
+                                   ((cast_unit_vec0
+                                       ((access_vec_dec reg_val
+                                           (( 0 : int): sail_values$ii))) : 1 words$word)))
+                            else
+                              if ((((((b__108 =
+                                         (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word))))
+                                      /\
+                                      (((b__109 =
+                                           (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                bindS
+                                  (seqS
+                                     (set_CauseReg_IV CP0Cause_ref
+                                        ((cast_unit_vec0
+                                            ((access_vec_dec reg_val
+                                                (( 23 : int): sail_values$ii))) : 1 words$word)))
+                                     (read_regS CP0Cause_ref))
+                                  (\ (w__1 : cheri_sequential_types$CauseReg) . 
+                                   let ip = ((get_CauseReg_IP w__1 : 8 words$word)) in
+                                   set_CauseReg_IP CP0Cause_ref
+                                     ((concat_vec
+                                         ((subrange_vec_dec ip
+                                             (( 7 : int): sail_values$ii)
+                                             (( 2 : int): sail_values$ii) : 6 words$word))
+                                         ((subrange_vec_dec reg_val
+                                             (( 9 : int): sail_values$ii)
+                                             (( 8 : int): sail_values$ii) : 2 words$word))
+                                      : 8 words$word))) else
+                                if ((((((b__108 =
+                                           (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))
+                                        /\
+                                        (((b__109 =
+                                             (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                  write_regS CP0EPC_ref reg_val else
+                                  if ((((((b__108 =
+                                             (vec_of_bits [B1;B0;B0;B0;B0] : 5 words$word))))
+                                          /\
+                                          (((b__109 =
+                                               (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                    returnS ()  else
+                                    if ((((((b__108 =
+                                               (vec_of_bits [B1;B0;B1;B0;B0] : 5 words$word))))
+                                            /\
+                                            (((b__109 =
+                                                 (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                      set_XContextReg_XPTEBase
+                                        TLBXContext_ref
+                                        ((subrange_vec_dec reg_val
+                                            (( 63 : int): sail_values$ii)
+                                            (( 33 : int): sail_values$ii) : 31 words$word))
+                                    else write_regS CP0ErrorEPC_ref reg_val
+  ))))`;
+
+
+(*val execute_MSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MSUBU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS HI_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS LO_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . 
+   let result =     
+((sub_vec
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           :  64 words$word)) mul_result
+       :  64 words$word)) in seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))))`;
+
+
+(*val execute_MSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MSUB:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS HI_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS LO_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . 
+   let result =     
+((sub_vec
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           :  64 words$word)) mul_result
+       :  64 words$word)) in seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))))`;
+
+
+(*val execute_MOVZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MOVZ:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   if (((w__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0]
+            :  64 words$word)))) then bindS
+     (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else returnS () )))`;
+
+
+(*val execute_MOVN : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MOVN:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   if (((w__0 <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                        B0]
+            :  64 words$word)))) then bindS
+     (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)
+   else returnS () )))`;
+
+
+(*val execute_MFLO : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MFLO:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd=  (bindS
+   (read_regS LO_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+
+
+(*val execute_MFHI : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MFHI:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd=  (bindS
+   (read_regS HI_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)))`;
+
+
+(*val execute_MFC0 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty3 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MFC0:(5)words$word ->(5)words$word ->(3)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sel double=  (bindS (seqS   
+(checkCP0Access () ) (case (rd, sel) of
+       (b__48, b__49) =>
+ if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B0] : 5 words$word)))) /\
+         (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+   bindS (read_regS TLBIndex_ref : ( 6 words$word) cheri_sequential_types$M)
+     (\ (w__0 : cheri_sequential_types$TLBIndexT) . 
+      let (idx : 31 cheri_sequential_types$bits) = ((zero_extend1
+                                                       (( 31 : int): sail_values$ii)
+                                                       w__0 : 31 words$word)) in
+      bindS
+        (read_regS TLBProbe_ref : ( 1 words$word) cheri_sequential_types$M)
+        (\ (w__1 : 1 cheri_sequential_types$bits) . 
+         returnS
+           ((concat_vec
+               (vec_of_bits
+                  [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                  B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 32 words$word)
+               ((concat_vec w__1 idx : 32 words$word)) : 64 words$word))))
+ else
+   if ((((((b__48 = (vec_of_bits [B0;B0;B0;B0;B1] : 5 words$word)))) /\
+           (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+     bindS
+       (read_regS TLBRandom_ref : ( 6 words$word) cheri_sequential_types$M)
+       (\ (w__2 : cheri_sequential_types$TLBIndexT) . 
+        returnS
+          ((zero_extend1 (( 64 : int): sail_values$ii) w__2 : 64 words$word)))
+   else
+     if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B0] : 5 words$word)))) /\
+             (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+       bindS (read_regS TLBEntryLo0_ref)
+         (\ (w__3 : cheri_sequential_types$TLBEntryLoReg) . 
+          returnS ((get_TLBEntryLoReg w__3 : 64 words$word))) else
+       if ((((((b__48 = (vec_of_bits [B0;B0;B0;B1;B1] : 5 words$word)))) /\
+               (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+         bindS (read_regS TLBEntryLo1_ref)
+           (\ (w__4 : cheri_sequential_types$TLBEntryLoReg) . 
+            returnS ((get_TLBEntryLoReg w__4 : 64 words$word))) else
+         if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word)))) /\
+                 (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+           bindS (read_regS TLBContext_ref)
+             (\ (w__5 : cheri_sequential_types$ContextReg) . 
+              returnS ((get_ContextReg w__5 : 64 words$word))) else
+           if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B0] : 5 words$word))))
+                   /\ (((b__49 = (vec_of_bits [B0;B1;B0] : 3 words$word))))))) then
+             (read_regS CP0UserLocal_ref : ( 64 words$word) cheri_sequential_types$M)
+           else
+             if ((((((b__48 = (vec_of_bits [B0;B0;B1;B0;B1] : 5 words$word))))
+                     /\ (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+               bindS
+                 (read_regS TLBPageMask_ref : ( 16 words$word) cheri_sequential_types$M)
+                 (\ (w__7 : 16 cheri_sequential_types$bits) . 
+                  returnS
+                    ((zero_extend1 (( 64 : int): sail_values$ii)
+                        ((concat_vec w__7
+                            (vec_of_bits
+                               [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0] : 12 words$word)
+                         : 28 words$word)) : 64 words$word))) else
+               if ((((((b__48 = (vec_of_bits [B0;B0;B1;B1;B0] : 5 words$word))))
+                       /\
+                       (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                 bindS
+                   (read_regS TLBWired_ref : ( 6 words$word) cheri_sequential_types$M)
+                   (\ (w__8 : cheri_sequential_types$TLBIndexT) . 
+                    returnS
+                      ((zero_extend1 (( 64 : int): sail_values$ii) w__8 : 64 words$word)))
+               else
+                 if ((((((b__48 =
+                            (vec_of_bits [B0;B0;B1;B1;B1] : 5 words$word))))
+                         /\
+                         (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                   bindS
+                     (read_regS CP0HWREna_ref : ( 32 words$word) cheri_sequential_types$M)
+                     (\ (w__9 : 32 cheri_sequential_types$bits) . 
+                      returnS
+                        ((zero_extend1 (( 64 : int): sail_values$ii) w__9 : 64 words$word)))
+                 else
+                   if ((((((b__48 =
+                              (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
+                           /\
+                           (((b__49 = (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                     (read_regS CP0BadVAddr_ref : ( 64 words$word) cheri_sequential_types$M)
+                   else
+                     if ((((((b__48 =
+                                (vec_of_bits [B0;B1;B0;B0;B0] : 5 words$word))))
+                             /\
+                             (((b__49 =
+                                  (vec_of_bits [B0;B0;B1] : 3 words$word))))))) then
+                       returnS
+                         ((zero_extend1 (( 64 : int): sail_values$ii)
+                             (vec_of_bits [B0] : 1 words$word) : 64 words$word))
+                     else
+                       if ((((((b__48 =
+                                  (vec_of_bits [B0;B1;B0;B0;B1] : 5 words$word))))
+                               /\
+                               (((b__49 =
+                                    (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                         bindS
+                           (read_regS CP0Count_ref : ( 32 words$word) cheri_sequential_types$M)
+                           (\ (w__11 : 32 cheri_sequential_types$bits) . 
+                            returnS
+                              ((zero_extend1 (( 64 : int): sail_values$ii)
+                                  w__11 : 64 words$word))) else
+                         if ((((((b__48 =
+                                    (vec_of_bits [B0;B1;B0;B1;B0] : 5 words$word))))
+                                 /\
+                                 (((b__49 =
+                                      (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                           bindS (read_regS TLBEntryHi_ref)
+                             (\ (w__12 : cheri_sequential_types$TLBEntryHiReg) . 
+                              returnS
+                                ((get_TLBEntryHiReg w__12 : 64 words$word)))
+                         else
+                           if ((((((b__48 =
+                                      (vec_of_bits [B0;B1;B0;B1;B1] : 5 words$word))))
+                                   /\
+                                   (((b__49 =
+                                        (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                             bindS
+                               (read_regS CP0Compare_ref : ( 32 words$word) cheri_sequential_types$M)
+                               (\ (w__13 : 32 cheri_sequential_types$bits) . 
+                                returnS
+                                  ((zero_extend1
+                                      (( 64 : int): sail_values$ii) w__13 : 64 words$word)))
+                           else
+                             if ((((((b__48 =
+                                        (vec_of_bits [B0;B1;B1;B0;B0] : 5 words$word))))
+                                     /\
+                                     (((b__49 =
+                                          (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                               bindS (read_regS CP0Status_ref)
+                                 (\ (w__14 : cheri_sequential_types$StatusReg) . 
+                                  returnS
+                                    ((zero_extend1
+                                        (( 64 : int): sail_values$ii)
+                                        ((get_StatusReg w__14 : 32 words$word)) : 64 words$word)))
+                             else
+                               if ((((((b__48 =
+                                          (vec_of_bits [B0;B1;B1;B0;B1] : 5 words$word))))
+                                       /\
+                                       (((b__49 =
+                                            (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                 bindS (read_regS CP0Cause_ref)
+                                   (\ (w__15 : cheri_sequential_types$CauseReg) . 
+                                    returnS
+                                      ((zero_extend1
+                                          (( 64 : int): sail_values$ii)
+                                          ((get_CauseReg w__15 : 32 words$word)) : 64 words$word)))
+                               else
+                                 if ((((((b__48 =
+                                            (vec_of_bits [B0;B1;B1;B1;B0] : 5 words$word))))
+                                         /\
+                                         (((b__49 =
+                                              (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                   (read_regS CP0EPC_ref : ( 64 words$word) cheri_sequential_types$M)
+                                 else
+                                   if ((((((b__48 =
+                                              (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word))))
+                                           /\
+                                           (((b__49 =
+                                                (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                     returnS
+                                       ((zero_extend1
+                                           (( 64 : int): sail_values$ii)
+                                           (vec_of_bits
+                                              [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                              B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                           : 32 words$word) : 64 words$word))
+                                   else
+                                     if ((((((b__48 =
+                                                (vec_of_bits [B0;B1;B1;B1;B1] : 5 words$word))))
+                                             /\
+                                             (((b__49 =
+                                                  (vec_of_bits [B1;B1;B0] : 3 words$word))))))) then
+                                       returnS
+                                         ((zero_extend1
+                                             (( 64 : int): sail_values$ii)
+                                             (vec_of_bits [B0] : 1 words$word) : 64 words$word))
+                                     else
+                                       if ((((((b__48 =
+                                                  (vec_of_bits
+                                                     [B0;B1;B1;B1;B1] : 5 words$word))))
+                                               /\
+                                               (((b__49 =
+                                                    (vec_of_bits [B1;B1;B1] : 3 words$word))))))) then
+                                         returnS
+                                           ((zero_extend1
+                                               (( 64 : int): sail_values$ii)
+                                               (vec_of_bits [B0] : 1 words$word) : 64 words$word))
+                                       else
+                                         if ((((((b__48 =
+                                                    (vec_of_bits
+                                                       [B1;B0;B0;B0;B0] : 5 words$word))))
+                                                 /\
+                                                 (((b__49 =
+                                                      (vec_of_bits [B0;B0;B0] : 3 words$word))))))) then
+                                           returnS
+                                             ((zero_extend1
+                                                 (( 64 : int): sail_values$ii)
+                                                 ((concat_vec
+                                                     (vec_of_bits [B1] : 1 words$word)
+                                                     ((concat_vec
+                                                         (vec_of_bits
+                                                            [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]
+                                                         : 15 words$word)
+                                                         ((concat_vec
+                                                             (vec_of_bits
+                                                                [B1] : 1 words$word)
+                                                             ((concat_vec
+                                                                 (vec_of_bits
+                                                                    [B1;B0] : 2 words$word)
+                                                                 ((concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B1] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    : 7 words$word))
+                                                                    : 10 words$word))
+                                                                  : 13 words$word))
+                                                              : 15 words$word))
+                                                          : 16 words$word))
+                                                      : 31 words$word))
+                                                  : 32 words$word))
+                                              : 64 words$word)) else
+                                           if ((((((b__48 =
+                                                      (vec_of_bits
+                                                         [B1;B0;B0;B0;B0] : 5 words$word))))
+                                                   /\
+                                                   (((b__49 =
+                                                        (vec_of_bits
+                                                           [B0;B0;B1] : 3 words$word))))))) then
+                                             returnS
+                                               ((zero_extend1
+                                                   (( 64 : int): sail_values$ii)
+                                                   ((concat_vec
+                                                       (vec_of_bits [B1] : 1 words$word)
+                                                       ((concat_vec
+                                                           TLBIndexMax
+                                                           ((concat_vec
+                                                               (vec_of_bits
+                                                                  [B0;B0;B0] : 3 words$word)
+                                                               ((concat_vec
+                                                                   (vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                   ((
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    (
+                                                                    bool_to_bits
+                                                                    have_cp2 : 1 words$word))
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0] : 1 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0] : 1 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0] : 1 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0]
+                                                                    : 1 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0]
+                                                                    : 1 words$word)
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0]
+                                                                    : 1 words$word)
+                                                                    : 2 words$word))
+                                                                    : 3 words$word))
+                                                                    : 4 words$word))
+                                                                    : 5 words$word))
+                                                                    : 6 words$word))
+                                                                    : 7 words$word))
+                                                                    : 10 words$word))
+                                                                    : 13 words$word))
+                                                                    : 16 words$word))
+                                                                    : 19 words$word))
+                                                                : 22 words$word))
+                                                            : 25 words$word))
+                                                        : 31 words$word))
+                                                    : 32 words$word))
+                                                : 64 words$word)) else
+                                             if ((((((b__48 =
+                                                        (vec_of_bits
+                                                           [B1;B0;B0;B0;B0] : 5 words$word))))
+                                                     /\
+                                                     (((b__49 =
+                                                          (vec_of_bits
+                                                             [B0;B1;B0] : 3 words$word))))))) then
+                                               returnS
+                                                 ((zero_extend1
+                                                     (( 64 : int): sail_values$ii)
+                                                     ((concat_vec
+                                                         (vec_of_bits [B1] : 1 words$word)
+                                                         ((concat_vec
+                                                             (vec_of_bits
+                                                                [B0;B0;B0] : 3 words$word)
+                                                             ((concat_vec
+                                                                 (vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                 ((concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    (
+                                                                    concat_vec
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0;B0] : 4 words$word)
+                                                                    : 8 words$word))
+                                                                    : 12 words$word))
+                                                                    : 16 words$word))
+                                                                    : 20 words$word))
+                                                                  : 24 words$word))
+                                                              : 28 words$word))
+                                                          : 31 words$word))
+                                                      : 32 words$word))
+                                                  : 64 words$word)) else
+                                               if ((((((b__48 =
+                                                          (vec_of_bits
+                                                             [B1;B0;B0;B0;B0] : 5 words$word))))
+                                                       /\
+                                                       (((b__49 =
+                                                            (vec_of_bits
+                                                               [B0;B1;B1] : 3 words$word))))))) then
+                                                 returnS
+                                                   (vec_of_bits
+                                                      [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                      B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                      B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                      B0] : 64 words$word)
+                                               else
+                                                 if ((((((b__48 =
+                                                            (vec_of_bits
+                                                               [B1;B0;B0;B0;B0] : 5 words$word))))
+                                                         /\
+                                                         (((b__49 =
+                                                              (vec_of_bits
+                                                                 [B1;B0;B1] : 3 words$word))))))) then
+                                                   returnS
+                                                     (vec_of_bits
+                                                        [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                        B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                                        B0] : 64 words$word)
+                                                 else
+                                                   if ((((((b__48 =
+                                                              (vec_of_bits
+                                                                 [B1;B0;B0;B0;B1] : 5 words$word))))
+                                                           /\
+                                                           (((b__49 =
+                                                                (vec_of_bits
+                                                                   [B0;B0;B0] : 3 words$word))))))) then
+                                                     (read_regS CP0LLAddr_ref : ( 64 words$word) cheri_sequential_types$M)
+                                                   else
+                                                     if ((((((b__48 =
+                                                                (vec_of_bits
+                                                                   [B1;B0;B0;B1;B0] : 5 words$word))))
+                                                             /\
+                                                             (((b__49 =
+                                                                  (vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word))))))) then
+                                                       returnS
+                                                         ((zero_extend1
+                                                             (( 64 : int): sail_values$ii)
+                                                             (vec_of_bits
+                                                                [B0] : 1 words$word) : 64 words$word))
+                                                     else
+                                                       if ((((((b__48 =
+                                                                  (vec_of_bits
+                                                                    [B1;B0;B0;B1;B1] : 5 words$word))))
+                                                               /\
+                                                               (((b__49 =
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word))))))) then
+                                                         returnS
+                                                           ((zero_extend1
+                                                               (( 64 : int): sail_values$ii)
+                                                               (vec_of_bits
+                                                                  [B0] : 1 words$word) : 64 words$word))
+                                                       else
+                                                         if ((((((b__48 =
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B1;B0;B1;B0;B0] : 5 words$word))))
+                                                                 /\
+                                                                 (((b__49 =
+                                                                    (
+                                                                    vec_of_bits
+                                                                    [B0;B0;B0] : 3 words$word))))))) then
+                                                           bindS
+                                                             (read_regS
+                                                                TLBXContext_ref)
+                                                             (\ (w__18 : cheri_sequential_types$XContextReg) . 
+                                                              returnS
+                                                                ((get_XContextReg
+                                                                    w__18 : 64 words$word)))
+                                                         else
+                                                           (read_regS
+                                                              CP0ErrorEPC_ref : ( 64 words$word) cheri_sequential_types$M)
+ )) (\ (result : 64 cheri_sequential_types$bits) . 
+   wGPR rt
+     (if double then result
+      else
+        (sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_MADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MADDU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mult_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS HI_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS LO_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . 
+   let result =     
+((add_vec mul_result
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))))`;
+
+
+(*val execute_MADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_MADD:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ ((NotWordVal rtVal))))) then
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)
+    else
+      returnS ((mults_vec ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                  ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 :  64 words$word))) (\ (mul_result : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS HI_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) .  bindS
+   (read_regS LO_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) . 
+   let result =     
+((add_vec mul_result
+        ((concat_vec ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            ((subrange_vec_dec w__2 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           :  64 words$word))
+       :  64 words$word)) in seqS   
+(write_regS
+     HI_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))   
+(write_regS
+     LO_ref
+     ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))))))`;
+
+
+(*val execute_Load : Cheri_sequential_types.WordType -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_Load:cheri_sequential_types$WordType -> bool -> bool ->(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) width sign linked base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
+      width
+     : ( 64 words$word) cheri_sequential_types$M) (\ (vAddr : 64 cheri_sequential_types$bits) . 
+   if ((~ ((isAddressAligned vAddr width)))) then SignalExceptionBadAddr AdEL vAddr
+   else bindS
+     (TLBTranslate vAddr LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+     (if linked then seqS (seqS        
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))        
+(write_regS CP0LLAddr_ref pAddr))
+        (case width of
+          B => bindS
+           (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__1 :  8 words$word) . 
+           returnS ((extendLoad w__1 sign  :  64 words$word)))
+        | H => bindS
+           (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__2 :  16 words$word) . 
+           returnS ((extendLoad w__2 sign  :  64 words$word)))
+        | W0 => bindS
+           (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 :  32 words$word) . 
+           returnS ((extendLoad w__3 sign  :  64 words$word)))
+        | D => bindS
+           (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__4 :  64 words$word) . 
+           returnS ((extendLoad w__4 sign  :  64 words$word)))
+        )
+      else
+        (case width of
+          B => bindS
+           (MEMr_wrapper pAddr (( 1 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__6 :  8 words$word) . 
+           returnS ((extendLoad w__6 sign  :  64 words$word)))
+        | H => bindS
+           (MEMr_wrapper pAddr (( 2 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__7 :  16 words$word) . 
+           returnS ((extendLoad w__7 sign  :  64 words$word)))
+        | W0 => bindS
+           (MEMr_wrapper pAddr (( 4 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__8 :  32 words$word) . 
+           returnS ((extendLoad w__8 sign  :  64 words$word)))
+        | D => bindS
+           (MEMr_wrapper pAddr (( 8 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__9 :  64 words$word) . 
+           returnS ((extendLoad w__9 sign  :  64 words$word)))
+        )) (\ (memResult : 64 cheri_sequential_types$bits) . 
+     wGPR rt memResult))))))`;
+
+
+(*val execute_LWR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_LWR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
+      W0
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (MEMr_wrapper
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  62 words$word))
+          (vec_of_bits [B0;B0]  :  2 words$word)
+         :  64 words$word)) (( 4 : int):sail_values$ii)
+     : ( 32 words$word) cheri_sequential_types$M) (\ mem_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__4 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) in
+   let (result : 32 cheri_sequential_types$bits) =     
+(if (((b__4 = (vec_of_bits [B0;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  24 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  8 words$word))
+         :  32 words$word)
+     else if (((b__4 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  16 words$word))
+         :  32 words$word)
+     else if (((b__4 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  8 words$word))
+          ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  24 words$word))
+         :  32 words$word)
+     else mem_val) in
+   wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result  :  64 words$word)))))))))`;
+
+
+(*val execute_LWL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_LWL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
+      W0
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (MEMr_wrapper
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  62 words$word))
+          (vec_of_bits [B0;B0]  :  2 words$word)
+         :  64 words$word)) (( 4 : int):sail_values$ii)
+     : ( 32 words$word) cheri_sequential_types$M) (\ mem_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__0 = ((subrange_vec_dec vAddr (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) in
+   let (result : 32 cheri_sequential_types$bits) =     
+(if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then mem_val
+     else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+          ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+         :  32 words$word)
+     else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then
+       (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+          ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+         :  32 words$word)
+     else
+       (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+          ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+         :  32 words$word)) in
+   wGPR rt ((sign_extend1 (( 64 : int):sail_values$ii) result  :  64 words$word)))))))))`;
+
+
+(*val execute_LUI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_LUI:(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt imm=   
+ (wGPR rt
+     ((sign_extend1 (( 64 : int):sail_values$ii)
+         ((concat_vec imm
+             (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)
+            :  32 words$word))
+        :  64 words$word))))`;
+
+
+(*val execute_LDR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_LDR:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
+      D
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (MEMr_wrapper
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  61 words$word))
+          (vec_of_bits [B0;B0;B0]  :  3 words$word)
+         :  64 words$word)) (( 8 : int):sail_values$ii)
+     : ( 64 words$word) cheri_sequential_types$M) (\ mem_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__24 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+   wGPR rt
+     (if (((b__24 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  56 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii)  :  8 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  48 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii)  :  16 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  40 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii)  :  24 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  32 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 40 : int):sail_values$ii)  :  24 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  40 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 48 : int):sail_values$ii)  :  16 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  48 words$word))
+          :  64 words$word)
+      else if (((b__24 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec reg_val (( 63 : int):sail_values$ii) (( 56 : int):sail_values$ii)  :  8 words$word))
+           ((subrange_vec_dec mem_val (( 63 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  56 words$word))
+          :  64 words$word)
+      else mem_val))))))))`;
+
+
+(*val execute_LDL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_LDL:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base rt offset=  (bindS
+   (rGPR base  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (addrWrapper ((add_vec ((sign_extend1 (( 64 : int):sail_values$ii) offset  :  64 words$word)) w__0  :  64 words$word)) LoadData
+      D
+     : ( 64 words$word) cheri_sequential_types$M) (\ vAddr .  bindS
+   (TLBTranslate vAddr StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+   (MEMr_wrapper
+      ((concat_vec ((subrange_vec_dec pAddr (( 63 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  61 words$word))
+          (vec_of_bits [B0;B0;B0]  :  3 words$word)
+         :  64 words$word)) (( 8 : int):sail_values$ii)
+     : ( 64 words$word) cheri_sequential_types$M) (\ mem_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ reg_val . 
+   let b__16 = ((subrange_vec_dec vAddr (( 2 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  3 words$word)) in
+   wGPR rt
+     (if (((b__16 = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) then mem_val
+      else if (((b__16 = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  56 words$word))
+           ((subrange_vec_dec reg_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  48 words$word))
+           ((subrange_vec_dec reg_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  40 words$word))
+           ((subrange_vec_dec reg_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+           ((subrange_vec_dec reg_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 23 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  24 words$word))
+           ((subrange_vec_dec reg_val (( 39 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  40 words$word))
+          :  64 words$word)
+      else if (((b__16 = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) then
+        (concat_vec ((subrange_vec_dec mem_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+           ((subrange_vec_dec reg_val (( 47 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  48 words$word))
+          :  64 words$word)
+      else
+        (concat_vec ((subrange_vec_dec mem_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+           ((subrange_vec_dec reg_val (( 55 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  56 words$word))
+          :  64 words$word)))))))))`;
+
+
+(*val execute_JR : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_JR:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs=  (bindS (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  execute_branch w__0)))`;
+
+
+(*val execute_JALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_JALR:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS (seqS   
+(execute_branch w__0)
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((add_vec_int w__1 (( 8 : int):sail_values$ii)  :  64 words$word))))))`;
+
+
+(*val execute_JAL : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_JAL:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(execute_branch
+     ((concat_vec
+         ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii)  :  64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii)  :  36 words$word))
+         ((concat_vec offset (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
+        :  64 words$word)))
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 :  64 words$word) . 
+   wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) ((add_vec_int w__1 (( 8 : int):sail_values$ii)  :  64 words$word))))))`;
+
+
+(*val execute_J : Machine_word.mword Machine_word.ty26 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_J:(26)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) offset=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . 
+   execute_branch
+     ((concat_vec
+         ((subrange_vec_dec ((add_vec_int w__0 (( 4 : int):sail_values$ii)  :  64 words$word)) (( 63 : int):sail_values$ii) (( 28 : int):sail_values$ii)  :  36 words$word))
+         ((concat_vec offset (vec_of_bits [B0;B0]  :  2 words$word)  :  28 words$word))
+        :  64 words$word)))))`;
+
+
+(*val execute_ImplementationDefinedStopFetching : unit -> unit*)
+
+val _ = Define `
+ ((execute_ImplementationDefinedStopFetching:unit -> unit) g__117=  () )`;
+
+
+(*val execute_HCF : unit -> unit*)
+
+val _ = Define `
+ ((execute_HCF:unit -> unit) g__122=  () )`;
+
+
+(*val execute_ERET : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ERET:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__127=  (bindS (seqS (seqS (seqS   
+(checkCP0Access () )   
+(ERETHook () ))   
+(write_regS CP0LLBit_ref (vec_of_bits [B0]  :  1 words$word)))   
+(read_regS CP0Status_ref)) (\ (w__0 : cheri_sequential_types$StatusReg) . 
+   if (((((bits_to_bool ((get_StatusReg_ERL w__0  :  1 words$word)))) = ((bit_to_bool B1))))) then bindS
+     (read_regS CP0ErrorEPC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 : 64 cheri_sequential_types$bits) .  seqS     
+(write_regS nextPC_ref w__1) (set_StatusReg_ERL CP0Status_ref (vec_of_bits [B0]  :  1 words$word)))
+   else bindS
+     (read_regS CP0EPC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) .  seqS     
+(write_regS nextPC_ref w__2) (set_StatusReg_EXL CP0Status_ref (vec_of_bits [B0]  :  1 words$word))))))`;
+
+
+(*val execute_DSUBU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSUBU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((sub_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_DSUB : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSUB:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let (temp65 : 65 cheri_sequential_types$bits) =     
+((sub_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec temp65 (( 64 : int):sail_values$ii)))))
+          ((bit_to_bool ((access_vec_dec temp65 (( 63 : int):sail_values$ii))))))) then
+     SignalException Ov
+   else wGPR rd ((subrange_vec_dec temp65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word))))))`;
+
+
+(*val execute_DSRLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) in bindS
+   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+
+
+(*val execute_DSRL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp . 
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in bindS
+   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (shift_bits_right instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRAV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRAV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let sa = ((subrange_vec_dec w__0 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word)) in bindS
+   (shift_bits_right_arith 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1)))))`;
+
+
+(*val execute_DSRA32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRA32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp . 
+   let sa32 = ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word)) in bindS
+   (shift_bits_right_arith 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa32  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSRA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSRA:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ temp .  bindS
+   (shift_bits_right_arith 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict temp sa  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0))))`;
+
+
+(*val execute_DSLLV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSLLV:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  bindS
+   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((subrange_vec_dec w__1 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :
+      64 words$word) . 
+   wGPR rd w__2)))))`;
+
+
+(*val execute_DSLL32 : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSLL32:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 ((concat_vec (vec_of_bits [B1]  :  1 words$word) sa  :  6 words$word))
+     : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd w__1))))`;
+
+
+(*val execute_DSLL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DSLL:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt rd sa=  (bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (shift_bits_left instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict w__0 sa  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) .  wGPR rd w__1))))`;
+
+
+(*val execute_DMULTU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DMULTU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let result = ((mult_vec w__0 w__1  :  128 words$word)) in seqS   
+(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii)  :  64 words$word)))   
+(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)))))))`;
+
+
+(*val execute_DMULT : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DMULT:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let result = ((mults_vec w__0 w__1  :  128 words$word)) in seqS   
+(write_regS HI_ref ((subrange_vec_dec result (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii)  :  64 words$word)))   
+(write_regS LO_ref ((subrange_vec_dec result (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)))))))`;
+
+
+(*val execute_DIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0]
+                     :  64 words$word)))))))))) then bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) .  bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . 
+      returnS (w__0, w__1)))
+    else
+      let si = (lem$w2ui ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))) in
+      let ti = (lem$w2ui ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))) in
+      let qi = (hardware_quot si ti) in
+      let ri = (hardware_mod si ti) in
+      returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii)  :  32 itself)) qi  :  32 words$word),
+               (to_bits ((make_the_value (( 32 : int):sail_values$ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in seqS   
+(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r  :  64 words$word)))   
+(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q  :  64 words$word))))))))`;
+
+
+(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rsVal .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rtVal .  bindS
+   (if (((((NotWordVal rsVal)) \/ (((((NotWordVal rtVal)) \/ (((rtVal = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                 B0]
+                     :  64 words$word)))))))))) then bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__0 : 32 cheri_sequential_types$bits) .  bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__1 : 32 cheri_sequential_types$bits) . 
+      returnS (w__0, w__1)))
+    else
+      let si = (integer_word$w2i ((subrange_vec_dec rsVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))) in
+      let ti = (integer_word$w2i ((subrange_vec_dec rtVal (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))) in
+      let qi = (hardware_quot si ti) in
+      let ri = (si - ((ti * qi))) in
+      returnS ((to_bits ((make_the_value (( 32 : int):sail_values$ii)  :  32 itself)) qi  :  32 words$word),
+               (to_bits ((make_the_value (( 32 : int):sail_values$ii)  :  32 itself)) ri  :  32 words$word))) (\ varstup .  let (q, r) = varstup in seqS   
+(write_regS HI_ref ((sign_extend1 (( 64 : int):sail_values$ii) r  :  64 words$word)))   
+(write_regS LO_ref ((sign_extend1 (( 64 : int):sail_values$ii) q  :  64 words$word))))))))`;
+
+
+(*val execute_DDIVU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DDIVU:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rsVal = (lem$w2ui w__0) in bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rtVal = (lem$w2ui w__1) in bindS
+   (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) .  bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . 
+      returnS (w__2, w__3)))
+    else
+      let qi = (hardware_quot rsVal rtVal) in
+      let ri = (hardware_mod rsVal rtVal) in
+      returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) qi  :  64 words$word),
+               (to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in seqS   
+(write_regS LO_ref q) (write_regS HI_ref r))))))`;
+
+
+(*val execute_DDIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DDIV:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rsVal = (integer_word$w2i w__0) in bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rtVal = (integer_word$w2i w__1) in bindS
+   (if (((rtVal = (( 0 : int):sail_values$ii)))) then bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 : 64 cheri_sequential_types$bits) .  bindS
+      (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 : 64 cheri_sequential_types$bits) . 
+      returnS (w__2, w__3)))
+    else
+      let qi = (hardware_quot rsVal rtVal) in
+      let ri = (rsVal - ((qi * rtVal))) in
+      returnS ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) qi  :  64 words$word),
+               (to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ri  :  64 words$word))) (\ varstup .  let (q, r) = varstup in seqS   
+(write_regS LO_ref q) (write_regS HI_ref r))))))`;
+
+
+(*val execute_DADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((add_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_DADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((add_vec w__0 ((sign_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_DADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let (sum65 : 65 cheri_sequential_types$bits) =     
+((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) imm  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii)))))
+          ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then
+     SignalException Ov
+   else wGPR rt ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)))))`;
+
+
+(*val execute_DADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_DADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let (sum65 : 65 cheri_sequential_types$bits) =     
+((add_vec ((sign_extend1 (( 65 : int):sail_values$ii) w__0  :  65 words$word)) ((sign_extend1 (( 65 : int):sail_values$ii) w__1  :  65 words$word))
+       :  65 words$word)) in
+   if ((neq_bool ((bit_to_bool ((access_vec_dec sum65 (( 64 : int):sail_values$ii)))))
+          ((bit_to_bool ((access_vec_dec sum65 (( 63 : int):sail_values$ii))))))) then
+     SignalException Ov
+   else wGPR rd ((subrange_vec_dec sum65 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word))))))`;
+
+
+(*val execute_ClearRegs : Cheri_sequential_types.ClearRegSet -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ClearRegs:cheri_sequential_types$ClearRegSet ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) regset m=  (seqS (seqS
+   (if ((((((regset = CLo))) \/ (((regset = CHi)))))) then checkCP2usable () 
+    else returnS () )
+   (if (((regset = CHi))) then
+      (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () 
+        (\ i unit_var . 
+          let r =            
+((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) ((i + (( 16 : int):sail_values$ii)))  :  5 words$word)) in bindS          
+(register_inaccessible r) (\ (w__0 : bool) . 
+          if (((((bit_to_bool ((access_vec_dec m i)))) /\ w__0))) then
+            raise_c2_exception CapEx_AccessSystemRegsViolation r
+          else returnS () )))
+    else returnS () ))
+   (foreachS (index_list (( 0 : int):sail_values$ii) (( 15 : int):sail_values$ii) (( 1 : int):sail_values$ii)) () 
+     (\ i unit_var . 
+       if ((bit_to_bool ((access_vec_dec m i)))) then
+         (case regset of
+           GPLo =>
+            wGPR ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) i  :  5 words$word))
+              ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word))
+         | GPHi =>
+            wGPR
+              ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) ((i + (( 16 : int):sail_values$ii)))
+                 :  5 words$word)) ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word))
+         | CLo =>
+            writeCapReg ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) i  :  5 words$word)) null_cap
+         | CHi =>
+            writeCapReg
+              ((to_bits ((make_the_value (( 5 : int):sail_values$ii)  :  5 itself)) ((i + (( 16 : int):sail_values$ii)))
+                 :  5 words$word)) null_cap
+         )
+       else returnS () ))))`;
+
+
+(*val execute_CWriteHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CWriteHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb sel=  (seqS   
+(checkCP2usable () )   
+(let l__24 = (lem$w2ui sel) in bindS
+   (if (((l__24 = (( 0 : int):sail_values$ii)))) then returnS (F, F)
+    else if (((l__24 = (( 1 : int):sail_values$ii)))) then returnS (F, F)
+    else if (((l__24 = (( 8 : int):sail_values$ii)))) then returnS (F, T)
+    else if (((l__24 = (( 22 : int):sail_values$ii)))) then returnS (T, F)
+    else if (((l__24 = (( 23 : int):sail_values$ii)))) then returnS (T, F)
+    else if (((l__24 = (( 29 : int):sail_values$ii)))) then returnS (T, T)
+    else if (((l__24 = (( 30 : int):sail_values$ii)))) then returnS (T, T)
+    else if (((l__24 = (( 31 : int):sail_values$ii)))) then returnS (T, T)
+    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS   
+(register_inaccessible cb) (\ (w__8 : bool) . 
+   if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(pcc_access_system_regs () ) (\ (w__9 : bool) . 
+     if (((needAccessSys /\ ((~ w__9))))) then
+       raise_c2_exception CapEx_AccessSystemRegsViolation sel
+     else bindS       
+(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . 
+       if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then
+         raise_c2_exception CapEx_AccessSystemRegsViolation sel
+       else bindS         
+(readCapReg cb) (\ capVal . 
+         let l__16 = (lem$w2ui sel) in
+         if (((l__16 = (( 0 : int):sail_values$ii)))) then writeCapReg DDC capVal
+         else if (((l__16 = (( 1 : int):sail_values$ii)))) then
+           write_regS CTLSU_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((l__16 = (( 8 : int):sail_values$ii)))) then
+           write_regS CTLSP_ref ((capStructToCapReg capVal  :  257 words$word))
+         else if (((l__16 = (( 22 : int):sail_values$ii)))) then writeCapReg KR1C capVal
+         else if (((l__16 = (( 23 : int):sail_values$ii)))) then writeCapReg KR2C capVal
+         else if (((l__16 = (( 29 : int):sail_values$ii)))) then writeCapReg KCC capVal
+         else if (((l__16 = (( 30 : int):sail_values$ii)))) then writeCapReg KDC capVal
+         else if (((l__16 = (( 31 : int):sail_values$ii)))) then writeCapReg EPCC capVal
+         else assert_expS F "should be unreachable code"))))))))`;
+
+
+(*val execute_CUnseal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CUnseal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let ct_cursor = (getCapCursor ct_val) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cs) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+     else bindS       
+(register_inaccessible ct) (\ (w__2 : bool) . 
+       if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+       else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+       else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct
+       else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs
+       else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct
+       else if (((ct_cursor <> ((lem$w2ui cs_val.CapStruct_otype))))) then
+         raise_c2_exception CapEx_TypeViolation ct
+       else if ((~ ct_val.CapStruct_permit_unseal)) then
+         raise_c2_exception CapEx_PermitUnsealViolation ct
+       else if ((ct_cursor < ((getCapBase ct_val)))) then
+         raise_c2_exception CapEx_LengthViolation ct
+       else if ((ct_cursor >= ((getCapTop ct_val)))) then
+         raise_c2_exception CapEx_LengthViolation ct
+       else
+         writeCapReg cd
+           (cs_val with<|
+             CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) ()   :  24 words$word)); CapStruct_global :=
+               (((cs_val.CapStruct_global /\ ct_val.CapStruct_global)))|>))))))))`;
+
+
+(*val execute_CToPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CToPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg ct)) (\ ct_val .  bindS   
+(readCapReg cb) (\ cb_val .  bindS   
+(register_inaccessible cb) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(register_inaccessible ct) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+     else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct
+     else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then
+       raise_c2_exception CapEx_SealViolation cb
+     else
+       let cbBase = (getCapBase cb_val) in
+       let cbTop = (getCapTop cb_val) in
+       let ctBase = (getCapBase ct_val) in
+       let ctTop = (getCapTop ct_val) in
+       wGPR rd
+         (if (((((~ cb_val.CapStruct_tag)) \/ (((((cbBase < ctBase)) \/ ((cbTop > ctTop)))))))) then
+            (zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)
+          else
+            (to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+               ((((getCapCursor cb_val)) - ctBase))
+              :  64 words$word))))))))`;
+
+
+(*val execute_CTestSubset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CTestSubset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let ct_top = (getCapTop ct_val) in
+   let ct_base = (getCapBase ct_val) in
+   let ct_perms = ((getCapPerms ct_val  :  31 words$word)) in
+   let cb_top = (getCapTop cb_val) in
+   let cb_base = (getCapBase cb_val) in
+   let cb_perms = ((getCapPerms cb_val  :  31 words$word)) in bindS   
+(register_inaccessible cb) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(register_inaccessible ct) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+     else
+       let (result : 1 cheri_sequential_types$bits) =         
+(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then
+           (vec_of_bits [B0]  :  1 words$word)
+         else if ((ct_base < cb_base)) then (vec_of_bits [B0]  :  1 words$word)
+         else if ((ct_top > cb_top)) then (vec_of_bits [B0]  :  1 words$word)
+         else if (((((and_vec ct_perms cb_perms  :  31 words$word)) <> ct_perms))) then
+           (vec_of_bits [B0]  :  1 words$word)
+         else (vec_of_bits [B1]  :  1 words$word)) in
+       wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) result  :  64 words$word))))))))`;
+
+
+(*val execute_CSub : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSub:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg ct)) (\ ct_val .  bindS   
+(readCapReg cb) (\ cb_val .  bindS   
+(register_inaccessible cb) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(register_inaccessible ct) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+     else
+       wGPR rd
+         ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+             ((((getCapCursor cb_val)) - ((getCapCursor ct_val))))
+            :  64 words$word))))))))`;
+
+
+(*val execute_CStore : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CStore:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs cb rt rd offset width conditional=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS   
+(register_inaccessible cb) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+   else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+   else if ((~ cb_val.CapStruct_permit_store)) then
+     raise_c2_exception CapEx_PermitStoreViolation cb
+   else
+     let size1 = (wordWidthBytes width) in
+     let cursor = (getCapCursor cb_val) in bindS
+     (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+     let vAddr =       
+(hardware_mod
+         ((((cursor + ((lem$w2ui w__1)))) + ((size1 * ((integer_word$w2i offset))))))
+         ((pow2 (( 64 : int):sail_values$ii)))) in
+     let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+     if ((((vAddr + size1)) > ((getCapTop cb_val)))) then
+       raise_c2_exception CapEx_LengthViolation cb
+     else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+     else if ((~ ((isAddressAligned vAddr64 width)))) then SignalExceptionBadAddr AdES vAddr64
+     else bindS
+       (TLBTranslate vAddr64 StoreData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+       (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . 
+       if conditional then bindS
+         (read_regS CP0LLBit_ref  : ( 1 words$word) cheri_sequential_types$M) (\ (w__2 : 1 cheri_sequential_types$bits) .  bindS
+         (if ((bit_to_bool ((access_vec_dec w__2 (( 0 : int):sail_values$ii))))) then
+            (case width of
+              B =>
+               MEMw_conditional_wrapper pAddr (( 1 : int):sail_values$ii)
+                 ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+            | H =>
+               MEMw_conditional_wrapper pAddr (( 2 : int):sail_values$ii)
+                 ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+            | W0 =>
+               MEMw_conditional_wrapper pAddr (( 4 : int):sail_values$ii)
+                 ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+            | D => MEMw_conditional_wrapper pAddr (( 8 : int):sail_values$ii) rs_val
+            )
+          else returnS F) (\ (success : bool) . 
+         wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+       else
+         (case width of
+           B => MEMw_wrapper pAddr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+         | H => MEMw_wrapper pAddr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))
+         | W0 => MEMw_wrapper pAddr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+         | D => MEMw_wrapper pAddr (( 8 : int):sail_values$ii) rs_val
+         ))))))))`;
+
+
+(*val execute_CSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSetOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val .  bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then
+       raise_c2_exception CapEx_SealViolation cb
+     else
+       let (success, newCap) = (setCapOffset cb_val rt_val) in
+       if success then writeCapReg cd newCap
+       else
+         writeCapReg cd
+           ((int_to_cap
+               ((add_vec
+                   ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase cb_val))
+                      :  64 words$word)) rt_val
+                  :  64 words$word))))))))))`;
+
+
+(*val execute_CSetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rt=  (bindS (seqS   
+(checkCP2usable () )   
+(pcc_access_system_regs () )) (\ (w__0 : bool) . 
+   if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation
+   else bindS
+     (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val .  seqS     
+(set_CapCauseReg_ExcCode CapCause_ref ((subrange_vec_dec rt_val (( 15 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  8 words$word)))     
+(set_CapCauseReg_RegNum CapCause_ref ((subrange_vec_dec rt_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)))))))`;
+
+
+(*val execute_CSetBoundsImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSetBoundsImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val . 
+   let immU = (lem$w2ui imm) in
+   let cursor = (getCapCursor cb_val) in
+   let base = (getCapBase cb_val) in
+   let top = (getCapTop cb_val) in
+   let newTop = (cursor + immU) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb
+     else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb
+     else  (case
+ setCapBounds cb_val
+   ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself))
+       cursor : 64 words$word))
+   ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself))
+       newTop : 65 words$word)) of
+     (_, newCap) =>
+ writeCapReg cd newCap
+ ))))))`;
+
+
+(*val execute_CSetBoundsExact : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSetBoundsExact:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rt_val = (lem$w2ui w__0) in
+   let cursor = (getCapCursor cb_val) in
+   let base = (getCapBase cb_val) in
+   let top = (getCapTop cb_val) in
+   let newTop = (cursor + rt_val) in bindS   
+(register_inaccessible cd) (\ (w__1 : bool) . 
+   if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__2 : bool) . 
+     if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb
+     else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb
+     else
+       let (exact, newCap) =         
+(setCapBounds cb_val
+           ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) cursor  :  64 words$word))
+           ((to_bits ((make_the_value (( 65 : int):sail_values$ii)  :  65 itself)) newTop  :  65 words$word))) in
+       if ((~ exact)) then raise_c2_exception CapEx_InexactBounds cb
+       else writeCapReg cd newCap))))))`;
+
+
+(*val execute_CSetBounds : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSetBounds:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rt_val = (lem$w2ui w__0) in
+   let cursor = (getCapCursor cb_val) in
+   let base = (getCapBase cb_val) in
+   let top = (getCapTop cb_val) in
+   let newTop = (cursor + rt_val) in bindS   
+(register_inaccessible cd) (\ (w__1 : bool) . 
+   if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__2 : bool) . 
+     if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((cursor < base)) then raise_c2_exception CapEx_LengthViolation cb
+     else if ((newTop > top)) then raise_c2_exception CapEx_LengthViolation cb
+     else  (case
+ setCapBounds cb_val
+   ((to_bits ((make_the_value (( 64 : int): sail_values$ii) : 64 itself))
+       cursor : 64 words$word))
+   ((to_bits ((make_the_value (( 65 : int): sail_values$ii) : 65 itself))
+       newTop : 65 words$word)) of
+     (_, newCap) =>
+ writeCapReg cd newCap
+ )))))))`;
+
+
+(*val execute_CSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let ct_cursor = (getCapCursor ct_val) in
+   let ct_top = (getCapTop ct_val) in
+   let ct_base = (getCapBase ct_val) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cs) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+     else bindS       
+(register_inaccessible ct) (\ (w__2 : bool) . 
+       if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+       else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+       else if ((~ ct_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation ct
+       else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs
+       else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct
+       else if ((~ ct_val.CapStruct_permit_seal)) then
+         raise_c2_exception CapEx_PermitSealViolation ct
+       else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct
+       else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct
+       else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct
+       else
+         let (success, newCap) =           
+(sealCap cs_val
+             ((to_bits ((make_the_value (( 24 : int):sail_values$ii)  :  24 itself)) ct_cursor  :  24 words$word))) in
+         if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs
+         else writeCapReg cd newCap)))))))`;
+
+
+(*val execute_CSC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CSC:(5)words$word ->(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb rt rd offset conditional=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val .  bindS   
+(readCapReg cb) (\ cb_val .  bindS   
+(register_inaccessible cs) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((~ cb_val.CapStruct_permit_store)) then
+       raise_c2_exception CapEx_PermitStoreViolation cb
+     else if ((~ cb_val.CapStruct_permit_store_cap)) then
+       raise_c2_exception CapEx_PermitStoreCapViolation cb
+     else if (((((~ cb_val.CapStruct_permit_store_local_cap)) /\ (((cs_val.CapStruct_tag /\ ((~ cs_val.CapStruct_global)))))))) then
+       raise_c2_exception CapEx_PermitStoreLocalCapViolation cb
+     else
+       let cursor = (getCapCursor cb_val) in bindS
+       (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+       let vAddr =         
+(hardware_mod
+           ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+           ((pow2 (( 64 : int):sail_values$ii)))) in
+       let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+       if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then
+         raise_c2_exception CapEx_LengthViolation cb
+       else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+       else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then
+         SignalExceptionBadAddr AdES vAddr64
+       else bindS
+         (TLBTranslateC vAddr64 StoreData  : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup .  let (pAddr, noStoreCap) = varstup in
+         if (((cs_val.CapStruct_tag /\ noStoreCap))) then
+           raise_c2_exception CapEx_TLBNoStoreCap cs
+         else if conditional then bindS
+           (read_regS CP0LLBit_ref  : ( 1 words$word) cheri_sequential_types$M) (\ (w__3 : 1 cheri_sequential_types$bits) .  bindS
+           (if ((bit_to_bool ((access_vec_dec w__3 (( 0 : int):sail_values$ii))))) then
+              MEMw_tagged_conditional pAddr cs_val.CapStruct_tag
+                ((capStructToMemBits cs_val  :  256 words$word))
+            else returnS F) (\ success . 
+           wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits success  :  1 words$word))  :  64 words$word))))
+         else MEMw_tagged pAddr cs_val.CapStruct_tag ((capStructToMemBits cs_val  :  256 words$word))))))))))`;
+
+
+(*val execute_CReturn : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CReturn:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__128=  (seqS (checkCP2usable () ) (raise_c2_exception_noreg CapEx_ReturnTrap)))`;
+
+
+(*val execute_CReadHwr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CReadHwr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd sel=  (seqS   
+(checkCP2usable () )   
+(let l__8 = (lem$w2ui sel) in bindS
+   (if (((l__8 = (( 0 : int):sail_values$ii)))) then returnS (F, F)
+    else if (((l__8 = (( 1 : int):sail_values$ii)))) then returnS (F, F)
+    else if (((l__8 = (( 8 : int):sail_values$ii)))) then returnS (F, T)
+    else if (((l__8 = (( 22 : int):sail_values$ii)))) then returnS (T, F)
+    else if (((l__8 = (( 23 : int):sail_values$ii)))) then returnS (T, F)
+    else if (((l__8 = (( 29 : int):sail_values$ii)))) then returnS (T, T)
+    else if (((l__8 = (( 30 : int):sail_values$ii)))) then returnS (T, T)
+    else if (((l__8 = (( 31 : int):sail_values$ii)))) then returnS (T, T)
+    else SignalException ResI) (\ varstup .  let ((needSup : bool), (needAccessSys : bool)) = varstup in bindS   
+(register_inaccessible cd) (\ (w__8 : bool) . 
+   if w__8 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(pcc_access_system_regs () ) (\ (w__9 : bool) . 
+     if (((needAccessSys /\ ((~ w__9))))) then
+       raise_c2_exception CapEx_AccessSystemRegsViolation sel
+     else bindS       
+(getAccessLevel () ) (\ (w__10 : cheri_sequential_types$AccessLevel) . 
+       if (((needSup /\ ((~ ((grantsAccess w__10 Supervisor))))))) then
+         raise_c2_exception CapEx_AccessSystemRegsViolation sel
+       else
+         let l__0 = (lem$w2ui sel) in bindS
+         (if (((l__0 = (( 0 : int):sail_values$ii)))) then readCapReg DDC
+          else if (((l__0 = (( 1 : int):sail_values$ii)))) then bindS
+            (read_regS CTLSU_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__12 :  257 words$word) . 
+            returnS ((capRegToCapStruct w__12)))
+          else if (((l__0 = (( 8 : int):sail_values$ii)))) then bindS
+            (read_regS CTLSP_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__13 :  257 words$word) . 
+            returnS ((capRegToCapStruct w__13)))
+          else if (((l__0 = (( 22 : int):sail_values$ii)))) then readCapReg KR1C
+          else if (((l__0 = (( 23 : int):sail_values$ii)))) then readCapReg KR2C
+          else if (((l__0 = (( 29 : int):sail_values$ii)))) then readCapReg KCC
+          else if (((l__0 = (( 30 : int):sail_values$ii)))) then readCapReg KDC
+          else if (((l__0 = (( 31 : int):sail_values$ii)))) then readCapReg EPCC
+          else seqS (assert_expS F "should be unreachable code") (undefined_CapStruct () )) (\ (capVal :
+           cheri_sequential_types$CapStruct) . 
+         writeCapReg cd capVal))))))))`;
+
+
+(*val execute_CPtrCmp : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.CPtrCmpOp -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CPtrCmp:(5)words$word ->(5)words$word ->(5)words$word -> cheri_sequential_types$CPtrCmpOp ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb ct op=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(register_inaccessible ct) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+     else bindS       
+(readCapReg cb) (\ cb_val .  bindS       
+(readCapReg ct) (\ ct_val . 
+       let equal = F in
+       let ltu = F in
+       let lts = F in
+       let ((equal : bool), (lts : bool), (ltu : bool)) =         
+(if ((neq_bool cb_val.CapStruct_tag ct_val.CapStruct_tag)) then
+           let ((lts : bool), (ltu : bool)) =             
+(if ((~ cb_val.CapStruct_tag)) then
+               let (ltu : bool) = T in
+               let (lts : bool) = T in
+               (lts, ltu)
+             else (lts, ltu)) in
+           (equal, lts, ltu)
+         else
+           let cursor1 = (getCapCursor cb_val) in
+           let cursor2 = (getCapCursor ct_val) in
+           let (equal : bool) = (cursor1 = cursor2) in
+           let (ltu : bool) = (cursor1 < cursor2) in
+           let (lts : bool) =             
+((integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) cursor1  :  64 words$word))) < (integer_word$w2i ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) cursor2  :  64 words$word)))) in
+           (equal, lts, ltu)) in
+       let (cmp : bool) =         
+((case op of
+           CEQ => equal
+         | CNE => ~ equal
+         | CLT => lts
+         | CLE => (lts \/ equal)
+         | CLTU => ltu
+         | CLEU => (ltu \/ equal)
+         | CEXEQ => (cb_val = ct_val)
+         | CNEXEQ => (cb_val <> ct_val)
+         )) in
+       wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits cmp  :  1 words$word))  :  64 words$word))))))))`;
+
+
+(*val execute_CMOVX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CMOVX:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt ismovn=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cd)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else bindS
+       (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+       if ((bits_to_bool
+              ((xor_vec
+                  ((bool_to_bits (((w__2 = ((zeros (( 64 : int):sail_values$ii) ()   :  64 words$word)))))  :  1 words$word))
+                  ((bool_to_bits ismovn  :  1 words$word))
+                 :  1 words$word)))) then bindS         
+(readCapReg cb) (\ (w__3 : cheri_sequential_types$CapStruct) .  writeCapReg cd w__3)
+       else returnS () )))))`;
+
+
+(*val execute_CLoad : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty8 -> bool -> Cheri_sequential_types.WordType -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CLoad:(5)words$word ->(5)words$word ->(5)words$word ->(8)words$word -> bool -> cheri_sequential_types$WordType -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) arg0 arg1 arg2 arg3 arg4 arg5 arg6=   
+ (let merge_var = (arg0, arg1, arg2, arg3, arg4, arg5, arg6) in
+   (case merge_var of
+     (rd, cb, rt, offset, signext, B, linked) => bindS (seqS      
+(checkCP2usable () )      
+(readCapReg cb)) (\ cb_val .  bindS      
+(register_inaccessible cb) (\ (w__0 : bool) . 
+      if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+      else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+      else if ((~ cb_val.CapStruct_permit_load)) then
+        raise_c2_exception CapEx_PermitLoadViolation cb
+      else
+        let cursor = (getCapCursor cb_val) in bindS
+        (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+        let vAddr =          
+(hardware_mod
+            ((((cursor + ((lem$w2ui w__1)))) + (((( 1 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+            ((pow2 (( 64 : int):sail_values$ii)))) in
+        let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+        if ((((vAddr + (( 1 : int):sail_values$ii))) > ((getCapTop cb_val)))) then
+          raise_c2_exception CapEx_LengthViolation cb
+        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+        else if ((~ ((isAddressAligned vAddr64 B)))) then SignalExceptionBadAddr AdEL vAddr64
+        else bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+          (if linked then bindS (seqS (seqS             
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))             
+(write_regS CP0LLAddr_ref pAddr))
+             (MEMr_reserve_wrapper pAddr (( 1 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M)) (\ (w__2 :  8 words$word) . 
+             returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else bindS
+             (MEMr_wrapper pAddr (( 1 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M) (\ (w__3 :  8 words$word) . 
+             returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . 
+          wGPR rd memResult)))))
+   | (rd, cb, rt, offset, signext, D, linked) => bindS (seqS      
+(checkCP2usable () )      
+(readCapReg cb)) (\ cb_val .  bindS      
+(register_inaccessible cb) (\ (w__0 : bool) . 
+      if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+      else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+      else if ((~ cb_val.CapStruct_permit_load)) then
+        raise_c2_exception CapEx_PermitLoadViolation cb
+      else
+        let cursor = (getCapCursor cb_val) in bindS
+        (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+        let vAddr =          
+(hardware_mod
+            ((((cursor + ((lem$w2ui w__1)))) + (((( 8 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+            ((pow2 (( 64 : int):sail_values$ii)))) in
+        let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+        if ((((vAddr + (( 8 : int):sail_values$ii))) > ((getCapTop cb_val)))) then
+          raise_c2_exception CapEx_LengthViolation cb
+        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+        else if ((~ ((isAddressAligned vAddr64 D)))) then SignalExceptionBadAddr AdEL vAddr64
+        else bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+          (if linked then bindS (seqS (seqS             
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))             
+(write_regS CP0LLAddr_ref pAddr))
+             (MEMr_reserve_wrapper pAddr (( 8 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__2 :  64 words$word) . 
+             returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else bindS
+             (MEMr_wrapper pAddr (( 8 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 :  64 words$word) . 
+             returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . 
+          wGPR rd memResult)))))
+   | (rd, cb, rt, offset, signext, H, linked) => bindS (seqS      
+(checkCP2usable () )      
+(readCapReg cb)) (\ cb_val .  bindS      
+(register_inaccessible cb) (\ (w__0 : bool) . 
+      if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+      else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+      else if ((~ cb_val.CapStruct_permit_load)) then
+        raise_c2_exception CapEx_PermitLoadViolation cb
+      else
+        let cursor = (getCapCursor cb_val) in bindS
+        (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+        let vAddr =          
+(hardware_mod
+            ((((cursor + ((lem$w2ui w__1)))) + (((( 2 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+            ((pow2 (( 64 : int):sail_values$ii)))) in
+        let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+        if ((((vAddr + (( 2 : int):sail_values$ii))) > ((getCapTop cb_val)))) then
+          raise_c2_exception CapEx_LengthViolation cb
+        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+        else if ((~ ((isAddressAligned vAddr64 H)))) then SignalExceptionBadAddr AdEL vAddr64
+        else bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+          (if linked then bindS (seqS (seqS             
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))             
+(write_regS CP0LLAddr_ref pAddr))
+             (MEMr_reserve_wrapper pAddr (( 2 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M)) (\ (w__2 :  16 words$word) . 
+             returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else bindS
+             (MEMr_wrapper pAddr (( 2 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M) (\ (w__3 :  16 words$word) . 
+             returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . 
+          wGPR rd memResult)))))
+   | (rd, cb, rt, offset, signext, W0, linked) => bindS (seqS      
+(checkCP2usable () )      
+(readCapReg cb)) (\ cb_val .  bindS      
+(register_inaccessible cb) (\ (w__0 : bool) . 
+      if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+      else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+      else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+      else if ((~ cb_val.CapStruct_permit_load)) then
+        raise_c2_exception CapEx_PermitLoadViolation cb
+      else
+        let cursor = (getCapCursor cb_val) in bindS
+        (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+        let vAddr =          
+(hardware_mod
+            ((((cursor + ((lem$w2ui w__1)))) + (((( 4 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+            ((pow2 (( 64 : int):sail_values$ii)))) in
+        let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+        if ((((vAddr + (( 4 : int):sail_values$ii))) > ((getCapTop cb_val)))) then
+          raise_c2_exception CapEx_LengthViolation cb
+        else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+        else if ((~ ((isAddressAligned vAddr64 W0)))) then SignalExceptionBadAddr AdEL vAddr64
+        else bindS
+          (TLBTranslate vAddr64 LoadData  : ( 64 words$word) cheri_sequential_types$M) (\ pAddr .  bindS
+          (if linked then bindS (seqS (seqS             
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))             
+(write_regS CP0LLAddr_ref pAddr))
+             (MEMr_reserve_wrapper pAddr (( 4 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__2 :  32 words$word) . 
+             returnS ((extendLoad w__2 signext  :  64 words$word)))
+           else bindS
+             (MEMr_wrapper pAddr (( 4 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M) (\ (w__3 :  32 words$word) . 
+             returnS ((extendLoad w__3 signext  :  64 words$word)))) (\ (memResult : 64 cheri_sequential_types$bits) . 
+          wGPR rd memResult)))))
+   )))`;
+
+
+(*val execute_CLC : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CLC:(5)words$word ->(5)words$word ->(5)words$word ->(11)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt offset linked=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((~ cb_val.CapStruct_permit_load)) then
+       raise_c2_exception CapEx_PermitLoadViolation cb
+     else
+       let cursor = (getCapCursor cb_val) in bindS
+       (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+       let vAddr =         
+(hardware_mod
+           ((((cursor + ((lem$w2ui w__2)))) + (((( 16 : int):sail_values$ii) * ((integer_word$w2i offset))))))
+           ((pow2 (( 64 : int):sail_values$ii)))) in
+       let vAddr64 = ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) vAddr  :  64 words$word)) in
+       if ((((vAddr + cap_size)) > ((getCapTop cb_val)))) then
+         raise_c2_exception CapEx_LengthViolation cb
+       else if ((vAddr < ((getCapBase cb_val)))) then raise_c2_exception CapEx_LengthViolation cb
+       else if (((((hardware_mod vAddr cap_size)) <> (( 0 : int):sail_values$ii)))) then
+         SignalExceptionBadAddr AdEL vAddr64
+       else bindS
+         (TLBTranslateC vAddr64 LoadData  : (( 64 words$word # bool)) cheri_sequential_types$M) (\ varstup .  let (pAddr, suppressTag) = varstup in
+         let cd = (lem$w2ui cd) in
+         if linked then bindS (seqS (seqS           
+(write_regS CP0LLBit_ref (vec_of_bits [B1]  :  1 words$word))           
+(write_regS CP0LLAddr_ref pAddr))
+           (MEMr_tagged_reserve pAddr  : ((bool #  256 words$word)) cheri_sequential_types$M)) (\ varstup .  let (tag, mem) = varstup in
+           write_regS
+             ((access_list_dec CapRegs cd  : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref))
+             ((memBitsToCapBits
+                 (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag))))))))
+                 mem
+                :  257 words$word)))
+         else bindS
+           (MEMr_tagged pAddr  : ((bool #  256 words$word)) cheri_sequential_types$M) (\ varstup .  let (tag, mem) = varstup in
+           write_regS
+             ((access_list_dec CapRegs cd  : (cheri_sequential_types$regstate, cheri_sequential_types$register_value, ( 257 words$word)) sail_values$register_ref))
+             ((memBitsToCapBits
+                 (((tag /\ (((cb_val.CapStruct_permit_load_cap /\ ((~ suppressTag))))))))
+                 mem
+                :  257 words$word))))))))))`;
+
+
+(*val execute_CJALR : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CJALR:(5)words$word ->(5)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb link=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val . 
+   let cb_ptr = (getCapCursor cb_val) in
+   let cb_top = (getCapTop cb_val) in
+   let cb_base = (getCapBase cb_val) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if (((link /\ w__0))) then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else if ((~ cb_val.CapStruct_permit_execute)) then
+       raise_c2_exception CapEx_PermitExecuteViolation cb
+     else if ((cb_ptr < cb_base)) then raise_c2_exception CapEx_LengthViolation cb
+     else if ((((cb_ptr + (( 4 : int):sail_values$ii))) > cb_top)) then
+       raise_c2_exception CapEx_LengthViolation cb
+     else if (((((hardware_mod cb_ptr (( 4 : int):sail_values$ii))) <> (( 0 : int):sail_values$ii)))) then SignalException AdEL
+     else seqS
+       (if link then bindS
+          (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__2 :  257 words$word) . 
+          let pcc = (capRegToCapStruct w__2) in bindS
+          (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 :  64 words$word) . 
+          let (success, linkCap) = (setCapOffset pcc ((add_vec_int w__3 (( 8 : int):sail_values$ii)  :  64 words$word))) in
+          if success then writeCapReg cd linkCap
+          else assert_expS F ""))
+        else returnS () )       
+(execute_branch_pcc cb_val))))))`;
+
+
+(*val execute_CIncOffsetImmediate : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CIncOffsetImmediate:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb imm=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val . 
+   let (imm64 : 64 cheri_sequential_types$bits) = ((sign_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word)) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if (((cb_val.CapStruct_tag /\ cb_val.CapStruct_sealed))) then
+       raise_c2_exception CapEx_SealViolation cb
+     else
+       let (success, newCap) = (incCapOffset cb_val imm64) in
+       if success then writeCapReg cd newCap
+       else
+         writeCapReg cd
+           ((int_to_cap
+               ((add_vec
+                   ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase cb_val))
+                      :  64 words$word)) imm64
+                  :  64 words$word)))))))))`;
+
+
+(*val execute_CIncOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CIncOffset:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val .  bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if (((cb_val.CapStruct_tag /\ (((cb_val.CapStruct_sealed /\ (((rt_val <> (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                       B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                                       B0]
+                           :  64 words$word)))))))))) then
+       raise_c2_exception CapEx_SealViolation cb
+     else
+       let (success, newCap) = (incCapOffset cb_val rt_val) in
+       if success then writeCapReg cd newCap
+       else
+         writeCapReg cd
+           ((int_to_cap
+               ((add_vec
+                   ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase cb_val))
+                      :  64 words$word)) rt_val
+                  :  64 words$word))))))))))`;
+
+
+(*val execute_CGetType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       (if capVal.CapStruct_sealed then (zero_extend1 (( 64 : int):sail_values$ii) capVal.CapStruct_otype  :  64 words$word)
+        else (replicate_bits ((cast_unit_vec0 B1  :  1 words$word)) (( 64 : int):sail_values$ii)  :  64 words$word))))))`;
+
+
+(*val execute_CGetTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_tag  :  1 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_CGetSealed : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetSealed:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       ((zero_extend1 (( 64 : int):sail_values$ii) ((bool_to_bits capVal.CapStruct_sealed  :  1 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_CGetPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms capVal  :  31 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_CGetPCCSetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetPCCSetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd rs=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cd)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS
+     (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 :  257 words$word) . 
+     let pcc = (capRegToCapStruct w__1) in bindS
+     (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ rs_val . 
+     let (success, newPCC) = (setCapOffset pcc rs_val) in
+     if success then writeCapReg cd newPCC
+     else writeCapReg cd ((int_to_cap rs_val)))))))`;
+
+
+(*val execute_CGetPCC : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetPCC:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cd)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS
+     (read_regS PCC_ref  : ( 257 words$word) cheri_sequential_types$M) (\ (w__1 :  257 words$word) . 
+     let pcc = (capRegToCapStruct w__1) in bindS
+     (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+     let (success, pcc2) = (setCapOffset pcc w__2) in seqS     
+(assert_expS success "") (writeCapReg cd pcc2))))))`;
+
+
+(*val execute_CGetOffset : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetOffset:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapOffset capVal))  :  64 words$word))))))`;
+
+
+(*val execute_CGetLen : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetLen:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     let len65 = (getCapLength capVal) in
+     wGPR rd
+       ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself))
+           (if ((len65 > MAX_U64)) then MAX_U64
+            else len65)
+          :  64 words$word))))))`;
+
+
+(*val execute_CGetCause : Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetCause:(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd=  (bindS (seqS   
+(checkCP2usable () )   
+(pcc_access_system_regs () )) (\ (w__0 : bool) . 
+   if ((~ w__0)) then raise_c2_exception_noreg CapEx_AccessSystemRegsViolation
+   else bindS     
+(read_regS CapCause_ref) (\ (w__1 : cheri_sequential_types$CapCauseReg) . 
+     wGPR rd ((zero_extend1 (( 64 : int):sail_values$ii) ((get_CapCauseReg w__1  :  16 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_CGetBase : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetBase:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase capVal))  :  64 words$word))))))`;
+
+
+(*val execute_CGetAddr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CGetAddr:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ capVal . 
+     wGPR rd
+       ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapCursor capVal))  :  64 words$word))))))`;
+
+
+(*val execute_CFromPtr : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CFromPtr:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val .  bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if (((rt = (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))) then writeCapReg cd null_cap
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else
+       let (success, newCap) = (setCapOffset cb_val rt_val) in
+       if success then writeCapReg cd newCap
+       else
+         writeCapReg cd
+           ((int_to_cap
+               ((add_vec
+                   ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((getCapBase cb_val))
+                      :  64 words$word)) rt_val
+                  :  64 words$word))))))))))`;
+
+
+(*val execute_CCopyType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CCopyType:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let cb_base = (getCapBase cb_val) in
+   let cb_top = (getCapTop cb_val) in
+   let ct_otype = (lem$w2ui ct_val.CapStruct_otype) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else bindS       
+(register_inaccessible ct) (\ (w__2 : bool) . 
+       if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+       else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+       else if ct_val.CapStruct_sealed then
+         if ((ct_otype < cb_base)) then raise_c2_exception CapEx_LengthViolation cb
+         else if ((ct_otype >= cb_top)) then raise_c2_exception CapEx_LengthViolation cb
+         else
+           let (success, cap) =             
+(setCapOffset cb_val
+               ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ((ct_otype - cb_base))
+                  :  64 words$word))) in seqS           
+(assert_expS success "") (writeCapReg cd cap)
+       else
+         writeCapReg cd
+           ((int_to_cap ((replicate_bits ((cast_unit_vec0 B1  :  1 words$word)) (( 64 : int):sail_values$ii)  :  64 words$word)))))))))))`;
+
+
+(*val execute_CClearTag : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CClearTag:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cd)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else bindS (readCapReg cb) (\ cb_val .  writeCapReg cd (cb_val with<| CapStruct_tag := F|>))))))`;
+
+
+(*val execute_CCheckType : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CCheckType:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val .  bindS   
+(readCapReg cb) (\ cb_val .  bindS   
+(register_inaccessible cs) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs
+     else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb
+     else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then
+       raise_c2_exception CapEx_TypeViolation cs
+     else returnS () ))))))`;
+
+
+(*val execute_CCheckPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CCheckPerm:(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val . 
+   let (cs_perms : 64 cheri_sequential_types$bits) =     
+((zero_extend1 (( 64 : int):sail_values$ii) ((getCapPerms cs_val  :  31 words$word))  :  64 words$word)) in bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_perms .  bindS   
+(register_inaccessible cs) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+   else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+   else if (((((and_vec cs_perms rt_perms  :  64 words$word)) <> rt_perms))) then
+     raise_c2_exception CapEx_UserDefViolation cs
+   else returnS () )))))`;
+
+
+(*val execute_CCall : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty11 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CCall:(5)words$word ->(5)words$word ->(11)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cs cb b__151=   
+ (if (((b__151 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  11 words$word)))) then bindS (seqS     
+(checkCP2usable () )     
+(readCapReg cs)) (\ cs_val .  bindS     
+(readCapReg cb) (\ cb_val . 
+     let cs_cursor = (getCapCursor cs_val) in bindS     
+(register_inaccessible cs) (\ (w__0 : bool) . 
+     if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+     else bindS       
+(register_inaccessible cb) (\ (w__1 : bool) . 
+       if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+       else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+       else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs
+       else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb
+       else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then
+         raise_c2_exception CapEx_TypeViolation cs
+       else if ((~ cs_val.CapStruct_permit_execute)) then
+         raise_c2_exception CapEx_PermitExecuteViolation cs
+       else if cb_val.CapStruct_permit_execute then
+         raise_c2_exception CapEx_PermitExecuteViolation cb
+       else if ((cs_cursor < ((getCapBase cs_val)))) then
+         raise_c2_exception CapEx_LengthViolation cs
+       else if ((cs_cursor >= ((getCapTop cs_val)))) then
+         raise_c2_exception CapEx_LengthViolation cs
+       else raise_c2_exception CapEx_CallTrap cs))))
+   else bindS (seqS     
+(checkCP2usable () )     
+(readCapReg cs)) (\ cs_val .  bindS     
+(readCapReg cb) (\ cb_val . 
+     let cs_cursor = (getCapCursor cs_val) in bindS     
+(register_inaccessible cs) (\ (w__2 : bool) . 
+     if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+     else bindS       
+(register_inaccessible cb) (\ (w__3 : bool) . 
+       if w__3 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+       else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+       else if ((~ cs_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cs
+       else if ((~ cb_val.CapStruct_sealed)) then raise_c2_exception CapEx_SealViolation cb
+       else if (((cs_val.CapStruct_otype <> cb_val.CapStruct_otype))) then
+         raise_c2_exception CapEx_TypeViolation cs
+       else if ((~ cs_val.CapStruct_permit_ccall)) then
+         raise_c2_exception CapEx_PermitCCallViolation cs
+       else if ((~ cb_val.CapStruct_permit_ccall)) then
+         raise_c2_exception CapEx_PermitCCallViolation cb
+       else if ((~ cs_val.CapStruct_permit_execute)) then
+         raise_c2_exception CapEx_PermitExecuteViolation cs
+       else if cb_val.CapStruct_permit_execute then
+         raise_c2_exception CapEx_PermitExecuteViolation cb
+       else if ((cs_cursor < ((getCapBase cs_val)))) then
+         raise_c2_exception CapEx_LengthViolation cs
+       else if ((cs_cursor >= ((getCapTop cs_val)))) then
+         raise_c2_exception CapEx_LengthViolation cs
+       else seqS (seqS         
+(execute_branch_pcc
+           (cs_val with<|
+             CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) ()   :  24 words$word))|>))         
+(write_regS inCCallDelay_ref (vec_of_bits [B1]  :  1 words$word)))         
+(write_regS
+           C26_ref
+           ((capStructToCapReg
+               (cb_val with<|
+                 CapStruct_sealed := F; CapStruct_otype := ((zeros (( 24 : int):sail_values$ii) ()   :  24 words$word))|>)
+              :  257 words$word)))))))))`;
+
+
+(*val execute_CCSeal : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CCSeal:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cs ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cs)) (\ cs_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let ct_cursor = (getCapCursor ct_val) in
+   let ct_top = (getCapTop ct_val) in
+   let ct_base = (getCapBase ct_val) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cs) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cs
+     else bindS       
+(register_inaccessible ct) (\ (w__2 : bool) . 
+       if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+       else if ((~ cs_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cs
+       else if (((((~ ct_val.CapStruct_tag)) \/ (((((getCapCursor ct_val)) = ((lem$w2ui ((replicate_bits ((cast_unit_vec0 B1  :  1 words$word)) (( 64 : int):sail_values$ii)  :  64 words$word))))))))))
+       then
+         writeCapReg cd cs_val
+       else if cs_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cs
+       else if ct_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation ct
+       else if ((~ ct_val.CapStruct_permit_seal)) then
+         raise_c2_exception CapEx_PermitSealViolation ct
+       else if ((ct_cursor < ct_base)) then raise_c2_exception CapEx_LengthViolation ct
+       else if ((ct_cursor >= ct_top)) then raise_c2_exception CapEx_LengthViolation ct
+       else if ((ct_cursor > max_otype)) then raise_c2_exception CapEx_LengthViolation ct
+       else
+         let (success, newCap) =           
+(sealCap cs_val
+             ((to_bits ((make_the_value (( 24 : int):sail_values$ii)  :  24 itself)) ct_cursor  :  24 words$word))) in
+         if ((~ success)) then raise_c2_exception CapEx_InexactBounds cs
+         else writeCapReg cd newCap)))))))`;
+
+
+(*val execute_CBuildCap : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CBuildCap:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb ct=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS   
+(readCapReg ct) (\ ct_val . 
+   let cb_base = (getCapBase cb_val) in
+   let ct_base = (getCapBase ct_val) in
+   let cb_top = (getCapTop cb_val) in
+   let ct_top = (getCapTop ct_val) in
+   let cb_perms = ((getCapPerms cb_val  :  31 words$word)) in
+   let ct_perms = ((getCapPerms ct_val  :  31 words$word)) in
+   let ct_offset = (getCapOffset ct_val) in bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else bindS       
+(register_inaccessible ct) (\ (w__2 : bool) . 
+       if w__2 then raise_c2_exception CapEx_AccessSystemRegsViolation ct
+       else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+       else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+       else if ((ct_base < cb_base)) then raise_c2_exception CapEx_LengthViolation cb
+       else if ((ct_top > cb_top)) then raise_c2_exception CapEx_LengthViolation cb
+       else if ((ct_base > ct_top)) then raise_c2_exception CapEx_LengthViolation ct
+       else if (((((and_vec ct_perms cb_perms  :  31 words$word)) <> ct_perms))) then
+         raise_c2_exception CapEx_UserDefViolation cb
+       else
+         let (exact, cd1) =           
+(setCapBounds cb_val
+             ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ct_base  :  64 words$word))
+             ((to_bits ((make_the_value (( 65 : int):sail_values$ii)  :  65 itself)) ct_top  :  65 words$word))) in
+         let (representable, cd2) =           
+(setCapOffset cd1
+             ((to_bits ((make_the_value (( 64 : int):sail_values$ii)  :  64 itself)) ct_offset  :  64 words$word))) in
+         let cd3 = (setCapPerms cd2 ct_perms) in seqS (seqS         
+(assert_expS exact "") (assert_expS representable "")) (writeCapReg cd cd3))))))))`;
+
+
+(*val execute_CBZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CBZ:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notzero=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . 
+     if ((bits_to_bool
+            ((xor_vec ((bool_to_bits (((w__1 = null_cap)))  :  1 words$word))
+                ((bool_to_bits notzero  :  1 words$word))
+               :  1 words$word)))) then
+       let (offset : 64 cheri_sequential_types$bits) =         
+((add_vec_int
+            ((sign_extend1 (( 64 : int):sail_values$ii)
+                ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+               :  64 words$word)) (( 4 : int):sail_values$ii)
+           :  64 words$word)) in bindS
+       (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+       execute_branch ((add_vec w__2 offset  :  64 words$word)))
+     else returnS () ))))`;
+
+
+(*val execute_CBX : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CBX:(5)words$word ->(16)words$word -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cb imm notset=  (bindS (seqS   
+(checkCP2usable () )   
+(register_inaccessible cb)) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+   else bindS     
+(readCapReg cb) (\ (w__1 : cheri_sequential_types$CapStruct) . 
+     if ((bits_to_bool
+            ((xor_vec ((bool_to_bits w__1.CapStruct_tag  :  1 words$word))
+                ((bool_to_bits notset  :  1 words$word))
+               :  1 words$word)))) then
+       let (offset : 64 cheri_sequential_types$bits) =         
+((add_vec_int
+            ((sign_extend1 (( 64 : int):sail_values$ii)
+                ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+               :  64 words$word)) (( 4 : int):sail_values$ii)
+           :  64 words$word)) in bindS
+       (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+       execute_branch ((add_vec w__2 offset  :  64 words$word)))
+     else returnS () ))))`;
+
+
+(*val execute_CAndPerm : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CAndPerm:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) cd cb rt=  (bindS (seqS   
+(checkCP2usable () )   
+(readCapReg cb)) (\ cb_val .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ rt_val .  bindS   
+(register_inaccessible cd) (\ (w__0 : bool) . 
+   if w__0 then raise_c2_exception CapEx_AccessSystemRegsViolation cd
+   else bindS     
+(register_inaccessible cb) (\ (w__1 : bool) . 
+     if w__1 then raise_c2_exception CapEx_AccessSystemRegsViolation cb
+     else if ((~ cb_val.CapStruct_tag)) then raise_c2_exception CapEx_TagViolation cb
+     else if cb_val.CapStruct_sealed then raise_c2_exception CapEx_SealViolation cb
+     else
+       let perms = ((getCapPerms cb_val  :  31 words$word)) in
+       let newCap =         
+(setCapPerms cb_val
+           ((and_vec perms ((subrange_vec_dec rt_val (( 30 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  31 words$word))  :  31 words$word))) in
+       writeCapReg cd newCap))))))`;
+
+
+(*val execute_CACHE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_CACHE:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) base op imm=  (checkCP0Access () ))`;
+
+
+(*val execute_C2Dump : Machine_word.mword Machine_word.ty5 -> unit*)
+
+val _ = Define `
+ ((execute_C2Dump:(5)words$word -> unit) rt=  () )`;
+
+
+(*val execute_BREAK : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_BREAK:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) g__119=  (SignalException Bp))`;
+
+
+(*val execute_BEQ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> bool -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_BEQ:(5)words$word ->(5)words$word ->(16)words$word -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rd imm ne likely=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rd  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   if ((bits_to_bool
+          ((xor_vec ((bool_to_bits (((w__0 = w__1)))  :  1 words$word))
+              ((bool_to_bits ne  :  1 words$word))
+             :  1 words$word)))) then
+     let (offset : 64 cheri_sequential_types$bits) =       
+((add_vec_int
+          ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+             :  64 words$word)) (( 4 : int):sail_values$ii)
+         :  64 words$word)) in bindS
+     (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+     execute_branch ((add_vec w__2 offset  :  64 words$word)))
+   else if likely then bindS
+     (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__3 :  64 words$word) . 
+     write_regS nextPC_ref ((add_vec_int w__3 (( 8 : int):sail_values$ii)  :  64 words$word)))
+   else returnS () ))))`;
+
+
+(*val execute_BCMPZ : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.Comparison -> bool -> bool -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_BCMPZ:(5)words$word ->(16)words$word -> cheri_sequential_types$Comparison -> bool -> bool ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs imm cmp link likely=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) . 
+   let linkVal = ((add_vec_int w__0 (( 8 : int):sail_values$ii)  :  64 words$word)) in bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ regVal . 
+   let condition =     
+(compare cmp regVal ((zero_extend1 (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in seqS
+   (if condition then
+      let (offset : 64 cheri_sequential_types$bits) =        
+((add_vec_int
+           ((sign_extend1 (( 64 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0]  :  2 words$word)  :  18 words$word))
+              :  64 words$word)) (( 4 : int):sail_values$ii)
+          :  64 words$word)) in bindS
+      (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+      execute_branch ((add_vec w__1 offset  :  64 words$word)))
+    else if likely then bindS
+      (read_regS PC_ref  : ( 64 words$word) cheri_sequential_types$M) (\ (w__2 :  64 words$word) . 
+      write_regS nextPC_ref ((add_vec_int w__2 (( 8 : int):sail_values$ii)  :  64 words$word)))
+    else returnS () )   
+(if link then wGPR (vec_of_bits [B1;B1;B1;B1;B1]  :  5 words$word) linkVal
+   else returnS () )))))`;
+
+
+(*val execute_ANDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ANDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   wGPR rt ((and_vec w__0 ((zero_extend1 (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_AND : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_AND:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   wGPR rd ((and_vec w__0 w__1  :  64 words$word))))))`;
+
+
+(*val execute_ADDU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ADDU:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ opA .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ opB . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     wGPR rd
+       ((sign_extend1 (( 64 : int):sail_values$ii)
+           ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+               ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word))))))`;
+
+
+(*val execute_ADDIU : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ADDIU:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ opA . 
+   if ((NotWordVal opA)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+   else
+     wGPR rt
+       ((sign_extend1 (( 64 : int):sail_values$ii)
+           ((add_vec ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+               ((sign_extend1 (( 32 : int):sail_values$ii) imm  :  32 words$word))
+              :  32 words$word))
+          :  64 words$word)))))`;
+
+
+(*val execute_ADDI : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty16 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ADDI:(5)words$word ->(5)words$word ->(16)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt imm=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ opA . 
+   if ((NotWordVal opA)) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rt w__0)
+   else
+     let (sum33 : 33 cheri_sequential_types$bits) =       
+((add_vec
+          ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  33 words$word))
+          ((sign_extend1 (( 33 : int):sail_values$ii) imm  :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii)))))
+            ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then
+       SignalException Ov
+     else
+       wGPR rt
+         ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))))`;
+
+
+(*val execute_ADD : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((execute_ADD:(5)words$word ->(5)words$word ->(5)words$word ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) rs rt rd=  (bindS
+   (rGPR rs  : ( 64 words$word) cheri_sequential_types$M) (\ (opA : 64 cheri_sequential_types$bits) .  bindS
+   (rGPR rt  : ( 64 words$word) cheri_sequential_types$M) (\ (opB : 64 cheri_sequential_types$bits) . 
+   if (((((NotWordVal opA)) \/ ((NotWordVal opB))))) then bindS
+     (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 :  64 words$word) .  wGPR rd w__0)
+   else
+     let (sum33 : 33 cheri_sequential_types$bits) =       
+((add_vec
+          ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opA (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  33 words$word))
+          ((sign_extend1 (( 33 : int):sail_values$ii) ((subrange_vec_dec opB (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  33 words$word))
+         :  33 words$word)) in
+     if ((neq_bool ((bit_to_bool ((access_vec_dec sum33 (( 32 : int):sail_values$ii)))))
+            ((bit_to_bool ((access_vec_dec sum33 (( 31 : int):sail_values$ii))))))) then
+       SignalException Ov
+     else
+       wGPR rd
+         ((sign_extend1 (( 64 : int):sail_values$ii) ((subrange_vec_dec sum33 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word))))))`;
+
+
+val _ = Define `
+ ((execute:cheri_sequential_types$ast ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) merge_var=   
+ ((case merge_var of
+     DADDIU (rs,rt,imm) => execute_DADDIU rs rt imm
+   | DADDU (rs,rt,rd) => execute_DADDU rs rt rd
+   | DADDI (rs,rt,imm) => execute_DADDI rs rt imm
+   | DADD (rs,rt,rd) => execute_DADD rs rt rd
+   | ADD (rs,rt,rd) => execute_ADD rs rt rd
+   | ADDI (rs,rt,imm) => execute_ADDI rs rt imm
+   | ADDU (rs,rt,rd) => execute_ADDU rs rt rd
+   | ADDIU (rs,rt,imm) => execute_ADDIU rs rt imm
+   | DSUBU (rs,rt,rd) => execute_DSUBU rs rt rd
+   | DSUB (rs,rt,rd) => execute_DSUB rs rt rd
+   | SUB0 (rs,rt,rd) => execute_SUB rs rt rd
+   | SUBU (rs,rt,rd) => execute_SUBU rs rt rd
+   | AND (rs,rt,rd) => execute_AND rs rt rd
+   | ANDI (rs,rt,imm) => execute_ANDI rs rt imm
+   | OR (rs,rt,rd) => execute_OR rs rt rd
+   | ORI (rs,rt,imm) => execute_ORI rs rt imm
+   | NOR (rs,rt,rd) => execute_NOR rs rt rd
+   | XOR (rs,rt,rd) => execute_XOR rs rt rd
+   | XORI (rs,rt,imm) => execute_XORI rs rt imm
+   | LUI (rt,imm) => execute_LUI rt imm
+   | DSLL (rt,rd,sa) => execute_DSLL rt rd sa
+   | DSLL32 (rt,rd,sa) => execute_DSLL32 rt rd sa
+   | DSLLV (rs,rt,rd) => execute_DSLLV rs rt rd
+   | DSRA (rt,rd,sa) => execute_DSRA rt rd sa
+   | DSRA32 (rt,rd,sa) => execute_DSRA32 rt rd sa
+   | DSRAV (rs,rt,rd) => execute_DSRAV rs rt rd
+   | DSRL (rt,rd,sa) => execute_DSRL rt rd sa
+   | DSRL32 (rt,rd,sa) => execute_DSRL32 rt rd sa
+   | DSRLV (rs,rt,rd) => execute_DSRLV rs rt rd
+   | SLL (rt,rd,sa) => execute_SLL rt rd sa
+   | SLLV (rs,rt,rd) => execute_SLLV rs rt rd
+   | SRA (rt,rd,sa) => execute_SRA rt rd sa
+   | SRAV (rs,rt,rd) => execute_SRAV rs rt rd
+   | SRL (rt,rd,sa) => execute_SRL rt rd sa
+   | SRLV (rs,rt,rd) => execute_SRLV rs rt rd
+   | SLT (rs,rt,rd) => execute_SLT rs rt rd
+   | SLTI (rs,rt,imm) => execute_SLTI rs rt imm
+   | SLTU (rs,rt,rd) => execute_SLTU rs rt rd
+   | SLTIU (rs,rt,imm) => execute_SLTIU rs rt imm
+   | MOVN (rs,rt,rd) => execute_MOVN rs rt rd
+   | MOVZ (rs,rt,rd) => execute_MOVZ rs rt rd
+   | MFHI (rd) => execute_MFHI rd
+   | MFLO (rd) => execute_MFLO rd
+   | MTHI (rs) => execute_MTHI rs
+   | MTLO (rs) => execute_MTLO rs
+   | MUL (rs,rt,rd) => execute_MUL rs rt rd
+   | MULT (rs,rt) => execute_MULT rs rt
+   | MULTU (rs,rt) => execute_MULTU rs rt
+   | DMULT (rs,rt) => execute_DMULT rs rt
+   | DMULTU (rs,rt) => execute_DMULTU rs rt
+   | MADD (rs,rt) => execute_MADD rs rt
+   | MADDU (rs,rt) => execute_MADDU rs rt
+   | MSUB (rs,rt) => execute_MSUB rs rt
+   | MSUBU (rs,rt) => execute_MSUBU rs rt
+   | DIV0 (rs,rt) => execute_DIV rs rt
+   | DIVU (rs,rt) => execute_DIVU rs rt
+   | DDIV (rs,rt) => execute_DDIV rs rt
+   | DDIVU (rs,rt) => execute_DDIVU rs rt
+   | J (offset) => execute_J offset
+   | JAL (offset) => execute_JAL offset
+   | JR (rs) => execute_JR rs
+   | JALR (rs,rd) => execute_JALR rs rd
+   | BEQ (rs,rd,imm,ne,likely) => execute_BEQ rs rd imm ne likely
+   | BCMPZ (rs,imm,cmp,link,likely) => execute_BCMPZ rs imm cmp link likely
+   | SYSCALL_THREAD_START (g__116) => returnS ((execute_SYSCALL_THREAD_START g__116))
+   | ImplementationDefinedStopFetching (g__117) =>
+      returnS ((execute_ImplementationDefinedStopFetching g__117))
+   | SYSCALL (g__118) => execute_SYSCALL g__118
+   | BREAK (g__119) => execute_BREAK g__119
+   | WAIT (g__120) => execute_WAIT g__120
+   | TRAPREG (rs,rt,cmp) => execute_TRAPREG rs rt cmp
+   | TRAPIMM (rs,imm,cmp) => execute_TRAPIMM rs imm cmp
+   | Load (width,sign,linked,base,rt,offset) => execute_Load width sign linked base rt offset
+   | Store (width,conditional,base,rt,offset) => execute_Store width conditional base rt offset
+   | LWL (base,rt,offset) => execute_LWL base rt offset
+   | LWR (base,rt,offset) => execute_LWR base rt offset
+   | SWL (base,rt,offset) => execute_SWL base rt offset
+   | SWR (base,rt,offset) => execute_SWR base rt offset
+   | LDL (base,rt,offset) => execute_LDL base rt offset
+   | LDR (base,rt,offset) => execute_LDR base rt offset
+   | SDL (base,rt,offset) => execute_SDL base rt offset
+   | SDR (base,rt,offset) => execute_SDR base rt offset
+   | CACHE (base,op,imm) => execute_CACHE base op imm
+   | PREF (base,op,imm) => returnS ((execute_PREF base op imm))
+   | SYNC (g__121) => execute_SYNC g__121
+   | MFC0 (rt,rd,sel,double) => execute_MFC0 rt rd sel double
+   | HCF (g__122) => returnS ((execute_HCF g__122))
+   | MTC0 (rt,rd,sel,double) => execute_MTC0 rt rd sel double
+   | TLBWI (g__123) => execute_TLBWI g__123
+   | TLBWR (g__124) => execute_TLBWR g__124
+   | TLBR (g__125) => execute_TLBR g__125
+   | TLBP (g__126) => execute_TLBP g__126
+   | RDHWR (rt,rd) => execute_RDHWR rt rd
+   | ERET (g__127) => execute_ERET g__127
+   | CGetPerm (rd,cb) => execute_CGetPerm rd cb
+   | CGetType (rd,cb) => execute_CGetType rd cb
+   | CGetBase (rd,cb) => execute_CGetBase rd cb
+   | CGetOffset (rd,cb) => execute_CGetOffset rd cb
+   | CGetLen (rd,cb) => execute_CGetLen rd cb
+   | CGetTag (rd,cb) => execute_CGetTag rd cb
+   | CGetSealed (rd,cb) => execute_CGetSealed rd cb
+   | CGetAddr (rd,cb) => execute_CGetAddr rd cb
+   | CGetPCC (cd) => execute_CGetPCC cd
+   | CGetPCCSetOffset (cd,rs) => execute_CGetPCCSetOffset cd rs
+   | CGetCause (rd) => execute_CGetCause rd
+   | CSetCause (rt) => execute_CSetCause rt
+   | CReadHwr (cd,sel) => execute_CReadHwr cd sel
+   | CWriteHwr (cb,sel) => execute_CWriteHwr cb sel
+   | CAndPerm (cd,cb,rt) => execute_CAndPerm cd cb rt
+   | CToPtr (rd,cb,ct) => execute_CToPtr rd cb ct
+   | CSub (rd,cb,ct) => execute_CSub rd cb ct
+   | CPtrCmp (rd,cb,ct,op) => execute_CPtrCmp rd cb ct op
+   | CIncOffset (cd,cb,rt) => execute_CIncOffset cd cb rt
+   | CIncOffsetImmediate (cd,cb,imm) => execute_CIncOffsetImmediate cd cb imm
+   | CSetOffset (cd,cb,rt) => execute_CSetOffset cd cb rt
+   | CSetBounds (cd,cb,rt) => execute_CSetBounds cd cb rt
+   | CSetBoundsImmediate (cd,cb,imm) => execute_CSetBoundsImmediate cd cb imm
+   | CSetBoundsExact (cd,cb,rt) => execute_CSetBoundsExact cd cb rt
+   | CClearTag (cd,cb) => execute_CClearTag cd cb
+   | CMOVX (cd,cb,rt,ismovn) => execute_CMOVX cd cb rt ismovn
+   | ClearRegs (regset,m) => execute_ClearRegs regset m
+   | CFromPtr (cd,cb,rt) => execute_CFromPtr cd cb rt
+   | CBuildCap (cd,cb,ct) => execute_CBuildCap cd cb ct
+   | CCopyType (cd,cb,ct) => execute_CCopyType cd cb ct
+   | CCheckPerm (cs,rt) => execute_CCheckPerm cs rt
+   | CCheckType (cs,cb) => execute_CCheckType cs cb
+   | CTestSubset (rd,cb,ct) => execute_CTestSubset rd cb ct
+   | CSeal (cd,cs,ct) => execute_CSeal cd cs ct
+   | CCSeal (cd,cs,ct) => execute_CCSeal cd cs ct
+   | CUnseal (cd,cs,ct) => execute_CUnseal cd cs ct
+   | CCall (cs,cb,b__151) => execute_CCall cs cb b__151
+   | CReturn (g__128) => execute_CReturn g__128
+   | CBX (cb,imm,notset) => execute_CBX cb imm notset
+   | CBZ (cb,imm,notzero) => execute_CBZ cb imm notzero
+   | CJALR (cd,cb,link) => execute_CJALR cd cb link
+   | CLoad (rd,cb,rt,offset,signext,arg5,linked) =>
+      execute_CLoad rd cb rt offset signext arg5 linked
+   | CStore (rs,cb,rt,rd,offset,width,conditional) =>
+      execute_CStore rs cb rt rd offset width conditional
+   | CSC (cs,cb,rt,rd,offset,conditional) => execute_CSC cs cb rt rd offset conditional
+   | CLC (cd,cb,rt,offset,linked) => execute_CLC cd cb rt offset linked
+   | C2Dump (rt) => returnS ((execute_C2Dump rt))
+   | RI (g__129) => execute_RI g__129
+   )))`;
+
+
+(*val supported_instructions : Cheri_sequential_types.ast -> Maybe.maybe Cheri_sequential_types.ast*)
+
+val _ = Define `
+ ((supported_instructions:cheri_sequential_types$ast ->(cheri_sequential_types$ast)option) instr=  (SOME instr))`;
+
+
+(*val initialize_registers : unit -> Cheri_sequential_types.M unit*)
+
+val _ = Define `
+ ((initialize_registers:unit ->(cheri_sequential_types$regstate)state_monad$sequential_state ->(((unit),(cheri_sequential_types$exception))state_monad$result#(cheri_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M) (\ (w__0 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS PC_ref w__0)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__1 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS nextPC_ref w__1)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__2 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS TLBProbe_ref w__2)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii)  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__3 : cheri_sequential_types$TLBIndexT) .  bindS (seqS   
+(write_regS TLBIndex_ref w__3)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii)  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__4 : cheri_sequential_types$TLBIndexT) .  bindS (seqS   
+(write_regS TLBRandom_ref w__4)   
+(undefined_TLBEntryLoReg () )) (\ (w__5 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(write_regS TLBEntryLo0_ref w__5)   
+(undefined_TLBEntryLoReg () )) (\ (w__6 : cheri_sequential_types$TLBEntryLoReg) .  bindS (seqS   
+(write_regS TLBEntryLo1_ref w__6)   
+(undefined_ContextReg () )) (\ (w__7 : cheri_sequential_types$ContextReg) .  bindS (seqS   
+(write_regS TLBContext_ref w__7)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 16 : int):sail_values$ii)  : ( 16 words$word) cheri_sequential_types$M)) (\ (w__8 : 16 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS TLBPageMask_ref w__8)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 6 : int):sail_values$ii)  : ( 6 words$word) cheri_sequential_types$M)) (\ (w__9 : cheri_sequential_types$TLBIndexT) .  bindS (seqS   
+(write_regS TLBWired_ref w__9)   
+(undefined_TLBEntryHiReg () )) (\ (w__10 : cheri_sequential_types$TLBEntryHiReg) .  bindS (seqS   
+(write_regS TLBEntryHi_ref w__10)   
+(undefined_XContextReg () )) (\ (w__11 : cheri_sequential_types$XContextReg) .  bindS (seqS   
+(write_regS TLBXContext_ref w__11)   
+(undefined_TLBEntry () )) (\ (w__12 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry00_ref w__12)   
+(undefined_TLBEntry () )) (\ (w__13 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry01_ref w__13)   
+(undefined_TLBEntry () )) (\ (w__14 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry02_ref w__14)   
+(undefined_TLBEntry () )) (\ (w__15 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry03_ref w__15)   
+(undefined_TLBEntry () )) (\ (w__16 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry04_ref w__16)   
+(undefined_TLBEntry () )) (\ (w__17 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry05_ref w__17)   
+(undefined_TLBEntry () )) (\ (w__18 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry06_ref w__18)   
+(undefined_TLBEntry () )) (\ (w__19 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry07_ref w__19)   
+(undefined_TLBEntry () )) (\ (w__20 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry08_ref w__20)   
+(undefined_TLBEntry () )) (\ (w__21 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry09_ref w__21)   
+(undefined_TLBEntry () )) (\ (w__22 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry10_ref w__22)   
+(undefined_TLBEntry () )) (\ (w__23 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry11_ref w__23)   
+(undefined_TLBEntry () )) (\ (w__24 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry12_ref w__24)   
+(undefined_TLBEntry () )) (\ (w__25 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry13_ref w__25)   
+(undefined_TLBEntry () )) (\ (w__26 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry14_ref w__26)   
+(undefined_TLBEntry () )) (\ (w__27 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry15_ref w__27)   
+(undefined_TLBEntry () )) (\ (w__28 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry16_ref w__28)   
+(undefined_TLBEntry () )) (\ (w__29 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry17_ref w__29)   
+(undefined_TLBEntry () )) (\ (w__30 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry18_ref w__30)   
+(undefined_TLBEntry () )) (\ (w__31 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry19_ref w__31)   
+(undefined_TLBEntry () )) (\ (w__32 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry20_ref w__32)   
+(undefined_TLBEntry () )) (\ (w__33 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry21_ref w__33)   
+(undefined_TLBEntry () )) (\ (w__34 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry22_ref w__34)   
+(undefined_TLBEntry () )) (\ (w__35 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry23_ref w__35)   
+(undefined_TLBEntry () )) (\ (w__36 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry24_ref w__36)   
+(undefined_TLBEntry () )) (\ (w__37 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry25_ref w__37)   
+(undefined_TLBEntry () )) (\ (w__38 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry26_ref w__38)   
+(undefined_TLBEntry () )) (\ (w__39 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry27_ref w__39)   
+(undefined_TLBEntry () )) (\ (w__40 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry28_ref w__40)   
+(undefined_TLBEntry () )) (\ (w__41 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry29_ref w__41)   
+(undefined_TLBEntry () )) (\ (w__42 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry30_ref w__42)   
+(undefined_TLBEntry () )) (\ (w__43 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry31_ref w__43)   
+(undefined_TLBEntry () )) (\ (w__44 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry32_ref w__44)   
+(undefined_TLBEntry () )) (\ (w__45 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry33_ref w__45)   
+(undefined_TLBEntry () )) (\ (w__46 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry34_ref w__46)   
+(undefined_TLBEntry () )) (\ (w__47 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry35_ref w__47)   
+(undefined_TLBEntry () )) (\ (w__48 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry36_ref w__48)   
+(undefined_TLBEntry () )) (\ (w__49 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry37_ref w__49)   
+(undefined_TLBEntry () )) (\ (w__50 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry38_ref w__50)   
+(undefined_TLBEntry () )) (\ (w__51 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry39_ref w__51)   
+(undefined_TLBEntry () )) (\ (w__52 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry40_ref w__52)   
+(undefined_TLBEntry () )) (\ (w__53 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry41_ref w__53)   
+(undefined_TLBEntry () )) (\ (w__54 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry42_ref w__54)   
+(undefined_TLBEntry () )) (\ (w__55 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry43_ref w__55)   
+(undefined_TLBEntry () )) (\ (w__56 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry44_ref w__56)   
+(undefined_TLBEntry () )) (\ (w__57 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry45_ref w__57)   
+(undefined_TLBEntry () )) (\ (w__58 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry46_ref w__58)   
+(undefined_TLBEntry () )) (\ (w__59 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry47_ref w__59)   
+(undefined_TLBEntry () )) (\ (w__60 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry48_ref w__60)   
+(undefined_TLBEntry () )) (\ (w__61 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry49_ref w__61)   
+(undefined_TLBEntry () )) (\ (w__62 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry50_ref w__62)   
+(undefined_TLBEntry () )) (\ (w__63 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry51_ref w__63)   
+(undefined_TLBEntry () )) (\ (w__64 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry52_ref w__64)   
+(undefined_TLBEntry () )) (\ (w__65 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry53_ref w__65)   
+(undefined_TLBEntry () )) (\ (w__66 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry54_ref w__66)   
+(undefined_TLBEntry () )) (\ (w__67 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry55_ref w__67)   
+(undefined_TLBEntry () )) (\ (w__68 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry56_ref w__68)   
+(undefined_TLBEntry () )) (\ (w__69 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry57_ref w__69)   
+(undefined_TLBEntry () )) (\ (w__70 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry58_ref w__70)   
+(undefined_TLBEntry () )) (\ (w__71 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry59_ref w__71)   
+(undefined_TLBEntry () )) (\ (w__72 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry60_ref w__72)   
+(undefined_TLBEntry () )) (\ (w__73 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry61_ref w__73)   
+(undefined_TLBEntry () )) (\ (w__74 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry62_ref w__74)   
+(undefined_TLBEntry () )) (\ (w__75 : cheri_sequential_types$TLBEntry) .  bindS (seqS   
+(write_regS TLBEntry63_ref w__75)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__76 : 32 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0Compare_ref w__76)   
+(undefined_CauseReg () )) (\ (w__77 : cheri_sequential_types$CauseReg) .  bindS (seqS   
+(write_regS CP0Cause_ref w__77)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__78 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0EPC_ref w__78)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__79 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0ErrorEPC_ref w__79)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__80 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0LLBit_ref w__80)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__81 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0LLAddr_ref w__81)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__82 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0BadVAddr_ref w__82)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__83 : 32 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0Count_ref w__83)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 32 : int):sail_values$ii)  : ( 32 words$word) cheri_sequential_types$M)) (\ (w__84 : 32 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0HWREna_ref w__84)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__85 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS CP0UserLocal_ref w__85)   
+(undefined_StatusReg () )) (\ (w__86 : cheri_sequential_types$StatusReg) .  bindS (seqS   
+(write_regS CP0Status_ref w__86)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__87 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS branchPending_ref w__87)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__88 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS inBranchDelay_ref w__88)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__89 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS delayedPC_ref w__89)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__90 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS HI_ref w__90)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__91 : 64 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS LO_ref w__91)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 64 : int):sail_values$ii)  : ( 64 words$word) cheri_sequential_types$M)) (\ (w__92 :  64 words$word) .  bindS
+   (undefined_vector (( 32 : int):sail_values$ii) w__92  : ( ( 64 words$word)list) cheri_sequential_types$M) (\ (w__93 : ( 64 cheri_sequential_types$bits) list) .  bindS (seqS   
+(write_regS GPR_ref w__93)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M)) (\ (w__94 : 8 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS UART_WDATA_ref w__94)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__95 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS UART_WRITTEN_ref w__95)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 8 : int):sail_values$ii)  : ( 8 words$word) cheri_sequential_types$M)) (\ (w__96 : 8 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS UART_RDATA_ref w__96)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__97 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS UART_RVALID_ref w__97)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__98 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS PCC_ref w__98)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__99 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS nextPCC_ref w__99)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__100 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS delayedPCC_ref w__100)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 1 : int):sail_values$ii)  : ( 1 words$word) cheri_sequential_types$M)) (\ (w__101 : 1 cheri_sequential_types$bits) .  bindS (seqS   
+(write_regS inCCallDelay_ref w__101)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__102 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C00_ref w__102)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__103 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C01_ref w__103)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__104 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C02_ref w__104)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__105 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C03_ref w__105)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__106 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C04_ref w__106)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__107 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C05_ref w__107)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__108 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C06_ref w__108)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__109 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C07_ref w__109)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__110 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C08_ref w__110)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__111 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C09_ref w__111)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__112 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C10_ref w__112)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__113 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C11_ref w__113)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__114 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C12_ref w__114)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__115 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C13_ref w__115)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__116 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C14_ref w__116)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__117 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C15_ref w__117)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__118 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C16_ref w__118)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__119 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C17_ref w__119)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__120 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C18_ref w__120)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__121 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C19_ref w__121)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__122 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C20_ref w__122)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__123 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C21_ref w__123)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__124 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C22_ref w__124)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__125 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C23_ref w__125)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__126 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C24_ref w__126)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__127 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C25_ref w__127)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__128 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C26_ref w__128)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__129 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C27_ref w__129)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__130 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C28_ref w__130)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__131 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C29_ref w__131)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__132 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C30_ref w__132)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__133 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS C31_ref w__133)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__134 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS CTLSU_ref w__134)
+   (undefined_bitvector 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict (( 257 : int):sail_values$ii)  : ( 257 words$word) cheri_sequential_types$M)) (\ (w__135 : cheri_sequential_types$CapReg) .  bindS (seqS   
+(write_regS CTLSP_ref w__135)   
+(undefined_CapCauseReg () )) (\ (w__136 : cheri_sequential_types$CapCauseReg) .  write_regS CapCause_ref w__136)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))`;
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml b/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml
new file mode 100644
index 00000000..459c100e
--- /dev/null
+++ b/snapshots/hol4/sail/cheri/cheri_sequential_typesScript.sml
@@ -0,0 +1,2285 @@
+(*Generated by Lem from cheri_sequential_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "cheri_sequential_types"
+
+(*Generated by Sail from cheri_sequential.*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators_mwords*)
+(*open import State_monad*)
+(*open import State*)
+val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
+
+
+
+val _ = Hol_datatype `
+ exception  =
+    ISAException of (unit)
+  | Error_not_implemented of (string)
+  | Error_misaligned_access of (unit)
+  | Error_EBREAK of (unit)
+  | Error_internal_error of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ CauseReg  =   Mk_CauseReg of ( 32 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ CapCauseReg  =   Mk_CapCauseReg of ( 16 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ TLBEntryLoReg  =   Mk_TLBEntryLoReg of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ TLBEntryHiReg  =   Mk_TLBEntryHiReg of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ ContextReg  =   Mk_ContextReg of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ XContextReg  =   Mk_XContextReg of ( 64 words$word)`;
+
+
+
+
+val _ = type_abbrev( "TLBIndexT"  , ``: 6 bits``);
+
+val _ = Hol_datatype `
+ TLBEntry  =   Mk_TLBEntry of ( 117 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ StatusReg  =   Mk_StatusReg of ( 32 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Exception =
+  Interrupt
+  | TLBMod
+  | TLBL
+  | TLBS
+  | AdEL
+  | AdES
+  | Sys
+  | Bp
+  | ResI
+  | CpU
+  | Ov
+  | Tr
+  | C2E
+  | C2Trap
+  | XTLBRefillL
+  | XTLBRefillS
+  | XTLBInvL
+  | XTLBInvS
+  | MCheck`;
+
+
+
+
+val _ = type_abbrev( "CapReg"  , ``: 257 bits``);
+
+val _ = Hol_datatype `
+ CapStruct  =
+  <| CapStruct_tag : bool;
+     CapStruct_padding : 8 bits;
+     CapStruct_otype : 24 bits;
+     CapStruct_uperms : 16 bits;
+     CapStruct_perm_reserved11_14 : 4 bits;
+     CapStruct_access_system_regs : bool;
+     CapStruct_permit_unseal : bool;
+     CapStruct_permit_ccall : bool;
+     CapStruct_permit_seal : bool;
+     CapStruct_permit_store_local_cap : bool;
+     CapStruct_permit_store_cap : bool;
+     CapStruct_permit_load_cap : bool;
+     CapStruct_permit_store : bool;
+     CapStruct_permit_load : bool;
+     CapStruct_permit_execute : bool;
+     CapStruct_global : bool;
+     CapStruct_sealed : bool;
+     CapStruct_address : 64 bits;
+     CapStruct_base : 64 bits;
+     CapStruct_length : 64 bits  |>`;
+
+
+
+val _ = Hol_datatype `
+ MemAccessType = Instruction | LoadData | StoreData`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessLevel = User | Supervisor | Kernel`;
+
+
+
+
+val _ = type_abbrev( "regno"  , ``: 5 bits``);
+
+val _ = type_abbrev( "imm16"  , ``: 16 bits``);
+
+val _ = type_abbrev( "regregreg"  , ``: (regno # regno # regno)``);
+
+val _ = type_abbrev( "regregimm16"  , ``: (regno # regno # imm16)``);
+
+val _ = Hol_datatype `
+ decode_failure =
+  No_matching_pattern | Unsupported_instruction | Illegal_instruction | Internal_error`;
+
+
+
+
+val _ = Hol_datatype `
+ Comparison = EQ' | NE | GE | GEU | GT' | LE | LT' | LTU`;
+
+
+
+
+val _ = Hol_datatype `
+ WordType = B | H | W0 | D`;
+
+
+
+
+val _ = type_abbrev( "CapLen"  , ``: int``);
+
+val _ = type_abbrev( "uint64"  , ``: int``);
+
+val _ = Hol_datatype `
+ CPtrCmpOp = CEQ | CNE | CLT | CLE | CLTU | CLEU | CEXEQ | CNEXEQ`;
+
+
+
+
+val _ = Hol_datatype `
+ ClearRegSet = GPLo | GPHi | CLo | CHi`;
+
+
+
+
+val _ = Hol_datatype `
+ ast  =
+    DADDIU of ((regno # regno # imm16))
+  | DADDU of ((regno # regno # regno))
+  | DADDI of ((regno # regno # 16 bits))
+  | DADD of ((regno # regno # regno))
+  | ADD of ((regno # regno # regno))
+  | ADDI of ((regno # regno # 16 bits))
+  | ADDU of ((regno # regno # regno))
+  | ADDIU of ((regno # regno # 16 bits))
+  | DSUBU of ((regno # regno # regno))
+  | DSUB of ((regno # regno # regno))
+  | SUB0 of ((regno # regno # regno))
+  | SUBU of ((regno # regno # regno))
+  | AND of ((regno # regno # regno))
+  | ANDI of ((regno # regno # 16 bits))
+  | OR of ((regno # regno # regno))
+  | ORI of ((regno # regno # 16 bits))
+  | NOR of ((regno # regno # regno))
+  | XOR of ((regno # regno # regno))
+  | XORI of ((regno # regno # 16 bits))
+  | LUI of ((regno # imm16))
+  | DSLL of ((regno # regno # regno))
+  | DSLL32 of ((regno # regno # regno))
+  | DSLLV of ((regno # regno # regno))
+  | DSRA of ((regno # regno # regno))
+  | DSRA32 of ((regno # regno # regno))
+  | DSRAV of ((regno # regno # regno))
+  | DSRL of ((regno # regno # regno))
+  | DSRL32 of ((regno # regno # regno))
+  | DSRLV of ((regno # regno # regno))
+  | SLL of ((regno # regno # regno))
+  | SLLV of ((regno # regno # regno))
+  | SRA of ((regno # regno # regno))
+  | SRAV of ((regno # regno # regno))
+  | SRL of ((regno # regno # regno))
+  | SRLV of ((regno # regno # regno))
+  | SLT of ((regno # regno # regno))
+  | SLTI of ((regno # regno # 16 bits))
+  | SLTU of ((regno # regno # regno))
+  | SLTIU of ((regno # regno # 16 bits))
+  | MOVN of ((regno # regno # regno))
+  | MOVZ of ((regno # regno # regno))
+  | MFHI of (regno)
+  | MFLO of (regno)
+  | MTHI of (regno)
+  | MTLO of (regno)
+  | MUL of ((regno # regno # regno))
+  | MULT of ((regno # regno))
+  | MULTU of ((regno # regno))
+  | DMULT of ((regno # regno))
+  | DMULTU of ((regno # regno))
+  | MADD of ((regno # regno))
+  | MADDU of ((regno # regno))
+  | MSUB of ((regno # regno))
+  | MSUBU of ((regno # regno))
+  | DIV0 of ((regno # regno))
+  | DIVU of ((regno # regno))
+  | DDIV of ((regno # regno))
+  | DDIVU of ((regno # regno))
+  | J of ( 26 bits)
+  | JAL of ( 26 bits)
+  | JR of (regno)
+  | JALR of ((regno # regno))
+  | BEQ of ((regno # regno # imm16 # bool # bool))
+  | BCMPZ of ((regno # imm16 # Comparison # bool # bool))
+  | SYSCALL_THREAD_START of (unit)
+  | ImplementationDefinedStopFetching of (unit)
+  | SYSCALL of (unit)
+  | BREAK of (unit)
+  | WAIT of (unit)
+  | TRAPREG of ((regno # regno # Comparison))
+  | TRAPIMM of ((regno # imm16 # Comparison))
+  | Load of ((WordType # bool # bool # regno # regno # imm16))
+  | Store of ((WordType # bool # regno # regno # imm16))
+  | LWL of ((regno # regno # 16 bits))
+  | LWR of ((regno # regno # 16 bits))
+  | SWL of ((regno # regno # 16 bits))
+  | SWR of ((regno # regno # 16 bits))
+  | LDL of ((regno # regno # 16 bits))
+  | LDR of ((regno # regno # 16 bits))
+  | SDL of ((regno # regno # 16 bits))
+  | SDR of ((regno # regno # 16 bits))
+  | CACHE of ((regno # regno # 16 bits))
+  | PREF of ((regno # regno # 16 bits))
+  | SYNC of (unit)
+  | MFC0 of ((regno # regno # 3 bits # bool))
+  | HCF of (unit)
+  | MTC0 of ((regno # regno # 3 bits # bool))
+  | TLBWI of (unit)
+  | TLBWR of (unit)
+  | TLBR of (unit)
+  | TLBP of (unit)
+  | RDHWR of ((regno # regno))
+  | ERET of (unit)
+  | CGetPerm of ((regno # regno))
+  | CGetType of ((regno # regno))
+  | CGetBase of ((regno # regno))
+  | CGetLen of ((regno # regno))
+  | CGetTag of ((regno # regno))
+  | CGetSealed of ((regno # regno))
+  | CGetOffset of ((regno # regno))
+  | CGetAddr of ((regno # regno))
+  | CGetPCC of (regno)
+  | CGetPCCSetOffset of ((regno # regno))
+  | CGetCause of (regno)
+  | CSetCause of (regno)
+  | CReadHwr of ((regno # regno))
+  | CWriteHwr of ((regno # regno))
+  | CAndPerm of ((regno # regno # regno))
+  | CToPtr of ((regno # regno # regno))
+  | CSub of ((regno # regno # regno))
+  | CPtrCmp of ((regno # regno # regno # CPtrCmpOp))
+  | CIncOffset of ((regno # regno # regno))
+  | CIncOffsetImmediate of ((regno # regno # 11 bits))
+  | CSetOffset of ((regno # regno # regno))
+  | CSetBounds of ((regno # regno # regno))
+  | CSetBoundsImmediate of ((regno # regno # 11 bits))
+  | CSetBoundsExact of ((regno # regno # regno))
+  | CClearTag of ((regno # regno))
+  | CMOVX of ((regno # regno # regno # bool))
+  | ClearRegs of ((ClearRegSet # 16 bits))
+  | CFromPtr of ((regno # regno # regno))
+  | CBuildCap of ((regno # regno # regno))
+  | CCopyType of ((regno # regno # regno))
+  | CCheckPerm of ((regno # regno))
+  | CCheckType of ((regno # regno))
+  | CTestSubset of ((regno # regno # regno))
+  | CSeal of ((regno # regno # regno))
+  | CCSeal of ((regno # regno # regno))
+  | CUnseal of ((regno # regno # regno))
+  | CCall of ((regno # regno # 11 bits))
+  | CReturn of (unit)
+  | CBX of ((regno # 16 bits # bool))
+  | CBZ of ((regno # 16 bits # bool))
+  | CJALR of ((regno # regno # bool))
+  | CLoad of ((regno # regno # regno # 8 bits # bool # WordType # bool))
+  | CStore of ((regno # regno # regno # regno # 8 bits # WordType # bool))
+  | CSC of ((regno # regno # regno # regno # 11 bits # bool))
+  | CLC of ((regno # regno # regno # 11 bits # bool))
+  | C2Dump of (regno)
+  | RI of (unit)`;
+
+
+
+
+val _ = Hol_datatype `
+ CapEx =
+  CapEx_None
+  | CapEx_LengthViolation
+  | CapEx_TagViolation
+  | CapEx_SealViolation
+  | CapEx_TypeViolation
+  | CapEx_CallTrap
+  | CapEx_ReturnTrap
+  | CapEx_TSSUnderFlow
+  | CapEx_UserDefViolation
+  | CapEx_TLBNoStoreCap
+  | CapEx_InexactBounds
+  | CapEx_GlobalViolation
+  | CapEx_PermitExecuteViolation
+  | CapEx_PermitLoadViolation
+  | CapEx_PermitStoreViolation
+  | CapEx_PermitLoadCapViolation
+  | CapEx_PermitStoreCapViolation
+  | CapEx_PermitStoreLocalCapViolation
+  | CapEx_PermitSealViolation
+  | CapEx_AccessSystemRegsViolation
+  | CapEx_PermitCCallViolation
+  | CapEx_AccessCCallIDCViolation
+  | CapEx_PermitUnsealViolation`;
+
+
+
+
+val _ = Hol_datatype `
+ register_value  =
+    Regval_vector of ((sail_values$ii # bool # register_value list))
+  | Regval_list of ( register_value list)
+  | Regval_option of ( register_value option)
+  | Regval_CapCauseReg of (CapCauseReg)
+  | Regval_CauseReg of (CauseReg)
+  | Regval_ContextReg of (ContextReg)
+  | Regval_StatusReg of (StatusReg)
+  | Regval_TLBEntry of (TLBEntry)
+  | Regval_TLBEntryHiReg of (TLBEntryHiReg)
+  | Regval_TLBEntryLoReg of (TLBEntryLoReg)
+  | Regval_XContextReg of (XContextReg)
+  | Regval_vector_16_dec_bit of ( 16 words$word)
+  | Regval_vector_1_dec_bit of ( 1 words$word)
+  | Regval_vector_257_dec_bit of ( 257 words$word)
+  | Regval_vector_32_dec_bit of ( 32 words$word)
+  | Regval_vector_64_dec_bit of ( 64 words$word)
+  | Regval_vector_6_dec_bit of ( 6 words$word)
+  | Regval_vector_8_dec_bit of ( 8 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate  =
+  <| CapCause : CapCauseReg;
+     CTLSP :  257 words$word;
+     CTLSU :  257 words$word;
+     C31 :  257 words$word;
+     C30 :  257 words$word;
+     C29 :  257 words$word;
+     C28 :  257 words$word;
+     C27 :  257 words$word;
+     C26 :  257 words$word;
+     C25 :  257 words$word;
+     C24 :  257 words$word;
+     C23 :  257 words$word;
+     C22 :  257 words$word;
+     C21 :  257 words$word;
+     C20 :  257 words$word;
+     C19 :  257 words$word;
+     C18 :  257 words$word;
+     C17 :  257 words$word;
+     C16 :  257 words$word;
+     C15 :  257 words$word;
+     C14 :  257 words$word;
+     C13 :  257 words$word;
+     C12 :  257 words$word;
+     C11 :  257 words$word;
+     C10 :  257 words$word;
+     C09 :  257 words$word;
+     C08 :  257 words$word;
+     C07 :  257 words$word;
+     C06 :  257 words$word;
+     C05 :  257 words$word;
+     C04 :  257 words$word;
+     C03 :  257 words$word;
+     C02 :  257 words$word;
+     C01 :  257 words$word;
+     C00 :  257 words$word;
+     inCCallDelay :  1 words$word;
+     delayedPCC :  257 words$word;
+     nextPCC :  257 words$word;
+     PCC :  257 words$word;
+     UART_RVALID :  1 words$word;
+     UART_RDATA :  8 words$word;
+     UART_WRITTEN :  1 words$word;
+     UART_WDATA :  8 words$word;
+     GPR : ( 64 words$word) list;
+     LO :  64 words$word;
+     HI :  64 words$word;
+     delayedPC :  64 words$word;
+     inBranchDelay :  1 words$word;
+     branchPending :  1 words$word;
+     CP0Status : StatusReg;
+     CP0UserLocal :  64 words$word;
+     CP0HWREna :  32 words$word;
+     CP0Count :  32 words$word;
+     CP0BadVAddr :  64 words$word;
+     CP0LLAddr :  64 words$word;
+     CP0LLBit :  1 words$word;
+     CP0ErrorEPC :  64 words$word;
+     CP0EPC :  64 words$word;
+     CP0Cause : CauseReg;
+     CP0Compare :  32 words$word;
+     TLBEntry63 : TLBEntry;
+     TLBEntry62 : TLBEntry;
+     TLBEntry61 : TLBEntry;
+     TLBEntry60 : TLBEntry;
+     TLBEntry59 : TLBEntry;
+     TLBEntry58 : TLBEntry;
+     TLBEntry57 : TLBEntry;
+     TLBEntry56 : TLBEntry;
+     TLBEntry55 : TLBEntry;
+     TLBEntry54 : TLBEntry;
+     TLBEntry53 : TLBEntry;
+     TLBEntry52 : TLBEntry;
+     TLBEntry51 : TLBEntry;
+     TLBEntry50 : TLBEntry;
+     TLBEntry49 : TLBEntry;
+     TLBEntry48 : TLBEntry;
+     TLBEntry47 : TLBEntry;
+     TLBEntry46 : TLBEntry;
+     TLBEntry45 : TLBEntry;
+     TLBEntry44 : TLBEntry;
+     TLBEntry43 : TLBEntry;
+     TLBEntry42 : TLBEntry;
+     TLBEntry41 : TLBEntry;
+     TLBEntry40 : TLBEntry;
+     TLBEntry39 : TLBEntry;
+     TLBEntry38 : TLBEntry;
+     TLBEntry37 : TLBEntry;
+     TLBEntry36 : TLBEntry;
+     TLBEntry35 : TLBEntry;
+     TLBEntry34 : TLBEntry;
+     TLBEntry33 : TLBEntry;
+     TLBEntry32 : TLBEntry;
+     TLBEntry31 : TLBEntry;
+     TLBEntry30 : TLBEntry;
+     TLBEntry29 : TLBEntry;
+     TLBEntry28 : TLBEntry;
+     TLBEntry27 : TLBEntry;
+     TLBEntry26 : TLBEntry;
+     TLBEntry25 : TLBEntry;
+     TLBEntry24 : TLBEntry;
+     TLBEntry23 : TLBEntry;
+     TLBEntry22 : TLBEntry;
+     TLBEntry21 : TLBEntry;
+     TLBEntry20 : TLBEntry;
+     TLBEntry19 : TLBEntry;
+     TLBEntry18 : TLBEntry;
+     TLBEntry17 : TLBEntry;
+     TLBEntry16 : TLBEntry;
+     TLBEntry15 : TLBEntry;
+     TLBEntry14 : TLBEntry;
+     TLBEntry13 : TLBEntry;
+     TLBEntry12 : TLBEntry;
+     TLBEntry11 : TLBEntry;
+     TLBEntry10 : TLBEntry;
+     TLBEntry09 : TLBEntry;
+     TLBEntry08 : TLBEntry;
+     TLBEntry07 : TLBEntry;
+     TLBEntry06 : TLBEntry;
+     TLBEntry05 : TLBEntry;
+     TLBEntry04 : TLBEntry;
+     TLBEntry03 : TLBEntry;
+     TLBEntry02 : TLBEntry;
+     TLBEntry01 : TLBEntry;
+     TLBEntry00 : TLBEntry;
+     TLBXContext : XContextReg;
+     TLBEntryHi : TLBEntryHiReg;
+     TLBWired :  6 words$word;
+     TLBPageMask :  16 words$word;
+     TLBContext : ContextReg;
+     TLBEntryLo1 : TLBEntryLoReg;
+     TLBEntryLo0 : TLBEntryLoReg;
+     TLBRandom :  6 words$word;
+     TLBIndex :  6 words$word;
+     TLBProbe :  1 words$word;
+     nextPC :  64 words$word;
+     PC :  64 words$word  |>`;
+
+
+
+
+
+(*val CapCauseReg_of_regval : register_value -> Maybe.maybe CapCauseReg*)
+
+val _ = Define `
+ ((CapCauseReg_of_regval:register_value ->(CapCauseReg)option) merge_var=   
+ ((case merge_var of   Regval_CapCauseReg (v) => SOME v | g__113 => NONE )))`;
+
+
+(*val regval_of_CapCauseReg : CapCauseReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_CapCauseReg:CapCauseReg -> register_value) v=  (Regval_CapCauseReg v))`;
+
+
+(*val CauseReg_of_regval : register_value -> Maybe.maybe CauseReg*)
+
+val _ = Define `
+ ((CauseReg_of_regval:register_value ->(CauseReg)option) merge_var=   
+ ((case merge_var of   Regval_CauseReg (v) => SOME v | g__112 => NONE )))`;
+
+
+(*val regval_of_CauseReg : CauseReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_CauseReg:CauseReg -> register_value) v=  (Regval_CauseReg v))`;
+
+
+(*val ContextReg_of_regval : register_value -> Maybe.maybe ContextReg*)
+
+val _ = Define `
+ ((ContextReg_of_regval:register_value ->(ContextReg)option) merge_var=   
+ ((case merge_var of   Regval_ContextReg (v) => SOME v | g__111 => NONE )))`;
+
+
+(*val regval_of_ContextReg : ContextReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_ContextReg:ContextReg -> register_value) v=  (Regval_ContextReg v))`;
+
+
+(*val StatusReg_of_regval : register_value -> Maybe.maybe StatusReg*)
+
+val _ = Define `
+ ((StatusReg_of_regval:register_value ->(StatusReg)option) merge_var=   
+ ((case merge_var of   Regval_StatusReg (v) => SOME v | g__110 => NONE )))`;
+
+
+(*val regval_of_StatusReg : StatusReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_StatusReg:StatusReg -> register_value) v=  (Regval_StatusReg v))`;
+
+
+(*val TLBEntry_of_regval : register_value -> Maybe.maybe TLBEntry*)
+
+val _ = Define `
+ ((TLBEntry_of_regval:register_value ->(TLBEntry)option) merge_var=   
+ ((case merge_var of   Regval_TLBEntry (v) => SOME v | g__109 => NONE )))`;
+
+
+(*val regval_of_TLBEntry : TLBEntry -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntry:TLBEntry -> register_value) v=  (Regval_TLBEntry v))`;
+
+
+(*val TLBEntryHiReg_of_regval : register_value -> Maybe.maybe TLBEntryHiReg*)
+
+val _ = Define `
+ ((TLBEntryHiReg_of_regval:register_value ->(TLBEntryHiReg)option) merge_var=   
+ ((case merge_var of   Regval_TLBEntryHiReg (v) => SOME v | g__108 => NONE )))`;
+
+
+(*val regval_of_TLBEntryHiReg : TLBEntryHiReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntryHiReg:TLBEntryHiReg -> register_value) v=  (Regval_TLBEntryHiReg v))`;
+
+
+(*val TLBEntryLoReg_of_regval : register_value -> Maybe.maybe TLBEntryLoReg*)
+
+val _ = Define `
+ ((TLBEntryLoReg_of_regval:register_value ->(TLBEntryLoReg)option) merge_var=   
+ ((case merge_var of   Regval_TLBEntryLoReg (v) => SOME v | g__107 => NONE )))`;
+
+
+(*val regval_of_TLBEntryLoReg : TLBEntryLoReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLBEntryLoReg:TLBEntryLoReg -> register_value) v=  (Regval_TLBEntryLoReg v))`;
+
+
+(*val XContextReg_of_regval : register_value -> Maybe.maybe XContextReg*)
+
+val _ = Define `
+ ((XContextReg_of_regval:register_value ->(XContextReg)option) merge_var=   
+ ((case merge_var of   Regval_XContextReg (v) => SOME v | g__106 => NONE )))`;
+
+
+(*val regval_of_XContextReg : XContextReg -> register_value*)
+
+val _ = Define `
+ ((regval_of_XContextReg:XContextReg -> register_value) v=  (Regval_XContextReg v))`;
+
+
+(*val vector_16_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty16)*)
+
+val _ = Define `
+ ((vector_16_dec_bit_of_regval:register_value ->((16)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_16_dec_bit (v) => SOME v | g__105 => NONE )))`;
+
+
+(*val regval_of_vector_16_dec_bit : Machine_word.mword Machine_word.ty16 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_16_dec_bit:(16)words$word -> register_value) v=  (Regval_vector_16_dec_bit v))`;
+
+
+(*val vector_1_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty1)*)
+
+val _ = Define `
+ ((vector_1_dec_bit_of_regval:register_value ->((1)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_1_dec_bit (v) => SOME v | g__104 => NONE )))`;
+
+
+(*val regval_of_vector_1_dec_bit : Machine_word.mword Machine_word.ty1 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_1_dec_bit:(1)words$word -> register_value) v=  (Regval_vector_1_dec_bit v))`;
+
+
+(*val vector_257_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty257)*)
+
+val _ = Define `
+ ((vector_257_dec_bit_of_regval:register_value ->((257)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_257_dec_bit (v) => SOME v | g__103 => NONE )))`;
+
+
+(*val regval_of_vector_257_dec_bit : Machine_word.mword Machine_word.ty257 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_257_dec_bit:(257)words$word -> register_value) v=  (Regval_vector_257_dec_bit v))`;
+
+
+(*val vector_32_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty32)*)
+
+val _ = Define `
+ ((vector_32_dec_bit_of_regval:register_value ->((32)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_32_dec_bit (v) => SOME v | g__102 => NONE )))`;
+
+
+(*val regval_of_vector_32_dec_bit : Machine_word.mword Machine_word.ty32 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_32_dec_bit:(32)words$word -> register_value) v=  (Regval_vector_32_dec_bit v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__101 => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v=  (Regval_vector_64_dec_bit v))`;
+
+
+(*val vector_6_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty6)*)
+
+val _ = Define `
+ ((vector_6_dec_bit_of_regval:register_value ->((6)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_6_dec_bit (v) => SOME v | g__100 => NONE )))`;
+
+
+(*val regval_of_vector_6_dec_bit : Machine_word.mword Machine_word.ty6 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_6_dec_bit:(6)words$word -> register_value) v=  (Regval_vector_6_dec_bit v))`;
+
+
+(*val vector_8_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty8)*)
+
+val _ = Define `
+ ((vector_8_dec_bit_of_regval:register_value ->((8)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_8_dec_bit (v) => SOME v | g__99 => NONE )))`;
+
+
+(*val regval_of_vector_8_dec_bit : Machine_word.mword Machine_word.ty8 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_8_dec_bit:(8)words$word -> register_value) v=  (Regval_vector_8_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+  (\x .  (case x of
+               Regval_vector (_, _, v) => just_list (MAP of_regval v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+  (\x .  (case x of
+               Regval_list v => just_list (MAP of_regval v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs=  (Regval_list (MAP regval_of xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= 
+  (\x .  (case x of   Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v=  (Regval_option (OPTION_MAP regval_of v)))`;
+
+
+
+val _ = Define `
+ ((CapCause_ref:((regstate),(register_value),(CapCauseReg))sail_values$register_ref)=  (<|
+  name := "CapCause";
+  read_from := (\ s .  s.CapCause);
+  write_to := (\ v s .  (( s with<| CapCause := v |>)));
+  of_regval := (\ v .  CapCauseReg_of_regval v);
+  regval_of := (\ v .  regval_of_CapCauseReg v) |>))`;
+
+
+val _ = Define `
+ ((CTLSP_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "CTLSP";
+  read_from := (\ s .  s.CTLSP);
+  write_to := (\ v s .  (( s with<| CTLSP := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CTLSU_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "CTLSU";
+  read_from := (\ s .  s.CTLSU);
+  write_to := (\ v s .  (( s with<| CTLSU := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C30_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C30";
+  read_from := (\ s .  s.C30);
+  write_to := (\ v s .  (( s with<| C30 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C28_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C28";
+  read_from := (\ s .  s.C28);
+  write_to := (\ v s .  (( s with<| C28 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C27_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C27";
+  read_from := (\ s .  s.C27);
+  write_to := (\ v s .  (( s with<| C27 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C26_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C26";
+  read_from := (\ s .  s.C26);
+  write_to := (\ v s .  (( s with<| C26 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C25_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C25";
+  read_from := (\ s .  s.C25);
+  write_to := (\ v s .  (( s with<| C25 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C24_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C24";
+  read_from := (\ s .  s.C24);
+  write_to := (\ v s .  (( s with<| C24 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C23_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C23";
+  read_from := (\ s .  s.C23);
+  write_to := (\ v s .  (( s with<| C23 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C22_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C22";
+  read_from := (\ s .  s.C22);
+  write_to := (\ v s .  (( s with<| C22 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C21_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C21";
+  read_from := (\ s .  s.C21);
+  write_to := (\ v s .  (( s with<| C21 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C20_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C20";
+  read_from := (\ s .  s.C20);
+  write_to := (\ v s .  (( s with<| C20 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C19_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C19";
+  read_from := (\ s .  s.C19);
+  write_to := (\ v s .  (( s with<| C19 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C18_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C18";
+  read_from := (\ s .  s.C18);
+  write_to := (\ v s .  (( s with<| C18 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C17_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C17";
+  read_from := (\ s .  s.C17);
+  write_to := (\ v s .  (( s with<| C17 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C16_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C16";
+  read_from := (\ s .  s.C16);
+  write_to := (\ v s .  (( s with<| C16 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C15_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C15";
+  read_from := (\ s .  s.C15);
+  write_to := (\ v s .  (( s with<| C15 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C14_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C14";
+  read_from := (\ s .  s.C14);
+  write_to := (\ v s .  (( s with<| C14 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C13_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C13";
+  read_from := (\ s .  s.C13);
+  write_to := (\ v s .  (( s with<| C13 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C12_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C12";
+  read_from := (\ s .  s.C12);
+  write_to := (\ v s .  (( s with<| C12 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C11_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C11";
+  read_from := (\ s .  s.C11);
+  write_to := (\ v s .  (( s with<| C11 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C10_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C10";
+  read_from := (\ s .  s.C10);
+  write_to := (\ v s .  (( s with<| C10 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C09_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C09";
+  read_from := (\ s .  s.C09);
+  write_to := (\ v s .  (( s with<| C09 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C08_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C08";
+  read_from := (\ s .  s.C08);
+  write_to := (\ v s .  (( s with<| C08 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C07_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C07";
+  read_from := (\ s .  s.C07);
+  write_to := (\ v s .  (( s with<| C07 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C06_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C06";
+  read_from := (\ s .  s.C06);
+  write_to := (\ v s .  (( s with<| C06 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C05_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C05";
+  read_from := (\ s .  s.C05);
+  write_to := (\ v s .  (( s with<| C05 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C04_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C04";
+  read_from := (\ s .  s.C04);
+  write_to := (\ v s .  (( s with<| C04 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C03_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C03";
+  read_from := (\ s .  s.C03);
+  write_to := (\ v s .  (( s with<| C03 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C02_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C02";
+  read_from := (\ s .  s.C02);
+  write_to := (\ v s .  (( s with<| C02 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C01_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C01";
+  read_from := (\ s .  s.C01);
+  write_to := (\ v s .  (( s with<| C01 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C00_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C00";
+  read_from := (\ s .  s.C00);
+  write_to := (\ v s .  (( s with<| C00 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((inCCallDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "inCCallDelay";
+  read_from := (\ s .  s.inCCallDelay);
+  write_to := (\ v s .  (( s with<| inCCallDelay := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((nextPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "nextPCC";
+  read_from := (\ s .  s.nextPCC);
+  write_to := (\ v s .  (( s with<| nextPCC := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((delayedPCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "delayedPCC";
+  read_from := (\ s .  s.delayedPCC);
+  write_to := (\ v s .  (( s with<| delayedPCC := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PCC_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "PCC";
+  read_from := (\ s .  s.PCC);
+  write_to := (\ v s .  (( s with<| PCC := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C31_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C31";
+  read_from := (\ s .  s.C31);
+  write_to := (\ v s .  (( s with<| C31 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((C29_ref:((regstate),(register_value),((257)words$word))sail_values$register_ref)=  (<|
+  name := "C29";
+  read_from := (\ s .  s.C29);
+  write_to := (\ v s .  (( s with<| C29 := v |>)));
+  of_regval := (\ v .  vector_257_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_257_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_RVALID_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "UART_RVALID";
+  read_from := (\ s .  s.UART_RVALID);
+  write_to := (\ v s .  (( s with<| UART_RVALID := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_RDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)=  (<|
+  name := "UART_RDATA";
+  read_from := (\ s .  s.UART_RDATA);
+  write_to := (\ v s .  (( s with<| UART_RDATA := v |>)));
+  of_regval := (\ v .  vector_8_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_8_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_WRITTEN_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "UART_WRITTEN";
+  read_from := (\ s .  s.UART_WRITTEN);
+  write_to := (\ v s .  (( s with<| UART_WRITTEN := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((UART_WDATA_ref:((regstate),(register_value),((8)words$word))sail_values$register_ref)=  (<|
+  name := "UART_WDATA";
+  read_from := (\ s .  s.UART_WDATA);
+  write_to := (\ v s .  (( s with<| UART_WDATA := v |>)));
+  of_regval := (\ v .  vector_8_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_8_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((GPR_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)=  (<|
+  name := "GPR";
+  read_from := (\ s .  s.GPR);
+  write_to := (\ v s .  (( s with<| GPR := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((LO_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "LO";
+  read_from := (\ s .  s.LO);
+  write_to := (\ v s .  (( s with<| LO := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((HI_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "HI";
+  read_from := (\ s .  s.HI);
+  write_to := (\ v s .  (( s with<| HI := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((delayedPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "delayedPC";
+  read_from := (\ s .  s.delayedPC);
+  write_to := (\ v s .  (( s with<| delayedPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((inBranchDelay_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "inBranchDelay";
+  read_from := (\ s .  s.inBranchDelay);
+  write_to := (\ v s .  (( s with<| inBranchDelay := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((branchPending_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "branchPending";
+  read_from := (\ s .  s.branchPending);
+  write_to := (\ v s .  (( s with<| branchPending := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Status_ref:((regstate),(register_value),(StatusReg))sail_values$register_ref)=  (<|
+  name := "CP0Status";
+  read_from := (\ s .  s.CP0Status);
+  write_to := (\ v s .  (( s with<| CP0Status := v |>)));
+  of_regval := (\ v .  StatusReg_of_regval v);
+  regval_of := (\ v .  regval_of_StatusReg v) |>))`;
+
+
+val _ = Define `
+ ((CP0UserLocal_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "CP0UserLocal";
+  read_from := (\ s .  s.CP0UserLocal);
+  write_to := (\ v s .  (( s with<| CP0UserLocal := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0HWREna_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)=  (<|
+  name := "CP0HWREna";
+  read_from := (\ s .  s.CP0HWREna);
+  write_to := (\ v s .  (( s with<| CP0HWREna := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Count_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)=  (<|
+  name := "CP0Count";
+  read_from := (\ s .  s.CP0Count);
+  write_to := (\ v s .  (( s with<| CP0Count := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0BadVAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "CP0BadVAddr";
+  read_from := (\ s .  s.CP0BadVAddr);
+  write_to := (\ v s .  (( s with<| CP0BadVAddr := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0LLAddr_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "CP0LLAddr";
+  read_from := (\ s .  s.CP0LLAddr);
+  write_to := (\ v s .  (( s with<| CP0LLAddr := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0LLBit_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "CP0LLBit";
+  read_from := (\ s .  s.CP0LLBit);
+  write_to := (\ v s .  (( s with<| CP0LLBit := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0ErrorEPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "CP0ErrorEPC";
+  read_from := (\ s .  s.CP0ErrorEPC);
+  write_to := (\ v s .  (( s with<| CP0ErrorEPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0EPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "CP0EPC";
+  read_from := (\ s .  s.CP0EPC);
+  write_to := (\ v s .  (( s with<| CP0EPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((CP0Cause_ref:((regstate),(register_value),(CauseReg))sail_values$register_ref)=  (<|
+  name := "CP0Cause";
+  read_from := (\ s .  s.CP0Cause);
+  write_to := (\ v s .  (( s with<| CP0Cause := v |>)));
+  of_regval := (\ v .  CauseReg_of_regval v);
+  regval_of := (\ v .  regval_of_CauseReg v) |>))`;
+
+
+val _ = Define `
+ ((CP0Compare_ref:((regstate),(register_value),((32)words$word))sail_values$register_ref)=  (<|
+  name := "CP0Compare";
+  read_from := (\ s .  s.CP0Compare);
+  write_to := (\ v s .  (( s with<| CP0Compare := v |>)));
+  of_regval := (\ v .  vector_32_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_32_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry63_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry63";
+  read_from := (\ s .  s.TLBEntry63);
+  write_to := (\ v s .  (( s with<| TLBEntry63 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry62_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry62";
+  read_from := (\ s .  s.TLBEntry62);
+  write_to := (\ v s .  (( s with<| TLBEntry62 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry61_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry61";
+  read_from := (\ s .  s.TLBEntry61);
+  write_to := (\ v s .  (( s with<| TLBEntry61 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry60_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry60";
+  read_from := (\ s .  s.TLBEntry60);
+  write_to := (\ v s .  (( s with<| TLBEntry60 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry59_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry59";
+  read_from := (\ s .  s.TLBEntry59);
+  write_to := (\ v s .  (( s with<| TLBEntry59 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry58_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry58";
+  read_from := (\ s .  s.TLBEntry58);
+  write_to := (\ v s .  (( s with<| TLBEntry58 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry57_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry57";
+  read_from := (\ s .  s.TLBEntry57);
+  write_to := (\ v s .  (( s with<| TLBEntry57 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry56_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry56";
+  read_from := (\ s .  s.TLBEntry56);
+  write_to := (\ v s .  (( s with<| TLBEntry56 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry55_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry55";
+  read_from := (\ s .  s.TLBEntry55);
+  write_to := (\ v s .  (( s with<| TLBEntry55 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry54_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry54";
+  read_from := (\ s .  s.TLBEntry54);
+  write_to := (\ v s .  (( s with<| TLBEntry54 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry53_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry53";
+  read_from := (\ s .  s.TLBEntry53);
+  write_to := (\ v s .  (( s with<| TLBEntry53 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry52_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry52";
+  read_from := (\ s .  s.TLBEntry52);
+  write_to := (\ v s .  (( s with<| TLBEntry52 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry51_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry51";
+  read_from := (\ s .  s.TLBEntry51);
+  write_to := (\ v s .  (( s with<| TLBEntry51 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry50_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry50";
+  read_from := (\ s .  s.TLBEntry50);
+  write_to := (\ v s .  (( s with<| TLBEntry50 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry49_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry49";
+  read_from := (\ s .  s.TLBEntry49);
+  write_to := (\ v s .  (( s with<| TLBEntry49 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry48_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry48";
+  read_from := (\ s .  s.TLBEntry48);
+  write_to := (\ v s .  (( s with<| TLBEntry48 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry47_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry47";
+  read_from := (\ s .  s.TLBEntry47);
+  write_to := (\ v s .  (( s with<| TLBEntry47 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry46_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry46";
+  read_from := (\ s .  s.TLBEntry46);
+  write_to := (\ v s .  (( s with<| TLBEntry46 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry45_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry45";
+  read_from := (\ s .  s.TLBEntry45);
+  write_to := (\ v s .  (( s with<| TLBEntry45 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry44_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry44";
+  read_from := (\ s .  s.TLBEntry44);
+  write_to := (\ v s .  (( s with<| TLBEntry44 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry43_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry43";
+  read_from := (\ s .  s.TLBEntry43);
+  write_to := (\ v s .  (( s with<| TLBEntry43 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry42_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry42";
+  read_from := (\ s .  s.TLBEntry42);
+  write_to := (\ v s .  (( s with<| TLBEntry42 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry41_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry41";
+  read_from := (\ s .  s.TLBEntry41);
+  write_to := (\ v s .  (( s with<| TLBEntry41 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry40_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry40";
+  read_from := (\ s .  s.TLBEntry40);
+  write_to := (\ v s .  (( s with<| TLBEntry40 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry39_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry39";
+  read_from := (\ s .  s.TLBEntry39);
+  write_to := (\ v s .  (( s with<| TLBEntry39 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry38_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry38";
+  read_from := (\ s .  s.TLBEntry38);
+  write_to := (\ v s .  (( s with<| TLBEntry38 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry37_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry37";
+  read_from := (\ s .  s.TLBEntry37);
+  write_to := (\ v s .  (( s with<| TLBEntry37 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry36_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry36";
+  read_from := (\ s .  s.TLBEntry36);
+  write_to := (\ v s .  (( s with<| TLBEntry36 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry35_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry35";
+  read_from := (\ s .  s.TLBEntry35);
+  write_to := (\ v s .  (( s with<| TLBEntry35 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry34_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry34";
+  read_from := (\ s .  s.TLBEntry34);
+  write_to := (\ v s .  (( s with<| TLBEntry34 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry33_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry33";
+  read_from := (\ s .  s.TLBEntry33);
+  write_to := (\ v s .  (( s with<| TLBEntry33 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry32_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry32";
+  read_from := (\ s .  s.TLBEntry32);
+  write_to := (\ v s .  (( s with<| TLBEntry32 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry31_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry31";
+  read_from := (\ s .  s.TLBEntry31);
+  write_to := (\ v s .  (( s with<| TLBEntry31 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry30_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry30";
+  read_from := (\ s .  s.TLBEntry30);
+  write_to := (\ v s .  (( s with<| TLBEntry30 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry29_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry29";
+  read_from := (\ s .  s.TLBEntry29);
+  write_to := (\ v s .  (( s with<| TLBEntry29 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry28_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry28";
+  read_from := (\ s .  s.TLBEntry28);
+  write_to := (\ v s .  (( s with<| TLBEntry28 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry27_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry27";
+  read_from := (\ s .  s.TLBEntry27);
+  write_to := (\ v s .  (( s with<| TLBEntry27 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry26_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry26";
+  read_from := (\ s .  s.TLBEntry26);
+  write_to := (\ v s .  (( s with<| TLBEntry26 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry25_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry25";
+  read_from := (\ s .  s.TLBEntry25);
+  write_to := (\ v s .  (( s with<| TLBEntry25 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry24_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry24";
+  read_from := (\ s .  s.TLBEntry24);
+  write_to := (\ v s .  (( s with<| TLBEntry24 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry23_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry23";
+  read_from := (\ s .  s.TLBEntry23);
+  write_to := (\ v s .  (( s with<| TLBEntry23 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry22_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry22";
+  read_from := (\ s .  s.TLBEntry22);
+  write_to := (\ v s .  (( s with<| TLBEntry22 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry21_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry21";
+  read_from := (\ s .  s.TLBEntry21);
+  write_to := (\ v s .  (( s with<| TLBEntry21 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry20_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry20";
+  read_from := (\ s .  s.TLBEntry20);
+  write_to := (\ v s .  (( s with<| TLBEntry20 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry19_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry19";
+  read_from := (\ s .  s.TLBEntry19);
+  write_to := (\ v s .  (( s with<| TLBEntry19 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry18_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry18";
+  read_from := (\ s .  s.TLBEntry18);
+  write_to := (\ v s .  (( s with<| TLBEntry18 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry17_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry17";
+  read_from := (\ s .  s.TLBEntry17);
+  write_to := (\ v s .  (( s with<| TLBEntry17 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry16_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry16";
+  read_from := (\ s .  s.TLBEntry16);
+  write_to := (\ v s .  (( s with<| TLBEntry16 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry15_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry15";
+  read_from := (\ s .  s.TLBEntry15);
+  write_to := (\ v s .  (( s with<| TLBEntry15 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry14_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry14";
+  read_from := (\ s .  s.TLBEntry14);
+  write_to := (\ v s .  (( s with<| TLBEntry14 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry13_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry13";
+  read_from := (\ s .  s.TLBEntry13);
+  write_to := (\ v s .  (( s with<| TLBEntry13 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry12_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry12";
+  read_from := (\ s .  s.TLBEntry12);
+  write_to := (\ v s .  (( s with<| TLBEntry12 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry11_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry11";
+  read_from := (\ s .  s.TLBEntry11);
+  write_to := (\ v s .  (( s with<| TLBEntry11 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry10_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry10";
+  read_from := (\ s .  s.TLBEntry10);
+  write_to := (\ v s .  (( s with<| TLBEntry10 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry09_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry09";
+  read_from := (\ s .  s.TLBEntry09);
+  write_to := (\ v s .  (( s with<| TLBEntry09 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry08_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry08";
+  read_from := (\ s .  s.TLBEntry08);
+  write_to := (\ v s .  (( s with<| TLBEntry08 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry07_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry07";
+  read_from := (\ s .  s.TLBEntry07);
+  write_to := (\ v s .  (( s with<| TLBEntry07 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry06_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry06";
+  read_from := (\ s .  s.TLBEntry06);
+  write_to := (\ v s .  (( s with<| TLBEntry06 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry05_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry05";
+  read_from := (\ s .  s.TLBEntry05);
+  write_to := (\ v s .  (( s with<| TLBEntry05 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry04_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry04";
+  read_from := (\ s .  s.TLBEntry04);
+  write_to := (\ v s .  (( s with<| TLBEntry04 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry03_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry03";
+  read_from := (\ s .  s.TLBEntry03);
+  write_to := (\ v s .  (( s with<| TLBEntry03 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry02_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry02";
+  read_from := (\ s .  s.TLBEntry02);
+  write_to := (\ v s .  (( s with<| TLBEntry02 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry01_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry01";
+  read_from := (\ s .  s.TLBEntry01);
+  write_to := (\ v s .  (( s with<| TLBEntry01 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntry00_ref:((regstate),(register_value),(TLBEntry))sail_values$register_ref)=  (<|
+  name := "TLBEntry00";
+  read_from := (\ s .  s.TLBEntry00);
+  write_to := (\ v s .  (( s with<| TLBEntry00 := v |>)));
+  of_regval := (\ v .  TLBEntry_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntry v) |>))`;
+
+
+val _ = Define `
+ ((TLBXContext_ref:((regstate),(register_value),(XContextReg))sail_values$register_ref)=  (<|
+  name := "TLBXContext";
+  read_from := (\ s .  s.TLBXContext);
+  write_to := (\ v s .  (( s with<| TLBXContext := v |>)));
+  of_regval := (\ v .  XContextReg_of_regval v);
+  regval_of := (\ v .  regval_of_XContextReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryHi_ref:((regstate),(register_value),(TLBEntryHiReg))sail_values$register_ref)=  (<|
+  name := "TLBEntryHi";
+  read_from := (\ s .  s.TLBEntryHi);
+  write_to := (\ v s .  (( s with<| TLBEntryHi := v |>)));
+  of_regval := (\ v .  TLBEntryHiReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryHiReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBWired_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)=  (<|
+  name := "TLBWired";
+  read_from := (\ s .  s.TLBWired);
+  write_to := (\ v s .  (( s with<| TLBWired := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBPageMask_ref:((regstate),(register_value),((16)words$word))sail_values$register_ref)=  (<|
+  name := "TLBPageMask";
+  read_from := (\ s .  s.TLBPageMask);
+  write_to := (\ v s .  (( s with<| TLBPageMask := v |>)));
+  of_regval := (\ v .  vector_16_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_16_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBContext_ref:((regstate),(register_value),(ContextReg))sail_values$register_ref)=  (<|
+  name := "TLBContext";
+  read_from := (\ s .  s.TLBContext);
+  write_to := (\ v s .  (( s with<| TLBContext := v |>)));
+  of_regval := (\ v .  ContextReg_of_regval v);
+  regval_of := (\ v .  regval_of_ContextReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryLo1_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)=  (<|
+  name := "TLBEntryLo1";
+  read_from := (\ s .  s.TLBEntryLo1);
+  write_to := (\ v s .  (( s with<| TLBEntryLo1 := v |>)));
+  of_regval := (\ v .  TLBEntryLoReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryLoReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBEntryLo0_ref:((regstate),(register_value),(TLBEntryLoReg))sail_values$register_ref)=  (<|
+  name := "TLBEntryLo0";
+  read_from := (\ s .  s.TLBEntryLo0);
+  write_to := (\ v s .  (( s with<| TLBEntryLo0 := v |>)));
+  of_regval := (\ v .  TLBEntryLoReg_of_regval v);
+  regval_of := (\ v .  regval_of_TLBEntryLoReg v) |>))`;
+
+
+val _ = Define `
+ ((TLBRandom_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)=  (<|
+  name := "TLBRandom";
+  read_from := (\ s .  s.TLBRandom);
+  write_to := (\ v s .  (( s with<| TLBRandom := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBIndex_ref:((regstate),(register_value),((6)words$word))sail_values$register_ref)=  (<|
+  name := "TLBIndex";
+  read_from := (\ s .  s.TLBIndex);
+  write_to := (\ v s .  (( s with<| TLBIndex := v |>)));
+  of_regval := (\ v .  vector_6_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_6_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((TLBProbe_ref:((regstate),(register_value),((1)words$word))sail_values$register_ref)=  (<|
+  name := "TLBProbe";
+  read_from := (\ s .  s.TLBProbe);
+  write_to := (\ v s .  (( s with<| TLBProbe := v |>)));
+  of_regval := (\ v .  vector_1_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_1_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "nextPC";
+  read_from := (\ s .  s.nextPC);
+  write_to := (\ v s .  (( s with<| nextPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "PC";
+  read_from := (\ s .  s.PC);
+  write_to := (\ v s .  (( s with<| PC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+(*val get_regval : string -> regstate -> Maybe.maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=  
+ (if reg_name = "CapCause" then SOME (CapCause_ref.regval_of (CapCause_ref.read_from s)) else
+  if reg_name = "CTLSP" then SOME (CTLSP_ref.regval_of (CTLSP_ref.read_from s)) else
+  if reg_name = "CTLSU" then SOME (CTLSU_ref.regval_of (CTLSU_ref.read_from s)) else
+  if reg_name = "C30" then SOME (C30_ref.regval_of (C30_ref.read_from s)) else
+  if reg_name = "C28" then SOME (C28_ref.regval_of (C28_ref.read_from s)) else
+  if reg_name = "C27" then SOME (C27_ref.regval_of (C27_ref.read_from s)) else
+  if reg_name = "C26" then SOME (C26_ref.regval_of (C26_ref.read_from s)) else
+  if reg_name = "C25" then SOME (C25_ref.regval_of (C25_ref.read_from s)) else
+  if reg_name = "C24" then SOME (C24_ref.regval_of (C24_ref.read_from s)) else
+  if reg_name = "C23" then SOME (C23_ref.regval_of (C23_ref.read_from s)) else
+  if reg_name = "C22" then SOME (C22_ref.regval_of (C22_ref.read_from s)) else
+  if reg_name = "C21" then SOME (C21_ref.regval_of (C21_ref.read_from s)) else
+  if reg_name = "C20" then SOME (C20_ref.regval_of (C20_ref.read_from s)) else
+  if reg_name = "C19" then SOME (C19_ref.regval_of (C19_ref.read_from s)) else
+  if reg_name = "C18" then SOME (C18_ref.regval_of (C18_ref.read_from s)) else
+  if reg_name = "C17" then SOME (C17_ref.regval_of (C17_ref.read_from s)) else
+  if reg_name = "C16" then SOME (C16_ref.regval_of (C16_ref.read_from s)) else
+  if reg_name = "C15" then SOME (C15_ref.regval_of (C15_ref.read_from s)) else
+  if reg_name = "C14" then SOME (C14_ref.regval_of (C14_ref.read_from s)) else
+  if reg_name = "C13" then SOME (C13_ref.regval_of (C13_ref.read_from s)) else
+  if reg_name = "C12" then SOME (C12_ref.regval_of (C12_ref.read_from s)) else
+  if reg_name = "C11" then SOME (C11_ref.regval_of (C11_ref.read_from s)) else
+  if reg_name = "C10" then SOME (C10_ref.regval_of (C10_ref.read_from s)) else
+  if reg_name = "C09" then SOME (C09_ref.regval_of (C09_ref.read_from s)) else
+  if reg_name = "C08" then SOME (C08_ref.regval_of (C08_ref.read_from s)) else
+  if reg_name = "C07" then SOME (C07_ref.regval_of (C07_ref.read_from s)) else
+  if reg_name = "C06" then SOME (C06_ref.regval_of (C06_ref.read_from s)) else
+  if reg_name = "C05" then SOME (C05_ref.regval_of (C05_ref.read_from s)) else
+  if reg_name = "C04" then SOME (C04_ref.regval_of (C04_ref.read_from s)) else
+  if reg_name = "C03" then SOME (C03_ref.regval_of (C03_ref.read_from s)) else
+  if reg_name = "C02" then SOME (C02_ref.regval_of (C02_ref.read_from s)) else
+  if reg_name = "C01" then SOME (C01_ref.regval_of (C01_ref.read_from s)) else
+  if reg_name = "C00" then SOME (C00_ref.regval_of (C00_ref.read_from s)) else
+  if reg_name = "inCCallDelay" then SOME (inCCallDelay_ref.regval_of (inCCallDelay_ref.read_from s)) else
+  if reg_name = "nextPCC" then SOME (nextPCC_ref.regval_of (nextPCC_ref.read_from s)) else
+  if reg_name = "delayedPCC" then SOME (delayedPCC_ref.regval_of (delayedPCC_ref.read_from s)) else
+  if reg_name = "PCC" then SOME (PCC_ref.regval_of (PCC_ref.read_from s)) else
+  if reg_name = "C31" then SOME (C31_ref.regval_of (C31_ref.read_from s)) else
+  if reg_name = "C29" then SOME (C29_ref.regval_of (C29_ref.read_from s)) else
+  if reg_name = "UART_RVALID" then SOME (UART_RVALID_ref.regval_of (UART_RVALID_ref.read_from s)) else
+  if reg_name = "UART_RDATA" then SOME (UART_RDATA_ref.regval_of (UART_RDATA_ref.read_from s)) else
+  if reg_name = "UART_WRITTEN" then SOME (UART_WRITTEN_ref.regval_of (UART_WRITTEN_ref.read_from s)) else
+  if reg_name = "UART_WDATA" then SOME (UART_WDATA_ref.regval_of (UART_WDATA_ref.read_from s)) else
+  if reg_name = "GPR" then SOME (GPR_ref.regval_of (GPR_ref.read_from s)) else
+  if reg_name = "LO" then SOME (LO_ref.regval_of (LO_ref.read_from s)) else
+  if reg_name = "HI" then SOME (HI_ref.regval_of (HI_ref.read_from s)) else
+  if reg_name = "delayedPC" then SOME (delayedPC_ref.regval_of (delayedPC_ref.read_from s)) else
+  if reg_name = "inBranchDelay" then SOME (inBranchDelay_ref.regval_of (inBranchDelay_ref.read_from s)) else
+  if reg_name = "branchPending" then SOME (branchPending_ref.regval_of (branchPending_ref.read_from s)) else
+  if reg_name = "CP0Status" then SOME (CP0Status_ref.regval_of (CP0Status_ref.read_from s)) else
+  if reg_name = "CP0UserLocal" then SOME (CP0UserLocal_ref.regval_of (CP0UserLocal_ref.read_from s)) else
+  if reg_name = "CP0HWREna" then SOME (CP0HWREna_ref.regval_of (CP0HWREna_ref.read_from s)) else
+  if reg_name = "CP0Count" then SOME (CP0Count_ref.regval_of (CP0Count_ref.read_from s)) else
+  if reg_name = "CP0BadVAddr" then SOME (CP0BadVAddr_ref.regval_of (CP0BadVAddr_ref.read_from s)) else
+  if reg_name = "CP0LLAddr" then SOME (CP0LLAddr_ref.regval_of (CP0LLAddr_ref.read_from s)) else
+  if reg_name = "CP0LLBit" then SOME (CP0LLBit_ref.regval_of (CP0LLBit_ref.read_from s)) else
+  if reg_name = "CP0ErrorEPC" then SOME (CP0ErrorEPC_ref.regval_of (CP0ErrorEPC_ref.read_from s)) else
+  if reg_name = "CP0EPC" then SOME (CP0EPC_ref.regval_of (CP0EPC_ref.read_from s)) else
+  if reg_name = "CP0Cause" then SOME (CP0Cause_ref.regval_of (CP0Cause_ref.read_from s)) else
+  if reg_name = "CP0Compare" then SOME (CP0Compare_ref.regval_of (CP0Compare_ref.read_from s)) else
+  if reg_name = "TLBEntry63" then SOME (TLBEntry63_ref.regval_of (TLBEntry63_ref.read_from s)) else
+  if reg_name = "TLBEntry62" then SOME (TLBEntry62_ref.regval_of (TLBEntry62_ref.read_from s)) else
+  if reg_name = "TLBEntry61" then SOME (TLBEntry61_ref.regval_of (TLBEntry61_ref.read_from s)) else
+  if reg_name = "TLBEntry60" then SOME (TLBEntry60_ref.regval_of (TLBEntry60_ref.read_from s)) else
+  if reg_name = "TLBEntry59" then SOME (TLBEntry59_ref.regval_of (TLBEntry59_ref.read_from s)) else
+  if reg_name = "TLBEntry58" then SOME (TLBEntry58_ref.regval_of (TLBEntry58_ref.read_from s)) else
+  if reg_name = "TLBEntry57" then SOME (TLBEntry57_ref.regval_of (TLBEntry57_ref.read_from s)) else
+  if reg_name = "TLBEntry56" then SOME (TLBEntry56_ref.regval_of (TLBEntry56_ref.read_from s)) else
+  if reg_name = "TLBEntry55" then SOME (TLBEntry55_ref.regval_of (TLBEntry55_ref.read_from s)) else
+  if reg_name = "TLBEntry54" then SOME (TLBEntry54_ref.regval_of (TLBEntry54_ref.read_from s)) else
+  if reg_name = "TLBEntry53" then SOME (TLBEntry53_ref.regval_of (TLBEntry53_ref.read_from s)) else
+  if reg_name = "TLBEntry52" then SOME (TLBEntry52_ref.regval_of (TLBEntry52_ref.read_from s)) else
+  if reg_name = "TLBEntry51" then SOME (TLBEntry51_ref.regval_of (TLBEntry51_ref.read_from s)) else
+  if reg_name = "TLBEntry50" then SOME (TLBEntry50_ref.regval_of (TLBEntry50_ref.read_from s)) else
+  if reg_name = "TLBEntry49" then SOME (TLBEntry49_ref.regval_of (TLBEntry49_ref.read_from s)) else
+  if reg_name = "TLBEntry48" then SOME (TLBEntry48_ref.regval_of (TLBEntry48_ref.read_from s)) else
+  if reg_name = "TLBEntry47" then SOME (TLBEntry47_ref.regval_of (TLBEntry47_ref.read_from s)) else
+  if reg_name = "TLBEntry46" then SOME (TLBEntry46_ref.regval_of (TLBEntry46_ref.read_from s)) else
+  if reg_name = "TLBEntry45" then SOME (TLBEntry45_ref.regval_of (TLBEntry45_ref.read_from s)) else
+  if reg_name = "TLBEntry44" then SOME (TLBEntry44_ref.regval_of (TLBEntry44_ref.read_from s)) else
+  if reg_name = "TLBEntry43" then SOME (TLBEntry43_ref.regval_of (TLBEntry43_ref.read_from s)) else
+  if reg_name = "TLBEntry42" then SOME (TLBEntry42_ref.regval_of (TLBEntry42_ref.read_from s)) else
+  if reg_name = "TLBEntry41" then SOME (TLBEntry41_ref.regval_of (TLBEntry41_ref.read_from s)) else
+  if reg_name = "TLBEntry40" then SOME (TLBEntry40_ref.regval_of (TLBEntry40_ref.read_from s)) else
+  if reg_name = "TLBEntry39" then SOME (TLBEntry39_ref.regval_of (TLBEntry39_ref.read_from s)) else
+  if reg_name = "TLBEntry38" then SOME (TLBEntry38_ref.regval_of (TLBEntry38_ref.read_from s)) else
+  if reg_name = "TLBEntry37" then SOME (TLBEntry37_ref.regval_of (TLBEntry37_ref.read_from s)) else
+  if reg_name = "TLBEntry36" then SOME (TLBEntry36_ref.regval_of (TLBEntry36_ref.read_from s)) else
+  if reg_name = "TLBEntry35" then SOME (TLBEntry35_ref.regval_of (TLBEntry35_ref.read_from s)) else
+  if reg_name = "TLBEntry34" then SOME (TLBEntry34_ref.regval_of (TLBEntry34_ref.read_from s)) else
+  if reg_name = "TLBEntry33" then SOME (TLBEntry33_ref.regval_of (TLBEntry33_ref.read_from s)) else
+  if reg_name = "TLBEntry32" then SOME (TLBEntry32_ref.regval_of (TLBEntry32_ref.read_from s)) else
+  if reg_name = "TLBEntry31" then SOME (TLBEntry31_ref.regval_of (TLBEntry31_ref.read_from s)) else
+  if reg_name = "TLBEntry30" then SOME (TLBEntry30_ref.regval_of (TLBEntry30_ref.read_from s)) else
+  if reg_name = "TLBEntry29" then SOME (TLBEntry29_ref.regval_of (TLBEntry29_ref.read_from s)) else
+  if reg_name = "TLBEntry28" then SOME (TLBEntry28_ref.regval_of (TLBEntry28_ref.read_from s)) else
+  if reg_name = "TLBEntry27" then SOME (TLBEntry27_ref.regval_of (TLBEntry27_ref.read_from s)) else
+  if reg_name = "TLBEntry26" then SOME (TLBEntry26_ref.regval_of (TLBEntry26_ref.read_from s)) else
+  if reg_name = "TLBEntry25" then SOME (TLBEntry25_ref.regval_of (TLBEntry25_ref.read_from s)) else
+  if reg_name = "TLBEntry24" then SOME (TLBEntry24_ref.regval_of (TLBEntry24_ref.read_from s)) else
+  if reg_name = "TLBEntry23" then SOME (TLBEntry23_ref.regval_of (TLBEntry23_ref.read_from s)) else
+  if reg_name = "TLBEntry22" then SOME (TLBEntry22_ref.regval_of (TLBEntry22_ref.read_from s)) else
+  if reg_name = "TLBEntry21" then SOME (TLBEntry21_ref.regval_of (TLBEntry21_ref.read_from s)) else
+  if reg_name = "TLBEntry20" then SOME (TLBEntry20_ref.regval_of (TLBEntry20_ref.read_from s)) else
+  if reg_name = "TLBEntry19" then SOME (TLBEntry19_ref.regval_of (TLBEntry19_ref.read_from s)) else
+  if reg_name = "TLBEntry18" then SOME (TLBEntry18_ref.regval_of (TLBEntry18_ref.read_from s)) else
+  if reg_name = "TLBEntry17" then SOME (TLBEntry17_ref.regval_of (TLBEntry17_ref.read_from s)) else
+  if reg_name = "TLBEntry16" then SOME (TLBEntry16_ref.regval_of (TLBEntry16_ref.read_from s)) else
+  if reg_name = "TLBEntry15" then SOME (TLBEntry15_ref.regval_of (TLBEntry15_ref.read_from s)) else
+  if reg_name = "TLBEntry14" then SOME (TLBEntry14_ref.regval_of (TLBEntry14_ref.read_from s)) else
+  if reg_name = "TLBEntry13" then SOME (TLBEntry13_ref.regval_of (TLBEntry13_ref.read_from s)) else
+  if reg_name = "TLBEntry12" then SOME (TLBEntry12_ref.regval_of (TLBEntry12_ref.read_from s)) else
+  if reg_name = "TLBEntry11" then SOME (TLBEntry11_ref.regval_of (TLBEntry11_ref.read_from s)) else
+  if reg_name = "TLBEntry10" then SOME (TLBEntry10_ref.regval_of (TLBEntry10_ref.read_from s)) else
+  if reg_name = "TLBEntry09" then SOME (TLBEntry09_ref.regval_of (TLBEntry09_ref.read_from s)) else
+  if reg_name = "TLBEntry08" then SOME (TLBEntry08_ref.regval_of (TLBEntry08_ref.read_from s)) else
+  if reg_name = "TLBEntry07" then SOME (TLBEntry07_ref.regval_of (TLBEntry07_ref.read_from s)) else
+  if reg_name = "TLBEntry06" then SOME (TLBEntry06_ref.regval_of (TLBEntry06_ref.read_from s)) else
+  if reg_name = "TLBEntry05" then SOME (TLBEntry05_ref.regval_of (TLBEntry05_ref.read_from s)) else
+  if reg_name = "TLBEntry04" then SOME (TLBEntry04_ref.regval_of (TLBEntry04_ref.read_from s)) else
+  if reg_name = "TLBEntry03" then SOME (TLBEntry03_ref.regval_of (TLBEntry03_ref.read_from s)) else
+  if reg_name = "TLBEntry02" then SOME (TLBEntry02_ref.regval_of (TLBEntry02_ref.read_from s)) else
+  if reg_name = "TLBEntry01" then SOME (TLBEntry01_ref.regval_of (TLBEntry01_ref.read_from s)) else
+  if reg_name = "TLBEntry00" then SOME (TLBEntry00_ref.regval_of (TLBEntry00_ref.read_from s)) else
+  if reg_name = "TLBXContext" then SOME (TLBXContext_ref.regval_of (TLBXContext_ref.read_from s)) else
+  if reg_name = "TLBEntryHi" then SOME (TLBEntryHi_ref.regval_of (TLBEntryHi_ref.read_from s)) else
+  if reg_name = "TLBWired" then SOME (TLBWired_ref.regval_of (TLBWired_ref.read_from s)) else
+  if reg_name = "TLBPageMask" then SOME (TLBPageMask_ref.regval_of (TLBPageMask_ref.read_from s)) else
+  if reg_name = "TLBContext" then SOME (TLBContext_ref.regval_of (TLBContext_ref.read_from s)) else
+  if reg_name = "TLBEntryLo1" then SOME (TLBEntryLo1_ref.regval_of (TLBEntryLo1_ref.read_from s)) else
+  if reg_name = "TLBEntryLo0" then SOME (TLBEntryLo0_ref.regval_of (TLBEntryLo0_ref.read_from s)) else
+  if reg_name = "TLBRandom" then SOME (TLBRandom_ref.regval_of (TLBRandom_ref.read_from s)) else
+  if reg_name = "TLBIndex" then SOME (TLBIndex_ref.regval_of (TLBIndex_ref.read_from s)) else
+  if reg_name = "TLBProbe" then SOME (TLBProbe_ref.regval_of (TLBProbe_ref.read_from s)) else
+  if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
+  if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+  NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=  
+ (if reg_name = "CapCause" then OPTION_MAP (\ v .  CapCause_ref.write_to v s) (CapCause_ref.of_regval v) else
+  if reg_name = "CTLSP" then OPTION_MAP (\ v .  CTLSP_ref.write_to v s) (CTLSP_ref.of_regval v) else
+  if reg_name = "CTLSU" then OPTION_MAP (\ v .  CTLSU_ref.write_to v s) (CTLSU_ref.of_regval v) else
+  if reg_name = "C30" then OPTION_MAP (\ v .  C30_ref.write_to v s) (C30_ref.of_regval v) else
+  if reg_name = "C28" then OPTION_MAP (\ v .  C28_ref.write_to v s) (C28_ref.of_regval v) else
+  if reg_name = "C27" then OPTION_MAP (\ v .  C27_ref.write_to v s) (C27_ref.of_regval v) else
+  if reg_name = "C26" then OPTION_MAP (\ v .  C26_ref.write_to v s) (C26_ref.of_regval v) else
+  if reg_name = "C25" then OPTION_MAP (\ v .  C25_ref.write_to v s) (C25_ref.of_regval v) else
+  if reg_name = "C24" then OPTION_MAP (\ v .  C24_ref.write_to v s) (C24_ref.of_regval v) else
+  if reg_name = "C23" then OPTION_MAP (\ v .  C23_ref.write_to v s) (C23_ref.of_regval v) else
+  if reg_name = "C22" then OPTION_MAP (\ v .  C22_ref.write_to v s) (C22_ref.of_regval v) else
+  if reg_name = "C21" then OPTION_MAP (\ v .  C21_ref.write_to v s) (C21_ref.of_regval v) else
+  if reg_name = "C20" then OPTION_MAP (\ v .  C20_ref.write_to v s) (C20_ref.of_regval v) else
+  if reg_name = "C19" then OPTION_MAP (\ v .  C19_ref.write_to v s) (C19_ref.of_regval v) else
+  if reg_name = "C18" then OPTION_MAP (\ v .  C18_ref.write_to v s) (C18_ref.of_regval v) else
+  if reg_name = "C17" then OPTION_MAP (\ v .  C17_ref.write_to v s) (C17_ref.of_regval v) else
+  if reg_name = "C16" then OPTION_MAP (\ v .  C16_ref.write_to v s) (C16_ref.of_regval v) else
+  if reg_name = "C15" then OPTION_MAP (\ v .  C15_ref.write_to v s) (C15_ref.of_regval v) else
+  if reg_name = "C14" then OPTION_MAP (\ v .  C14_ref.write_to v s) (C14_ref.of_regval v) else
+  if reg_name = "C13" then OPTION_MAP (\ v .  C13_ref.write_to v s) (C13_ref.of_regval v) else
+  if reg_name = "C12" then OPTION_MAP (\ v .  C12_ref.write_to v s) (C12_ref.of_regval v) else
+  if reg_name = "C11" then OPTION_MAP (\ v .  C11_ref.write_to v s) (C11_ref.of_regval v) else
+  if reg_name = "C10" then OPTION_MAP (\ v .  C10_ref.write_to v s) (C10_ref.of_regval v) else
+  if reg_name = "C09" then OPTION_MAP (\ v .  C09_ref.write_to v s) (C09_ref.of_regval v) else
+  if reg_name = "C08" then OPTION_MAP (\ v .  C08_ref.write_to v s) (C08_ref.of_regval v) else
+  if reg_name = "C07" then OPTION_MAP (\ v .  C07_ref.write_to v s) (C07_ref.of_regval v) else
+  if reg_name = "C06" then OPTION_MAP (\ v .  C06_ref.write_to v s) (C06_ref.of_regval v) else
+  if reg_name = "C05" then OPTION_MAP (\ v .  C05_ref.write_to v s) (C05_ref.of_regval v) else
+  if reg_name = "C04" then OPTION_MAP (\ v .  C04_ref.write_to v s) (C04_ref.of_regval v) else
+  if reg_name = "C03" then OPTION_MAP (\ v .  C03_ref.write_to v s) (C03_ref.of_regval v) else
+  if reg_name = "C02" then OPTION_MAP (\ v .  C02_ref.write_to v s) (C02_ref.of_regval v) else
+  if reg_name = "C01" then OPTION_MAP (\ v .  C01_ref.write_to v s) (C01_ref.of_regval v) else
+  if reg_name = "C00" then OPTION_MAP (\ v .  C00_ref.write_to v s) (C00_ref.of_regval v) else
+  if reg_name = "inCCallDelay" then OPTION_MAP (\ v .  inCCallDelay_ref.write_to v s) (inCCallDelay_ref.of_regval v) else
+  if reg_name = "nextPCC" then OPTION_MAP (\ v .  nextPCC_ref.write_to v s) (nextPCC_ref.of_regval v) else
+  if reg_name = "delayedPCC" then OPTION_MAP (\ v .  delayedPCC_ref.write_to v s) (delayedPCC_ref.of_regval v) else
+  if reg_name = "PCC" then OPTION_MAP (\ v .  PCC_ref.write_to v s) (PCC_ref.of_regval v) else
+  if reg_name = "C31" then OPTION_MAP (\ v .  C31_ref.write_to v s) (C31_ref.of_regval v) else
+  if reg_name = "C29" then OPTION_MAP (\ v .  C29_ref.write_to v s) (C29_ref.of_regval v) else
+  if reg_name = "UART_RVALID" then OPTION_MAP (\ v .  UART_RVALID_ref.write_to v s) (UART_RVALID_ref.of_regval v) else
+  if reg_name = "UART_RDATA" then OPTION_MAP (\ v .  UART_RDATA_ref.write_to v s) (UART_RDATA_ref.of_regval v) else
+  if reg_name = "UART_WRITTEN" then OPTION_MAP (\ v .  UART_WRITTEN_ref.write_to v s) (UART_WRITTEN_ref.of_regval v) else
+  if reg_name = "UART_WDATA" then OPTION_MAP (\ v .  UART_WDATA_ref.write_to v s) (UART_WDATA_ref.of_regval v) else
+  if reg_name = "GPR" then OPTION_MAP (\ v .  GPR_ref.write_to v s) (GPR_ref.of_regval v) else
+  if reg_name = "LO" then OPTION_MAP (\ v .  LO_ref.write_to v s) (LO_ref.of_regval v) else
+  if reg_name = "HI" then OPTION_MAP (\ v .  HI_ref.write_to v s) (HI_ref.of_regval v) else
+  if reg_name = "delayedPC" then OPTION_MAP (\ v .  delayedPC_ref.write_to v s) (delayedPC_ref.of_regval v) else
+  if reg_name = "inBranchDelay" then OPTION_MAP (\ v .  inBranchDelay_ref.write_to v s) (inBranchDelay_ref.of_regval v) else
+  if reg_name = "branchPending" then OPTION_MAP (\ v .  branchPending_ref.write_to v s) (branchPending_ref.of_regval v) else
+  if reg_name = "CP0Status" then OPTION_MAP (\ v .  CP0Status_ref.write_to v s) (CP0Status_ref.of_regval v) else
+  if reg_name = "CP0UserLocal" then OPTION_MAP (\ v .  CP0UserLocal_ref.write_to v s) (CP0UserLocal_ref.of_regval v) else
+  if reg_name = "CP0HWREna" then OPTION_MAP (\ v .  CP0HWREna_ref.write_to v s) (CP0HWREna_ref.of_regval v) else
+  if reg_name = "CP0Count" then OPTION_MAP (\ v .  CP0Count_ref.write_to v s) (CP0Count_ref.of_regval v) else
+  if reg_name = "CP0BadVAddr" then OPTION_MAP (\ v .  CP0BadVAddr_ref.write_to v s) (CP0BadVAddr_ref.of_regval v) else
+  if reg_name = "CP0LLAddr" then OPTION_MAP (\ v .  CP0LLAddr_ref.write_to v s) (CP0LLAddr_ref.of_regval v) else
+  if reg_name = "CP0LLBit" then OPTION_MAP (\ v .  CP0LLBit_ref.write_to v s) (CP0LLBit_ref.of_regval v) else
+  if reg_name = "CP0ErrorEPC" then OPTION_MAP (\ v .  CP0ErrorEPC_ref.write_to v s) (CP0ErrorEPC_ref.of_regval v) else
+  if reg_name = "CP0EPC" then OPTION_MAP (\ v .  CP0EPC_ref.write_to v s) (CP0EPC_ref.of_regval v) else
+  if reg_name = "CP0Cause" then OPTION_MAP (\ v .  CP0Cause_ref.write_to v s) (CP0Cause_ref.of_regval v) else
+  if reg_name = "CP0Compare" then OPTION_MAP (\ v .  CP0Compare_ref.write_to v s) (CP0Compare_ref.of_regval v) else
+  if reg_name = "TLBEntry63" then OPTION_MAP (\ v .  TLBEntry63_ref.write_to v s) (TLBEntry63_ref.of_regval v) else
+  if reg_name = "TLBEntry62" then OPTION_MAP (\ v .  TLBEntry62_ref.write_to v s) (TLBEntry62_ref.of_regval v) else
+  if reg_name = "TLBEntry61" then OPTION_MAP (\ v .  TLBEntry61_ref.write_to v s) (TLBEntry61_ref.of_regval v) else
+  if reg_name = "TLBEntry60" then OPTION_MAP (\ v .  TLBEntry60_ref.write_to v s) (TLBEntry60_ref.of_regval v) else
+  if reg_name = "TLBEntry59" then OPTION_MAP (\ v .  TLBEntry59_ref.write_to v s) (TLBEntry59_ref.of_regval v) else
+  if reg_name = "TLBEntry58" then OPTION_MAP (\ v .  TLBEntry58_ref.write_to v s) (TLBEntry58_ref.of_regval v) else
+  if reg_name = "TLBEntry57" then OPTION_MAP (\ v .  TLBEntry57_ref.write_to v s) (TLBEntry57_ref.of_regval v) else
+  if reg_name = "TLBEntry56" then OPTION_MAP (\ v .  TLBEntry56_ref.write_to v s) (TLBEntry56_ref.of_regval v) else
+  if reg_name = "TLBEntry55" then OPTION_MAP (\ v .  TLBEntry55_ref.write_to v s) (TLBEntry55_ref.of_regval v) else
+  if reg_name = "TLBEntry54" then OPTION_MAP (\ v .  TLBEntry54_ref.write_to v s) (TLBEntry54_ref.of_regval v) else
+  if reg_name = "TLBEntry53" then OPTION_MAP (\ v .  TLBEntry53_ref.write_to v s) (TLBEntry53_ref.of_regval v) else
+  if reg_name = "TLBEntry52" then OPTION_MAP (\ v .  TLBEntry52_ref.write_to v s) (TLBEntry52_ref.of_regval v) else
+  if reg_name = "TLBEntry51" then OPTION_MAP (\ v .  TLBEntry51_ref.write_to v s) (TLBEntry51_ref.of_regval v) else
+  if reg_name = "TLBEntry50" then OPTION_MAP (\ v .  TLBEntry50_ref.write_to v s) (TLBEntry50_ref.of_regval v) else
+  if reg_name = "TLBEntry49" then OPTION_MAP (\ v .  TLBEntry49_ref.write_to v s) (TLBEntry49_ref.of_regval v) else
+  if reg_name = "TLBEntry48" then OPTION_MAP (\ v .  TLBEntry48_ref.write_to v s) (TLBEntry48_ref.of_regval v) else
+  if reg_name = "TLBEntry47" then OPTION_MAP (\ v .  TLBEntry47_ref.write_to v s) (TLBEntry47_ref.of_regval v) else
+  if reg_name = "TLBEntry46" then OPTION_MAP (\ v .  TLBEntry46_ref.write_to v s) (TLBEntry46_ref.of_regval v) else
+  if reg_name = "TLBEntry45" then OPTION_MAP (\ v .  TLBEntry45_ref.write_to v s) (TLBEntry45_ref.of_regval v) else
+  if reg_name = "TLBEntry44" then OPTION_MAP (\ v .  TLBEntry44_ref.write_to v s) (TLBEntry44_ref.of_regval v) else
+  if reg_name = "TLBEntry43" then OPTION_MAP (\ v .  TLBEntry43_ref.write_to v s) (TLBEntry43_ref.of_regval v) else
+  if reg_name = "TLBEntry42" then OPTION_MAP (\ v .  TLBEntry42_ref.write_to v s) (TLBEntry42_ref.of_regval v) else
+  if reg_name = "TLBEntry41" then OPTION_MAP (\ v .  TLBEntry41_ref.write_to v s) (TLBEntry41_ref.of_regval v) else
+  if reg_name = "TLBEntry40" then OPTION_MAP (\ v .  TLBEntry40_ref.write_to v s) (TLBEntry40_ref.of_regval v) else
+  if reg_name = "TLBEntry39" then OPTION_MAP (\ v .  TLBEntry39_ref.write_to v s) (TLBEntry39_ref.of_regval v) else
+  if reg_name = "TLBEntry38" then OPTION_MAP (\ v .  TLBEntry38_ref.write_to v s) (TLBEntry38_ref.of_regval v) else
+  if reg_name = "TLBEntry37" then OPTION_MAP (\ v .  TLBEntry37_ref.write_to v s) (TLBEntry37_ref.of_regval v) else
+  if reg_name = "TLBEntry36" then OPTION_MAP (\ v .  TLBEntry36_ref.write_to v s) (TLBEntry36_ref.of_regval v) else
+  if reg_name = "TLBEntry35" then OPTION_MAP (\ v .  TLBEntry35_ref.write_to v s) (TLBEntry35_ref.of_regval v) else
+  if reg_name = "TLBEntry34" then OPTION_MAP (\ v .  TLBEntry34_ref.write_to v s) (TLBEntry34_ref.of_regval v) else
+  if reg_name = "TLBEntry33" then OPTION_MAP (\ v .  TLBEntry33_ref.write_to v s) (TLBEntry33_ref.of_regval v) else
+  if reg_name = "TLBEntry32" then OPTION_MAP (\ v .  TLBEntry32_ref.write_to v s) (TLBEntry32_ref.of_regval v) else
+  if reg_name = "TLBEntry31" then OPTION_MAP (\ v .  TLBEntry31_ref.write_to v s) (TLBEntry31_ref.of_regval v) else
+  if reg_name = "TLBEntry30" then OPTION_MAP (\ v .  TLBEntry30_ref.write_to v s) (TLBEntry30_ref.of_regval v) else
+  if reg_name = "TLBEntry29" then OPTION_MAP (\ v .  TLBEntry29_ref.write_to v s) (TLBEntry29_ref.of_regval v) else
+  if reg_name = "TLBEntry28" then OPTION_MAP (\ v .  TLBEntry28_ref.write_to v s) (TLBEntry28_ref.of_regval v) else
+  if reg_name = "TLBEntry27" then OPTION_MAP (\ v .  TLBEntry27_ref.write_to v s) (TLBEntry27_ref.of_regval v) else
+  if reg_name = "TLBEntry26" then OPTION_MAP (\ v .  TLBEntry26_ref.write_to v s) (TLBEntry26_ref.of_regval v) else
+  if reg_name = "TLBEntry25" then OPTION_MAP (\ v .  TLBEntry25_ref.write_to v s) (TLBEntry25_ref.of_regval v) else
+  if reg_name = "TLBEntry24" then OPTION_MAP (\ v .  TLBEntry24_ref.write_to v s) (TLBEntry24_ref.of_regval v) else
+  if reg_name = "TLBEntry23" then OPTION_MAP (\ v .  TLBEntry23_ref.write_to v s) (TLBEntry23_ref.of_regval v) else
+  if reg_name = "TLBEntry22" then OPTION_MAP (\ v .  TLBEntry22_ref.write_to v s) (TLBEntry22_ref.of_regval v) else
+  if reg_name = "TLBEntry21" then OPTION_MAP (\ v .  TLBEntry21_ref.write_to v s) (TLBEntry21_ref.of_regval v) else
+  if reg_name = "TLBEntry20" then OPTION_MAP (\ v .  TLBEntry20_ref.write_to v s) (TLBEntry20_ref.of_regval v) else
+  if reg_name = "TLBEntry19" then OPTION_MAP (\ v .  TLBEntry19_ref.write_to v s) (TLBEntry19_ref.of_regval v) else
+  if reg_name = "TLBEntry18" then OPTION_MAP (\ v .  TLBEntry18_ref.write_to v s) (TLBEntry18_ref.of_regval v) else
+  if reg_name = "TLBEntry17" then OPTION_MAP (\ v .  TLBEntry17_ref.write_to v s) (TLBEntry17_ref.of_regval v) else
+  if reg_name = "TLBEntry16" then OPTION_MAP (\ v .  TLBEntry16_ref.write_to v s) (TLBEntry16_ref.of_regval v) else
+  if reg_name = "TLBEntry15" then OPTION_MAP (\ v .  TLBEntry15_ref.write_to v s) (TLBEntry15_ref.of_regval v) else
+  if reg_name = "TLBEntry14" then OPTION_MAP (\ v .  TLBEntry14_ref.write_to v s) (TLBEntry14_ref.of_regval v) else
+  if reg_name = "TLBEntry13" then OPTION_MAP (\ v .  TLBEntry13_ref.write_to v s) (TLBEntry13_ref.of_regval v) else
+  if reg_name = "TLBEntry12" then OPTION_MAP (\ v .  TLBEntry12_ref.write_to v s) (TLBEntry12_ref.of_regval v) else
+  if reg_name = "TLBEntry11" then OPTION_MAP (\ v .  TLBEntry11_ref.write_to v s) (TLBEntry11_ref.of_regval v) else
+  if reg_name = "TLBEntry10" then OPTION_MAP (\ v .  TLBEntry10_ref.write_to v s) (TLBEntry10_ref.of_regval v) else
+  if reg_name = "TLBEntry09" then OPTION_MAP (\ v .  TLBEntry09_ref.write_to v s) (TLBEntry09_ref.of_regval v) else
+  if reg_name = "TLBEntry08" then OPTION_MAP (\ v .  TLBEntry08_ref.write_to v s) (TLBEntry08_ref.of_regval v) else
+  if reg_name = "TLBEntry07" then OPTION_MAP (\ v .  TLBEntry07_ref.write_to v s) (TLBEntry07_ref.of_regval v) else
+  if reg_name = "TLBEntry06" then OPTION_MAP (\ v .  TLBEntry06_ref.write_to v s) (TLBEntry06_ref.of_regval v) else
+  if reg_name = "TLBEntry05" then OPTION_MAP (\ v .  TLBEntry05_ref.write_to v s) (TLBEntry05_ref.of_regval v) else
+  if reg_name = "TLBEntry04" then OPTION_MAP (\ v .  TLBEntry04_ref.write_to v s) (TLBEntry04_ref.of_regval v) else
+  if reg_name = "TLBEntry03" then OPTION_MAP (\ v .  TLBEntry03_ref.write_to v s) (TLBEntry03_ref.of_regval v) else
+  if reg_name = "TLBEntry02" then OPTION_MAP (\ v .  TLBEntry02_ref.write_to v s) (TLBEntry02_ref.of_regval v) else
+  if reg_name = "TLBEntry01" then OPTION_MAP (\ v .  TLBEntry01_ref.write_to v s) (TLBEntry01_ref.of_regval v) else
+  if reg_name = "TLBEntry00" then OPTION_MAP (\ v .  TLBEntry00_ref.write_to v s) (TLBEntry00_ref.of_regval v) else
+  if reg_name = "TLBXContext" then OPTION_MAP (\ v .  TLBXContext_ref.write_to v s) (TLBXContext_ref.of_regval v) else
+  if reg_name = "TLBEntryHi" then OPTION_MAP (\ v .  TLBEntryHi_ref.write_to v s) (TLBEntryHi_ref.of_regval v) else
+  if reg_name = "TLBWired" then OPTION_MAP (\ v .  TLBWired_ref.write_to v s) (TLBWired_ref.of_regval v) else
+  if reg_name = "TLBPageMask" then OPTION_MAP (\ v .  TLBPageMask_ref.write_to v s) (TLBPageMask_ref.of_regval v) else
+  if reg_name = "TLBContext" then OPTION_MAP (\ v .  TLBContext_ref.write_to v s) (TLBContext_ref.of_regval v) else
+  if reg_name = "TLBEntryLo1" then OPTION_MAP (\ v .  TLBEntryLo1_ref.write_to v s) (TLBEntryLo1_ref.of_regval v) else
+  if reg_name = "TLBEntryLo0" then OPTION_MAP (\ v .  TLBEntryLo0_ref.write_to v s) (TLBEntryLo0_ref.of_regval v) else
+  if reg_name = "TLBRandom" then OPTION_MAP (\ v .  TLBRandom_ref.write_to v s) (TLBRandom_ref.of_regval v) else
+  if reg_name = "TLBIndex" then OPTION_MAP (\ v .  TLBIndex_ref.write_to v s) (TLBIndex_ref.of_regval v) else
+  if reg_name = "TLBProbe" then OPTION_MAP (\ v .  TLBProbe_ref.write_to v s) (TLBProbe_ref.of_regval v) else
+  if reg_name = "nextPC" then OPTION_MAP (\ v .  nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
+  if reg_name = "PC" then OPTION_MAP (\ v .  PC_ref.write_to v s) (PC_ref.of_regval v) else
+  NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))=  (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``);
+val _ = type_abbrev((*  'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``);
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml b/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml
new file mode 100644
index 00000000..26c1d0a7
--- /dev/null
+++ b/snapshots/hol4/sail/cheri/mips_extras_sequentialScript.sml
@@ -0,0 +1,235 @@
+(*Generated by Lem from /home/bcampbe2/local/rems/github/sail/mips/mips_extras_sequential.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory state_monadTheory stateTheory sail_operatorsTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "mips_extras_sequential"
+
+(*open import Pervasives*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators*)
+(*open import State_monad*)
+(*open import State*)
+
+(*val MEMr             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*)
+(*val MEMr_reserve     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval 'b 'e*)
+(*val MEMr_tag         : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*)
+(*val MEMr_tag_reserve : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> State_monad.monadS 'regval (bool * 'b) 'e*)
+
+val _ = Define `
+ ((MEMr:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=              (read_memS 
+  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1))`;
+
+val _ = Define `
+ ((MEMr_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,'b,'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=      (read_memS 
+  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_reserve addr size1))`;
+
+
+(*val read_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> State_monad.monadS 'regval bool 'e*)
+val _ = Define `
+ ((read_tag_bool:'a sail_values$Bitvector_class -> 'a ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr=  (bindS  
+(read_tagS dict_Sail_values_Bitvector_a addr) (\ t . 
+  maybe_failS "read_tag_bool" (bool_of_bitU t))))`;
+
+
+(*val write_tag_bool : forall 'regval 'a 'e. Bitvector 'a => 'a -> bool -> State_monad.monadS 'regval unit 'e*)
+val _ = Define `
+ ((write_tag_bool:'a sail_values$Bitvector_class -> 'a -> bool ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr t=  (bindS (write_tagS 
+  dict_Sail_values_Bitvector_a addr (bitU_of_bool t)) 
+  (\b .  (case (b ) of ( _ ) => returnS ()  ))))`;
+
+
+val _ = Define `
+ ((MEMr_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=  (bindS  
+(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v .  bindS  
+(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . 
+  returnS (t, v)))))`;
+
+
+val _ = Define `
+ ((MEMr_tag_reserve:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int ->('regval,(bool#'b),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1=  (bindS  
+(read_memS dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b Read_plain addr size1) (\ v .  bindS  
+(read_tag_bool dict_Sail_values_Bitvector_a addr) (\ t . 
+  returnS (t, v)))))`;
+
+
+
+(*val MEMea                 : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*)
+(*val MEMea_conditional     : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*)
+(*val MEMea_tag             : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*)
+(*val MEMea_tag_conditional : forall 'regval 'a 'e. Bitvector 'a => 'a -> Num.integer -> State_monad.monadS 'regval unit 'e*)
+
+val _ = Define `
+ ((MEMea:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1=                  (write_mem_eaS 
+  dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1=      (write_mem_eaS 
+  dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+
+
+val _ = Define `
+ ((MEMea_tag:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1=              (write_mem_eaS 
+  dict_Sail_values_Bitvector_a Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_tag_conditional:'a sail_values$Bitvector_class -> 'a -> int ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a addr size1=  (write_mem_eaS 
+  dict_Sail_values_Bitvector_a Write_conditional addr (nat_of_int size1)))`;
+
+
+
+(*val MEMval                 : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval unit 'e*)
+(*val MEMval_conditional     : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> 'b -> State_monad.monadS 'regval bool 'e*)
+(*val MEMval_tag             : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval unit 'e*)
+(*val MEMval_tag_conditional : forall 'regval 'a 'b 'e. Bitvector 'a, Bitvector 'b => 'a -> Num.integer -> bool -> 'b -> State_monad.monadS 'regval bool 'e*)
+
+val _ = Define `
+ ((MEMval:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v=                       (bindS (write_mem_valS 
+  dict_Sail_values_Bitvector_b v) (\b .  (case (b ) of ( _ ) => returnS ()  ))))`;
+
+val _ = Define `
+ ((MEMval_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 v=           (bindS (write_mem_valS 
+  dict_Sail_values_Bitvector_b v) (\ b .  returnS (if b then T else F))))`;
+
+val _ = Define `
+ ((MEMval_tag:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(unit),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v=              (bindS (write_mem_valS 
+  dict_Sail_values_Bitvector_b v) (\b .  (case (b ) of
+            ( _ ) => bindS
+                       (write_tag_bool dict_Sail_values_Bitvector_a addr t)
+                       (\u .  (case (u ) of ( _ ) => returnS ()  ))
+        ))))`;
+
+val _ = Define `
+ ((MEMval_tag_conditional:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> bool -> 'b ->('regval,(bool),'e)state_monad$monadS)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b addr size1 t v=  (bindS (write_mem_valS 
+  dict_Sail_values_Bitvector_b v) (\ b .  bindS (write_tag_bool 
+  dict_Sail_values_Bitvector_a addr t) (\u .  (case (u ) of ( _ ) => returnS (if b then T else F) )))))`;
+
+
+(*val MEM_sync  : forall 'regval 'e. unit -> State_monad.monadS 'regval unit 'e*)
+
+val _ = Define `
+ ((MEM_sync:unit -> 'regval state_monad$sequential_state ->(((unit),'e)state_monad$result#'regval state_monad$sequential_state)set) () =  (returnS () ))`;
+  (*barrier Barrier_MIPS_SYNC*)
+
+(* Some wrappers copied from aarch64_extras *)
+(* TODO: Harmonise into a common library *)
+
+val _ = Define `
+ ((get_slice_int_bl:int -> int -> int ->(bool)list) len n lo=  
+( 
+  (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in
+  let bs = (bools_of_int (hi +( 1 : int)) n) in
+  subrange_list F bs hi lo))`;
+
+
+(*val get_slice_int : forall 'a. Bitvector 'a => Num.integer -> Num.integer -> Num.integer -> 'a*)
+val _ = Define `
+ ((get_slice_int:'a sail_values$Bitvector_class -> int -> int -> int -> 'a)dict_Sail_values_Bitvector_a len n lo=  (
+  dict_Sail_values_Bitvector_a.of_bools_method (get_slice_int_bl len n lo)))`;
+
+
+val _ = Define `
+ ((write_ram:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'e -> int -> 'f -> 'b -> 'a -> 'd state_monad$sequential_state ->(((unit),'c)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b _ size1 _ addr data=  (seqS  
+(MEMea dict_Sail_values_Bitvector_b addr size1)  
+(MEMval dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_a addr size1 data)))`;
+
+
+val _ = Define `
+ ((read_ram:'a sail_values$Bitvector_class -> 'c sail_values$Bitvector_class -> 'e -> int -> 'f -> 'a -> 'd state_monad$sequential_state ->(('c,'b)state_monad$result#'d state_monad$sequential_state)set)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c _ size1 _ addr=  (MEMr 
+  dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_c addr size1))`;
+
+
+val _ = Define `
+ ((string_of_bits:'a sail_values$Bitvector_class -> 'a -> string)dict_Sail_values_Bitvector_a bs=  (string_of_bv 
+  (instance_Sail_values_Bitvector_list_dict
+     instance_Sail_values_BitU_Sail_values_bitU_dict) (dict_Sail_values_Bitvector_a.bits_of_method bs)))`;
+
+val _ = Define `
+ ((string_of_int:'a lem_show$Show_class -> 'a -> string)dict_Show_Show_a= 
+  (dict_Show_Show_a.show_method))`;
+
+
+val _ = Define `
+ ((sign_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len=  (maybe_failwith (
+  dict_Sail_values_Bitvector_b.of_bits_method (exts_bv dict_Sail_values_Bitvector_a len bits))))`;
+
+val _ = Define `
+ ((zero_extend0:'a sail_values$Bitvector_class -> 'b sail_values$Bitvector_class -> 'a -> int -> 'b)dict_Sail_values_Bitvector_a dict_Sail_values_Bitvector_b bits len=  (maybe_failwith (
+  dict_Sail_values_Bitvector_b.of_bits_method (extz_bv dict_Sail_values_Bitvector_a len bits))))`;
+
+
+val _ = Define `
+ ((shift_bits_left:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=  
+ (let r = (OPTION_BIND (
+  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (shiftl_bv dict_Sail_values_Bitvector_d v n))) in
+  maybe_failS "shift_bits_left" r))`;
+
+val _ = Define `
+ ((shift_bits_right:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=  
+ (let r = (OPTION_BIND (
+  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (shiftr_bv dict_Sail_values_Bitvector_d v n))) in
+  maybe_failS "shift_bits_right" r))`;
+
+val _ = Define `
+ ((shift_bits_right_arith:'b sail_values$Bitvector_class -> 'd sail_values$Bitvector_class -> 'e sail_values$Bitvector_class -> 'd -> 'e -> 'c state_monad$sequential_state ->(('b,'a)state_monad$result#'c state_monad$sequential_state)set)dict_Sail_values_Bitvector_b dict_Sail_values_Bitvector_d dict_Sail_values_Bitvector_e v n=  
+ (let r = (OPTION_BIND (
+  dict_Sail_values_Bitvector_e.unsigned_method n) (\ n .  dict_Sail_values_Bitvector_b.of_bits_method (arith_shiftr_bv dict_Sail_values_Bitvector_d v n))) in
+  maybe_failS "shift_bits_right_arith" r))`;
+
+
+(* Use constants for undefined values for now *)
+val _ = Define `
+ ((internal_pick:'a list -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) vs=  (returnS (HD vs)))`;
+
+val _ = Define `
+ ((undefined_bool0:unit ->('c,(bool),'a)state_monad$monadS)=  undefined_boolS)`;
+
+val _ = Define `
+ ((undefined_string:unit -> 'b state_monad$sequential_state ->(((string),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS ""))`;
+
+val _ = Define `
+ ((undefined_unit:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS () ))`;
+
+val _ = Define `
+ ((undefined_int:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS (( 0 : int):sail_values$ii)))`;
+
+(*val undefined_vector : forall 'rv 'a 'e. Num.integer -> 'a -> State_monad.monadS 'rv (list 'a) 'e*)
+val _ = Define `
+ ((undefined_vector:int -> 'a -> 'rv state_monad$sequential_state ->((('a list),'e)state_monad$result#'rv state_monad$sequential_state)set) len u=  (returnS (repeat [u] len)))`;
+
+(*val undefined_bitvector : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*)
+val _ = Define `
+ ((undefined_bitvector:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a len=  (returnS (
+  dict_Sail_values_Bitvector_a.of_bools_method (repeat [F] len))))`;
+
+(*val undefined_bits : forall 'rv 'a 'e. Bitvector 'a => Num.integer -> State_monad.monadS 'rv 'a 'e*)
+val _ = Define `
+ ((undefined_bits:'a sail_values$Bitvector_class -> int ->('rv,'a,'e)state_monad$monadS)dict_Sail_values_Bitvector_a= 
+  (undefined_bitvector dict_Sail_values_Bitvector_a))`;
+
+val _ = Define `
+ ((undefined_bit:unit -> 'b state_monad$sequential_state ->(((sail_values$bitU),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS B0))`;
+
+val _ = Define `
+ ((undefined_real:unit -> 'b state_monad$sequential_state ->(((real),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS (realFromFrac(( 0 : int))(( 1 : int)))))`;
+
+val _ = Define `
+ ((undefined_range:'a -> 'd -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i j=  (returnS i))`;
+
+val _ = Define `
+ ((undefined_atom:'a -> 'c state_monad$sequential_state ->(('a,'b)state_monad$result#'c state_monad$sequential_state)set) i=  (returnS i))`;
+
+val _ = Define `
+ ((undefined_nat:unit -> 'b state_monad$sequential_state ->(((int),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS (( 0 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((skip:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (returnS () ))`;
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/lib/hol/Holmakefile b/snapshots/hol4/sail/lib/hol/Holmakefile
new file mode 100644
index 00000000..45ed41ff
--- /dev/null
+++ b/snapshots/hol4/sail/lib/hol/Holmakefile
@@ -0,0 +1,27 @@
+SCRIPTS = sail_instr_kindsScript.sml sail_valuesScript.sml sail_operatorsScript.sml \
+  sail_operators_mwordsScript.sml sail_operators_bitlistsScript.sml \
+  state_monadScript.sml stateScript.sml promptScript.sml prompt_monadScript.sml
+
+EXTRA_CLEANS = $(SCRIPTS)
+
+THYS = $(patsubst %Script.sml,%Theory.uo,$(SCRIPTS))
+
+LEMDIR=../../../lem/hol-lib
+
+INCLUDES = $(LEMDIR)
+
+all: $(THYS)
+.PHONY: all
+
+ifdef POLY
+HOLHEAP = sail-heap
+EXTRA_CLEANS = $(SCRIPTS) $(HOLHEAP) $(HOLHEAP).o
+
+BASE_HEAP = $(LEMDIR)/lemheap
+
+$(HOLHEAP):
+	$(protect $(HOLDIR)/bin/buildheap) -o $(HOLHEAP) -b $(BASE_HEAP)
+
+all: $(HOLHEAP)
+
+endif
diff --git a/snapshots/hol4/sail/riscv/Holmakefile b/snapshots/hol4/sail/riscv/Holmakefile
new file mode 100644
index 00000000..626e6f2f
--- /dev/null
+++ b/snapshots/hol4/sail/riscv/Holmakefile
@@ -0,0 +1,11 @@
+LEMDIR=../../lem/hol-lib
+
+INCLUDES = $(LEMDIR) ../lib/hol
+
+all: riscv_sequentialTheory.uo
+.PHONY: all
+
+ifdef POLY
+BASE_HEAP = ../lib/hol/sail-heap
+
+endif
diff --git a/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml
new file mode 100644
index 00000000..541bc1d3
--- /dev/null
+++ b/snapshots/hol4/sail/riscv/riscv_extras_sequentialScript.sml
@@ -0,0 +1,127 @@
+(*Generated by Lem from riscv_extras_sequential.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasivesTheory lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_extras_sequential"
+
+(*open import Pervasives*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators_mwords*)
+(*open import State_monad*)
+(*open import State*)
+
+val _ = type_abbrev((*  'a *) "bitvector" , ``:  'a words$word``);
+
+(*val barrierS : forall 'rv 'e. Sail_instr_kinds.barrier_kind -> State_monad.monadS 'rv unit 'e*)
+val _ = Define `
+ ((barrierS:sail_instr_kinds$barrier_kind -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) _=  (returnS () ))`;
+
+
+val _ = Define `
+ ((MEM_fence_rw_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (barrierS Barrier_RISCV_rw_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_rw:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)  () =  (barrierS Barrier_RISCV_r_rw))`;
+
+val _ = Define `
+ ((MEM_fence_r_r:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)   () =  (barrierS Barrier_RISCV_r_r))`;
+
+val _ = Define `
+ ((MEM_fence_rw_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)  () =  (barrierS Barrier_RISCV_rw_w))`;
+
+val _ = Define `
+ ((MEM_fence_w_w:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)   () =  (barrierS Barrier_RISCV_w_w))`;
+
+val _ = Define `
+ ((MEM_fence_i:unit -> 'b state_monad$sequential_state ->(((unit),'a)state_monad$result#'b state_monad$sequential_state)set)     () =  (barrierS Barrier_RISCV_i))`;
+
+
+(*val MEMea                            : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+(*val MEMea_release                    : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+(*val MEMea_strong_release             : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+(*val MEMea_conditional                : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+(*val MEMea_conditional_release        : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+(*val MEMea_conditional_strong_release : forall 'rv 'a 'e. Size 'a => bitvector 'a -> Num.integer -> State_monad.monadS 'rv unit 'e*)
+
+val _ = Define `
+ ((MEMea:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=                       (write_mem_eaS 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=               (write_mem_eaS 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=        (write_mem_eaS 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_strong_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=           (write_mem_eaS 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=   (write_mem_eaS 
+  instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_release addr (nat_of_int size1)))`;
+
+val _ = Define `
+ ((MEMea_conditional_strong_release:'a words$word -> int -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addr size1=                                           
+(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_RISCV_conditional_strong_release addr (nat_of_int size1)))`;
+
+
+(*val write_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
+  Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> bitvector 'b -> State_monad.monadS 'rv unit 'e*)
+val _ = Define `
+ ((write_ram:int -> int -> 'a words$word -> 'a words$word -> 'b words$word -> 'rv state_monad$sequential_state ->(((unit),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address value=  (bindS (seqS  
+(write_mem_eaS instance_Sail_values_Bitvector_Machine_word_mword_dict Write_plain address (nat_of_int size1))  
+(write_mem_valS instance_Sail_values_Bitvector_Machine_word_mword_dict value)) (\b .  (case (b ) of ( _ ) => returnS ()  ))))`;
+
+
+(*val read_ram : forall 'rv 'a 'b 'e. Size 'a, Size 'b =>
+  Num.integer -> Num.integer -> bitvector 'a -> bitvector 'a -> State_monad.monadS 'rv (bitvector 'b) 'e*)
+val _ = Define `
+ ((read_ram:int -> int -> 'a words$word -> 'a words$word -> 'rv state_monad$sequential_state ->((('b words$word),'e)state_monad$result#'rv state_monad$sequential_state)set) addrsize size1 hexRAM address=  
+ (read_memS instance_Sail_values_Bitvector_Machine_word_mword_dict instance_Sail_values_Bitvector_Machine_word_mword_dict Read_plain address size1))`;
+
+
+val _ = Define `
+ ((speculate_conditional_success:unit -> 'b state_monad$sequential_state ->(((bool),'a)state_monad$result#'b state_monad$sequential_state)set) () =  (excl_resultS () ))`;
+
+
+(*val get_slice_int : forall 'a. Size 'a => Num.integer -> Num.integer -> Num.integer -> bitvector 'a*)
+val _ = Define `
+ ((get_slice_int:int -> int -> int -> 'a words$word) len n lo=  
+( 
+  (* TODO: Is this the intended behaviour? *)let hi = ((lo + len) -( 1 : int)) in
+  let bits = (bits_of_int (hi +( 1 : int)) n) in
+  of_bits_failwith instance_Sail_values_Bitvector_Machine_word_mword_dict (subrange_list F bits hi lo)))`;
+
+
+(*val shift_bits_right : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_right:'a words$word -> 'b words$word -> 'a words$word) v m=  (shiftr v (lem$w2ui m)))`;
+
+(*val shift_bits_left : forall 'a 'b. Size 'a, Size 'b => bitvector 'a -> bitvector 'b -> bitvector 'a*)
+val _ = Define `
+ ((shift_bits_left:'a words$word -> 'b words$word -> 'a words$word) v m=  (shiftl v (lem$w2ui m)))`;
+
+
+(*val print_string : string -> string -> unit*)
+val _ = Define `
+ ((print_string:string -> string -> unit) msg s=  (prerr_endline ( STRCAT msg s)))`;
+
+
+(*val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit*)
+val _ = Define `
+ ((print_bits:string -> 'a words$word -> unit) msg bs=  (prerr_endline ( STRCAT msg (show_bitlist (MAP bitU_of_bool (bitstring$w2v bs))))))`;
+
+
+val _ = Define `
+ ((reg_deref0:('d,'c,'b)sail_values$register_ref ->('d,'b,'a)state_monad$monadS)=  read_regS)`;
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml b/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml
new file mode 100644
index 00000000..463da979
--- /dev/null
+++ b/snapshots/hol4/sail/riscv/riscv_sequentialAuxiliaryScript.sml
@@ -0,0 +1,41 @@
+(*Generated by Lem from riscv_sequential.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory riscv_sequentialTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+open lemLib;
+(* val _ = lemLib.run_interactive := true; *)
+val _ = new_theory "riscv_sequentialAuxiliary"
+
+
+(****************************************************)
+(*                                                  *)
+(* Termination Proofs                               *)
+(*                                                  *)
+(****************************************************)
+
+(* val gst = Defn.tgoal_no_defn (walk39_def, walk39_ind) *)
+val (walk39_rw, walk39_ind_rw) =
+  Defn.tprove_no_defn ((walk39_def, walk39_ind),
+    cheat (* the termination proof *)
+  )
+val walk39_rw = save_thm ("walk39_rw", walk39_rw);
+val walk39_ind_rw = save_thm ("walk39_ind_rw", walk39_ind_rw);
+
+
+(* val gst = Defn.tgoal_no_defn (execute_def, execute_ind) *)
+val (execute_rw, execute_ind_rw) =
+  Defn.tprove_no_defn ((execute_def, execute_ind),
+    cheat (* the termination proof *)
+  )
+val execute_rw = save_thm ("execute_rw", execute_rw);
+val execute_ind_rw = save_thm ("execute_ind_rw", execute_ind_rw);
+
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml b/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml
new file mode 100644
index 00000000..22d8e899
--- /dev/null
+++ b/snapshots/hol4/sail/riscv/riscv_sequentialScript.sml
@@ -0,0 +1,7554 @@
+(*Generated by Lem from riscv_sequential.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory riscv_sequential_typesTheory riscv_extras_sequentialTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_sequential"
+
+(*Generated by Sail from riscv_sequential.*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators_mwords*)
+(*open import State_monad*)
+(*open import State*)
+(*open import Riscv_sequential_types*)
+(*open import Riscv_extras_sequential*)
+
+
+
+
+
+
+
+
+
+(*val builtin_and_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*)
+
+
+
+(*val builtin_or_vec : forall 'n. Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n -> Riscv_sequential_types.bits 'n*)
+
+
+
+(*val __raw_SetSlice_int : forall 'w. Num.integer -> Sail_values.ii -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Sail_values.ii*)
+
+(*val __GetSlice_int : forall 'n. Size 'n => Num.integer -> Sail_values.ii -> Sail_values.ii -> Machine_word.mword 'n*)
+
+val _ = Define `
+ ((GetSlice_int:int -> int -> int -> 'n words$word) n m o1=  ((get_slice_int n m o1  :  'n words$word)))`;
+
+
+(*val __raw_SetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w -> Riscv_sequential_types.bits 'n*)
+
+(*val __raw_GetSlice_bits : forall 'n 'w. Num.integer -> Num.integer -> Riscv_sequential_types.bits 'n -> Sail_values.ii -> Riscv_sequential_types.bits 'w*)
+
+(*val cast_unit_vec : Sail_values.bitU -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((cast_unit_vec0:sail_values$bitU ->(1)words$word) b=   
+ ((case b of   B0 => (vec_of_bits [B0]  :  1 words$word) | B1 => (vec_of_bits [B1]  :  1 words$word) )))`;
+
+
+(*val DecStr : Sail_values.ii -> string*)
+
+(*val HexStr : Sail_values.ii -> string*)
+
+(*val __RISCV_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((RISCV_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (seqS   
+(write_ram (( 64 : int):sail_values$ii) width
+     (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                   B0]
+       :  64 words$word) addr data)   
+(returnS T)))`;
+
+
+(*val __TraceMemoryWrite : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*)
+
+(*val __RISCV_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Maybe.maybe (Machine_word.mword 'int8_times_n))*)
+
+val _ = Define `
+ ((RISCV_read:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=  (bindS
+   (read_ram (( 64 : int):sail_values$ii) width
+      (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                    B0]
+        :  64 words$word) addr
+     : ( 'int8_times_n words$word) riscv_sequential_types$M) (\ (w__0 :  'int8_times_n words$word) . 
+   returnS (SOME w__0))))`;
+
+
+(*val __TraceMemoryRead : forall 'int8_times_n 'm. Num.integer -> Riscv_sequential_types.bits 'm -> Riscv_sequential_types.bits 'int8_times_n -> unit*)
+
+(*val ex_nat : Sail_values.ii -> Num.integer*)
+
+val _ = Define `
+ ((ex_nat:int -> int) n=  n)`;
+
+
+(*val ex_int : Sail_values.ii -> Num.integer*)
+
+val _ = Define `
+ ((ex_int:int -> int) n=  n)`;
+
+
+(*val coerce_int_nat : Sail_values.ii -> Riscv_sequential_types.M Sail_values.ii*)
+
+val _ = Define `
+ ((coerce_int_nat:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((int),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) x=  (seqS (assert_expS T "") (returnS x)))`;
+
+
+(*val EXTS : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+(*val EXTZ : forall 'n 'm . Size 'm, Size 'n => Num.integer -> Machine_word.mword 'n -> Machine_word.mword 'm*)
+
+val _ = Define `
+ ((EXTS:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((sign_extend v m__tv  :  'm words$word)))`;
+
+
+val _ = Define `
+ ((EXTZ:int -> 'n words$word -> 'm words$word) (m__tv : int) v=  ((zero_extend v m__tv  :  'm words$word)))`;
+
+
+
+
+
+
+
+
+
+
+
+
+(*val bool_to_bits : bool -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((bool_to_bits:bool ->(1)words$word) x=  (if x then (vec_of_bits [B1]  :  1 words$word) else (vec_of_bits [B0]  :  1 words$word)))`;
+
+
+(*val bit_to_bool : Sail_values.bitU -> bool*)
+
+val _ = Define `
+ ((bit_to_bool:sail_values$bitU -> bool) b=  ((case b of   B1 => T | B0 => F )))`;
+
+
+(*val vector64 : Sail_values.ii -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((vector64:int ->(64)words$word) n=  ((get_slice_int (( 64 : int):sail_values$ii) n (( 0 : int):sail_values$ii)  :  64 words$word)))`;
+
+
+(*val to_bits : forall 'l. Size 'l => Num.integer -> Sail_values.ii -> Machine_word.mword 'l*)
+
+val _ = Define `
+ ((to_bits:int -> int -> 'l words$word) l n=  ((get_slice_int l n (( 0 : int):sail_values$ii)  :  'l words$word)))`;
+
+
+(*val shift_right_arith64 : Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((shift_right_arith64:(64)words$word ->(6)words$word ->(64)words$word) (v : 64 riscv_sequential_types$bits) (shift : 6 riscv_sequential_types$bits)=   
+ (let (v128 : 128 riscv_sequential_types$bits) = ((EXTS (( 128 : int):sail_values$ii) v  :  128 words$word)) in
+   (subrange_vec_dec ((shift_bits_right v128 shift  :  128 words$word)) (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)))`;
+
+
+(*val shift_right_arith32 : Machine_word.mword Machine_word.ty32 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty32*)
+
+val _ = Define `
+ ((shift_right_arith32:(32)words$word ->(5)words$word ->(32)words$word) (v : 32 riscv_sequential_types$bits) (shift : 5 riscv_sequential_types$bits)=   
+ (let (v64 : 64 riscv_sequential_types$bits) = ((EXTS (( 64 : int):sail_values$ii) v  :  64 words$word)) in
+   (subrange_vec_dec ((shift_bits_right v64 shift  :  64 words$word)) (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)))`;
+
+
+val _ = Define `
+ ((xlen:int)=  ((( 64 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_unsigned:int)=  (((pow2 xlen)) - (( 1 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((xlen_max_signed:int)=  (((pow2 ((xlen - (( 1 : int):sail_values$ii))))) - (( 1 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((xlen_min_signed:int)=  ((( 0 : int):sail_values$ii) - ((pow2 ((xlen - (( 1 : int):sail_values$ii)))))))`;
+
+
+(*val regbits_to_regno : Machine_word.mword Machine_word.ty5 -> Num.integer*)
+
+val _ = Define `
+ ((regbits_to_regno:(5)words$word -> int) b=   
+ (let r = (lem$w2ui b) in
+   r))`;
+
+
+(*val creg2reg_bits : Machine_word.mword Machine_word.ty3 -> Machine_word.mword Machine_word.ty5*)
+
+val _ = Define `
+ ((creg2reg_bits:(3)words$word ->(5)words$word) creg=  ((concat_vec (vec_of_bits [B0;B1]  :  2 words$word) creg  :  5 words$word)))`;
+
+
+val _ = Define `
+((zreg:(5)words$word)=  ((vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))`;
+
+
+val _ = Define `
+((ra:(5)words$word)=  ((vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))`;
+
+
+val _ = Define `
+((sp:(5)words$word)=  ((vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))`;
+
+
+(*val rX : Num.integer -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((rX:int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) l__81=   
+ (if (((l__81 = (( 0 : int):sail_values$ii)))) then
+     returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0]
+               :  64 words$word)
+   else bindS     
+(read_regS Xs_ref) (\ (w__0 : riscv_sequential_types$xlenbits list) . 
+     returnS ((access_list_dec w__0 l__81  :  64 words$word)))))`;
+
+
+(*val wX : Num.integer -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((wX:int ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r v=   
+ (if (((r <> (( 0 : int):sail_values$ii)))) then bindS     
+(read_regS Xs_ref) (\ (w__0 : ( 64 words$word) list) .  seqS     
+(write_regS Xs_ref ((update_list_dec w__0 r v  : ( 64 words$word) list)))     
+(returnS ((prerr_endline
+                 ((STRCAT "x"
+                     ((STRCAT ((stringFromInteger r))
+                         ((STRCAT " <- " ((string_of_vec v))))))))))))
+   else returnS () ))`;
+
+
+(*val reg_name_abi : Machine_word.mword Machine_word.ty5 -> string*)
+
+val _ = Define `
+ ((reg_name_abi:(5)words$word -> string) r=   
+ (let b__0 = r in
+   if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) then
+     "zero"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) then
+     "ra"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) then
+     "sp"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) then
+     "gp"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) then
+     "tp"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B1]  :  5 words$word)))))) then
+     "t0"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B0]  :  5 words$word)))))) then
+     "t1"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B1;B1]  :  5 words$word)))))) then
+     "t2"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) then
+     "fp"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B1]  :  5 words$word)))))) then
+     "s1"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B0]  :  5 words$word)))))) then
+     "a0"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B1;B1]  :  5 words$word)))))) then
+     "a1"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) then
+     "a2"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B1]  :  5 words$word)))))) then
+     "a3"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B0]  :  5 words$word)))))) then
+     "a4"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B1;B1]  :  5 words$word)))))) then
+     "a5"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) then
+     "a6"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B1]  :  5 words$word)))))) then
+     "a7"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B0]  :  5 words$word)))))) then
+     "s2"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B1;B1]  :  5 words$word)))))) then
+     "s3"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) then
+     "s4"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B1]  :  5 words$word)))))) then
+     "s5"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B0]  :  5 words$word)))))) then
+     "s6"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B1;B1]  :  5 words$word)))))) then
+     "s7"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) then
+     "s8"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B1]  :  5 words$word)))))) then
+     "s9"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B0]  :  5 words$word)))))) then
+     "s10"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B1;B1]  :  5 words$word)))))) then
+     "s11"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) then
+     "t3"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B1]  :  5 words$word)))))) then
+     "t4"
+   else if (((((regbits_to_regno b__0)) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B1;B0]  :  5 words$word)))))) then
+     "t5"
+   else "t6"))`;
+
+
+(*val Architecture_of_num : Num.integer -> Riscv_sequential_types.Architecture*)
+
+val _ = Define `
+ ((Architecture_of_num:int -> riscv_sequential_types$Architecture) arg_=   
+ (let l__79 = arg_ in
+   if (((l__79 = (( 0 : int):sail_values$ii)))) then RV32
+   else if (((l__79 = (( 1 : int):sail_values$ii)))) then RV64
+   else RV128))`;
+
+
+(*val num_of_Architecture : Riscv_sequential_types.Architecture -> Num.integer*)
+
+val _ = Define `
+ ((num_of_Architecture:riscv_sequential_types$Architecture -> int) arg_=   
+ ((case arg_ of   RV32 => (( 0 : int):sail_values$ii) | RV64 => (( 1 : int):sail_values$ii) | RV128 => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val architecture : Machine_word.mword Machine_word.ty2 -> Maybe.maybe Riscv_sequential_types.Architecture*)
+
+val _ = Define `
+ ((architecture:(2)words$word ->(riscv_sequential_types$Architecture)option) a=   
+ (let b__0 = a in
+   if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then SOME RV32
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then SOME RV64
+   else if (((b__0 = (vec_of_bits [B1;B1]  :  2 words$word)))) then SOME RV128
+   else NONE))`;
+
+
+(*val arch_to_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((arch_to_bits:riscv_sequential_types$Architecture ->(2)words$word) a=   
+ ((case a of
+     RV32 => (vec_of_bits [B0;B1]  :  2 words$word)
+   | RV64 => (vec_of_bits [B1;B0]  :  2 words$word)
+   | RV128 => (vec_of_bits [B1;B1]  :  2 words$word)
+   )))`;
+
+
+(*val Privilege_of_num : Num.integer -> Riscv_sequential_types.Privilege*)
+
+val _ = Define `
+ ((Privilege_of_num:int -> riscv_sequential_types$Privilege) arg_=   
+ (let l__77 = arg_ in
+   if (((l__77 = (( 0 : int):sail_values$ii)))) then User
+   else if (((l__77 = (( 1 : int):sail_values$ii)))) then Supervisor
+   else Machine))`;
+
+
+(*val num_of_Privilege : Riscv_sequential_types.Privilege -> Num.integer*)
+
+val _ = Define `
+ ((num_of_Privilege:riscv_sequential_types$Privilege -> int) arg_=   
+ ((case arg_ of   User => (( 0 : int):sail_values$ii) | Supervisor => (( 1 : int):sail_values$ii) | Machine => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val privLevel_to_bits : Riscv_sequential_types.Privilege -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((privLevel_to_bits:riscv_sequential_types$Privilege ->(2)words$word) p=   
+ ((case p of
+     User => (vec_of_bits [B0;B0]  :  2 words$word)
+   | Supervisor => (vec_of_bits [B0;B1]  :  2 words$word)
+   | Machine => (vec_of_bits [B1;B1]  :  2 words$word)
+   )))`;
+
+
+(*val privLevel_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege*)
+
+val _ = Define `
+ ((privLevel_of_bits:(2)words$word -> riscv_sequential_types$Privilege) p=   
+ (let b__0 = p in
+   if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then User
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Supervisor
+   else Machine))`;
+
+
+(*val privLevel_to_str : Riscv_sequential_types.Privilege -> string*)
+
+val _ = Define `
+ ((privLevel_to_str:riscv_sequential_types$Privilege -> string) p=  ((case p of   User => "U" | Supervisor => "S" | Machine => "M" )))`;
+
+
+(*val AccessType_of_num : Num.integer -> Riscv_sequential_types.AccessType*)
+
+val _ = Define `
+ ((AccessType_of_num:int -> riscv_sequential_types$AccessType) arg_=   
+ (let l__74 = arg_ in
+   if (((l__74 = (( 0 : int):sail_values$ii)))) then Read
+   else if (((l__74 = (( 1 : int):sail_values$ii)))) then Write
+   else if (((l__74 = (( 2 : int):sail_values$ii)))) then ReadWrite
+   else Execute))`;
+
+
+(*val num_of_AccessType : Riscv_sequential_types.AccessType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_AccessType:riscv_sequential_types$AccessType -> int) arg_=   
+ ((case arg_ of   Read => (( 0 : int):sail_values$ii) | Write => (( 1 : int):sail_values$ii) | ReadWrite => (( 2 : int):sail_values$ii) | Execute => (( 3 : int):sail_values$ii) )))`;
+
+
+(*val ReadType_of_num : Num.integer -> Riscv_sequential_types.ReadType*)
+
+val _ = Define `
+ ((ReadType_of_num:int -> riscv_sequential_types$ReadType) arg_=   
+ (let l__73 = arg_ in
+   if (((l__73 = (( 0 : int):sail_values$ii)))) then Instruction
+   else Data))`;
+
+
+(*val num_of_ReadType : Riscv_sequential_types.ReadType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_ReadType:riscv_sequential_types$ReadType -> int) arg_=  ((case arg_ of   Instruction => (( 0 : int):sail_values$ii) | Data => (( 1 : int):sail_values$ii) )))`;
+
+
+(*val ExceptionType_of_num : Num.integer -> Riscv_sequential_types.ExceptionType*)
+
+val _ = Define `
+ ((ExceptionType_of_num:int -> riscv_sequential_types$ExceptionType) arg_=   
+ (let l__58 = arg_ in
+   if (((l__58 = (( 0 : int):sail_values$ii)))) then E_Fetch_Addr_Align
+   else if (((l__58 = (( 1 : int):sail_values$ii)))) then E_Fetch_Access_Fault
+   else if (((l__58 = (( 2 : int):sail_values$ii)))) then E_Illegal_Instr
+   else if (((l__58 = (( 3 : int):sail_values$ii)))) then E_Breakpoint
+   else if (((l__58 = (( 4 : int):sail_values$ii)))) then E_Load_Addr_Align
+   else if (((l__58 = (( 5 : int):sail_values$ii)))) then E_Load_Access_Fault
+   else if (((l__58 = (( 6 : int):sail_values$ii)))) then E_SAMO_Addr_Align
+   else if (((l__58 = (( 7 : int):sail_values$ii)))) then E_SAMO_Access_Fault
+   else if (((l__58 = (( 8 : int):sail_values$ii)))) then E_U_EnvCall
+   else if (((l__58 = (( 9 : int):sail_values$ii)))) then E_S_EnvCall
+   else if (((l__58 = (( 10 : int):sail_values$ii)))) then E_Reserved_10
+   else if (((l__58 = (( 11 : int):sail_values$ii)))) then E_M_EnvCall
+   else if (((l__58 = (( 12 : int):sail_values$ii)))) then E_Fetch_Page_Fault
+   else if (((l__58 = (( 13 : int):sail_values$ii)))) then E_Load_Page_Fault
+   else if (((l__58 = (( 14 : int):sail_values$ii)))) then E_Reserved_14
+   else E_SAMO_Page_Fault))`;
+
+
+(*val num_of_ExceptionType : Riscv_sequential_types.ExceptionType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_ExceptionType:riscv_sequential_types$ExceptionType -> int) arg_=   
+ ((case arg_ of
+     E_Fetch_Addr_Align => (( 0 : int):sail_values$ii)
+   | E_Fetch_Access_Fault => (( 1 : int):sail_values$ii)
+   | E_Illegal_Instr => (( 2 : int):sail_values$ii)
+   | E_Breakpoint => (( 3 : int):sail_values$ii)
+   | E_Load_Addr_Align => (( 4 : int):sail_values$ii)
+   | E_Load_Access_Fault => (( 5 : int):sail_values$ii)
+   | E_SAMO_Addr_Align => (( 6 : int):sail_values$ii)
+   | E_SAMO_Access_Fault => (( 7 : int):sail_values$ii)
+   | E_U_EnvCall => (( 8 : int):sail_values$ii)
+   | E_S_EnvCall => (( 9 : int):sail_values$ii)
+   | E_Reserved_10 => (( 10 : int):sail_values$ii)
+   | E_M_EnvCall => (( 11 : int):sail_values$ii)
+   | E_Fetch_Page_Fault => (( 12 : int):sail_values$ii)
+   | E_Load_Page_Fault => (( 13 : int):sail_values$ii)
+   | E_Reserved_14 => (( 14 : int):sail_values$ii)
+   | E_SAMO_Page_Fault => (( 15 : int):sail_values$ii)
+   )))`;
+
+
+(*val exceptionType_to_bits : Riscv_sequential_types.ExceptionType -> Machine_word.mword Machine_word.ty4*)
+
+val _ = Define `
+ ((exceptionType_to_bits:riscv_sequential_types$ExceptionType ->(4)words$word) e=   
+ ((case e of
+     E_Fetch_Addr_Align => (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+   | E_Fetch_Access_Fault => (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)
+   | E_Illegal_Instr => (vec_of_bits [B0;B0;B1;B0]  :  4 words$word)
+   | E_Breakpoint => (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+   | E_Load_Addr_Align => (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)
+   | E_Load_Access_Fault => (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)
+   | E_SAMO_Addr_Align => (vec_of_bits [B0;B1;B1;B0]  :  4 words$word)
+   | E_SAMO_Access_Fault => (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)
+   | E_U_EnvCall => (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)
+   | E_S_EnvCall => (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)
+   | E_Reserved_10 => (vec_of_bits [B1;B0;B1;B0]  :  4 words$word)
+   | E_M_EnvCall => (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)
+   | E_Fetch_Page_Fault => (vec_of_bits [B1;B1;B0;B0]  :  4 words$word)
+   | E_Load_Page_Fault => (vec_of_bits [B1;B1;B0;B1]  :  4 words$word)
+   | E_Reserved_14 => (vec_of_bits [B1;B1;B1;B0]  :  4 words$word)
+   | E_SAMO_Page_Fault => (vec_of_bits [B1;B1;B1;B1]  :  4 words$word)
+   )))`;
+
+
+(*val exceptionType_to_str : Riscv_sequential_types.ExceptionType -> string*)
+
+val _ = Define `
+ ((exceptionType_to_str:riscv_sequential_types$ExceptionType -> string) e=   
+ ((case e of
+     E_Fetch_Addr_Align => "fisaligned-fetch"
+   | E_Fetch_Access_Fault => "fetch-access-fault"
+   | E_Illegal_Instr => "illegal-instruction"
+   | E_Breakpoint => "breakpoint"
+   | E_Load_Addr_Align => "misaligned-load"
+   | E_Load_Access_Fault => "load-access-fault"
+   | E_SAMO_Addr_Align => "misaliged-store/amo"
+   | E_SAMO_Access_Fault => "store/amo-access-fault"
+   | E_U_EnvCall => "u-call"
+   | E_S_EnvCall => "s-call"
+   | E_Reserved_10 => "reserved-0"
+   | E_M_EnvCall => "m-call"
+   | E_Fetch_Page_Fault => "fetch-page-fault"
+   | E_Load_Page_Fault => "load-page-fault"
+   | E_Reserved_14 => "reserved-1"
+   | E_SAMO_Page_Fault => "store/amo-page-fault"
+   )))`;
+
+
+(*val InterruptType_of_num : Num.integer -> Riscv_sequential_types.InterruptType*)
+
+val _ = Define `
+ ((InterruptType_of_num:int -> riscv_sequential_types$InterruptType) arg_=   
+ (let l__50 = arg_ in
+   if (((l__50 = (( 0 : int):sail_values$ii)))) then I_U_Software
+   else if (((l__50 = (( 1 : int):sail_values$ii)))) then I_S_Software
+   else if (((l__50 = (( 2 : int):sail_values$ii)))) then I_M_Software
+   else if (((l__50 = (( 3 : int):sail_values$ii)))) then I_U_Timer
+   else if (((l__50 = (( 4 : int):sail_values$ii)))) then I_S_Timer
+   else if (((l__50 = (( 5 : int):sail_values$ii)))) then I_M_Timer
+   else if (((l__50 = (( 6 : int):sail_values$ii)))) then I_U_External
+   else if (((l__50 = (( 7 : int):sail_values$ii)))) then I_S_External
+   else I_M_External))`;
+
+
+(*val num_of_InterruptType : Riscv_sequential_types.InterruptType -> Num.integer*)
+
+val _ = Define `
+ ((num_of_InterruptType:riscv_sequential_types$InterruptType -> int) arg_=   
+ ((case arg_ of
+     I_U_Software => (( 0 : int):sail_values$ii)
+   | I_S_Software => (( 1 : int):sail_values$ii)
+   | I_M_Software => (( 2 : int):sail_values$ii)
+   | I_U_Timer => (( 3 : int):sail_values$ii)
+   | I_S_Timer => (( 4 : int):sail_values$ii)
+   | I_M_Timer => (( 5 : int):sail_values$ii)
+   | I_U_External => (( 6 : int):sail_values$ii)
+   | I_S_External => (( 7 : int):sail_values$ii)
+   | I_M_External => (( 8 : int):sail_values$ii)
+   )))`;
+
+
+(*val interruptType_to_bits : Riscv_sequential_types.InterruptType -> Machine_word.mword Machine_word.ty4*)
+
+val _ = Define `
+ ((interruptType_to_bits:riscv_sequential_types$InterruptType ->(4)words$word) i=   
+ ((case i of
+     I_U_Software => (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)
+   | I_S_Software => (vec_of_bits [B0;B0;B0;B1]  :  4 words$word)
+   | I_M_Software => (vec_of_bits [B0;B0;B1;B1]  :  4 words$word)
+   | I_U_Timer => (vec_of_bits [B0;B1;B0;B0]  :  4 words$word)
+   | I_S_Timer => (vec_of_bits [B0;B1;B0;B1]  :  4 words$word)
+   | I_M_Timer => (vec_of_bits [B0;B1;B1;B1]  :  4 words$word)
+   | I_U_External => (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)
+   | I_S_External => (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)
+   | I_M_External => (vec_of_bits [B1;B0;B1;B1]  :  4 words$word)
+   )))`;
+
+
+(*val TrapVectorMode_of_num : Num.integer -> Riscv_sequential_types.TrapVectorMode*)
+
+val _ = Define `
+ ((TrapVectorMode_of_num:int -> riscv_sequential_types$TrapVectorMode) arg_=   
+ (let l__48 = arg_ in
+   if (((l__48 = (( 0 : int):sail_values$ii)))) then TV_Direct
+   else if (((l__48 = (( 1 : int):sail_values$ii)))) then TV_Vector
+   else TV_Reserved))`;
+
+
+(*val num_of_TrapVectorMode : Riscv_sequential_types.TrapVectorMode -> Num.integer*)
+
+val _ = Define `
+ ((num_of_TrapVectorMode:riscv_sequential_types$TrapVectorMode -> int) arg_=   
+ ((case arg_ of   TV_Direct => (( 0 : int):sail_values$ii) | TV_Vector => (( 1 : int):sail_values$ii) | TV_Reserved => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val trapVectorMode_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.TrapVectorMode*)
+
+val _ = Define `
+ ((trapVectorMode_of_bits:(2)words$word -> riscv_sequential_types$TrapVectorMode) m=   
+ (let b__0 = m in
+   if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then TV_Direct
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then TV_Vector
+   else TV_Reserved))`;
+
+
+(*val not_implemented : forall 'a. string -> Riscv_sequential_types.M 'a*)
+
+val _ = Define `
+ ((not_implemented:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) message=  (throwS (Error_not_implemented message)))`;
+
+
+(*val internal_error : forall 'a. string -> Riscv_sequential_types.M 'a*)
+
+val _ = Define `
+ ((internal_error:string ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(('a,(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) s=  (seqS (assert_expS F s) (throwS (Error_internal_error () ))))`;
+
+
+(*val ExtStatus_of_num : Num.integer -> Riscv_sequential_types.ExtStatus*)
+
+val _ = Define `
+ ((ExtStatus_of_num:int -> riscv_sequential_types$ExtStatus) arg_=   
+ (let l__45 = arg_ in
+   if (((l__45 = (( 0 : int):sail_values$ii)))) then Off
+   else if (((l__45 = (( 1 : int):sail_values$ii)))) then Initial
+   else if (((l__45 = (( 2 : int):sail_values$ii)))) then Clean
+   else Dirty))`;
+
+
+(*val num_of_ExtStatus : Riscv_sequential_types.ExtStatus -> Num.integer*)
+
+val _ = Define `
+ ((num_of_ExtStatus:riscv_sequential_types$ExtStatus -> int) arg_=   
+ ((case arg_ of   Off => (( 0 : int):sail_values$ii) | Initial => (( 1 : int):sail_values$ii) | Clean => (( 2 : int):sail_values$ii) | Dirty => (( 3 : int):sail_values$ii) )))`;
+
+
+(*val extStatus_to_bits : Riscv_sequential_types.ExtStatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((extStatus_to_bits:riscv_sequential_types$ExtStatus ->(2)words$word) e=   
+ ((case e of
+     Off => (vec_of_bits [B0;B0]  :  2 words$word)
+   | Initial => (vec_of_bits [B0;B1]  :  2 words$word)
+   | Clean => (vec_of_bits [B1;B0]  :  2 words$word)
+   | Dirty => (vec_of_bits [B1;B1]  :  2 words$word)
+   )))`;
+
+
+(*val extStatus_of_bits : Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.ExtStatus*)
+
+val _ = Define `
+ ((extStatus_of_bits:(2)words$word -> riscv_sequential_types$ExtStatus) e=   
+ (let b__0 = e in
+   if (((b__0 = (vec_of_bits [B0;B0]  :  2 words$word)))) then Off
+   else if (((b__0 = (vec_of_bits [B0;B1]  :  2 words$word)))) then Initial
+   else if (((b__0 = (vec_of_bits [B1;B0]  :  2 words$word)))) then Clean
+   else Dirty))`;
+
+
+(*val SATPMode_of_num : Num.integer -> Riscv_sequential_types.SATPMode*)
+
+val _ = Define `
+ ((SATPMode_of_num:int -> riscv_sequential_types$SATPMode) arg_=   
+ (let l__43 = arg_ in
+   if (((l__43 = (( 0 : int):sail_values$ii)))) then Sbare
+   else if (((l__43 = (( 1 : int):sail_values$ii)))) then Sv32
+   else Sv39))`;
+
+
+(*val num_of_SATPMode : Riscv_sequential_types.SATPMode -> Num.integer*)
+
+val _ = Define `
+ ((num_of_SATPMode:riscv_sequential_types$SATPMode -> int) arg_=  ((case arg_ of   Sbare => (( 0 : int):sail_values$ii) | Sv32 => (( 1 : int):sail_values$ii) | Sv39 => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val satpMode_of_bits : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty4 -> Maybe.maybe Riscv_sequential_types.SATPMode*)
+
+val _ = Define `
+ ((satpMode_of_bits:riscv_sequential_types$Architecture ->(4)words$word ->(riscv_sequential_types$SATPMode)option) (a : riscv_sequential_types$Architecture) (m : riscv_sequential_types$satp_mode)= 
+  ((case (a, m) of   (g__113, b__0) => SOME Sbare )))`;
+
+
+(*val uop_of_num : Num.integer -> Riscv_sequential_types.uop*)
+
+val _ = Define `
+ ((uop_of_num:int -> riscv_sequential_types$uop) arg_=   
+ (let l__42 = arg_ in
+   if (((l__42 = (( 0 : int):sail_values$ii)))) then RISCV_LUI
+   else RISCV_AUIPC))`;
+
+
+(*val num_of_uop : Riscv_sequential_types.uop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_uop:riscv_sequential_types$uop -> int) arg_=  ((case arg_ of   RISCV_LUI => (( 0 : int):sail_values$ii) | RISCV_AUIPC => (( 1 : int):sail_values$ii) )))`;
+
+
+(*val bop_of_num : Num.integer -> Riscv_sequential_types.bop*)
+
+val _ = Define `
+ ((bop_of_num:int -> riscv_sequential_types$bop) arg_=   
+ (let l__37 = arg_ in
+   if (((l__37 = (( 0 : int):sail_values$ii)))) then RISCV_BEQ
+   else if (((l__37 = (( 1 : int):sail_values$ii)))) then RISCV_BNE
+   else if (((l__37 = (( 2 : int):sail_values$ii)))) then RISCV_BLT
+   else if (((l__37 = (( 3 : int):sail_values$ii)))) then RISCV_BGE
+   else if (((l__37 = (( 4 : int):sail_values$ii)))) then RISCV_BLTU
+   else RISCV_BGEU))`;
+
+
+(*val num_of_bop : Riscv_sequential_types.bop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_bop:riscv_sequential_types$bop -> int) arg_=   
+ ((case arg_ of
+     RISCV_BEQ => (( 0 : int):sail_values$ii)
+   | RISCV_BNE => (( 1 : int):sail_values$ii)
+   | RISCV_BLT => (( 2 : int):sail_values$ii)
+   | RISCV_BGE => (( 3 : int):sail_values$ii)
+   | RISCV_BLTU => (( 4 : int):sail_values$ii)
+   | RISCV_BGEU => (( 5 : int):sail_values$ii)
+   )))`;
+
+
+(*val iop_of_num : Num.integer -> Riscv_sequential_types.iop*)
+
+val _ = Define `
+ ((iop_of_num:int -> riscv_sequential_types$iop) arg_=   
+ (let l__32 = arg_ in
+   if (((l__32 = (( 0 : int):sail_values$ii)))) then RISCV_ADDI
+   else if (((l__32 = (( 1 : int):sail_values$ii)))) then RISCV_SLTI
+   else if (((l__32 = (( 2 : int):sail_values$ii)))) then RISCV_SLTIU
+   else if (((l__32 = (( 3 : int):sail_values$ii)))) then RISCV_XORI
+   else if (((l__32 = (( 4 : int):sail_values$ii)))) then RISCV_ORI
+   else RISCV_ANDI))`;
+
+
+(*val num_of_iop : Riscv_sequential_types.iop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_iop:riscv_sequential_types$iop -> int) arg_=   
+ ((case arg_ of
+     RISCV_ADDI => (( 0 : int):sail_values$ii)
+   | RISCV_SLTI => (( 1 : int):sail_values$ii)
+   | RISCV_SLTIU => (( 2 : int):sail_values$ii)
+   | RISCV_XORI => (( 3 : int):sail_values$ii)
+   | RISCV_ORI => (( 4 : int):sail_values$ii)
+   | RISCV_ANDI => (( 5 : int):sail_values$ii)
+   )))`;
+
+
+(*val sop_of_num : Num.integer -> Riscv_sequential_types.sop*)
+
+val _ = Define `
+ ((sop_of_num:int -> riscv_sequential_types$sop) arg_=   
+ (let l__30 = arg_ in
+   if (((l__30 = (( 0 : int):sail_values$ii)))) then RISCV_SLLI
+   else if (((l__30 = (( 1 : int):sail_values$ii)))) then RISCV_SRLI
+   else RISCV_SRAI))`;
+
+
+(*val num_of_sop : Riscv_sequential_types.sop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_sop:riscv_sequential_types$sop -> int) arg_=   
+ ((case arg_ of   RISCV_SLLI => (( 0 : int):sail_values$ii) | RISCV_SRLI => (( 1 : int):sail_values$ii) | RISCV_SRAI => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val rop_of_num : Num.integer -> Riscv_sequential_types.rop*)
+
+val _ = Define `
+ ((rop_of_num:int -> riscv_sequential_types$rop) arg_=   
+ (let l__21 = arg_ in
+   if (((l__21 = (( 0 : int):sail_values$ii)))) then RISCV_ADD
+   else if (((l__21 = (( 1 : int):sail_values$ii)))) then RISCV_SUB
+   else if (((l__21 = (( 2 : int):sail_values$ii)))) then RISCV_SLL
+   else if (((l__21 = (( 3 : int):sail_values$ii)))) then RISCV_SLT
+   else if (((l__21 = (( 4 : int):sail_values$ii)))) then RISCV_SLTU
+   else if (((l__21 = (( 5 : int):sail_values$ii)))) then RISCV_XOR
+   else if (((l__21 = (( 6 : int):sail_values$ii)))) then RISCV_SRL
+   else if (((l__21 = (( 7 : int):sail_values$ii)))) then RISCV_SRA
+   else if (((l__21 = (( 8 : int):sail_values$ii)))) then RISCV_OR
+   else RISCV_AND))`;
+
+
+(*val num_of_rop : Riscv_sequential_types.rop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_rop:riscv_sequential_types$rop -> int) arg_=   
+ ((case arg_ of
+     RISCV_ADD => (( 0 : int):sail_values$ii)
+   | RISCV_SUB => (( 1 : int):sail_values$ii)
+   | RISCV_SLL => (( 2 : int):sail_values$ii)
+   | RISCV_SLT => (( 3 : int):sail_values$ii)
+   | RISCV_SLTU => (( 4 : int):sail_values$ii)
+   | RISCV_XOR => (( 5 : int):sail_values$ii)
+   | RISCV_SRL => (( 6 : int):sail_values$ii)
+   | RISCV_SRA => (( 7 : int):sail_values$ii)
+   | RISCV_OR => (( 8 : int):sail_values$ii)
+   | RISCV_AND => (( 9 : int):sail_values$ii)
+   )))`;
+
+
+(*val ropw_of_num : Num.integer -> Riscv_sequential_types.ropw*)
+
+val _ = Define `
+ ((ropw_of_num:int -> riscv_sequential_types$ropw) arg_=   
+ (let l__17 = arg_ in
+   if (((l__17 = (( 0 : int):sail_values$ii)))) then RISCV_ADDW
+   else if (((l__17 = (( 1 : int):sail_values$ii)))) then RISCV_SUBW
+   else if (((l__17 = (( 2 : int):sail_values$ii)))) then RISCV_SLLW
+   else if (((l__17 = (( 3 : int):sail_values$ii)))) then RISCV_SRLW
+   else RISCV_SRAW))`;
+
+
+(*val num_of_ropw : Riscv_sequential_types.ropw -> Num.integer*)
+
+val _ = Define `
+ ((num_of_ropw:riscv_sequential_types$ropw -> int) arg_=   
+ ((case arg_ of
+     RISCV_ADDW => (( 0 : int):sail_values$ii)
+   | RISCV_SUBW => (( 1 : int):sail_values$ii)
+   | RISCV_SLLW => (( 2 : int):sail_values$ii)
+   | RISCV_SRLW => (( 3 : int):sail_values$ii)
+   | RISCV_SRAW => (( 4 : int):sail_values$ii)
+   )))`;
+
+
+(*val amoop_of_num : Num.integer -> Riscv_sequential_types.amoop*)
+
+val _ = Define `
+ ((amoop_of_num:int -> riscv_sequential_types$amoop) arg_=   
+ (let l__9 = arg_ in
+   if (((l__9 = (( 0 : int):sail_values$ii)))) then AMOSWAP
+   else if (((l__9 = (( 1 : int):sail_values$ii)))) then AMOADD
+   else if (((l__9 = (( 2 : int):sail_values$ii)))) then AMOXOR
+   else if (((l__9 = (( 3 : int):sail_values$ii)))) then AMOAND
+   else if (((l__9 = (( 4 : int):sail_values$ii)))) then AMOOR
+   else if (((l__9 = (( 5 : int):sail_values$ii)))) then AMOMIN
+   else if (((l__9 = (( 6 : int):sail_values$ii)))) then AMOMAX
+   else if (((l__9 = (( 7 : int):sail_values$ii)))) then AMOMINU
+   else AMOMAXU))`;
+
+
+(*val num_of_amoop : Riscv_sequential_types.amoop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_amoop:riscv_sequential_types$amoop -> int) arg_=   
+ ((case arg_ of
+     AMOSWAP => (( 0 : int):sail_values$ii)
+   | AMOADD => (( 1 : int):sail_values$ii)
+   | AMOXOR => (( 2 : int):sail_values$ii)
+   | AMOAND => (( 3 : int):sail_values$ii)
+   | AMOOR => (( 4 : int):sail_values$ii)
+   | AMOMIN => (( 5 : int):sail_values$ii)
+   | AMOMAX => (( 6 : int):sail_values$ii)
+   | AMOMINU => (( 7 : int):sail_values$ii)
+   | AMOMAXU => (( 8 : int):sail_values$ii)
+   )))`;
+
+
+(*val csrop_of_num : Num.integer -> Riscv_sequential_types.csrop*)
+
+val _ = Define `
+ ((csrop_of_num:int -> riscv_sequential_types$csrop) arg_=   
+ (let l__7 = arg_ in
+   if (((l__7 = (( 0 : int):sail_values$ii)))) then CSRRW
+   else if (((l__7 = (( 1 : int):sail_values$ii)))) then CSRRS
+   else CSRRC))`;
+
+
+(*val num_of_csrop : Riscv_sequential_types.csrop -> Num.integer*)
+
+val _ = Define `
+ ((num_of_csrop:riscv_sequential_types$csrop -> int) arg_=  ((case arg_ of   CSRRW => (( 0 : int):sail_values$ii) | CSRRS => (( 1 : int):sail_values$ii) | CSRRC => (( 2 : int):sail_values$ii) )))`;
+
+
+(*val word_width_of_num : Num.integer -> Riscv_sequential_types.word_width*)
+
+val _ = Define `
+ ((word_width_of_num:int -> riscv_sequential_types$word_width) arg_=   
+ (let l__4 = arg_ in
+   if (((l__4 = (( 0 : int):sail_values$ii)))) then BYTE
+   else if (((l__4 = (( 1 : int):sail_values$ii)))) then HALF
+   else if (((l__4 = (( 2 : int):sail_values$ii)))) then WORD
+   else DOUBLE))`;
+
+
+(*val num_of_word_width : Riscv_sequential_types.word_width -> Num.integer*)
+
+val _ = Define `
+ ((num_of_word_width:riscv_sequential_types$word_width -> int) arg_=   
+ ((case arg_ of   BYTE => (( 0 : int):sail_values$ii) | HALF => (( 1 : int):sail_values$ii) | WORD => (( 2 : int):sail_values$ii) | DOUBLE => (( 3 : int):sail_values$ii) )))`;
+
+
+(*val is_aligned_addr : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool*)
+
+val _ = Define `
+ ((is_aligned_addr:(64)words$word -> int -> bool) (addr : riscv_sequential_types$xlenbits) (width : int)= 
+   (((ex_int ((hardware_mod ((lem$w2ui addr)) width)))) = (( 0 : int):sail_values$ii)))`;
+
+
+(*val checked_mem_read : forall 'int8_times_n. Size 'int8_times_n => Riscv_sequential_types.ReadType -> Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+val _ = Define `
+ ((checked_mem_read:riscv_sequential_types$ReadType ->(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (t : riscv_sequential_types$ReadType) (addr : riscv_sequential_types$xlenbits) (width : int)=  (bindS
+   (RISCV_read addr width  : ( ( 'int8_times_n words$word)option) riscv_sequential_types$M) (\ (w__0 :
+      ( 'int8_times_n words$word)option) . 
+   returnS ((case (t, w__0) of
+              (Instruction, NONE) => MemException E_Fetch_Access_Fault
+            | (Data, NONE) => MemException E_Load_Access_Fault
+            | (_, SOME (v)) => MemValue v
+            )))))`;
+
+
+(*val MEMr : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+(*val MEMr_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+(*val MEMr_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+(*val MEMr_reserved : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+(*val MEMr_reserved_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+(*val MEMr_reserved_strong_acquire : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+val _ = Define `
+ ((MEMr:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=  ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+val _ = Define `
+ ((MEMr_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+val _ = Define `
+ ((MEMr_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+val _ = Define `
+ ((MEMr_reserved_strong_acquire:(64)words$word -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width=   
+ ((checked_mem_read Data addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)))`;
+
+
+(*val mem_read : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n))*)
+
+val _ = Define `
+ ((mem_read:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((('int8_times_n words$word)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl res=   
+ (if ((((((aq \/ res))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     returnS (MemException E_Load_Addr_Align)
+   else
+     (case (aq, rl, res) of
+       (F, F, F) => (MEMr addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     | (T, F, F) => (MEMr_acquire addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     | (F, F, T) =>
+        (MEMr_reserved addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     | (T, F, T) =>
+        (MEMr_reserved_acquire addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     | (F, T, F) => throwS (Error_not_implemented "load.rl")
+     | (T, T, F) =>
+        (MEMr_strong_acquire addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     | (F, T, T) => throwS (Error_not_implemented "lr.rl")
+     | (T, T, T) =>
+        (MEMr_reserved_strong_acquire addr width  : ( ( 'int8_times_n words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+     )))`;
+
+
+(*val mem_write_ea : Machine_word.mword Machine_word.ty64 -> Num.integer -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_ea:(64)words$word -> int -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width aq rl con=   
+ (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     returnS (MemException E_SAMO_Addr_Align)
+   else
+     (case (aq, rl, con) of
+       (F, F, F) => seqS (MEMea addr width) (returnS (MemValue () ))
+     | (F, T, F) => seqS (MEMea_release addr width) (returnS (MemValue () ))
+     | (F, F, T) => seqS (MEMea_conditional addr width) (returnS (MemValue () ))
+     | (F, T, T) => seqS (MEMea_conditional_release addr width) (returnS (MemValue () ))
+     | (T, F, F) => throwS (Error_not_implemented "store.aq")
+     | (T, T, F) => seqS (MEMea_strong_release addr width) (returnS (MemValue () ))
+     | (T, F, T) => throwS (Error_not_implemented "sc.aq")
+     | (T, T, T) => seqS (MEMea_conditional_strong_release addr width) (returnS (MemValue () ))
+     )))`;
+
+
+(*val checked_mem_write : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+val _ = Define `
+ ((checked_mem_write:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (width : int) (data : 'int8_times_n riscv_sequential_types$bits)=  (bindS   
+(RISCV_write addr width data) (\ (w__0 : bool) . 
+   returnS (if w__0 then MemValue () 
+            else MemException E_SAMO_Access_Fault))))`;
+
+
+(*val MEMval : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+(*val MEMval_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+(*val MEMval_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+(*val MEMval_conditional : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+(*val MEMval_conditional_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+(*val MEMval_conditional_strong_release : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+val _ = Define `
+ ((MEMval:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+val _ = Define `
+ ((MEMval_conditional_strong_release:(64)words$word -> int -> 'int8_times_n words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width data=  (checked_mem_write addr width data))`;
+
+
+(*val mem_write_value : forall 'int8_times_n. Size 'int8_times_n => Machine_word.mword Machine_word.ty64 -> Num.integer -> Machine_word.mword 'int8_times_n -> bool -> bool -> bool -> Riscv_sequential_types.M (Riscv_sequential_types.MemoryOpResult unit)*)
+
+val _ = Define `
+ ((mem_write_value:(64)words$word -> int -> 'int8_times_n words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((unit)riscv_sequential_types$MemoryOpResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) addr width value aq rl con=   
+ (if ((((((rl \/ con))) /\ ((~ ((is_aligned_addr addr width))))))) then
+     returnS (MemException E_SAMO_Addr_Align)
+   else
+     (case (aq, rl, con) of
+       (F, F, F) => MEMval addr width value
+     | (F, T, F) => MEMval_release addr width value
+     | (F, F, T) => MEMval_conditional addr width value
+     | (F, T, T) => MEMval_conditional_release addr width value
+     | (T, F, F) => throwS (Error_not_implemented "store.aq")
+     | (T, T, F) => MEMval_strong_release addr width value
+     | (T, F, T) => throwS (Error_not_implemented "sc.aq")
+     | (T, T, T) => MEMval_conditional_strong_release addr width value
+     )))`;
+
+
+(*val _get_Misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Misa:riscv_sequential_types$Misa ->(64)words$word) (Mk_Misa (v))=  v)`;
+
+
+(*val _set_Misa : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Misa v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_SV39_PTE : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64*)
+
+(*val _set_SV39_PTE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Misa_MXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_MXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_MXL : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_MXL:riscv_sequential_types$Misa ->(2)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 62 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_Z:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_Z : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_Z:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_Z : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_Z:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 25 : int):sail_values$ii) (( 25 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_Y:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_Y : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_Y:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_Y : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_Y:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 24 : int):sail_values$ii) (( 24 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_X:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_X : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_X:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 23 : int):sail_values$ii) (( 23 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_X : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_X : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_W:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_W : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_W:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_W : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_W : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_V:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_V : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_V:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_V : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_V : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_U:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_U : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_U:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_U : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_U : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_T:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_T : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_T:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_T : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_T:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_S:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_S : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_S:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_S : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_S:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_R:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_R : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_R:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_R : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_R : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_Q:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_Q : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_Q:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_Q : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_Q:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 16 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_P:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_P : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_P:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_P : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_P:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_O:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_O : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_O:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_O : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_O:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 14 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_N:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_N : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_N:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_N : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_N:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_M:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_M : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_M:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_M : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_M:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_L:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_L : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_L:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_L : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_L:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_K:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_K : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_K:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_K : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_K:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_J:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_J : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_J:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_J : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_J:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_I:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_I : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_I:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_I : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_I:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_H:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_H : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_H:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_H : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_H:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_G:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_G : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_G:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_G : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_G : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_F:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_F : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_F:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_F : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_F:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_E:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_E : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_E:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_E : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_E:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_D:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_D : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_D:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_D : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_D : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_C:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_C : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_C:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_C : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_C:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_B:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_B : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_B:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_B : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_B:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Misa_A:riscv_sequential_types$Misa ->(1)words$word) (Mk_Misa (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Misa_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Misa_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Misa))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   let r = ((get_Misa w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Misa r))))`;
+
+
+(*val _update_Misa_A : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((update_Misa_A:riscv_sequential_types$Misa ->(1)words$word -> riscv_sequential_types$Misa) (Mk_Misa (v)) x=   
+ (Mk_Misa ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.PTE_Bits*)
+
+(*val _get_PTE_Bits_A : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_PTE_Bits_A : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val legalize_misa : Riscv_sequential_types.Misa -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Misa*)
+
+val _ = Define `
+ ((legalize_misa:riscv_sequential_types$Misa ->(64)words$word -> riscv_sequential_types$Misa) (m : riscv_sequential_types$Misa) (v : riscv_sequential_types$xlenbits)=  m)`;
+
+
+(*val _get_Mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Mstatus:riscv_sequential_types$Mstatus ->(64)words$word) (Mk_Mstatus (v))=  v)`;
+
+
+(*val _set_Mstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Mstatus v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SD : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SD:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_SD : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_SD : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mstatus_SXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 35 : int):sail_values$ii) (( 34 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_UXL : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UXL:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_UXL : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*)
+
+(*val _set_Sstatus_UXL : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_TSR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TSR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_TSR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TSR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 22 : int):sail_values$ii) (( 22 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_TW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_TW : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TW:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 21 : int):sail_values$ii) (( 21 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_TVM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_TVM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_TVM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_TVM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 20 : int):sail_values$ii) (( 20 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_MXR : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MXR:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_MXR : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_MXR : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SUM : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SUM:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_SUM : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_SUM : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_MPRV : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPRV:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_MPRV : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPRV:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 17 : int):sail_values$ii) (( 17 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_XS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_XS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_XS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*)
+
+(*val _set_Sstatus_XS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_FS : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_FS:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_FS : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2*)
+
+(*val _set_Sstatus_FS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mstatus_MPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_MPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPP:riscv_sequential_types$Mstatus ->(2)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SPP : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPP:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_SPP : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_SPP : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_MPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_MPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_SPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_SPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_UPIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UPIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_UPIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_UPIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_MIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_MIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_MIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_MIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_SIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_SIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_SIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_SIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word) (Mk_Mstatus (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   let r = ((get_Mstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mstatus r))))`;
+
+
+(*val _update_Mstatus_UIE : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((update_Mstatus_UIE:riscv_sequential_types$Mstatus ->(1)words$word -> riscv_sequential_types$Mstatus) (Mk_Mstatus (v)) x=   
+ (Mk_Mstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sstatus*)
+
+(*val _get_Sstatus_UIE : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sstatus_UIE : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val legalize_mstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((legalize_mstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (o1 : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)=   
+ (let (m : riscv_sequential_types$Mstatus) = (Mk_Mstatus v) in
+   let m = (update_Mstatus_XS m ((extStatus_to_bits Off  :  2 words$word))) in
+   let m =     
+(update_Mstatus_SD m
+       ((bool_to_bits
+           ((((((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_FS m  :  2 words$word))))
+                      :  2 words$word)) = ((extStatus_to_bits Dirty  :  2 words$word))))) \/ (((((extStatus_to_bits ((extStatus_of_bits ((get_Mstatus_XS m  :  2 words$word))))
+                      :  2 words$word)) = ((extStatus_to_bits Dirty  :  2 words$word))))))))
+          :  1 words$word))) in
+   let m = (update_Mstatus_SXL m ((get_Mstatus_SXL o1  :  2 words$word))) in
+   let m = (update_Mstatus_UXL m ((get_Mstatus_UXL o1  :  2 words$word))) in
+   let m = (update_Mstatus_UPIE m ((bool_to_bits F  :  1 words$word))) in
+   update_Mstatus_UIE m ((bool_to_bits F  :  1 words$word))))`;
+
+
+(*val cur_Architecture : unit -> Riscv_sequential_types.M Riscv_sequential_types.Architecture*)
+
+val _ = Define `
+ ((cur_Architecture:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Architecture),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) .  bindS
+   (case w__0 of
+     Machine => bindS      
+(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) .  returnS ((get_Misa_MXL w__1  :  2 words$word)))
+   | Supervisor => bindS      
+(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . 
+      returnS ((get_Mstatus_SXL w__2  :  2 words$word)))
+   | User => bindS      
+(read_regS mstatus_ref) (\ (w__3 : riscv_sequential_types$Mstatus) . 
+      returnS ((get_Mstatus_UXL w__3  :  2 words$word)))
+   ) (\ (a : riscv_sequential_types$arch_xlen) . 
+   (case ((architecture a)) of
+     SOME (a) => returnS a
+   | NONE => internal_error "Invalid current architecture"
+   )))))`;
+
+
+(*val in32BitMode : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((in32BitMode:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS (cur_Architecture () ) (\ (w__0 : riscv_sequential_types$Architecture) .  returnS (((w__0 = RV32))))))`;
+
+
+(*val haveAtomics : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((haveAtomics:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   returnS (((((get_Misa_A w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+
+
+(*val haveRVC : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((haveRVC:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   returnS (((((get_Misa_C w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+
+
+(*val haveMulDiv : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((haveMulDiv:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) . 
+   returnS (((((get_Misa_M w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))`;
+
+
+(*val haveFP : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((haveFP:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS misa_ref) (\ (w__0 : riscv_sequential_types$Misa) .  bindS   
+(read_regS misa_ref) (\ (w__1 : riscv_sequential_types$Misa) . 
+   returnS ((((((((get_Misa_F w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ (((((get_Misa_D w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))))))`;
+
+
+(*val _get_Minterrupts : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Minterrupts:riscv_sequential_types$Minterrupts ->(64)words$word) (Mk_Minterrupts (v))=  v)`;
+
+
+(*val _set_Minterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Minterrupts v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_MEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_MEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_SEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_SEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_SEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_UEI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UEI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_UEI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_UEI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_MTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_MTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_STI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_STI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_STI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_STI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_UTI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_UTI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_UTI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_UTI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_MSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_MSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_MSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_MSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_SSI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_SSI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_SSI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_SSI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word) (Mk_Minterrupts (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Minterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Minterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Minterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) . 
+   let r = ((get_Minterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Minterrupts r))))`;
+
+
+(*val _update_Minterrupts_USI : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((update_Minterrupts_USI:riscv_sequential_types$Minterrupts ->(1)words$word -> riscv_sequential_types$Minterrupts) (Mk_Minterrupts (v)) x=   
+ (Mk_Minterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sinterrupts*)
+
+(*val _get_Sinterrupts_USI : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sinterrupts_USI : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val legalize_mip : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((legalize_mip:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)=   
+ (let v = (Mk_Minterrupts v) in
+   let m = (update_Minterrupts_SEI o1 ((get_Minterrupts_SEI v  :  1 words$word))) in
+   let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v  :  1 words$word))) in
+   update_Minterrupts_SSI m ((get_Minterrupts_SSI v  :  1 words$word))))`;
+
+
+(*val legalize_mie : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((legalize_mie:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)=   
+ (let v = (Mk_Minterrupts v) in
+   let m = (update_Minterrupts_MEI o1 ((get_Minterrupts_MEI v  :  1 words$word))) in
+   let m = (update_Minterrupts_MTI m ((get_Minterrupts_MTI v  :  1 words$word))) in
+   let m = (update_Minterrupts_MSI m ((get_Minterrupts_MSI v  :  1 words$word))) in
+   let m = (update_Minterrupts_SEI m ((get_Minterrupts_SEI v  :  1 words$word))) in
+   let m = (update_Minterrupts_STI m ((get_Minterrupts_STI v  :  1 words$word))) in
+   update_Minterrupts_SSI m ((get_Minterrupts_SSI v  :  1 words$word))))`;
+
+
+(*val legalize_mideleg : Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((legalize_mideleg:riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)=   
+ (let m = (Mk_Minterrupts v) in
+   let m = (update_Minterrupts_MEI m ((bool_to_bits F  :  1 words$word))) in
+   let m = (update_Minterrupts_MTI m ((bool_to_bits F  :  1 words$word))) in
+   update_Minterrupts_MSI m ((bool_to_bits F  :  1 words$word))))`;
+
+
+(*val _get_Medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Medeleg:riscv_sequential_types$Medeleg ->(64)words$word) (Mk_Medeleg (v))=  v)`;
+
+
+(*val _set_Medeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Medeleg v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_SAMO_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 15 : int):sail_values$ii) (( 15 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Load_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 13 : int):sail_values$ii) (( 13 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Page_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Page_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Fetch_Page_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Page_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_MEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_MEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_MEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_MEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 10 : int):sail_values$ii) (( 10 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_SEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_SEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_UEnvCall : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_UEnvCall:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_UEnvCall : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_UEnvCall : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_SAMO_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_SAMO_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_SAMO_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_SAMO_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_SAMO_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_SAMO_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Load_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Load_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Load_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Load_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Load_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Load_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Load_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Breakpoint : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Breakpoint:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Breakpoint : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Breakpoint : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Illegal_Instr : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Illegal_Instr:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Illegal_Instr : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Illegal_Instr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=   
+ ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Fetch_Access_Fault : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Access_Fault:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Access_Fault : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Fetch_Access_Fault : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val _get_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word) (Mk_Medeleg (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Medeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Medeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Medeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let r = ((get_Medeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Medeleg r))))`;
+
+
+(*val _update_Medeleg_Fetch_Addr_Align : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((update_Medeleg_Fetch_Addr_Align:riscv_sequential_types$Medeleg ->(1)words$word -> riscv_sequential_types$Medeleg) (Mk_Medeleg (v)) x=   
+ (Mk_Medeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Sedeleg*)
+
+(*val _get_Sedeleg_Fetch_Addr_Align : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1*)
+
+(*val _set_Sedeleg_Fetch_Addr_Align : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+(*val legalize_medeleg : Riscv_sequential_types.Medeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Medeleg*)
+
+val _ = Define `
+ ((legalize_medeleg:riscv_sequential_types$Medeleg ->(64)words$word -> riscv_sequential_types$Medeleg) (o1 : riscv_sequential_types$Medeleg) (v : riscv_sequential_types$xlenbits)=   
+ (let m = (Mk_Medeleg v) in
+   update_Medeleg_MEnvCall m ((bool_to_bits F  :  1 words$word))))`;
+
+
+(*val _get_Mtvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Mtvec:riscv_sequential_types$Mtvec ->(64)words$word) (Mk_Mtvec (v))=  v)`;
+
+
+(*val _set_Mtvec : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mtvec:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Mtvec v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62*)
+
+val _ = Define `
+ ((get_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word) (Mk_Mtvec (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  62 words$word)))`;
+
+
+(*val _set_Mtvec_Base : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Base:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(62)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . 
+   let r = ((get_Mtvec w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mtvec r))))`;
+
+
+(*val _update_Mtvec_Base : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty62 -> Riscv_sequential_types.Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Base:riscv_sequential_types$Mtvec ->(62)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x=   
+ (Mk_Mtvec ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word) (Mk_Mtvec (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_Mtvec_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mtvec_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mtvec))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mtvec) . 
+   let r = ((get_Mtvec w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mtvec r))))`;
+
+
+(*val _update_Mtvec_Mode : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Mtvec*)
+
+val _ = Define `
+ ((update_Mtvec_Mode:riscv_sequential_types$Mtvec ->(2)words$word -> riscv_sequential_types$Mtvec) (Mk_Mtvec (v)) x=   
+ (Mk_Mtvec ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _update_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.Satp64*)
+
+(*val _get_Satp64_Mode : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4*)
+
+(*val _set_Satp64_Mode : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*)
+
+(*val legalize_tvec : Riscv_sequential_types.Mtvec -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mtvec*)
+
+val _ = Define `
+ ((legalize_tvec:riscv_sequential_types$Mtvec ->(64)words$word -> riscv_sequential_types$Mtvec) (o1 : riscv_sequential_types$Mtvec) (v : riscv_sequential_types$xlenbits)=   
+ (let v = (Mk_Mtvec v) in
+   (case ((trapVectorMode_of_bits ((get_Mtvec_Mode v  :  2 words$word)))) of
+     TV_Direct => v
+   | TV_Vector => v
+   | _ => update_Mtvec_Mode v ((get_Mtvec_Mode o1  :  2 words$word))
+   )))`;
+
+
+(*val _get_Mcause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Mcause:riscv_sequential_types$Mcause ->(64)words$word) (Mk_Mcause (v))=  v)`;
+
+
+(*val _set_Mcause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mcause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Mcause v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1*)
+
+val _ = Define `
+ ((get_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word) (Mk_Mcause (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+(*val _set_Mcause_IsInterrupt : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mcause_IsInterrupt:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . 
+   let r = ((get_Mcause w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mcause r))))`;
+
+
+(*val _update_Mcause_IsInterrupt : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty1 -> Riscv_sequential_types.Mcause*)
+
+val _ = Define `
+ ((update_Mcause_IsInterrupt:riscv_sequential_types$Mcause ->(1)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x=   
+ (Mk_Mcause ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63*)
+
+val _ = Define `
+ ((get_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word) (Mk_Mcause (v))=  ((subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  63 words$word)))`;
+
+
+(*val _set_Mcause_Cause : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Mcause_Cause:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Mcause))sail_values$register_ref ->(63)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Mcause) . 
+   let r = ((get_Mcause w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Mcause r))))`;
+
+
+(*val _update_Mcause_Cause : Riscv_sequential_types.Mcause -> Machine_word.mword Machine_word.ty63 -> Riscv_sequential_types.Mcause*)
+
+val _ = Define `
+ ((update_Mcause_Cause:riscv_sequential_types$Mcause ->(63)words$word -> riscv_sequential_types$Mcause) (Mk_Mcause (v)) x=   
+ (Mk_Mcause ((update_subrange_vec_dec v (( 62 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val tvec_addr : Riscv_sequential_types.Mtvec -> Riscv_sequential_types.Mcause -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((tvec_addr:riscv_sequential_types$Mtvec -> riscv_sequential_types$Mcause ->((64)words$word)option) (m : riscv_sequential_types$Mtvec) (c : riscv_sequential_types$Mcause)=   
+ (let (base : riscv_sequential_types$xlenbits) =     
+((concat_vec ((get_Mtvec_Base m  :  62 words$word)) (vec_of_bits [B0;B0]  :  2 words$word)
+       :  64 words$word)) in
+   (case ((trapVectorMode_of_bits ((get_Mtvec_Mode m  :  2 words$word)))) of
+     TV_Direct => SOME base
+   | TV_Vector =>
+      if (((((get_Mcause_IsInterrupt c  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+      then
+        SOME ((add_vec base
+                 ((shift_bits_left
+                     ((EXTZ (( 64 : int):sail_values$ii) ((get_Mcause_Cause c  :  63 words$word))  :  64 words$word))
+                     (vec_of_bits [B1;B0]  :  2 words$word)
+                    :  64 words$word))
+                :  64 words$word))
+      else SOME base
+   | TV_Reserved => NONE
+   )))`;
+
+
+(*val legalize_xepc : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((legalize_xepc:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) v=  (bindS   
+(haveRVC () ) (\ (w__0 : bool) . 
+   returnS ((and_vec v
+               ((EXTS (( 64 : int):sail_values$ii)
+                   (if w__0 then (vec_of_bits [B1;B1;B0]  :  3 words$word)
+                    else (vec_of_bits [B1;B0;B0]  :  3 words$word))
+                  :  64 words$word))
+              :  64 words$word)))))`;
+
+
+(*val _get_Sstatus : Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Sstatus:riscv_sequential_types$Sstatus ->(64)words$word) (Mk_Sstatus (v))=  v)`;
+
+
+(*val _set_Sstatus : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Sstatus:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Sstatus v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SD:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SD:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 63 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_UXL:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_UXL:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 33 : int):sail_values$ii) (( 32 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_MXR:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_MXR:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 19 : int):sail_values$ii) (( 19 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SUM:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SUM:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 18 : int):sail_values$ii) (( 18 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_XS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_XS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 16 : int):sail_values$ii) (( 15 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_FS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_FS:riscv_sequential_types$Sstatus ->(2)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 14 : int):sail_values$ii) (( 13 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPP:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPP:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_UPIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_UPIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_SIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_SIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word) (Mk_Sstatus (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sstatus_UIE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sstatus))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sstatus) . 
+   let r = ((get_Sstatus w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sstatus r))))`;
+
+
+val _ = Define `
+ ((update_Sstatus_UIE:riscv_sequential_types$Sstatus ->(1)words$word -> riscv_sequential_types$Sstatus) (Mk_Sstatus (v)) x=   
+ (Mk_Sstatus ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val lower_mstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus*)
+
+val _ = Define `
+ ((lower_mstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus) m=   
+ (let s = (Mk_Sstatus ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in
+   let s = (update_Sstatus_SD s ((get_Mstatus_SD m  :  1 words$word))) in
+   let s = (update_Sstatus_UXL s ((get_Mstatus_UXL m  :  2 words$word))) in
+   let s = (update_Sstatus_MXR s ((get_Mstatus_MXR m  :  1 words$word))) in
+   let s = (update_Sstatus_SUM s ((get_Mstatus_SUM m  :  1 words$word))) in
+   let s = (update_Sstatus_XS s ((get_Mstatus_XS m  :  2 words$word))) in
+   let s = (update_Sstatus_FS s ((get_Mstatus_FS m  :  2 words$word))) in
+   let s = (update_Sstatus_SPP s ((get_Mstatus_SPP m  :  1 words$word))) in
+   let s = (update_Sstatus_SPIE s ((get_Mstatus_SPIE m  :  1 words$word))) in
+   let s = (update_Sstatus_UPIE s ((get_Mstatus_UPIE m  :  1 words$word))) in
+   let s = (update_Sstatus_SIE s ((get_Mstatus_SIE m  :  1 words$word))) in
+   update_Sstatus_UIE s ((get_Mstatus_UIE m  :  1 words$word))))`;
+
+
+(*val lift_sstatus : Riscv_sequential_types.Mstatus -> Riscv_sequential_types.Sstatus -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((lift_sstatus:riscv_sequential_types$Mstatus -> riscv_sequential_types$Sstatus -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (s : riscv_sequential_types$Sstatus)=   
+ (let m = (update_Mstatus_SD m ((get_Sstatus_SD s  :  1 words$word))) in
+   let m = (update_Mstatus_UXL m ((get_Sstatus_UXL s  :  2 words$word))) in
+   let m = (update_Mstatus_MXR m ((get_Sstatus_MXR s  :  1 words$word))) in
+   let m = (update_Mstatus_SUM m ((get_Sstatus_SUM s  :  1 words$word))) in
+   let m = (update_Mstatus_XS m ((get_Sstatus_XS s  :  2 words$word))) in
+   let m = (update_Mstatus_FS m ((get_Sstatus_FS s  :  2 words$word))) in
+   let m = (update_Mstatus_SPP m ((get_Sstatus_SPP s  :  1 words$word))) in
+   let m = (update_Mstatus_SPIE m ((get_Sstatus_SPIE s  :  1 words$word))) in
+   let m = (update_Mstatus_UPIE m ((get_Sstatus_UPIE s  :  1 words$word))) in
+   let m = (update_Mstatus_SIE m ((get_Sstatus_SIE s  :  1 words$word))) in
+   update_Mstatus_UIE m ((get_Sstatus_UIE s  :  1 words$word))))`;
+
+
+(*val legalize_sstatus : Riscv_sequential_types.Mstatus -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Mstatus*)
+
+val _ = Define `
+ ((legalize_sstatus:riscv_sequential_types$Mstatus ->(64)words$word -> riscv_sequential_types$Mstatus) (m : riscv_sequential_types$Mstatus) (v : riscv_sequential_types$xlenbits)=  (lift_sstatus m (Mk_Sstatus v)))`;
+
+
+(*val _get_Sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word) (Mk_Sedeleg (v))=  v)`;
+
+
+(*val _set_Sedeleg : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Sedeleg:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Sedeleg v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_UEnvCall:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_UEnvCall:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=   
+ ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_SAMO_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_SAMO_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=   
+ ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Load_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Load_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Breakpoint:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Breakpoint:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Illegal_Instr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Illegal_Instr:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=   
+ ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Access_Fault:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Access_Fault:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word) (Mk_Sedeleg (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sedeleg_Fetch_Addr_Align:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sedeleg))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sedeleg) . 
+   let r = ((get_Sedeleg w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sedeleg r))))`;
+
+
+val _ = Define `
+ ((update_Sedeleg_Fetch_Addr_Align:riscv_sequential_types$Sedeleg ->(1)words$word -> riscv_sequential_types$Sedeleg) (Mk_Sedeleg (v)) x=   
+ (Mk_Sedeleg ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val legalize_sedeleg : Riscv_sequential_types.Sedeleg -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Sedeleg*)
+
+val _ = Define `
+ ((legalize_sedeleg:riscv_sequential_types$Sedeleg ->(64)words$word -> riscv_sequential_types$Sedeleg) (s : riscv_sequential_types$Sedeleg) (v : riscv_sequential_types$xlenbits)=   
+ (Mk_Sedeleg ((EXTZ (( 64 : int):sail_values$ii) ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  9 words$word))  :  64 words$word))))`;
+
+
+(*val _get_Sinterrupts : Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Sinterrupts:riscv_sequential_types$Sinterrupts ->(64)words$word) (Mk_Sinterrupts (v))=  v)`;
+
+
+(*val _set_Sinterrupts : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Sinterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Sinterrupts:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Sinterrupts v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 9 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_UEI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_UEI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_STI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_STI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_UTI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_UTI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_SSI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_SSI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+val _ = Define `
+ ((get_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word) (Mk_Sinterrupts (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_Sinterrupts_USI:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Sinterrupts))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Sinterrupts) . 
+   let r = ((get_Sinterrupts w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Sinterrupts r))))`;
+
+
+val _ = Define `
+ ((update_Sinterrupts_USI:riscv_sequential_types$Sinterrupts ->(1)words$word -> riscv_sequential_types$Sinterrupts) (Mk_Sinterrupts (v)) x=   
+ (Mk_Sinterrupts ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val lower_mip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*)
+
+val _ = Define `
+ ((lower_mip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)=   
+ (let (s : riscv_sequential_types$Sinterrupts) =     
+(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in
+   let s =     
+(update_Sinterrupts_SEI s
+       ((and_vec ((get_Minterrupts_SEI m  :  1 words$word)) ((get_Minterrupts_SEI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_STI s
+       ((and_vec ((get_Minterrupts_STI m  :  1 words$word)) ((get_Minterrupts_STI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_SSI s
+       ((and_vec ((get_Minterrupts_SSI m  :  1 words$word)) ((get_Minterrupts_SSI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_UEI s
+       ((and_vec ((get_Minterrupts_UEI m  :  1 words$word)) ((get_Minterrupts_UEI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_UTI s
+       ((and_vec ((get_Minterrupts_UTI m  :  1 words$word)) ((get_Minterrupts_UTI d  :  1 words$word))
+          :  1 words$word))) in
+   update_Sinterrupts_USI s
+     ((and_vec ((get_Minterrupts_USI m  :  1 words$word)) ((get_Minterrupts_USI d  :  1 words$word))
+        :  1 words$word))))`;
+
+
+(*val lower_mie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts*)
+
+val _ = Define `
+ ((lower_mie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts)=   
+ (let (s : riscv_sequential_types$Sinterrupts) =     
+(Mk_Sinterrupts ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))) in
+   let s =     
+(update_Sinterrupts_SEI s
+       ((and_vec ((get_Minterrupts_SEI m  :  1 words$word)) ((get_Minterrupts_SEI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_STI s
+       ((and_vec ((get_Minterrupts_STI m  :  1 words$word)) ((get_Minterrupts_STI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_SSI s
+       ((and_vec ((get_Minterrupts_SSI m  :  1 words$word)) ((get_Minterrupts_SSI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_UEI s
+       ((and_vec ((get_Minterrupts_UEI m  :  1 words$word)) ((get_Minterrupts_UEI d  :  1 words$word))
+          :  1 words$word))) in
+   let s =     
+(update_Sinterrupts_UTI s
+       ((and_vec ((get_Minterrupts_UTI m  :  1 words$word)) ((get_Minterrupts_UTI d  :  1 words$word))
+          :  1 words$word))) in
+   update_Sinterrupts_USI s
+     ((and_vec ((get_Minterrupts_USI m  :  1 words$word)) ((get_Minterrupts_USI d  :  1 words$word))
+        :  1 words$word))))`;
+
+
+(*val lift_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((lift_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)=   
+ (let (m : riscv_sequential_types$Minterrupts) = o1 in
+   let m =     
+(update_Minterrupts_SSI m
+       ((and_vec ((get_Sinterrupts_SSI s  :  1 words$word)) ((get_Minterrupts_SSI d  :  1 words$word))
+          :  1 words$word))) in
+   let m =     
+(update_Minterrupts_UEI m
+       ((and_vec ((get_Minterrupts_UEI m  :  1 words$word)) ((get_Minterrupts_UEI d  :  1 words$word))
+          :  1 words$word))) in
+   update_Minterrupts_USI m
+     ((and_vec ((get_Minterrupts_USI m  :  1 words$word)) ((get_Minterrupts_USI d  :  1 words$word))
+        :  1 words$word))))`;
+
+
+(*val legalize_sip : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((legalize_sip:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)=   
+ (lift_sip m d (Mk_Sinterrupts v)))`;
+
+
+(*val lift_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Sinterrupts -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((lift_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Sinterrupts -> riscv_sequential_types$Minterrupts) (o1 : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (s : riscv_sequential_types$Sinterrupts)=   
+ (let (m : riscv_sequential_types$Minterrupts) = o1 in
+   let m =     
+(if (((((get_Minterrupts_SEI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+       update_Minterrupts_SEI m ((get_Sinterrupts_SEI s  :  1 words$word))
+     else m) in
+   let m =     
+(if (((((get_Minterrupts_STI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+       update_Minterrupts_STI m ((get_Sinterrupts_STI s  :  1 words$word))
+     else m) in
+   let m =     
+(if (((((get_Minterrupts_SSI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+       update_Minterrupts_SSI m ((get_Sinterrupts_SSI s  :  1 words$word))
+     else m) in
+   let m =     
+(if (((((get_Minterrupts_UEI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+       update_Minterrupts_UEI m ((get_Sinterrupts_UEI s  :  1 words$word))
+     else m) in
+   let m =     
+(if (((((get_Minterrupts_UTI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+       update_Minterrupts_UTI m ((get_Sinterrupts_UTI s  :  1 words$word))
+     else m) in
+   if (((((get_Minterrupts_USI d  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+     update_Minterrupts_USI m ((get_Sinterrupts_USI s  :  1 words$word))
+   else m))`;
+
+
+(*val legalize_sie : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.Minterrupts*)
+
+val _ = Define `
+ ((legalize_sie:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(64)words$word -> riscv_sequential_types$Minterrupts) (m : riscv_sequential_types$Minterrupts) (d : riscv_sequential_types$Minterrupts) (v : riscv_sequential_types$xlenbits)=   
+ (lift_sie m d (Mk_Sinterrupts v)))`;
+
+
+(*val _get_Satp64 : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((get_Satp64:riscv_sequential_types$Satp64 ->(64)words$word) (Mk_Satp64 (v))=  v)`;
+
+
+(*val _set_Satp64 : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Satp64:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_Satp64 v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii)  :  4 words$word)))`;
+
+
+val _ = Define `
+ ((set_Satp64_Mode:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . 
+   let r = ((get_Satp64 w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Satp64 r))))`;
+
+
+val _ = Define `
+ ((update_Satp64_Mode:riscv_sequential_types$Satp64 ->(4)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x=   
+ (Mk_Satp64 ((update_subrange_vec_dec v (( 63 : int):sail_values$ii) (( 60 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16*)
+
+val _ = Define `
+ ((get_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii)  :  16 words$word)))`;
+
+
+(*val _set_Satp64_Asid : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Satp64_Asid:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(16)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . 
+   let r = ((get_Satp64 w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Satp64 r))))`;
+
+
+(*val _update_Satp64_Asid : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty16 -> Riscv_sequential_types.Satp64*)
+
+val _ = Define `
+ ((update_Satp64_Asid:riscv_sequential_types$Satp64 ->(16)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x=   
+ (Mk_Satp64 ((update_subrange_vec_dec v (( 59 : int):sail_values$ii) (( 44 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44*)
+
+val _ = Define `
+ ((get_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word) (Mk_Satp64 (v))=  ((subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  44 words$word)))`;
+
+
+(*val _set_Satp64_PPN : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_Satp64_PPN:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$Satp64))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$Satp64) . 
+   let r = ((get_Satp64 w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_Satp64 r))))`;
+
+
+(*val _update_Satp64_PPN : Riscv_sequential_types.Satp64 -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.Satp64*)
+
+val _ = Define `
+ ((update_Satp64_PPN:riscv_sequential_types$Satp64 ->(44)words$word -> riscv_sequential_types$Satp64) (Mk_Satp64 (v)) x=   
+ (Mk_Satp64 ((update_subrange_vec_dec v (( 43 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val legalize_satp : Riscv_sequential_types.Architecture -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64 -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((legalize_satp:riscv_sequential_types$Architecture ->(64)words$word ->(64)words$word ->(64)words$word) (a : riscv_sequential_types$Architecture) (o1 : riscv_sequential_types$xlenbits) (v : riscv_sequential_types$xlenbits)=   
+ (let s = (Mk_Satp64 v) in
+   (case ((satpMode_of_bits a ((get_Satp64_Mode s  :  4 words$word)))) of
+     NONE => o1
+   | SOME (Sv32) => o1
+   | SOME (_) => (get_Satp64 s  :  64 words$word)
+   )))`;
+
+
+(*val csr_name : Machine_word.mword Machine_word.ty12 -> string*)
+
+val _ = Define `
+ ((csr_name:(12)words$word -> string) csr=   
+ (let b__0 = csr in
+   if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "ustatus"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "uie"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "utvec"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "fflags"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "frm"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "fcsr"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "cycle"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "time"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "instret"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "cycleh"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "timeh"
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "instreth"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "sstatus"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "sedeleg"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "sideleg"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "sie"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "stvec"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     "scounteren"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "sscratch"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "sepc"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "scause"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "stval"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "sip"
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "satp"
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     "mvendorid"
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     "marchid"
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mimpid"
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mhartid"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mstatus"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "misa"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "medeleg"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mideleg"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mie"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     "mtvec"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     "mcounteren"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mscratch"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     "mepc"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "mcause"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     "mtval"
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     "mip"
+   else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mcycle"
+   else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "minstret"
+   else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     "mcycleh"
+   else if (((b__0 = (vec_of_bits [B1;B0;B1;B1;B1;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     "minstreth"
+   else "UNKNOWN"))`;
+
+
+(*val csrAccess : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((csrAccess:(12)words$word ->(2)words$word) csr=  ((subrange_vec_dec csr (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val csrPriv : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((csrPriv:(12)words$word ->(2)words$word) csr=  ((subrange_vec_dec csr (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val is_CSR_defined : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool*)
+
+val _ = Define `
+ ((is_CSR_defined:(12)words$word -> riscv_sequential_types$Privilege -> bool) (csr : 12 riscv_sequential_types$bits) (p : riscv_sequential_types$Privilege)=   
+ (let b__0 = csr in
+   if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     (((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B1;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     ((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word))))) \/ (((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))))
+   else F))`;
+
+
+(*val check_CSR_access : Machine_word.mword Machine_word.ty2 -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.Privilege -> bool -> bool*)
+
+val _ = Define `
+ ((check_CSR_access:(2)words$word ->(2)words$word -> riscv_sequential_types$Privilege -> bool -> bool) csrrw csrpr p isWrite= 
+   (((~ ((((((((bool_to_bits isWrite  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((csrrw = (vec_of_bits [B1;B1]  :  2 words$word))))))))) /\ ((((lem$w2ui ((privLevel_to_bits p  :  2 words$word))) >= (lem$w2ui csrpr))))))`;
+
+
+(*val check_TVM_SATP : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((check_TVM_SATP:(12)words$word -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege)=  (bindS   
+(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+   returnS ((~ ((((((csr = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) /\ ((((((((privLevel_to_bits p  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))) /\ (((((get_Mstatus_TVM w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))))))))))`;
+
+
+(*val check_CSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.Privilege -> bool -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((check_CSR:(12)words$word -> riscv_sequential_types$Privilege -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (p : riscv_sequential_types$Privilege) (isWrite : bool)=  (bindS   
+(check_TVM_SATP csr p) (\ (w__0 : bool) . 
+   returnS (((((is_CSR_defined csr p)) /\ (((((check_CSR_access ((csrAccess csr  :  2 words$word)) ((csrPriv csr  :  2 words$word)) p
+                       isWrite)) /\ w__0)))))))))`;
+
+
+(*val exception_delegatee : Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.Privilege*)
+
+val _ = Define `
+ ((exception_delegatee:riscv_sequential_types$ExceptionType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$Privilege),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (e : riscv_sequential_types$ExceptionType) (p : riscv_sequential_types$Privilege)=   
+ (let idx = (num_of_ExceptionType e) in bindS   
+(read_regS medeleg_ref) (\ (w__0 : riscv_sequential_types$Medeleg) . 
+   let super = (access_vec_dec ((get_Medeleg w__0  :  64 words$word)) idx) in bindS   
+(read_regS sedeleg_ref) (\ (w__1 : riscv_sequential_types$Sedeleg) . 
+   let user = (access_vec_dec ((get_Sedeleg w__1  :  64 words$word)) idx) in bindS   
+(read_regS misa_ref) (\ (w__2 : riscv_sequential_types$Misa) . 
+   let deleg =     
+(if ((((((((get_Misa_S w__2  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((bit_to_bool super))))) then
+       Supervisor
+     else Machine) in
+   returnS (if ((((lem$w2ui ((privLevel_to_bits deleg  :  2 words$word))) < (lem$w2ui ((privLevel_to_bits p  :  2 words$word)))))) then
+              p
+            else deleg))))))`;
+
+
+(*val findPendingInterrupt : Machine_word.mword Machine_word.ty64 -> Maybe.maybe Riscv_sequential_types.InterruptType*)
+
+val _ = Define `
+ ((findPendingInterrupt:(64)words$word ->(riscv_sequential_types$InterruptType)option) ip=   
+ (let ip = (Mk_Minterrupts ip) in
+   if (((((get_Minterrupts_MEI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+     SOME I_M_External
+   else if (((((get_Minterrupts_MSI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_M_Software
+   else if (((((get_Minterrupts_MTI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_M_Timer
+   else if (((((get_Minterrupts_SEI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_S_External
+   else if (((((get_Minterrupts_SSI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_S_Software
+   else if (((((get_Minterrupts_STI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_S_Timer
+   else if (((((get_Minterrupts_UEI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_U_External
+   else if (((((get_Minterrupts_USI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_U_Software
+   else if (((((get_Minterrupts_UTI ip  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+   then
+     SOME I_U_Timer
+   else NONE))`;
+
+
+(*val curInterrupt : Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.Minterrupts -> Riscv_sequential_types.M (Maybe.maybe ((Riscv_sequential_types.InterruptType * Riscv_sequential_types.Privilege)))*)
+
+val _ = Define `
+ ((curInterrupt:riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts -> riscv_sequential_types$Minterrupts ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((riscv_sequential_types$InterruptType#riscv_sequential_types$Privilege)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (pend : riscv_sequential_types$Minterrupts) (enbl : riscv_sequential_types$Minterrupts) (delg : riscv_sequential_types$Minterrupts)=   
+ (let (en_mip : riscv_sequential_types$xlenbits) =     
+((and_vec ((get_Minterrupts pend  :  64 words$word)) ((get_Minterrupts enbl  :  64 words$word))
+       :  64 words$word)) in
+   if (((en_mip = ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))) then
+     returnS NONE
+   else
+     let eff_mip =       
+((and_vec en_mip ((not_vec ((get_Minterrupts delg  :  64 words$word))  :  64 words$word))
+         :  64 words$word)) in
+     let eff_sip = ((and_vec en_mip ((get_Minterrupts delg  :  64 words$word))  :  64 words$word)) in bindS     
+(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+     if ((((((((get_Mstatus_MIE w__0  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((eff_mip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))))) then
+       returnS ((case ((findPendingInterrupt eff_mip)) of
+                  SOME (i) =>
+                   let r = (i, Machine) in
+                   SOME r
+                | NONE => NONE
+                ))
+     else bindS       
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) .  bindS       
+(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) .  bindS       
+(read_regS cur_privilege_ref) (\ (w__3 : riscv_sequential_types$Privilege) . 
+       returnS (if ((((((((get_Mstatus_SIE w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((eff_sip <> ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word))))) /\ ((((((((privLevel_to_bits w__2  :  2 words$word)) = ((privLevel_to_bits Supervisor  :  2 words$word))))) \/ (((((privLevel_to_bits w__3  :  2 words$word)) = ((privLevel_to_bits User  :  2 words$word)))))))))))))) then
+                  (case ((findPendingInterrupt eff_sip)) of
+                    SOME (i) =>
+                     let r = (i, Supervisor) in
+                     SOME r
+                  | NONE => NONE
+                  )
+                else NONE)))))))`;
+
+
+(*val tval : Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Machine_word.mword Machine_word.ty64*)
+
+val _ = Define `
+ ((tval:((64)words$word)option ->(64)words$word) excinfo=   
+ ((case excinfo of
+     SOME (e) => e
+   | NONE => (EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)
+   )))`;
+
+
+(*val handle_trap : Riscv_sequential_types.Privilege -> bool -> Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty64 -> Maybe.maybe (Machine_word.mword Machine_word.ty64) -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((handle_trap:riscv_sequential_types$Privilege -> bool ->(4)words$word ->(64)words$word ->(riscv_sequential_types$xlenbits)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (del_priv : riscv_sequential_types$Privilege) (intr : bool) (c : riscv_sequential_types$exc_code) (pc : riscv_sequential_types$xlenbits) (info :
+   riscv_sequential_types$xlenbits option)=   
+ (let (_ : unit) =     
+(prerr_endline
+       ((STRCAT "handling "
+           ((STRCAT (if intr then "int#" else "exc#")
+               ((STRCAT ((string_of_vec c))
+                   ((STRCAT " at priv " ((privLevel_to_str del_priv))))))))))) in
+   (case del_priv of
+     Machine => bindS (seqS (seqS      
+(set_Mcause_IsInterrupt mcause_ref ((bool_to_bits intr  :  1 words$word)))      
+(set_Mcause_Cause mcause_ref ((EXTZ (( 63 : int):sail_values$ii) c  :  63 words$word))))      
+(read_regS mstatus_ref)) (\ (w__0 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(set_Mstatus_MPIE mstatus_ref ((get_Mstatus_MIE w__0  :  1 words$word)))      
+(set_Mstatus_MIE mstatus_ref ((bool_to_bits F  :  1 words$word))))      
+(read_regS cur_privilege_ref)) (\ (w__1 : riscv_sequential_types$Privilege) .  bindS (seqS (seqS (seqS (seqS      
+(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits w__1  :  2 words$word)))      
+(write_regS mtval_ref ((tval info  :  64 words$word))))      
+(write_regS mepc_ref pc))      
+(write_regS cur_privilege_ref del_priv))      
+(read_regS mtvec_ref)) (\ (w__2 : riscv_sequential_types$Mtvec) .  bindS      
+(read_regS mcause_ref) (\ (w__3 : riscv_sequential_types$Mcause) . 
+      (case ((tvec_addr w__2 w__3  :  ( 64 words$word)option)) of
+        SOME (epc) => returnS epc
+      | NONE => (internal_error "Invalid mtvec mode"  : ( 64 words$word) riscv_sequential_types$M)
+      )))))
+   | Supervisor => bindS (seqS (seqS      
+(set_Mcause_IsInterrupt scause_ref ((bool_to_bits intr  :  1 words$word)))      
+(set_Mcause_Cause scause_ref ((EXTZ (( 63 : int):sail_values$ii) c  :  63 words$word))))      
+(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(set_Mstatus_SPIE mstatus_ref ((get_Mstatus_SIE w__6  :  1 words$word)))      
+(set_Mstatus_SIE mstatus_ref ((bool_to_bits F  :  1 words$word))))      
+(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) .  bindS
+      (case w__7 of
+        User => returnS ((bool_to_bits F  :  1 words$word))
+      | Supervisor => returnS ((bool_to_bits T  :  1 words$word))
+      | Machine => (internal_error "invalid privilege for s-mode trap"  : ( 1 words$word) riscv_sequential_types$M)
+      ) (\ (w__9 :  1 words$word) .  bindS (seqS (seqS (seqS (seqS      
+(set_Mstatus_SPP mstatus_ref w__9)      
+(write_regS stval_ref ((tval info  :  64 words$word))))      
+(write_regS sepc_ref pc))      
+(write_regS cur_privilege_ref del_priv))      
+(read_regS stvec_ref)) (\ (w__10 : riscv_sequential_types$Mtvec) .  bindS      
+(read_regS scause_ref) (\ (w__11 : riscv_sequential_types$Mcause) . 
+      (case ((tvec_addr w__10 w__11  :  ( 64 words$word)option)) of
+        SOME (epc) => returnS epc
+      | NONE => (internal_error "Invalid stvec mode"  : ( 64 words$word) riscv_sequential_types$M)
+      ))))))
+   | User => (internal_error "the N extension is currently unsupported"  : ( 64 words$word) riscv_sequential_types$M)
+   )))`;
+
+
+(*val handle_exception : Riscv_sequential_types.Privilege -> Riscv_sequential_types.ctl_result -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((handle_exception:riscv_sequential_types$Privilege -> riscv_sequential_types$ctl_result ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (cur_priv : riscv_sequential_types$Privilege) (ctl : riscv_sequential_types$ctl_result) (pc : riscv_sequential_types$xlenbits)=   
+ ((case (cur_priv, ctl) of
+     (_, CTL_TRAP (e)) => bindS      
+(exception_delegatee e.sync_exception_trap cur_priv) (\ del_priv . 
+      let (_ : unit) =        
+(prerr_endline
+          ((STRCAT "trapping from "
+              ((STRCAT ((privLevel_to_str cur_priv))
+                  ((STRCAT " to "
+                      ((STRCAT ((privLevel_to_str del_priv))
+                          ((STRCAT " to handle "
+                              ((exceptionType_to_str e.sync_exception_trap))))))))))))) in
+      (handle_trap del_priv F ((exceptionType_to_bits e.sync_exception_trap  :  4 words$word)) pc
+         e.sync_exception_excinfo
+        : ( 64 words$word) riscv_sequential_types$M))
+   | (_, CTL_MRET (_)) => bindS      
+(read_regS cur_privilege_ref) (\ prev_priv .  bindS      
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(set_Mstatus_MIE mstatus_ref ((get_Mstatus_MPIE w__1  :  1 words$word)))      
+(set_Mstatus_MPIE mstatus_ref ((bool_to_bits T  :  1 words$word))))      
+(read_regS mstatus_ref)) (\ (w__2 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(write_regS cur_privilege_ref ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))      
+(set_Mstatus_MPP mstatus_ref ((privLevel_to_bits User  :  2 words$word))))      
+(read_regS cur_privilege_ref)) (\ (w__3 : riscv_sequential_types$Privilege) . 
+      let (_ : unit) =        
+(prerr_endline
+          ((STRCAT "ret-ing from "
+              ((STRCAT ((privLevel_to_str prev_priv))
+                  ((STRCAT " to " ((privLevel_to_str w__3))))))))) in
+      (read_regS mepc_ref  : ( 64 words$word) riscv_sequential_types$M)))))
+   | (_, CTL_SRET (_)) => bindS      
+(read_regS cur_privilege_ref) (\ prev_priv .  bindS      
+(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(set_Mstatus_SIE mstatus_ref ((get_Mstatus_SPIE w__5  :  1 words$word)))      
+(set_Mstatus_SPIE mstatus_ref ((bool_to_bits T  :  1 words$word))))      
+(read_regS mstatus_ref)) (\ (w__6 : riscv_sequential_types$Mstatus) .  bindS (seqS (seqS      
+(write_regS
+        cur_privilege_ref
+        (if (((((get_Mstatus_SPP w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))
+         then
+           Supervisor
+         else User))      
+(set_Mstatus_SPP mstatus_ref ((bool_to_bits F  :  1 words$word))))      
+(read_regS cur_privilege_ref)) (\ (w__7 : riscv_sequential_types$Privilege) . 
+      let (_ : unit) =        
+(prerr_endline
+          ((STRCAT "ret-ing from "
+              ((STRCAT ((privLevel_to_str prev_priv))
+                  ((STRCAT " to " ((privLevel_to_str w__7))))))))) in
+      (read_regS sepc_ref  : ( 64 words$word) riscv_sequential_types$M)))))
+   )))`;
+
+
+(*val handle_mem_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.ExceptionType -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((handle_mem_exception:(64)words$word -> riscv_sequential_types$ExceptionType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (addr : riscv_sequential_types$xlenbits) (e : riscv_sequential_types$ExceptionType)=   
+ (let (t : riscv_sequential_types$sync_exception) = (<| sync_exception_trap := e;  sync_exception_excinfo := (SOME addr) |>) in bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) .  bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) .  bindS
+   (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . 
+   write_regS nextPC_ref w__2)))))`;
+
+
+(*val handle_decode_exception : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((handle_decode_exception:(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) instbits=   
+ (let (t : riscv_sequential_types$sync_exception) =     
+(<| sync_exception_trap := E_Illegal_Instr; 
+        sync_exception_excinfo := (SOME instbits) |>) in bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) .  bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) .  bindS
+   (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . 
+   write_regS nextPC_ref w__2)))))`;
+
+
+(*val handle_interrupt : Riscv_sequential_types.InterruptType -> Riscv_sequential_types.Privilege -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((handle_interrupt:riscv_sequential_types$InterruptType -> riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (i : riscv_sequential_types$InterruptType) (del_priv : riscv_sequential_types$Privilege)=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS
+   (handle_trap del_priv T ((interruptType_to_bits i  :  4 words$word)) w__0 NONE
+     : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) . 
+   write_regS nextPC_ref w__1))))`;
+
+
+(*val handle_illegal : unit -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((handle_illegal:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =   
+ (let (t : riscv_sequential_types$sync_exception) =     
+(<| sync_exception_trap := E_Illegal_Instr; 
+        sync_exception_excinfo := NONE |>) in bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) .  bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) .  bindS
+   (handle_exception w__0 (CTL_TRAP t) w__1  : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 : riscv_sequential_types$xlenbits) . 
+   write_regS nextPC_ref w__2)))))`;
+
+
+(*val init_sys : unit -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((init_sys:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS (seqS (seqS (seqS (seqS (seqS   
+(write_regS cur_privilege_ref Machine)   
+(set_Misa_MXL misa_ref ((arch_to_bits RV64  :  2 words$word))))   
+(set_Misa_C misa_ref ((bool_to_bits T  :  1 words$word))))   
+(set_Misa_U misa_ref ((bool_to_bits T  :  1 words$word))))   
+(set_Misa_S misa_ref ((bool_to_bits T  :  1 words$word))))   
+(read_regS misa_ref)) (\ (w__0 : riscv_sequential_types$Misa) .  bindS (seqS   
+(set_Mstatus_SXL mstatus_ref ((get_Misa_MXL w__0  :  2 words$word)))   
+(read_regS misa_ref)) (\ (w__1 : riscv_sequential_types$Misa) .  seqS (seqS   
+(set_Mstatus_UXL mstatus_ref ((get_Misa_MXL w__1  :  2 words$word)))   
+(set_Mstatus_SD mstatus_ref ((bool_to_bits F  :  1 words$word))))   
+(write_regS mhartid_ref ((EXTZ (( 64 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  64 words$word)))))))`;
+
+
+(*val tick_clock : unit -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((tick_clock:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS mcycle_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   write_regS mcycle_ref ((add_vec_int w__0 (( 1 : int):sail_values$ii)  :  64 words$word)))))`;
+
+
+val _ = Define `
+ ((PAGESIZE_BITS:int)=  ((( 12 : int):sail_values$ii)))`;
+
+
+(*val _get_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_PTE_Bits:riscv_sequential_types$PTE_Bits ->(8)words$word) (Mk_PTE_Bits (v))=  v)`;
+
+
+(*val _set_PTE_Bits : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.PTE_Bits -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_PTE_Bits:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_PTE_Bits v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_D:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_D:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_A:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_A:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_G:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_G:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_U:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_U:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 4 : int):sail_values$ii) (( 4 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_X:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_X:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 3 : int):sail_values$ii) (( 3 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_W:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_W:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_R:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_R:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 1 : int):sail_values$ii) (( 1 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+val _ = Define `
+ ((get_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word) (Mk_PTE_Bits (v))=  ((subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  1 words$word)))`;
+
+
+val _ = Define `
+ ((set_PTE_Bits_V:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$PTE_Bits))sail_values$register_ref ->(1)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$PTE_Bits) . 
+   let r = ((get_PTE_Bits w__0  :  8 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  8 words$word)) in
+   write_regS r_ref (Mk_PTE_Bits r))))`;
+
+
+val _ = Define `
+ ((update_PTE_Bits_V:riscv_sequential_types$PTE_Bits ->(1)words$word -> riscv_sequential_types$PTE_Bits) (Mk_PTE_Bits (v)) x=   
+ (Mk_PTE_Bits ((update_subrange_vec_dec v (( 0 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  8 words$word))))`;
+
+
+(*val isPTEPtr : Machine_word.mword Machine_word.ty8 -> bool*)
+
+val _ = Define `
+ ((isPTEPtr:(8)words$word -> bool) p=   
+ (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+
+
+(*val isInvalidPTE : Machine_word.mword Machine_word.ty8 -> bool*)
+
+val _ = Define `
+ ((isInvalidPTE:(8)words$word -> bool) p=   
+ (let a = (Mk_PTE_Bits p) in
+   ((((((get_PTE_Bits_V a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ ((((((((get_PTE_Bits_W a  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_R a  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))))))))`;
+
+
+(*val checkPTEPermission : Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((checkPTEPermission:riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> riscv_sequential_types$PTE_Bits ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (ac : riscv_sequential_types$AccessType) (priv : riscv_sequential_types$Privilege) (mxr : bool) (sum : bool) (p : riscv_sequential_types$PTE_Bits)=   
+ ((case (ac, priv) of
+     (Read, User) =>
+      returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
+   | (Write, User) =>
+      returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (ReadWrite, User) =>
+      returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
+   | (Execute, User) =>
+      returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (Read, Supervisor) =>
+      returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr)))))))))
+   | (Write, Supervisor) =>
+      returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ sum))) /\ (((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (ReadWrite, Supervisor) =>
+      returnS (((((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) \/ sum))) /\ ((((((((get_PTE_Bits_W p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ ((((((((get_PTE_Bits_R p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) \/ ((((((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) /\ mxr))))))))))))
+   | (Execute, Supervisor) =>
+      returnS ((((((((get_PTE_Bits_U p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))))) /\ (((((get_PTE_Bits_X p  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))))))
+   | (_, Machine) => internal_error "m-mode mem perm check"
+   )))`;
+
+
+(*val update_PTE_Bits : Riscv_sequential_types.PTE_Bits -> Riscv_sequential_types.AccessType -> Maybe.maybe Riscv_sequential_types.PTE_Bits*)
+
+val _ = Define `
+ ((update_PTE_Bits:riscv_sequential_types$PTE_Bits -> riscv_sequential_types$AccessType ->(riscv_sequential_types$PTE_Bits)option) (p : riscv_sequential_types$PTE_Bits) (a : riscv_sequential_types$AccessType)=   
+ (let update_d =
+     (((((((a = Write))) \/ (((a = ReadWrite)))))) /\ (((((get_PTE_Bits_D p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word)))))) in
+   let update_a = (((get_PTE_Bits_A p  :  1 words$word)) = ((bool_to_bits F  :  1 words$word))) in
+   if (((update_d \/ update_a))) then
+     let np = (update_PTE_Bits_A p ((bool_to_bits T  :  1 words$word))) in
+     let np = (if update_d then update_PTE_Bits_D p ((bool_to_bits T  :  1 words$word)) else np) in
+     SOME np
+   else NONE))`;
+
+
+(*val PTW_Error_of_num : Num.integer -> Riscv_sequential_types.PTW_Error*)
+
+val _ = Define `
+ ((PTW_Error_of_num:int -> riscv_sequential_types$PTW_Error) arg_=   
+ (let l__0 = arg_ in
+   if (((l__0 = (( 0 : int):sail_values$ii)))) then PTW_Access
+   else if (((l__0 = (( 1 : int):sail_values$ii)))) then PTW_Invalid_PTE
+   else if (((l__0 = (( 2 : int):sail_values$ii)))) then PTW_No_Permission
+   else if (((l__0 = (( 3 : int):sail_values$ii)))) then PTW_Misaligned
+   else PTW_PTE_Update))`;
+
+
+(*val num_of_PTW_Error : Riscv_sequential_types.PTW_Error -> Num.integer*)
+
+val _ = Define `
+ ((num_of_PTW_Error:riscv_sequential_types$PTW_Error -> int) arg_=   
+ ((case arg_ of
+     PTW_Access => (( 0 : int):sail_values$ii)
+   | PTW_Invalid_PTE => (( 1 : int):sail_values$ii)
+   | PTW_No_Permission => (( 2 : int):sail_values$ii)
+   | PTW_Misaligned => (( 3 : int):sail_values$ii)
+   | PTW_PTE_Update => (( 4 : int):sail_values$ii)
+   )))`;
+
+
+(*val translationException : Riscv_sequential_types.AccessType -> Riscv_sequential_types.PTW_Error -> Riscv_sequential_types.ExceptionType*)
+
+val _ = Define `
+ ((translationException:riscv_sequential_types$AccessType -> riscv_sequential_types$PTW_Error -> riscv_sequential_types$ExceptionType) (a : riscv_sequential_types$AccessType) (f : riscv_sequential_types$PTW_Error)= 
+  ((case (a, f) of
+         (Read, PTW_Access) => E_Load_Access_Fault
+     | (Read, _) => E_Load_Page_Fault
+     | (Write, PTW_Access) => E_SAMO_Access_Fault
+     | (Write, _) => E_SAMO_Page_Fault
+     | (Fetch, PTW_Access) => E_Fetch_Access_Fault
+     | (Fetch, _) => E_Fetch_Page_Fault
+   )))`;
+
+
+val _ = Define `
+ ((SV39_LEVEL_BITS:int)=  ((( 9 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((SV39_LEVELS:int)=  ((( 3 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((PTE39_LOG_SIZE:int)=  ((( 3 : int):sail_values$ii)))`;
+
+
+val _ = Define `
+ ((PTE39_SIZE:int)=  ((( 8 : int):sail_values$ii)))`;
+
+
+(*val _get_SV39_Vaddr : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39*)
+
+val _ = Define `
+ ((get_SV39_Vaddr:riscv_sequential_types$SV39_Vaddr ->(39)words$word) (Mk_SV39_Vaddr (v))=  v)`;
+
+
+(*val _set_SV39_Vaddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_SV39_Vaddr v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word) (Mk_SV39_Vaddr (v))=  ((subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  27 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_VPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_VPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(27)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . 
+   let r = ((get_SV39_Vaddr w__0  :  39 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) v  :  39 words$word)) in
+   write_regS r_ref (Mk_SV39_Vaddr r))))`;
+
+
+(*val _update_SV39_Vaddr_VPNi : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty27 -> Riscv_sequential_types.SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_VPNi:riscv_sequential_types$SV39_Vaddr ->(27)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x=   
+ (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 38 : int):sail_values$ii) (( 12 : int):sail_values$ii) x  :  39 words$word))))`;
+
+
+(*val _get_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12*)
+
+val _ = Define `
+ ((get_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word) (Mk_SV39_Vaddr (v))=  ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  12 words$word)))`;
+
+
+(*val _set_SV39_Vaddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_Vaddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Vaddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Vaddr) . 
+   let r = ((get_SV39_Vaddr w__0  :  39 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  39 words$word)) in
+   write_regS r_ref (Mk_SV39_Vaddr r))))`;
+
+
+(*val _update_SV39_Vaddr_PgOfs : Riscv_sequential_types.SV39_Vaddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Vaddr*)
+
+val _ = Define `
+ ((update_SV39_Vaddr_PgOfs:riscv_sequential_types$SV39_Vaddr ->(12)words$word -> riscv_sequential_types$SV39_Vaddr) (Mk_SV39_Vaddr (v)) x=   
+ (Mk_SV39_Vaddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  39 words$word))))`;
+
+
+(*val _update_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.SV39_Paddr*)
+
+(*val _get_SV39_Paddr_PgOfs : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12*)
+
+(*val _set_SV39_Paddr_PgOfs : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M unit*)
+
+(*val _get_SV39_Paddr : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56*)
+
+val _ = Define `
+ ((get_SV39_Paddr:riscv_sequential_types$SV39_Paddr ->(56)words$word) (Mk_SV39_Paddr (v))=  v)`;
+
+
+(*val _set_SV39_Paddr : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_SV39_Paddr v) in
+   write_regS r_ref r)))`;
+
+
+(*val _get_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word) (Mk_SV39_Paddr (v))=  ((subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  44 words$word)))`;
+
+
+(*val _set_SV39_Paddr_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_Paddr_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . 
+   let r = ((get_SV39_Paddr w__0  :  56 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) v  :  56 words$word)) in
+   write_regS r_ref (Mk_SV39_Paddr r))))`;
+
+
+(*val _update_SV39_Paddr_PPNi : Riscv_sequential_types.SV39_Paddr -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_Paddr*)
+
+val _ = Define `
+ ((update_SV39_Paddr_PPNi:riscv_sequential_types$SV39_Paddr ->(44)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x=   
+ (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 55 : int):sail_values$ii) (( 12 : int):sail_values$ii) x  :  56 words$word))))`;
+
+
+(*val _update_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.SV39_PTE*)
+
+(*val _get_SV39_PTE_PPNi : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44*)
+
+(*val _set_SV39_PTE_PPNi : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty44 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((get_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word) (Mk_SV39_Paddr (v))=  ((subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  12 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV39_Paddr_PgOfs:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_Paddr))sail_values$register_ref ->(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_Paddr) . 
+   let r = ((get_SV39_Paddr w__0  :  56 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  56 words$word)) in
+   write_regS r_ref (Mk_SV39_Paddr r))))`;
+
+
+val _ = Define `
+ ((update_SV39_Paddr_PgOfs:riscv_sequential_types$SV39_Paddr ->(12)words$word -> riscv_sequential_types$SV39_Paddr) (Mk_SV39_Paddr (v)) x=   
+ (Mk_SV39_Paddr ((update_subrange_vec_dec v (( 11 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  56 words$word))))`;
+
+
+val _ = Define `
+ ((get_SV39_PTE:riscv_sequential_types$SV39_PTE ->(64)words$word) (Mk_SV39_PTE (v))=  v)`;
+
+
+val _ = Define `
+ ((set_SV39_PTE:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ r . 
+   let r = (Mk_SV39_PTE v) in
+   write_regS r_ref r)))`;
+
+
+val _ = Define `
+ ((get_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  44 words$word)))`;
+
+
+val _ = Define `
+ ((set_SV39_PTE_PPNi:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(44)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . 
+   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_SV39_PTE r))))`;
+
+
+val _ = Define `
+ ((update_SV39_PTE_PPNi:riscv_sequential_types$SV39_PTE ->(44)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x=   
+ (Mk_SV39_PTE ((update_subrange_vec_dec v (( 53 : int):sail_values$ii) (( 10 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2*)
+
+val _ = Define `
+ ((get_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  2 words$word)))`;
+
+
+(*val _set_SV39_PTE_RSW : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_RSW:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(2)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . 
+   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_SV39_PTE r))))`;
+
+
+(*val _update_SV39_PTE_RSW : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty2 -> Riscv_sequential_types.SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_RSW:riscv_sequential_types$SV39_PTE ->(2)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x=   
+ (Mk_SV39_PTE ((update_subrange_vec_dec v (( 9 : int):sail_values$ii) (( 8 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val _get_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8*)
+
+val _ = Define `
+ ((get_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word) (Mk_SV39_PTE (v))=  ((subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)))`;
+
+
+(*val _set_SV39_PTE_BITS : Sail_values.register_ref Riscv_sequential_types.regstate Riscv_sequential_types.register_value Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((set_SV39_PTE_BITS:((riscv_sequential_types$regstate),(riscv_sequential_types$register_value),(riscv_sequential_types$SV39_PTE))sail_values$register_ref ->(8)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) r_ref v=  (bindS   
+(reg_deref0 r_ref) (\ (w__0 : riscv_sequential_types$SV39_PTE) . 
+   let r = ((get_SV39_PTE w__0  :  64 words$word)) in
+   let r = ((update_subrange_vec_dec r (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) v  :  64 words$word)) in
+   write_regS r_ref (Mk_SV39_PTE r))))`;
+
+
+(*val _update_SV39_PTE_BITS : Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty8 -> Riscv_sequential_types.SV39_PTE*)
+
+val _ = Define `
+ ((update_SV39_PTE_BITS:riscv_sequential_types$SV39_PTE ->(8)words$word -> riscv_sequential_types$SV39_PTE) (Mk_SV39_PTE (v)) x=   
+ (Mk_SV39_PTE ((update_subrange_vec_dec v (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii) x  :  64 words$word))))`;
+
+
+(*val curAsid64 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty16)*)
+
+val _ = Define `
+ ((curAsid64:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((16)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let satp64 = (Mk_Satp64 w__0) in
+   returnS ((get_Satp64_Asid satp64  :  16 words$word)))))`;
+
+
+(*val curPTB39 : unit -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty56)*)
+
+val _ = Define `
+ ((curPTB39:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((56)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let satp64 = (Mk_Satp64 w__0) in
+   returnS ((EXTZ (( 56 : int):sail_values$ii)
+               ((shiftl ((get_Satp64_PPN satp64  :  44 words$word)) PAGESIZE_BITS  :  44 words$word))
+              :  56 words$word)))))`;
+
+
+(*val walk39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M Riscv_sequential_types.PTW_Result*)
+
+ val walk39_defn = Hol_defn "walk39" `
+ ((walk39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$PTW_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vaddr ac priv mxr sum ptb level global=   
+ (let va = (Mk_SV39_Vaddr vaddr) in
+   let (pt_ofs : riscv_sequential_types$paddr39) =     
+((shiftl
+        ((EXTZ (( 56 : int):sail_values$ii)
+            ((subrange_vec_dec
+                ((shiftr ((get_SV39_Vaddr_VPNi va  :  27 words$word))
+                    ((level * SV39_LEVEL_BITS))
+                   :  27 words$word)) SV39_LEVEL_BITS (( 0 : int):sail_values$ii)
+               :  10 words$word))
+           :  56 words$word)) PTE39_LOG_SIZE
+       :  56 words$word)) in
+   let pte_addr = ((add_vec ptb pt_ofs  :  56 words$word)) in bindS
+   (checked_mem_read Data ((EXTZ (( 64 : int):sail_values$ii) pte_addr  :  64 words$word)) (( 8 : int):sail_values$ii)
+     : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__0 : ( 64 words$word) riscv_sequential_types$MemoryOpResult) . 
+   (case w__0 of
+     MemException (_) => returnS (PTW_Failure PTW_Access)
+   | MemValue (v) =>
+      let pte = (Mk_SV39_PTE v) in
+      let pbits = ((get_SV39_PTE_BITS pte  :  8 words$word)) in
+      let pattr = (Mk_PTE_Bits pbits) in
+      let is_global =
+        (global \/ (((((get_PTE_Bits_G pattr  :  1 words$word)) = ((bool_to_bits T  :  1 words$word)))))) in
+      if ((isInvalidPTE pbits)) then returnS (PTW_Failure PTW_Invalid_PTE)
+      else if ((isPTEPtr pbits)) then
+        if (((level = (( 0 : int):sail_values$ii)))) then returnS (PTW_Failure PTW_Invalid_PTE)
+        else
+          walk39 vaddr ac priv mxr sum
+            ((EXTZ (( 56 : int):sail_values$ii) ((get_SV39_PTE_PPNi pte  :  44 words$word))  :  56 words$word))
+            ((level - (( 1 : int):sail_values$ii))) is_global
+      else bindS        
+(checkPTEPermission ac priv mxr sum pattr) (\ (w__3 : bool) . 
+        returnS (if ((~ w__3)) then PTW_Failure PTW_No_Permission
+                 else if ((level > (( 0 : int):sail_values$ii))) then
+                   let masked =                     
+((and_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                        ((EXTZ (( 44 : int):sail_values$ii)
+                            ((sub_vec_int
+                                ((shiftl (vec_of_bits [B1]  :  1 words$word)
+                                    ((level * SV39_LEVEL_BITS))
+                                   :  1 words$word)) (( 1 : int):sail_values$ii)
+                               :  1 words$word))
+                           :  44 words$word))
+                       :  44 words$word)) in
+                   if (((masked <> ((EXTZ (( 44 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  44 words$word)))))
+                   then
+                     PTW_Failure PTW_Misaligned
+                   else
+                     let ppn =                       
+((or_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                          ((and_vec
+                              ((EXTZ (( 44 : int):sail_values$ii) ((get_SV39_Vaddr_VPNi va  :  27 words$word))  :  44 words$word))
+                              ((EXTZ (( 44 : int):sail_values$ii)
+                                  ((sub_vec_int
+                                      ((shiftl (vec_of_bits [B1]  :  1 words$word)
+                                          ((level * SV39_LEVEL_BITS))
+                                         :  1 words$word)) (( 1 : int):sail_values$ii)
+                                     :  1 words$word))
+                                 :  44 words$word))
+                             :  44 words$word))
+                         :  44 words$word)) in
+                     PTW_Success ((concat_vec ppn ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
+                                    :  56 words$word),pte,pte_addr,level,is_global)
+                 else
+                   PTW_Success ((concat_vec ((get_SV39_PTE_PPNi pte  :  44 words$word))
+                                   ((get_SV39_Vaddr_PgOfs va  :  12 words$word))
+                                  :  56 words$word),pte,pte_addr,level,is_global)))
+   ))))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn walk39_defn;
+
+(*val make_TLB39_Entry : Machine_word.mword Machine_word.ty16 -> bool -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Sail_values.ii -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.M Riscv_sequential_types.TLB39_Entry*)
+
+val _ = Define `
+ ((make_TLB39_Entry:(16)words$word -> bool ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE -> int ->(56)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TLB39_Entry),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid global vAddr pAddr pte level pteAddr=   
+ (let (shift : sail_values$ii) = (PAGESIZE_BITS + ((level * SV39_LEVEL_BITS))) in
+   let (vAddrMask : riscv_sequential_types$vaddr39) =     
+((sub_vec_int
+        ((shiftl ((EXTZ (( 39 : int):sail_values$ii) (vec_of_bits [B1]  :  1 words$word)  :  39 words$word)) shift  :  39 words$word))
+        (( 1 : int):sail_values$ii)
+       :  39 words$word)) in
+   let (vMatchMask : riscv_sequential_types$vaddr39) = ((not_vec vAddrMask  :  39 words$word)) in bindS
+   (read_regS mcycle_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) . 
+   returnS (<| TLB39_Entry_asid := asid; 
+               TLB39_Entry_global := global; 
+               TLB39_Entry_pte := pte; 
+               TLB39_Entry_pteAddr := pteAddr; 
+               TLB39_Entry_vAddrMask := vAddrMask; 
+               TLB39_Entry_vMatchMask := vMatchMask; 
+               TLB39_Entry_vAddr := ((and_vec vAddr vMatchMask  :  39 words$word)); 
+               TLB39_Entry_pAddr :=
+                 ((shiftl ((shiftr pAddr shift  :  56 words$word)) shift  :  56 words$word)); 
+               TLB39_Entry_age := w__0 |>))))`;
+
+
+val _ = Define `
+ ((TLBEntries:int)=  ((( 32 : int):sail_values$ii)))`;
+
+
+(*val lookupTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.M (Maybe.maybe ((Sail_values.ii * Riscv_sequential_types.TLB39_Entry)))*)
+
+val _ = Define `
+ ((lookupTLB39:(16)words$word ->(39)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((int#riscv_sequential_types$TLB39_Entry)option),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vaddr=  (bindS   
+(read_regS tlb39_ref) (\ (w__0 :  riscv_sequential_types$TLB39_Entry option) . 
+   returnS ((case w__0 of
+              NONE => NONE
+            | SOME (e) =>
+               if ((((((e.TLB39_Entry_global \/ (((e.TLB39_Entry_asid = asid)))))) /\ (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask vaddr  :  39 words$word)))))))) then
+                 SOME ((( 0 : int):sail_values$ii), e)
+               else NONE
+            )))))`;
+
+
+(*val addToTLB39 : Machine_word.mword Machine_word.ty16 -> Machine_word.mword Machine_word.ty39 -> Machine_word.mword Machine_word.ty56 -> Riscv_sequential_types.SV39_PTE -> Machine_word.mword Machine_word.ty56 -> Sail_values.ii -> bool -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((addToTLB39:(16)words$word ->(39)words$word ->(56)words$word -> riscv_sequential_types$SV39_PTE ->(56)words$word -> int -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid vAddr pAddr pte pteAddr level global=  (bindS   
+(make_TLB39_Entry asid global vAddr pAddr pte level pteAddr) (\ ent . 
+   write_regS tlb39_ref (SOME ent))))`;
+
+
+(*val writeTLB39 : Sail_values.ii -> Riscv_sequential_types.TLB39_Entry -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((writeTLB39:int -> riscv_sequential_types$TLB39_Entry ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (idx : sail_values$ii) (ent : riscv_sequential_types$TLB39_Entry)=  (write_regS tlb39_ref (SOME ent)))`;
+
+
+(*val flushTLB : Maybe.maybe (Machine_word.mword Machine_word.ty16) -> Maybe.maybe (Machine_word.mword Machine_word.ty39) -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((flushTLB:((16)words$word)option ->((39)words$word)option ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) asid addr=  (bindS   
+(read_regS tlb39_ref) (\ (w__0 :  riscv_sequential_types$TLB39_Entry option) . 
+   let (ent :  riscv_sequential_types$TLB39_Entry option) =     
+((case (w__0, asid, addr) of
+       (NONE, _, _) => NONE
+     | (SOME (e), NONE, NONE) => NONE
+     | (SOME (e), NONE, SOME (a)) =>
+        if (((e.TLB39_Entry_vAddr = ((and_vec e.TLB39_Entry_vMatchMask a  :  39 words$word))))) then
+          NONE
+        else SOME e
+     | (SOME (e), SOME (i), NONE) =>
+        if ((((((e.TLB39_Entry_asid = i))) /\ ((~ e.TLB39_Entry_global))))) then NONE
+        else SOME e
+     | (SOME (e), SOME (i), SOME (a)) =>
+        if ((((((e.TLB39_Entry_asid = i))) /\ ((((((e.TLB39_Entry_vAddr = ((and_vec a e.TLB39_Entry_vMatchMask  :  39 words$word))))) /\ ((~ e.TLB39_Entry_global)))))))) then
+          NONE
+        else SOME e
+     )) in
+   write_regS tlb39_ref ent)))`;
+
+
+val _ = Define `
+ ((enable_dirty_update:bool)=  T)`;
+
+
+(*val translate39 : Machine_word.mword Machine_word.ty39 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.Privilege -> bool -> bool -> Sail_values.ii -> Riscv_sequential_types.M Riscv_sequential_types.TR39_Result*)
+
+val _ = Define `
+ ((translate39:(39)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$Privilege -> bool -> bool -> int ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR39_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac priv mxr sum level=  (bindS
+   (curAsid64 ()   : ( 16 words$word) riscv_sequential_types$M) (\ asid .  bindS   
+(lookupTLB39 asid vAddr) (\ (w__0 :  ((sail_values$ii # riscv_sequential_types$TLB39_Entry))option) . 
+   (case w__0 of
+     SOME (idx,ent) =>
+      let pteBits = (Mk_PTE_Bits ((get_SV39_PTE_BITS ent.TLB39_Entry_pte  :  8 words$word))) in bindS      
+(checkPTEPermission ac priv mxr sum pteBits) (\ (w__1 : bool) . 
+      if ((~ w__1)) then returnS (TR39_Failure PTW_No_Permission)
+      else
+        (case ((update_PTE_Bits pteBits ac)) of
+          NONE =>
+           returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
+                                     ((EXTZ (( 56 : int):sail_values$ii)
+                                         ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
+                                        :  56 words$word))
+                                    :  56 words$word)))
+        | SOME (pbits) =>
+           if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update)
+           else
+             let (n_ent : riscv_sequential_types$TLB39_Entry) = ent in
+             let n_ent =               
+((n_ent with<|
+                 TLB39_Entry_pte :=
+                   ((update_SV39_PTE_BITS ent.TLB39_Entry_pte ((get_PTE_Bits pbits  :  8 words$word))))|>)) in bindS (seqS             
+(writeTLB39 idx n_ent)             
+(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) ent.TLB39_Entry_pteAddr  :  64 words$word)) (( 8 : int):sail_values$ii)
+               ((get_SV39_PTE ent.TLB39_Entry_pte  :  64 words$word)))) (\ (w__2 : unit
+               riscv_sequential_types$MemoryOpResult) .  seqS
+             (case w__2 of
+               MemValue (_) => returnS () 
+             | MemException (e) => internal_error "invalid physical address in TLB"
+             )             
+(returnS (TR39_Address ((or_vec ent.TLB39_Entry_pAddr
+                                       ((EXTZ (( 56 : int):sail_values$ii)
+                                           ((and_vec vAddr ent.TLB39_Entry_vAddrMask  :  39 words$word))
+                                          :  56 words$word))
+                                      :  56 words$word)))))
+        ))
+   | NONE => bindS
+      (curPTB39 ()   : ( 56 words$word) riscv_sequential_types$M) (\ (w__6 :  56 words$word) .  bindS      
+(walk39 vAddr ac priv mxr sum w__6 level F) (\ (w__7 : riscv_sequential_types$PTW_Result) . 
+      (case w__7 of
+        PTW_Failure (f) => returnS (TR39_Failure f)
+      | PTW_Success (pAddr,pte,pteAddr,level,global) =>
+         (case ((update_PTE_Bits (Mk_PTE_Bits ((get_SV39_PTE_BITS pte  :  8 words$word))) ac)) of
+           NONE => seqS            
+(addToTLB39 asid vAddr pAddr pte pteAddr level global) (returnS (TR39_Address pAddr))
+         | SOME (pbits) =>
+            if ((~ enable_dirty_update)) then returnS (TR39_Failure PTW_PTE_Update)
+            else
+              let (w_pte : riscv_sequential_types$SV39_PTE) =                
+(update_SV39_PTE_BITS pte ((get_PTE_Bits pbits  :  8 words$word))) in bindS              
+(checked_mem_write ((EXTZ (( 64 : int):sail_values$ii) pteAddr  :  64 words$word)) (( 8 : int):sail_values$ii)
+                ((get_SV39_PTE w_pte  :  64 words$word))) (\ (w__8 : unit riscv_sequential_types$MemoryOpResult) . 
+              (case w__8 of
+                MemValue (_) => seqS                 
+(addToTLB39 asid vAddr pAddr w_pte pteAddr level global)                 
+(returnS (TR39_Address pAddr))
+              | MemException (e) => returnS (TR39_Failure PTW_Access)
+              ))
+         )
+      )))
+   )))))`;
+
+
+(*val translationMode : Riscv_sequential_types.Privilege -> Riscv_sequential_types.M Riscv_sequential_types.SATPMode*)
+
+val _ = Define `
+ ((translationMode:riscv_sequential_types$Privilege ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$SATPMode),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) priv=   
+ (if (((((privLevel_to_bits priv  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
+   then
+     returnS Sbare
+   else bindS     
+(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) . 
+     let arch = (architecture ((get_Mstatus_SXL w__0  :  2 words$word))) in
+     (case arch of
+       SOME (RV64) => bindS
+        (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) . 
+        let (mbits : riscv_sequential_types$satp_mode) = ((get_Satp64_Mode (Mk_Satp64 w__1)  :  4 words$word)) in
+        (case ((satpMode_of_bits RV64 mbits)) of
+          SOME (m) => returnS m
+        | NONE => internal_error "invalid RV64 translation mode in satp"
+        ))
+     | _ => internal_error "unsupported address translation arch"
+     ))))`;
+
+
+(*val translateAddr : Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.AccessType -> Riscv_sequential_types.ReadType -> Riscv_sequential_types.M Riscv_sequential_types.TR_Result*)
+
+val _ = Define `
+ ((translateAddr:(64)words$word -> riscv_sequential_types$AccessType -> riscv_sequential_types$ReadType ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$TR_Result),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) vAddr ac rt=  (bindS
+   (case rt of
+     Instruction => read_regS cur_privilege_ref
+   | Data => bindS      
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . 
+      if (((((get_Mstatus_MPRV w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then bindS        
+(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . 
+        returnS ((privLevel_of_bits ((get_Mstatus_MPP w__2  :  2 words$word)))))
+      else read_regS cur_privilege_ref)
+   ) (\ (effPriv : riscv_sequential_types$Privilege) .  bindS   
+(read_regS mstatus_ref) (\ (w__5 : riscv_sequential_types$Mstatus) . 
+   let (mxr : bool) =
+     (((get_Mstatus_MXR w__5  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in bindS   
+(read_regS mstatus_ref) (\ (w__6 : riscv_sequential_types$Mstatus) . 
+   let (sum : bool) =
+     (((get_Mstatus_SUM w__6  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))) in bindS   
+(translationMode effPriv) (\ (mode : riscv_sequential_types$SATPMode) .  
+  (case mode of
+        Sbare => returnS (TR_Address vAddr)
+    | SV39 => bindS
+                (translate39
+                   ((subrange_vec_dec vAddr (( 38 : int): sail_values$ii)
+                       (( 0 : int): sail_values$ii) : 39 words$word)) 
+                 ac effPriv mxr sum
+                   ((SV39_LEVELS - (( 1 : int): sail_values$ii))))
+                (\ (w__7 : riscv_sequential_types$TR39_Result) . 
+                 returnS
+                   ((case w__7 of
+                          TR39_Address (pa) => TR_Address
+                                                 ((EXTZ
+                                                     (( 64 : int): sail_values$ii)
+                                                     pa : 64 words$word))
+                      | TR39_Failure (f) => TR_Failure
+                                              ((translationException ac f))
+                    )))
+  )))))))`;
+
+
+(*val decode : Machine_word.mword Machine_word.ty32 -> Maybe.maybe Riscv_sequential_types.ast*)
+
+(*val decodeCompressed : Machine_word.mword Machine_word.ty16 -> Maybe.maybe Riscv_sequential_types.ast*)
+
+(*val execute : Riscv_sequential_types.ast -> Riscv_sequential_types.M unit*)
+
+(*val print_insn : Riscv_sequential_types.ast -> string*)
+
+(*val extend_value : forall 'int8_times_n . Size 'int8_times_n => bool -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((extend_value:bool ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult ->((64)words$word)riscv_sequential_types$MemoryOpResult) is_unsigned value=   
+ ((case value of
+     MemValue (v) =>
+      MemValue (if is_unsigned then (EXTZ (( 64 : int):sail_values$ii) v  :  64 words$word)
+                else (EXTS (( 64 : int):sail_values$ii) v  :  64 words$word))
+   | MemException (e) => MemException e
+   )))`;
+
+
+(*val process_load : forall 'int8_times_n . Size 'int8_times_n => Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.MemoryOpResult (Machine_word.mword 'int8_times_n) -> bool -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((process_load:(5)words$word ->(64)words$word ->('int8_times_n words$word)riscv_sequential_types$MemoryOpResult -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rd addr value is_unsigned=   
+ ((case ((extend_value is_unsigned value  : ( 64 words$word) riscv_sequential_types$MemoryOpResult)) of
+     MemValue (result) => wX ((regbits_to_regno rd)) result
+   | MemException (e) => handle_mem_exception addr e
+   )))`;
+
+
+(*val process_loadres : forall 'int8_times_n . Riscv_sequential_types.regbits -> Riscv_sequential_types.xlenbits -> Riscv_sequential_types.MemoryOpResult (Riscv_sequential_types.bits 'int8_times_n) -> bool -> unit*)
+
+(*val readCSR : Machine_word.mword Machine_word.ty12 -> Riscv_sequential_types.M (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((readCSR:(12)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->((((64)words$word),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr=   
+ (let b__0 = csr in
+   if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B0;B1]  :  12 words$word)))) then
+     (read_regS mvendorid_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B0]  :  12 words$word)))) then
+     (read_regS marchid_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B0;B1;B1]  :  12 words$word)))) then
+     (read_regS mimpid_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B1;B1;B0;B0;B0;B1;B0;B1;B0;B0]  :  12 words$word)))) then
+     (read_regS mhartid_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mstatus_ref) (\ (w__4 : riscv_sequential_types$Mstatus) .  returnS ((get_Mstatus w__4  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS     
+(read_regS medeleg_ref) (\ (w__5 : riscv_sequential_types$Medeleg) .  returnS ((get_Medeleg w__5  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS     
+(read_regS mideleg_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) . 
+     returnS ((get_Minterrupts w__6  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mie_ref) (\ (w__7 : riscv_sequential_types$Minterrupts) . 
+     returnS ((get_Minterrupts w__7  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then bindS     
+(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) .  returnS ((get_Mtvec w__8  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (read_regS mscratch_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     (read_regS mepc_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS     
+(read_regS mcause_ref) (\ (w__11 : riscv_sequential_types$Mcause) .  returnS ((get_Mcause w__11  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     (read_regS mtval_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mip_ref) (\ (w__13 : riscv_sequential_types$Minterrupts) . 
+     returnS ((get_Minterrupts w__13  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mstatus_ref) (\ (w__14 : riscv_sequential_types$Mstatus) . 
+     returnS ((get_Mstatus w__14  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS     
+(read_regS sedeleg_ref) (\ (w__15 : riscv_sequential_types$Sedeleg) . 
+     returnS ((get_Sedeleg w__15  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS     
+(read_regS sideleg_ref) (\ (w__16 : riscv_sequential_types$Sinterrupts) . 
+     returnS ((get_Sinterrupts w__16  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mie_ref) (\ (w__17 : riscv_sequential_types$Minterrupts) .  bindS     
+(read_regS mideleg_ref) (\ (w__18 : riscv_sequential_types$Minterrupts) . 
+     returnS ((get_Sinterrupts ((lower_mie w__17 w__18))  :  64 words$word))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then bindS     
+(read_regS stvec_ref) (\ (w__19 : riscv_sequential_types$Mtvec) .  returnS ((get_Mtvec w__19  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (read_regS sscratch_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     (read_regS sepc_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS     
+(read_regS scause_ref) (\ (w__22 : riscv_sequential_types$Mcause) .  returnS ((get_Mcause w__22  :  64 words$word)))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then
+     (read_regS stval_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS     
+(read_regS mip_ref) (\ (w__24 : riscv_sequential_types$Minterrupts) .  bindS     
+(read_regS mideleg_ref) (\ (w__25 : riscv_sequential_types$Minterrupts) . 
+     returnS ((get_Sinterrupts ((lower_mip w__24 w__25))  :  64 words$word))))
+   else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then
+     (read_regS mcycle_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then
+     (read_regS mtime_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else if (((b__0 = (vec_of_bits [B1;B1;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then
+     (read_regS minstret_ref  : ( 64 words$word) riscv_sequential_types$M)
+   else
+     let (_ : unit) = (print_bits "unhandled read to CSR " csr) in
+     returnS (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                           B0]
+               :  64 words$word)))`;
+
+
+(*val writeCSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty64 -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((writeCSR:(12)words$word ->(64)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) (csr : riscv_sequential_types$csreg) (value : riscv_sequential_types$xlenbits)=   
+ (let b__0 = csr in bindS
+   (if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mstatus_ref) (\ (w__0 : riscv_sequential_types$Mstatus) .  bindS (seqS      
+(write_regS mstatus_ref ((legalize_mstatus w__0 value)))      
+(read_regS mstatus_ref)) (\ (w__1 : riscv_sequential_types$Mstatus) . 
+      returnS (SOME ((get_Mstatus w__1  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS      
+(read_regS medeleg_ref) (\ (w__2 : riscv_sequential_types$Medeleg) .  bindS (seqS      
+(write_regS medeleg_ref ((legalize_medeleg w__2 value)))      
+(read_regS medeleg_ref)) (\ (w__3 : riscv_sequential_types$Medeleg) . 
+      returnS (SOME ((get_Medeleg w__3  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS      
+(read_regS mideleg_ref) (\ (w__4 : riscv_sequential_types$Minterrupts) .  bindS (seqS      
+(write_regS mideleg_ref ((legalize_mideleg w__4 value)))      
+(read_regS mideleg_ref)) (\ (w__5 : riscv_sequential_types$Minterrupts) . 
+      returnS (SOME ((get_Minterrupts w__5  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mie_ref) (\ (w__6 : riscv_sequential_types$Minterrupts) .  bindS (seqS      
+(write_regS mie_ref ((legalize_mie w__6 value)))      
+(read_regS mie_ref)) (\ (w__7 : riscv_sequential_types$Minterrupts) . 
+      returnS (SOME ((get_Minterrupts w__7  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then bindS      
+(read_regS mtvec_ref) (\ (w__8 : riscv_sequential_types$Mtvec) .  bindS (seqS      
+(write_regS mtvec_ref ((legalize_tvec w__8 value)))      
+(read_regS mtvec_ref)) (\ (w__9 : riscv_sequential_types$Mtvec) . 
+      returnS (SOME ((get_Mtvec w__9  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS (seqS      
+(write_regS mscratch_ref value)
+      (read_regS mscratch_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__10 :  64 words$word) . 
+      returnS (SOME w__10))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then bindS
+      (legalize_xepc value  : ( 64 words$word) riscv_sequential_types$M) (\ (w__11 : riscv_sequential_types$xlenbits) .  bindS (seqS      
+(write_regS mepc_ref w__11)
+      (read_regS mepc_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__12 :  64 words$word) .  returnS (SOME w__12)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS (seqS      
+(set_Mcause mcause_ref value)      
+(read_regS mcause_ref)) (\ (w__13 : riscv_sequential_types$Mcause) . 
+      returnS (SOME ((get_Mcause w__13  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS (seqS      
+(write_regS mtval_ref value)
+      (read_regS mtval_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__14 :  64 words$word) .  returnS (SOME w__14))
+    else if (((b__0 = (vec_of_bits [B0;B0;B1;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mip_ref) (\ (w__15 : riscv_sequential_types$Minterrupts) .  bindS (seqS      
+(write_regS mip_ref ((legalize_mip w__15 value)))      
+(read_regS mip_ref)) (\ (w__16 : riscv_sequential_types$Minterrupts) . 
+      returnS (SOME ((get_Minterrupts w__16  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mstatus_ref) (\ (w__17 : riscv_sequential_types$Mstatus) .  bindS (seqS      
+(write_regS mstatus_ref ((legalize_sstatus w__17 value)))      
+(read_regS mstatus_ref)) (\ (w__18 : riscv_sequential_types$Mstatus) . 
+      returnS (SOME ((get_Mstatus w__18  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS      
+(read_regS sedeleg_ref) (\ (w__19 : riscv_sequential_types$Sedeleg) .  bindS (seqS      
+(write_regS sedeleg_ref ((legalize_sedeleg w__19 value)))      
+(read_regS sedeleg_ref)) (\ (w__20 : riscv_sequential_types$Sedeleg) . 
+      returnS (SOME ((get_Sedeleg w__20  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS (seqS      
+(set_Sinterrupts sideleg_ref value)      
+(read_regS sideleg_ref)) (\ (w__21 : riscv_sequential_types$Sinterrupts) . 
+      returnS (SOME ((get_Sinterrupts w__21  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mie_ref) (\ (w__22 : riscv_sequential_types$Minterrupts) .  bindS      
+(read_regS mideleg_ref) (\ (w__23 : riscv_sequential_types$Minterrupts) .  bindS (seqS      
+(write_regS mie_ref ((legalize_sie w__22 w__23 value)))      
+(read_regS mie_ref)) (\ (w__24 : riscv_sequential_types$Minterrupts) . 
+      returnS (SOME ((get_Minterrupts w__24  :  64 words$word))))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1]  :  12 words$word)))) then bindS      
+(read_regS stvec_ref) (\ (w__25 : riscv_sequential_types$Mtvec) .  bindS (seqS      
+(write_regS stvec_ref ((legalize_tvec w__25 value)))      
+(read_regS stvec_ref)) (\ (w__26 : riscv_sequential_types$Mtvec) . 
+      returnS (SOME ((get_Mtvec w__26  :  64 words$word)))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS (seqS      
+(write_regS sscratch_ref value)
+      (read_regS sscratch_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__27 :  64 words$word) . 
+      returnS (SOME w__27))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B1]  :  12 words$word)))) then bindS
+      (legalize_xepc value  : ( 64 words$word) riscv_sequential_types$M) (\ (w__28 : riscv_sequential_types$xlenbits) .  bindS (seqS      
+(write_regS sepc_ref w__28)
+      (read_regS sepc_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__29 :  64 words$word) .  returnS (SOME w__29)))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B0]  :  12 words$word)))) then bindS (seqS      
+(set_Mcause scause_ref value)      
+(read_regS scause_ref)) (\ (w__30 : riscv_sequential_types$Mcause) . 
+      returnS (SOME ((get_Mcause w__30  :  64 words$word))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B1;B1]  :  12 words$word)))) then bindS (seqS      
+(write_regS stval_ref value)
+      (read_regS stval_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__31 :  64 words$word) .  returnS (SOME w__31))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B0;B1;B0;B0;B0;B1;B0;B0]  :  12 words$word)))) then bindS      
+(read_regS mip_ref) (\ (w__32 : riscv_sequential_types$Minterrupts) .  bindS      
+(read_regS mideleg_ref) (\ (w__33 : riscv_sequential_types$Minterrupts) .  bindS (seqS      
+(write_regS mip_ref ((legalize_sip w__32 w__33 value)))      
+(read_regS mip_ref)) (\ (w__34 : riscv_sequential_types$Minterrupts) . 
+      returnS (SOME ((get_Minterrupts w__34  :  64 words$word))))))
+    else if (((b__0 = (vec_of_bits [B0;B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)))) then bindS      
+(cur_Architecture () ) (\ (w__35 : riscv_sequential_types$Architecture) .  bindS
+      (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__36 :  64 words$word) .  bindS (seqS      
+(write_regS satp_ref ((legalize_satp w__35 w__36 value  :  64 words$word)))
+      (read_regS satp_ref  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__37 :  64 words$word) .  returnS (SOME w__37))))
+    else returnS NONE) (\ (res :  riscv_sequential_types$xlenbits option) . 
+   returnS ((case res of
+              SOME (v) =>
+               prerr_endline
+                 ((STRCAT "CSR "
+                     ((STRCAT ((csr_name csr))
+                         ((STRCAT " <- "
+                             ((STRCAT ((string_of_vec v))
+                                 ((STRCAT " (input: "
+                                     ((STRCAT ((string_of_vec value)) ")"))))))))))))
+            | NONE => print_bits "unhandled write to CSR " csr
+            )))))`;
+
+
+(*val signalIllegalInstruction : unit -> Riscv_sequential_types.M unit*)
+
+val _ = Define `
+ ((signalIllegalInstruction:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (not_implemented "illegal instruction"))`;
+
+
+val _ = Define `
+ ((decode:(32)words$word ->(riscv_sequential_types$ast)option) v__0=   
+ (if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B1;B1;B1]  :  7 words$word)))) then
+     let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  20 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (UTYPE (imm,rd,RISCV_LUI))
+   else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B1;B1;B1]  :  7 words$word)))) then
+     let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  20 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (UTYPE (imm,rd,RISCV_AUIPC))
+   else if (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B1;B1;B1;B1]  :  7 words$word)))) then
+     let (imm : 20 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  20 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RISCV_JAL ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm (( 19 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word))
+                             ((concat_vec
+                                 ((cast_unit_vec0 ((access_vec_dec imm (( 8 : int):sail_values$ii)))  :  1 words$word))
+                                 ((concat_vec ((subrange_vec_dec imm (( 18 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  6 words$word))
+                                     ((concat_vec
+                                         ((subrange_vec_dec imm (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  4 words$word))
+                                         (vec_of_bits [B0]  :  1 words$word)
+                                        :  5 words$word))
+                                    :  11 words$word))
+                                :  12 words$word))
+                            :  20 words$word))
+                        :  21 words$word),rd))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B1;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RISCV_JALR (imm,rs1,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BEQ))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BNE))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BLT))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BGE))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BLTU))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (BTYPE ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm7 (( 6 : int):sail_values$ii)))  :  1 words$word))
+                     ((concat_vec ((cast_unit_vec0 ((access_vec_dec imm5 (( 0 : int):sail_values$ii)))  :  1 words$word))
+                         ((concat_vec ((subrange_vec_dec imm7 (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+                             ((concat_vec ((subrange_vec_dec imm5 (( 4 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  4 words$word))
+                                 (vec_of_bits [B0]  :  1 words$word)
+                                :  5 words$word))
+                            :  11 words$word))
+                        :  12 words$word))
+                    :  13 words$word),rs2,rs1,RISCV_BGEU))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_ADDI))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_SLTI))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_SLTIU))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_XORI))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_ORI))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ITYPE (imm,rs1,rd,RISCV_ANDI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  6 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SLLI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  6 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRLI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 26 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 6 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 25 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  6 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTIOP (shamt,rs1,rd,RISCV_SRAI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_ADD))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SUB))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SLL))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SLT))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SLTU))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_XOR))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SRL))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_SRA))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_OR))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPE (rs2,rs1,rd,RISCV_AND))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,F,BYTE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,F,HALF,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,F,WORD,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,F,DOUBLE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,T,BYTE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,T,HALF,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOAD (imm,rs1,rd,T,WORD,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,BYTE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,HALF,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,WORD,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm7 : 7 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm5 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORE ((concat_vec imm7 imm5  :  12 words$word),rs2,rs1,DOUBLE,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word))))))) then
+     let (imm : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (ADDIW (imm,rs1,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTW (shamt,rs1,rd,RISCV_SLLI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTW (shamt,rs1,rd,RISCV_SRLI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (shamt : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SHIFTW (shamt,rs1,rd,RISCV_SRAI))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPEW (rs2,rs1,rd,RISCV_ADDW))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPEW (rs2,rs1,rd,RISCV_SUBW))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPEW (rs2,rs1,rd,RISCV_SLLW))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPEW (rs2,rs1,rd,RISCV_SRLW))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B0;B0;B0;B0]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (RTYPEW (rs2,rs1,rd,RISCV_SRAW))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MUL (rs2,rs1,rd,F,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MUL (rs2,rs1,rd,T,T,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MUL (rs2,rs1,rd,T,T,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MUL (rs2,rs1,rd,T,F,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIV0 (rs2,rs1,rd,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIV0 (rs2,rs1,rd,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (REM (rs2,rs1,rd,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B0;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (REM (rs2,rs1,rd,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (MULW (rs2,rs1,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIVW (rs2,rs1,rd,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (DIVW (rs2,rs1,rd,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (REMW (rs2,rs1,rd,T))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B1]  :  7 words$word)))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B1;B1;B0;B1;B1]  :  7 words$word)))))))))) then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (REMW (rs2,rs1,rd,F))
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 28 : int):sail_values$ii)  :  4 words$word)) = (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  20 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+                     :  20 words$word))))))) then
+     let (pred : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 27 : int):sail_values$ii) (( 24 : int):sail_values$ii)  :  4 words$word)) in
+     let (succ : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 23 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  4 words$word)) in
+     SOME (FENCE (pred,succ))
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;
+                             B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B1]
+                 :  32 words$word)))) then
+     SOME (FENCEI () )
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+                 :  32 words$word)))) then
+     SOME (ECALL () )
+   else if (((v__0 = (vec_of_bits [B0;B0;B1;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+                 :  32 words$word)))) then
+     SOME (MRET () )
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+                 :  32 words$word)))) then
+     SOME (SRET () )
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+                 :  32 words$word)))) then
+     SOME (EBREAK () )
+   else if (((v__0 = (vec_of_bits [B0;B0;B0;B1;B0;B0;B0;B0;B0;B1;B0;B1;B0;B0;B0;B0;B0;B0;B0;B0;B0;
+                             B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]
+                 :  32 words$word)))) then
+     SOME (WFI () )
+   else if ((((((((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 25 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B1;B0;B0;B1]  :  7 words$word)))) /\ (((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  15 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B1;B1;B1;B0;B0;B1;B1]  :  15 words$word)))))))
+   then
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (SFENCE_VMA (rs1,rs2))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word))))))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (LOADRES (bit_to_bool aq,bit_to_bool rl,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (STORECON (bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B1]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOSWAP,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOADD,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOXOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOAND,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOOR,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMIN,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B0;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMAX,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B0;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMINU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,WORD,rd))
+   else if ((((((((regbits_to_regno ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 27 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B1;B1;B1;B0;B0]  :  5 words$word)))))) /\ ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B1;B0;B1;B1;B1;B1]  :  7 words$word)))))))))) then
+     let aq = (access_vec_dec v__0 (( 26 : int):sail_values$ii)) in
+     let rl = (access_vec_dec v__0 (( 25 : int):sail_values$ii)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 24 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (AMO (AMOMAXU,bit_to_bool aq,bit_to_bool rl,rs2,rs1,DOUBLE,rd))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,F,CSRRW))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,F,CSRRS))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,F,CSRRC))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,T,CSRRW))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,T,CSRRS))
+   else if ((((((((subrange_vec_dec v__0 (( 14 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__0 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B1;B1;B1;B0;B0;B1;B1]  :  7 words$word))))))) then
+     let (csr : 12 riscv_sequential_types$bits) = ((subrange_vec_dec v__0 (( 31 : int):sail_values$ii) (( 20 : int):sail_values$ii)  :  12 words$word)) in
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 19 : int):sail_values$ii) (( 15 : int):sail_values$ii)  :  5 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__0 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (CSR (csr,rs1,rd,T,CSRRC))
+   else NONE))`;
+
+
+val _ = Define `
+ ((decodeCompressed:(16)words$word ->(riscv_sequential_types$ast)option) v__418=   
+ (if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzi1 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (nzi0 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     if ((((((nzi1 = (vec_of_bits [B0]  :  1 words$word)))) /\ (((((regbits_to_regno nzi0)) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B0;B0]  :  5 words$word))))))))) then
+       SOME (NOP () )
+     else NONE
+   else if (((v__418 = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  16 words$word)))) then
+     SOME (ILLEGAL () )
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (nz54 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  2 words$word)) in
+     let (nz96 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  4 words$word)) in
+     let (nz2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)) in
+     let (nz3 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let nzimm =       
+((concat_vec nz96 ((concat_vec nz54 ((concat_vec nz3 nz2  :  2 words$word))  :  4 words$word))
+         :  8 words$word)) in
+     if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0]  :  8 words$word)))) then NONE
+     else SOME (C_ADDI4SPN (rd,nzimm))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)) in
+     let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  :  4 words$word))  :  5 words$word)) in
+     SOME (C_LW (uimm,rs1,rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) in
+     let (rd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let uimm = ((concat_vec ui76 ui53  :  5 words$word)) in
+     SOME (C_LD (uimm,rs1,rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs1 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui2 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)) in
+     let (ui6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let uimm = ((concat_vec ui6 ((concat_vec ui53 ui2  :  4 words$word))  :  5 words$word)) in
+     SOME (C_SW (uimm,rs1,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs1 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) in
+     let (rs2 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let uimm = ((concat_vec ui76 ui53  :  5 words$word)) in
+     SOME (C_SD (uimm,rs1,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (nzi40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let nzi = ((concat_vec nzi5 nzi40  :  6 words$word)) in
+     if ((((((nzi = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
+       NONE
+     else SOME (C_ADDI (nzi,rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (C_ADDIW ((concat_vec imm5 imm40  :  6 words$word),rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
+     else SOME (C_LI ((concat_vec imm5 imm40  :  6 words$word),rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ ((((((((regbits_to_regno ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)))) = ((regbits_to_regno (vec_of_bits [B0;B0;B0;B1;B0]  :  5 words$word)))))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzi9 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (nzi4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)) in
+     let (nzi6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  1 words$word)) in
+     let (nzi87 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  2 words$word)) in
+     let (nzi5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)) in
+     let nzimm =       
+((concat_vec nzi9
+          ((concat_vec nzi87 ((concat_vec nzi6 ((concat_vec nzi5 nzi4  :  2 words$word))  :  3 words$word))
+             :  5 words$word))
+         :  6 words$word)) in
+     if (((nzimm = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
+     else SOME (C_ADDI16SP nzimm)
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (imm17 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (imm1612 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     if ((((((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno sp)))))))) then
+       NONE
+     else SOME (C_LUI ((concat_vec imm17 imm1612  :  6 words$word),rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
+     if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
+     else SOME (C_SRLI (shamt,rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
+     if (((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) then NONE
+     else SOME (C_SRAI (shamt,rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B0]  :  3 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (i40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     SOME (C_ANDI ((concat_vec i5 i40  :  6 words$word),rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_SUB (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_XOR (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_OR (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B0;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_AND (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B0]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_SUBW (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  6 words$word)) = (vec_of_bits [B1;B0;B0;B1;B1;B1]  :  6 words$word)))) /\ ((((((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word)))))))))) then
+     let (rsd : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     SOME (C_ADDW (rsd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B0;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i11 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (i4 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 11 : int):sail_values$ii)  :  1 words$word)) in
+     let (i98 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 10 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  2 words$word)) in
+     let (i10 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 8 : int):sail_values$ii)  :  1 words$word)) in
+     let (i6 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 7 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  1 words$word)) in
+     let (i7 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 6 : int):sail_values$ii)  :  1 words$word)) in
+     let (i31 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 5 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  3 words$word)) in
+     let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)) in
+     SOME (C_J ((concat_vec i11
+                   ((concat_vec i10
+                       ((concat_vec i98
+                           ((concat_vec i7
+                               ((concat_vec i6
+                                   ((concat_vec i5 ((concat_vec i4 i31  :  4 words$word))  :  5 words$word))
+                                  :  6 words$word))
+                              :  7 words$word))
+                          :  9 words$word))
+                      :  10 words$word))
+                  :  11 words$word)))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)) in
+     let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) in
+     let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  2 words$word)) in
+     let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)) in
+     SOME (C_BEQZ ((concat_vec i8
+                      ((concat_vec i76
+                          ((concat_vec i5 ((concat_vec i43 i21  :  4 words$word))  :  5 words$word))
+                         :  7 words$word))
+                     :  8 words$word),rs))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B0;B1]  :  2 words$word))))))) then
+     let (i8 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (i43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  2 words$word)) in
+     let (rs : riscv_sequential_types$cregbits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (i76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) in
+     let (i21 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 3 : int):sail_values$ii)  :  2 words$word)) in
+     let (i5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 2 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  1 words$word)) in
+     SOME (C_BNEZ ((concat_vec i8
+                      ((concat_vec i76
+                          ((concat_vec i5 ((concat_vec i43 i21  :  4 words$word))  :  5 words$word))
+                         :  7 words$word))
+                     :  8 words$word),rs))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B0;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (nzui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (nzui40 : 5 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let (shamt : 6 riscv_sequential_types$bits) = ((concat_vec nzui5 nzui40  :  6 words$word)) in
+     if ((((((shamt = (vec_of_bits [B0;B0;B0;B0;B0;B0]  :  6 words$word)))) \/ (((((regbits_to_regno rsd)) = ((regbits_to_regno zreg)))))))) then
+       NONE
+     else SOME (C_SLLI (shamt,rsd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (ui42 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 4 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 3 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  2 words$word)) in
+     let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ((concat_vec ui5 ui42  :  4 words$word))  :  6 words$word)) in
+     if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
+     else SOME (C_LWSP (uimm,rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B0;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui5 : 1 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  1 words$word)) in
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (ui43 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 5 : int):sail_values$ii)  :  2 words$word)) in
+     let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 4 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  3 words$word)) in
+     let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ((concat_vec ui5 ui43  :  3 words$word))  :  6 words$word)) in
+     if (((((regbits_to_regno rd)) = ((regbits_to_regno zreg))))) then NONE
+     else SOME (C_LDSP (uimm,rd))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B0]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui52 : 4 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 9 : int):sail_values$ii)  :  4 words$word)) in
+     let (ui76 : 2 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 8 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  2 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui76 ui52  :  6 words$word)) in
+     SOME (C_SWSP (uimm,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 13 : int):sail_values$ii)  :  3 words$word)) = (vec_of_bits [B1;B1;B1]  :  3 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (ui53 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 12 : int):sail_values$ii) (( 10 : int):sail_values$ii)  :  3 words$word)) in
+     let (ui86 : 3 riscv_sequential_types$bits) = ((subrange_vec_dec v__418 (( 9 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  3 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     let (uimm : 6 riscv_sequential_types$bits) = ((concat_vec ui86 ui53  :  6 words$word)) in
+     SOME (C_SDSP (uimm,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE
+     else SOME (C_JR rs1)
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  7 words$word)) = (vec_of_bits [B0;B0;B0;B0;B0;B1;B0]  :  7 words$word))))))) then
+     let (rs1 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     if (((((regbits_to_regno rs1)) = ((regbits_to_regno zreg))))) then NONE
+     else SOME (C_JALR rs1)
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B0]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (rd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     if ((((((((regbits_to_regno rs2)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rd)) = ((regbits_to_regno zreg)))))))) then
+       NONE
+     else SOME (C_MV (rd,rs2))
+   else if ((((((((subrange_vec_dec v__418 (( 15 : int):sail_values$ii) (( 12 : int):sail_values$ii)  :  4 words$word)) = (vec_of_bits [B1;B0;B0;B1]  :  4 words$word)))) /\ (((((subrange_vec_dec v__418 (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B0]  :  2 words$word))))))) then
+     let (rsd : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 11 : int):sail_values$ii) (( 7 : int):sail_values$ii)  :  5 words$word)) in
+     let (rs2 : riscv_sequential_types$regbits) = ((subrange_vec_dec v__418 (( 6 : int):sail_values$ii) (( 2 : int):sail_values$ii)  :  5 words$word)) in
+     if ((((((((regbits_to_regno rsd)) = ((regbits_to_regno zreg))))) \/ (((((regbits_to_regno rs2)) = ((regbits_to_regno zreg)))))))) then
+       NONE
+     else SOME (C_ADD (rsd,rs2))
+   else NONE))`;
+
+
+(*val execute_WFI : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_WFI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__110=  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . 
+   (case w__0 of
+     Machine => returnS () 
+   | Supervisor => bindS      
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . 
+      if (((((get_Mstatus_TW w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+        handle_illegal () 
+      else returnS () )
+   | User => handle_illegal () 
+   ))))`;
+
+
+(*val execute_UTYPE : Machine_word.mword Machine_word.ty20 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.uop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_UTYPE:(20)words$word ->(5)words$word -> riscv_sequential_types$uop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd op=   
+ (let (off : riscv_sequential_types$xlenbits) =     
+((EXTS (( 64 : int):sail_values$ii)
+        ((concat_vec imm (vec_of_bits [B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0;B0]  :  12 words$word)
+           :  32 words$word))
+       :  64 words$word)) in bindS
+   (case op of
+     RISCV_LUI => returnS off
+   | RISCV_AUIPC => bindS
+      (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+      returnS ((add_vec w__0 off  :  64 words$word)))
+   ) (\ (ret : riscv_sequential_types$xlenbits) . 
+   wX ((regbits_to_regno rd)) ret)))`;
+
+
+(*val execute_STORECON : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_STORECON:bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs2 rs1 width rd=  (bindS   
+(speculate_conditional_success () ) (\ (w__0 : bool) . 
+   let (status : 1 riscv_sequential_types$bits) =     
+(if w__0 then (vec_of_bits [B0]  :  1 words$word)
+     else (vec_of_bits [B1]  :  1 words$word)) in seqS   
+(wX ((regbits_to_regno rd)) ((EXTZ (( 64 : int):sail_values$ii) status  :  64 words$word)))   
+(if (((status = (vec_of_bits [B1]  :  1 words$word)))) then returnS () 
+   else bindS
+     (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) .  bindS     
+(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . 
+     (case w__1 of
+       TR_Failure (e) => handle_mem_exception vaddr e
+     | TR_Address (addr) => bindS
+        (case width of
+          WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl T
+        | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl T
+        | _ => internal_error "STORECON expected word or double"
+        ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . 
+        (case eares of
+          MemException (e) => handle_mem_exception addr e
+        | MemValue (_) => bindS
+           (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val .  bindS
+           (case width of
+             WORD =>
+              mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                aq rl T
+           | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl T
+           | _ => internal_error "STORECON expected word or double"
+           ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . 
+           (case res of
+             MemValue (_) => returnS () 
+           | MemException (e) => handle_mem_exception addr e
+           )))
+        ))
+     )))))))`;
+
+
+(*val execute_STORE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_STORE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 width aq rl=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)) in bindS   
+(translateAddr vaddr Write Data) (\ (w__1 : riscv_sequential_types$TR_Result) . 
+   (case w__1 of
+     TR_Failure (e) => handle_mem_exception vaddr e
+   | TR_Address (addr) => bindS
+      (case width of
+        BYTE => mem_write_ea addr (( 1 : int):sail_values$ii) aq rl F
+      | HALF => mem_write_ea addr (( 2 : int):sail_values$ii) aq rl F
+      | WORD => mem_write_ea addr (( 4 : int):sail_values$ii) aq rl F
+      | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) aq rl F
+      ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . 
+      (case eares of
+        MemException (e) => handle_mem_exception addr e
+      | MemValue (_) => bindS
+         (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val .  bindS
+         (case width of
+           BYTE =>
+            mem_write_value addr (( 1 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 7 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  8 words$word)) aq
+              rl F
+         | HALF =>
+            mem_write_value addr (( 2 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word)) aq
+              rl F
+         | WORD =>
+            mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec rs2_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) aq
+              rl F
+         | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) rs2_val aq rl F
+         ) (\ (res : unit riscv_sequential_types$MemoryOpResult) . 
+         (case res of
+           MemValue (_) => returnS () 
+         | MemException (e) => handle_mem_exception addr e
+         )))
+      ))
+   )))))`;
+
+
+(*val execute_SRET : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_SRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__108=  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . 
+   (case w__0 of
+     User => handle_illegal () 
+   | Supervisor => bindS      
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) . 
+      if (((((get_Mstatus_TSR w__1  :  1 words$word)) = ((bool_to_bits T  :  1 words$word))))) then
+        handle_illegal () 
+      else bindS        
+(read_regS cur_privilege_ref) (\ (w__2 : riscv_sequential_types$Privilege) .  bindS
+        (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 :  64 words$word) .  bindS
+        (handle_exception w__2 (CTL_SRET () ) w__3  : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . 
+        write_regS nextPC_ref w__4))))
+   | Machine => bindS      
+(read_regS cur_privilege_ref) (\ (w__5 : riscv_sequential_types$Privilege) .  bindS
+      (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 :  64 words$word) .  bindS
+      (handle_exception w__5 (CTL_SRET () ) w__6  : ( 64 words$word) riscv_sequential_types$M) (\ (w__7 : riscv_sequential_types$xlenbits) . 
+      write_regS nextPC_ref w__7)))
+   ))))`;
+
+
+(*val execute_SHIFTW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_SHIFTW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in
+   let (result : 32 riscv_sequential_types$bits) =     
+((case op of
+       RISCV_SLLI => (shift_bits_left rs1_val shamt  :  32 words$word)
+     | RISCV_SRLI => (shift_bits_right rs1_val shamt  :  32 words$word)
+     | RISCV_SRAI => (shift_right_arith32 rs1_val shamt  :  32 words$word)
+     )) in
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result  :  64 words$word)))))`;
+
+
+(*val execute_SHIFTIOP : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.sop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_SHIFTIOP:(6)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$sop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) shamt rs1 rd op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . 
+   let (result : riscv_sequential_types$xlenbits) =     
+((case op of
+       RISCV_SLLI => (shift_bits_left rs1_val shamt  :  64 words$word)
+     | RISCV_SRLI => (shift_bits_right rs1_val shamt  :  64 words$word)
+     | RISCV_SRAI => (shift_right_arith64 rs1_val shamt  :  64 words$word)
+     )) in
+   wX ((regbits_to_regno rd)) result)))`;
+
+
+(*val execute_SFENCE_VMA : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_SFENCE_VMA:(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs1 rs2=  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . 
+   if (((((privLevel_to_bits w__0  :  2 words$word)) = ((privLevel_to_bits User  :  2 words$word)))))
+   then
+     handle_illegal () 
+   else bindS     
+(read_regS mstatus_ref) (\ (w__1 : riscv_sequential_types$Mstatus) .  bindS     
+(read_regS mstatus_ref) (\ (w__2 : riscv_sequential_types$Mstatus) . 
+     let p__104 =
+       (architecture ((get_Mstatus_SXL w__1  :  2 words$word)), (get_Mstatus_TVM w__2  :  1 words$word)) in
+     (case p__104 of
+       (SOME (RV64), v_0) =>
+        if (((v_0 = ((bool_to_bits T  :  1 words$word))))) then handle_illegal () 
+        else bindS
+          (if (((((regbits_to_regno rs1)) = (( 0 : int):sail_values$ii)))) then returnS NONE
+           else bindS
+             (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 :  64 words$word) . 
+             returnS (SOME ((subrange_vec_dec w__3 (( 38 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  39 words$word))))) (\ (addr :
+             riscv_sequential_types$vaddr39 option) .  bindS
+          (if (((((regbits_to_regno rs2)) = (( 0 : int):sail_values$ii)))) then returnS NONE
+           else bindS
+             (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 :  64 words$word) . 
+             returnS (SOME ((subrange_vec_dec w__4 (( 15 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  16 words$word))))) (\ (asid :
+             riscv_sequential_types$asid64 option) . 
+          flushTLB asid addr))
+     | (g__102, g__103) => internal_error "unimplemented sfence architecture"
+     ))))))`;
+
+
+(*val execute_RTYPEW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.ropw -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_RTYPEW:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$ropw ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in
+   let (result : 32 riscv_sequential_types$bits) =     
+((case op of
+       RISCV_ADDW => (add_vec rs1_val rs2_val  :  32 words$word)
+     | RISCV_SUBW => (sub_vec rs1_val rs2_val  :  32 words$word)
+     | RISCV_SLLW =>
+        (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word))
+          :  32 words$word)
+     | RISCV_SRLW =>
+        (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word))
+          :  32 words$word)
+     | RISCV_SRAW =>
+        (shift_right_arith32 rs1_val ((subrange_vec_dec rs2_val (( 4 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  5 words$word))
+          :  32 words$word)
+     )) in
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) result  :  64 words$word))))))`;
+
+
+(*val execute_RTYPE : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.rop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_RTYPE:(5)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$rop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val .  bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . 
+   let (result : riscv_sequential_types$xlenbits) =     
+((case op of
+       RISCV_ADD => (add_vec rs1_val rs2_val  :  64 words$word)
+     | RISCV_SUB => (sub_vec rs1_val rs2_val  :  64 words$word)
+     | RISCV_SLL =>
+        (shift_bits_left rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+          :  64 words$word)
+     | RISCV_SLT =>
+        (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val))))  :  1 words$word))  :  64 words$word)
+     | RISCV_SLTU =>
+        (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui rs2_val))))  :  1 words$word))  :  64 words$word)
+     | RISCV_XOR => (xor_vec rs1_val rs2_val  :  64 words$word)
+     | RISCV_SRL =>
+        (shift_bits_right rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+          :  64 words$word)
+     | RISCV_SRA =>
+        (shift_right_arith64 rs1_val ((subrange_vec_dec rs2_val (( 5 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  6 words$word))
+          :  64 words$word)
+     | RISCV_OR => (or_vec rs1_val rs2_val  :  64 words$word)
+     | RISCV_AND => (and_vec rs1_val rs2_val  :  64 words$word)
+     )) in
+   wX ((regbits_to_regno rd)) result))))`;
+
+
+(*val execute_RISCV_JALR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_RISCV_JALR:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd=  (bindS
+   (read_regS nextPC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) .  bindS (seqS   
+(wX ((regbits_to_regno rd)) w__0)
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M)) (\ (w__1 :  64 words$word) . 
+   let (newPC : riscv_sequential_types$xlenbits) = ((add_vec w__1 ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)) in
+   write_regS
+     nextPC_ref
+     ((concat_vec ((subrange_vec_dec newPC (( 63 : int):sail_values$ii) (( 1 : int):sail_values$ii)  :  63 words$word))
+         (vec_of_bits [B0]  :  1 words$word)
+        :  64 words$word))))))`;
+
+
+(*val execute_RISCV_JAL : Machine_word.mword Machine_word.ty21 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_RISCV_JAL:(21)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rd=  (bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (pc : riscv_sequential_types$xlenbits) .  bindS
+   (read_regS nextPC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) .  seqS   
+(wX ((regbits_to_regno rd)) w__0)   
+(let (offset : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word)) in
+   write_regS nextPC_ref ((add_vec pc offset  :  64 words$word)))))))`;
+
+
+(*val execute_REMW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_REMW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in
+   let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+   let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+   let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) r  :  32 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_REM : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_REM:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val .  bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . 
+   let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+   let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+   let (r : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then rs1_int else hardware_mod rs1_int rs2_int) in
+   wX ((regbits_to_regno rd)) ((to_bits xlen r  :  64 words$word))))))`;
+
+
+(*val execute_NOP : unit -> unit*)
+
+ val _ = Define `
+ ((execute_NOP:unit -> unit) g__111=  () )`;
+
+
+(*val execute_MULW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_MULW:(5)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in
+   let (rs1_int : sail_values$ii) = (integer_word$w2i rs1_val) in
+   let (rs2_int : sail_values$ii) = (integer_word$w2i rs2_val) in
+   let result32 =     
+((subrange_vec_dec ((to_bits (( 64 : int):sail_values$ii) ((rs1_int * rs2_int))  :  64 words$word)) (( 31 : int):sail_values$ii)
+        (( 0 : int):sail_values$ii)
+       :  32 words$word)) in
+   let (result : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) result32  :  64 words$word)) in
+   wX ((regbits_to_regno rd)) result))))`;
+
+
+(*val execute_MUL : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> bool -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_MUL:(5)words$word ->(5)words$word ->(5)words$word -> bool -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd high signed1 signed2=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val .  bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . 
+   let (rs1_int : sail_values$ii) = (if signed1 then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+   let (rs2_int : sail_values$ii) = (if signed2 then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+   let result128 = ((to_bits (( 128 : int):sail_values$ii) ((rs1_int * rs2_int))  :  128 words$word)) in
+   let result =     
+(if high then (subrange_vec_dec result128 (( 127 : int):sail_values$ii) (( 64 : int):sail_values$ii)  :  64 words$word)
+     else (subrange_vec_dec result128 (( 63 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  64 words$word)) in
+   wX ((regbits_to_regno rd)) result))))`;
+
+
+(*val execute_MRET : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_MRET:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__107=  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . 
+   if (((((privLevel_to_bits w__0  :  2 words$word)) = ((privLevel_to_bits Machine  :  2 words$word)))))
+   then bindS     
+(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) .  bindS
+     (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 :  64 words$word) .  bindS
+     (handle_exception w__1 (CTL_MRET () ) w__2  : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . 
+     write_regS nextPC_ref w__3)))
+   else handle_illegal () )))`;
+
+
+(*val execute_LOADRES : bool -> bool -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_LOADRES:bool -> bool ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) aq rl rs1 width rd=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) .  bindS   
+(translateAddr vaddr Read Data) (\ (w__0 : riscv_sequential_types$TR_Result) . 
+   (case w__0 of
+     TR_Failure (e) => handle_mem_exception vaddr e
+   | TR_Address (addr) =>
+      (case width of
+        WORD => bindS
+         (mem_read addr (( 4 : int):sail_values$ii) aq rl T  : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__1 : ( 32 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd addr w__1 F)
+      | DOUBLE => bindS
+         (mem_read addr (( 8 : int):sail_values$ii) aq rl T  : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 64 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd addr w__2 F)
+      | _ => internal_error "LOADRES expected WORD or DOUBLE"
+      )
+   )))))`;
+
+
+(*val execute_LOAD : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.word_width -> bool -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_LOAD:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$word_width -> bool -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd is_unsigned width aq rl=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let (vaddr : riscv_sequential_types$xlenbits) = ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)) in bindS   
+(translateAddr vaddr Read Data) (\ (w__1 : riscv_sequential_types$TR_Result) . 
+   (case w__1 of
+     TR_Failure (e) => handle_mem_exception vaddr e
+   | TR_Address (addr) =>
+      (case width of
+        BYTE => bindS
+         (mem_read addr (( 1 : int):sail_values$ii) aq rl F  : ( ( 8 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__2 : ( 8 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd vaddr w__2 is_unsigned)
+      | HALF => bindS
+         (mem_read addr (( 2 : int):sail_values$ii) aq rl F  : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__3 : ( 16 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd vaddr w__3 is_unsigned)
+      | WORD => bindS
+         (mem_read addr (( 4 : int):sail_values$ii) aq rl F  : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd vaddr w__4 is_unsigned)
+      | DOUBLE => bindS
+         (mem_read addr (( 8 : int):sail_values$ii) aq rl F  : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word)
+           riscv_sequential_types$MemoryOpResult) . 
+         process_load rd vaddr w__5 is_unsigned)
+      )
+   )))))`;
+
+
+(*val execute_ITYPE : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.iop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_ITYPE:(12)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$iop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val . 
+   let (immext : riscv_sequential_types$xlenbits) = ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word)) in
+   let (result : riscv_sequential_types$xlenbits) =     
+((case op of
+       RISCV_ADDI => (add_vec rs1_val immext  :  64 words$word)
+     | RISCV_SLTI =>
+        (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((integer_word$w2i rs1_val) < (integer_word$w2i immext))))  :  1 words$word))  :  64 words$word)
+     | RISCV_SLTIU =>
+        (EXTZ (( 64 : int):sail_values$ii) ((bool_to_bits ((((lem$w2ui rs1_val) < (lem$w2ui immext))))  :  1 words$word))  :  64 words$word)
+     | RISCV_XORI => (xor_vec rs1_val immext  :  64 words$word)
+     | RISCV_ORI => (or_vec rs1_val immext  :  64 words$word)
+     | RISCV_ANDI => (and_vec rs1_val immext  :  64 words$word)
+     )) in
+   wX ((regbits_to_regno rd)) result)))`;
+
+
+(*val execute_ILLEGAL : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_ILLEGAL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__112=  (handle_illegal () ))`;
+
+
+(*val execute_FENCEI : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_FENCEI:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__105=  (MEM_fence_i () ))`;
+
+
+(*val execute_FENCE : Machine_word.mword Machine_word.ty4 -> Machine_word.mword Machine_word.ty4 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_FENCE:(4)words$word ->(4)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) pred succ= 
+  ((case (pred, succ) of
+         (b__0, b__1) =>
+   if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\
+           (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then
+     MEM_fence_rw_rw ()  else
+     if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\
+             (((b__1 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word))))))) then
+       MEM_fence_r_rw ()  else
+       if ((((((b__0 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word)))) /\
+               (((b__1 = (vec_of_bits [B0;B0;B1;B0] : 4 words$word))))))) then
+         MEM_fence_r_r ()  else
+         if ((((((b__0 = (vec_of_bits [B0;B0;B1;B1] : 4 words$word)))) /\
+                 (((b__1 = (vec_of_bits [B0;B0;B0;B1] : 4 words$word))))))) then
+           MEM_fence_rw_w ()  else MEM_fence_w_w () 
+   )))`;
+
+
+(*val execute_ECALL : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_ECALL:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__106=  (bindS   
+(read_regS cur_privilege_ref) (\ (w__0 : riscv_sequential_types$Privilege) . 
+   let (t : riscv_sequential_types$sync_exception) =     
+(<| sync_exception_trap :=
+          ((case w__0 of
+             User => E_U_EnvCall
+           | Supervisor => E_S_EnvCall
+           | Machine => E_M_EnvCall
+           )); 
+        sync_exception_excinfo := NONE |>) in bindS   
+(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) .  bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__2 :  64 words$word) .  bindS
+   (handle_exception w__1 (CTL_TRAP t) w__2  : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 : riscv_sequential_types$xlenbits) . 
+   write_regS nextPC_ref w__3))))))`;
+
+
+(*val execute_EBREAK : unit -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_EBREAK:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) g__109=  (throwS (Error_EBREAK () )))`;
+
+
+(*val execute_DIVW : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_DIVW:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let rs1_val = ((subrange_vec_dec w__0 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 :  64 words$word) . 
+   let rs2_val = ((subrange_vec_dec w__1 (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) in
+   let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+   let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+   let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in
+   let (q' : sail_values$ii) =     
+(if (((s /\ ((q > ((((pow2 (( 31 : int):sail_values$ii))) - (( 1 : int):sail_values$ii)))))))) then
+       (( 0 : int):sail_values$ii) - ((ex_int ((pow0 (( 2 : int):sail_values$ii) (( 31 : int):sail_values$ii)))))
+     else q) in
+   wX ((regbits_to_regno rd)) ((EXTS (( 64 : int):sail_values$ii) ((to_bits (( 32 : int):sail_values$ii) q'  :  32 words$word))  :  64 words$word))))))`;
+
+
+(*val execute_DIV : Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_DIV:(5)words$word ->(5)words$word ->(5)words$word -> bool ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) rs2 rs1 rd s=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val .  bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . 
+   let (rs1_int : sail_values$ii) = (if s then integer_word$w2i rs1_val else lem$w2ui rs1_val) in
+   let (rs2_int : sail_values$ii) = (if s then integer_word$w2i rs2_val else lem$w2ui rs2_val) in
+   let (q : sail_values$ii) = (if (((rs2_int = (( 0 : int):sail_values$ii)))) then ((( 0 : int)-( 1 : int)):sail_values$ii) else hardware_quot rs1_int rs2_int) in
+   let (q' : sail_values$ii) = (if (((s /\ ((q > xlen_max_signed))))) then xlen_min_signed else q) in
+   wX ((regbits_to_regno rd)) ((to_bits xlen q'  :  64 words$word))))))`;
+
+
+(*val execute_C_ADDIW : Machine_word.mword Machine_word.ty6 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_C_ADDIW:(6)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rsd=   
+ (let (imm : 32 riscv_sequential_types$bits) = ((EXTS (( 32 : int):sail_values$ii) imm  :  32 words$word)) in bindS
+   (rX ((regbits_to_regno rsd))  : ( 64 words$word) riscv_sequential_types$M) (\ rs_val . 
+   let (res : 32 riscv_sequential_types$bits) =     
+((add_vec ((subrange_vec_dec rs_val (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word)) imm  :  32 words$word)) in
+   wX ((regbits_to_regno rsd)) ((EXTS (( 64 : int):sail_values$ii) res  :  64 words$word)))))`;
+
+
+(*val execute_CSR : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> bool -> Riscv_sequential_types.csrop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_CSR:(12)words$word ->(5)words$word ->(5)words$word -> bool -> riscv_sequential_types$csrop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) csr rs1 rd is_imm op=  (bindS
+   (if is_imm then returnS ((EXTZ (( 64 : int):sail_values$ii) rs1  :  64 words$word))
+    else (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M)) (\ (rs1_val : riscv_sequential_types$xlenbits) . 
+   let (isWrite : bool) =     
+((case op of
+       CSRRW => T
+     | _ => if is_imm then (((lem$w2ui rs1_val)) <> (( 0 : int):sail_values$ii)) else (((lem$w2ui rs1)) <> (( 0 : int):sail_values$ii))
+     )) in bindS   
+(read_regS cur_privilege_ref) (\ (w__1 : riscv_sequential_types$Privilege) .  bindS   
+(check_CSR csr w__1 isWrite) (\ (w__2 : bool) . 
+   if ((~ w__2)) then handle_illegal () 
+   else bindS
+     (readCSR csr  : ( 64 words$word) riscv_sequential_types$M) (\ csr_val .  seqS
+     (if isWrite then
+        let (new_val : riscv_sequential_types$xlenbits) =          
+((case op of
+            CSRRW => rs1_val
+          | CSRRS => (or_vec csr_val rs1_val  :  64 words$word)
+          | CSRRC => (and_vec csr_val ((not_vec rs1_val  :  64 words$word))  :  64 words$word)
+          )) in
+        writeCSR csr new_val
+      else returnS () )     
+(wX ((regbits_to_regno rd)) csr_val)))))))`;
+
+
+(*val execute_BTYPE : Machine_word.mword Machine_word.ty13 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.bop -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_BTYPE:(13)words$word ->(5)words$word ->(5)words$word -> riscv_sequential_types$bop ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs2 rs1 op=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ rs1_val .  bindS
+   (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ rs2_val . 
+   let (taken : bool) =     
+((case op of
+       RISCV_BEQ => (rs1_val = rs2_val)
+     | RISCV_BNE => (rs1_val <> rs2_val)
+     | RISCV_BLT => ((integer_word$w2i rs1_val) < (integer_word$w2i rs2_val))
+     | RISCV_BGE => ((integer_word$w2i rs1_val) >= (integer_word$w2i rs2_val))
+     | RISCV_BLTU => ((lem$w2ui rs1_val) < (lem$w2ui rs2_val))
+     | RISCV_BGEU => ((lem$w2ui rs1_val) >= (lem$w2ui rs2_val))
+     )) in
+   if taken then bindS
+     (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+     write_regS nextPC_ref ((add_vec w__0 ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word))  :  64 words$word)))
+   else returnS () ))))`;
+
+
+(*val execute_AMO : Riscv_sequential_types.amoop -> bool -> bool -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.word_width -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_AMO:riscv_sequential_types$amoop -> bool -> bool ->(5)words$word ->(5)words$word -> riscv_sequential_types$word_width ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) op aq rl rs2 rs1 width rd=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (vaddr : riscv_sequential_types$xlenbits) .  bindS   
+(translateAddr vaddr ReadWrite Data) (\ (w__0 : riscv_sequential_types$TR_Result) . 
+   (case w__0 of
+     TR_Failure (e) => handle_mem_exception vaddr e
+   | TR_Address (addr) => bindS
+      (case width of
+        WORD => mem_write_ea addr (( 4 : int):sail_values$ii) (((aq /\ rl))) rl T
+      | DOUBLE => mem_write_ea addr (( 8 : int):sail_values$ii) (((aq /\ rl))) rl T
+      | _ => internal_error "AMO expected WORD or DOUBLE"
+      ) (\ (eares : unit riscv_sequential_types$MemoryOpResult) . 
+      (case eares of
+        MemException (e) => handle_mem_exception addr e
+      | MemValue (_) => bindS
+         (case width of
+           WORD => bindS
+            (mem_read addr (( 4 : int):sail_values$ii) aq (((aq /\ rl))) T  : ( ( 32 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__4 : ( 32 words$word)
+              riscv_sequential_types$MemoryOpResult) . 
+            returnS ((extend_value F w__4  : ( 64 words$word) riscv_sequential_types$MemoryOpResult)))
+         | DOUBLE => bindS
+            (mem_read addr (( 8 : int):sail_values$ii) aq (((aq /\ rl))) T  : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__5 : ( 64 words$word)
+              riscv_sequential_types$MemoryOpResult) . 
+            returnS ((extend_value F w__5  : ( 64 words$word) riscv_sequential_types$MemoryOpResult)))
+         | _ => (internal_error "AMO expected WORD or DOUBLE"  : ( ( 64 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M)
+         ) (\ (rval : riscv_sequential_types$xlenbits riscv_sequential_types$MemoryOpResult) . 
+         (case rval of
+           MemException (e) => handle_mem_exception addr e
+         | MemValue (loaded) => bindS
+            (rX ((regbits_to_regno rs2))  : ( 64 words$word) riscv_sequential_types$M) (\ (rs2_val : riscv_sequential_types$xlenbits) . 
+            let (result : riscv_sequential_types$xlenbits) =              
+((case op of
+                AMOSWAP => rs2_val
+              | AMOADD => (add_vec rs2_val loaded  :  64 words$word)
+              | AMOXOR => (xor_vec rs2_val loaded  :  64 words$word)
+              | AMOAND => (and_vec rs2_val loaded  :  64 words$word)
+              | AMOOR => (or_vec rs2_val loaded  :  64 words$word)
+              | AMOMIN => (vector64 ((int_min ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded))))  :  64 words$word)
+              | AMOMAX => (vector64 ((int_max ((integer_word$w2i rs2_val)) ((integer_word$w2i loaded))))  :  64 words$word)
+              | AMOMINU => (vector64 ((int_min ((lem$w2ui rs2_val)) ((lem$w2ui loaded))))  :  64 words$word)
+              | AMOMAXU => (vector64 ((int_max ((lem$w2ui rs2_val)) ((lem$w2ui loaded))))  :  64 words$word)
+              )) in bindS
+            (case width of
+              WORD =>
+               mem_write_value addr (( 4 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))
+                 (((aq /\ rl))) rl T
+            | DOUBLE => mem_write_value addr (( 8 : int):sail_values$ii) result (((aq /\ rl))) rl T
+            | _ => internal_error "AMO expected WORD or DOUBLE"
+            ) (\ (wval : unit riscv_sequential_types$MemoryOpResult) . 
+            (case wval of
+              MemValue (_) => wX ((regbits_to_regno rd)) loaded
+            | MemException (e) => handle_mem_exception addr e
+            )))
+         ))
+      ))
+   )))))`;
+
+
+(*val execute_ADDIW : Machine_word.mword Machine_word.ty12 -> Machine_word.mword Machine_word.ty5 -> Machine_word.mword Machine_word.ty5 -> Riscv_sequential_types.M unit*)
+
+ val _ = Define `
+ ((execute_ADDIW:(12)words$word ->(5)words$word ->(5)words$word ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) imm rs1 rd=  (bindS
+   (rX ((regbits_to_regno rs1))  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 :  64 words$word) . 
+   let (result : riscv_sequential_types$xlenbits) = ((add_vec ((EXTS (( 64 : int):sail_values$ii) imm  :  64 words$word)) w__0  :  64 words$word)) in
+   wX ((regbits_to_regno rd))
+     ((EXTS (( 64 : int):sail_values$ii) ((subrange_vec_dec result (( 31 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  32 words$word))  :  64 words$word)))))`;
+
+
+ val execute_defn = Hol_defn "execute" `
+ ((execute:riscv_sequential_types$ast ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((unit),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) merge_var=   
+ ((case merge_var of
+     C_ADDI4SPN (rdc,nzimm) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((concat_vec (vec_of_bits [B0;B0]  :  2 words$word)
+           ((concat_vec nzimm (vec_of_bits [B0;B0]  :  2 words$word)  :  10 words$word))
+          :  12 words$word)) in
+      let rd = ((creg2reg_bits rdc  :  5 words$word)) in
+      execute (ITYPE (imm,sp,rd,RISCV_ADDI))
+   | C_LW (uimm,rsc,rdc) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0]  :  2 words$word)  :  7 words$word))
+          :  12 words$word)) in
+      let rd = ((creg2reg_bits rdc  :  5 words$word)) in
+      let rs = ((creg2reg_bits rsc  :  5 words$word)) in
+      execute (LOAD (imm,rs,rd,F,WORD,F,F))
+   | C_LD (uimm,rsc,rdc) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0]  :  3 words$word)  :  8 words$word))
+          :  12 words$word)) in
+      let rd = ((creg2reg_bits rdc  :  5 words$word)) in
+      let rs = ((creg2reg_bits rsc  :  5 words$word)) in
+      execute (LOAD (imm,rs,rd,F,DOUBLE,F,F))
+   | C_SW (uimm,rsc1,rsc2) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0]  :  2 words$word)  :  7 words$word))
+          :  12 words$word)) in
+      let rs1 = ((creg2reg_bits rsc1  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rsc2  :  5 words$word)) in
+      execute (STORE (imm,rs2,rs1,WORD,F,F))
+   | C_SD (uimm,rsc1,rsc2) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0]  :  3 words$word)  :  8 words$word))
+          :  12 words$word)) in
+      let rs1 = ((creg2reg_bits rsc1  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rsc2  :  5 words$word)) in
+      execute (STORE (imm,rs2,rs1,DOUBLE,F,F))
+   | C_ADDI (nzi,rsd) =>
+      let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) nzi  :  12 words$word)) in
+      execute (ITYPE (imm,rsd,rsd,RISCV_ADDI))
+   | C_JAL (imm) =>
+      execute
+        (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0]  :  1 words$word)  :  12 words$word))
+                      :  21 words$word),ra))
+   | C_LI (imm,rd) =>
+      let (imm : 12 riscv_sequential_types$bits) = ((EXTS (( 12 : int):sail_values$ii) imm  :  12 words$word)) in
+      execute (ITYPE (imm,zreg,rd,RISCV_ADDI))
+   | C_ADDI16SP (imm) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTS (( 12 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0;B0;B0;B0]  :  4 words$word)  :  10 words$word))
+          :  12 words$word)) in
+      execute (ITYPE (imm,sp,sp,RISCV_ADDI))
+   | C_LUI (imm,rd) =>
+      let (res : 20 riscv_sequential_types$bits) = ((EXTS (( 20 : int):sail_values$ii) imm  :  20 words$word)) in
+      execute (UTYPE (res,rd,RISCV_LUI))
+   | C_SRLI (shamt,rsd) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRLI))
+   | C_SRAI (shamt,rsd) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SRAI))
+   | C_ANDI (imm,rsd) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      execute (ITYPE ((EXTS (( 12 : int):sail_values$ii) imm  :  12 words$word),rsd,rsd,RISCV_ANDI))
+   | C_SUB (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPE (rs2,rsd,rsd,RISCV_SUB))
+   | C_XOR (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPE (rs2,rsd,rsd,RISCV_XOR))
+   | C_OR (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPE (rs2,rsd,rsd,RISCV_OR))
+   | C_AND (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPE (rs2,rsd,rsd,RISCV_AND))
+   | C_SUBW (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPEW (rs2,rsd,rsd,RISCV_SUBW))
+   | C_ADDW (rsd,rs2) =>
+      let rsd = ((creg2reg_bits rsd  :  5 words$word)) in
+      let rs2 = ((creg2reg_bits rs2  :  5 words$word)) in
+      execute (RTYPEW (rs2,rsd,rsd,RISCV_ADDW))
+   | C_J (imm) =>
+      execute
+        (RISCV_JAL ((EXTS (( 21 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0]  :  1 words$word)  :  12 words$word))
+                      :  21 words$word),zreg))
+   | C_BEQZ (imm,rs) =>
+      execute
+        (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0]  :  1 words$word)  :  9 words$word))
+                  :  13 words$word),zreg,(creg2reg_bits rs  :  5 words$word),RISCV_BEQ))
+   | C_BNEZ (imm,rs) =>
+      execute
+        (BTYPE ((EXTS (( 13 : int):sail_values$ii) ((concat_vec imm (vec_of_bits [B0]  :  1 words$word)  :  9 words$word))
+                  :  13 words$word),zreg,(creg2reg_bits rs  :  5 words$word),RISCV_BNE))
+   | C_SLLI (shamt,rsd) => execute (SHIFTIOP (shamt,rsd,rsd,RISCV_SLLI))
+   | C_LWSP (uimm,rd) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0]  :  2 words$word)  :  8 words$word))
+          :  12 words$word)) in
+      execute (LOAD (imm,sp,rd,F,WORD,F,F))
+   | C_LDSP (uimm,rd) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0]  :  3 words$word)  :  9 words$word))
+          :  12 words$word)) in
+      execute (LOAD (imm,sp,rd,F,DOUBLE,F,F))
+   | C_SWSP (uimm,rs2) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0]  :  2 words$word)  :  8 words$word))
+          :  12 words$word)) in
+      execute (STORE (imm,rs2,sp,WORD,F,F))
+   | C_SDSP (uimm,rs2) =>
+      let (imm : 12 riscv_sequential_types$bits) =        
+((EXTZ (( 12 : int):sail_values$ii) ((concat_vec uimm (vec_of_bits [B0;B0;B0]  :  3 words$word)  :  9 words$word))
+          :  12 words$word)) in
+      execute (STORE (imm,rs2,sp,DOUBLE,F,F))
+   | C_JR (rs1) =>
+      execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  12 words$word),rs1,zreg))
+   | C_JALR (rs1) =>
+      execute (RISCV_JALR ((EXTZ (( 12 : int):sail_values$ii) (vec_of_bits [B0]  :  1 words$word)  :  12 words$word),rs1,ra))
+   | C_MV (rd,rs2) => execute (RTYPE (rs2,zreg,rd,RISCV_ADD))
+   | C_ADD (rsd,rs2) => execute (RTYPE (rs2,rsd,rsd,RISCV_ADD))
+   | UTYPE (imm,rd,op) => execute_UTYPE imm rd op
+   | RISCV_JAL (imm,rd) => execute_RISCV_JAL imm rd
+   | RISCV_JALR (imm,rs1,rd) => execute_RISCV_JALR imm rs1 rd
+   | BTYPE (imm,rs2,rs1,op) => execute_BTYPE imm rs2 rs1 op
+   | ITYPE (imm,rs1,rd,op) => execute_ITYPE imm rs1 rd op
+   | SHIFTIOP (shamt,rs1,rd,op) => execute_SHIFTIOP shamt rs1 rd op
+   | RTYPE (rs2,rs1,rd,op) => execute_RTYPE rs2 rs1 rd op
+   | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) => execute_LOAD imm rs1 rd is_unsigned width aq rl
+   | STORE (imm,rs2,rs1,width,aq,rl) => execute_STORE imm rs2 rs1 width aq rl
+   | ADDIW (imm,rs1,rd) => execute_ADDIW imm rs1 rd
+   | SHIFTW (shamt,rs1,rd,op) => execute_SHIFTW shamt rs1 rd op
+   | RTYPEW (rs2,rs1,rd,op) => execute_RTYPEW rs2 rs1 rd op
+   | MUL (rs2,rs1,rd,high,signed1,signed2) => execute_MUL rs2 rs1 rd high signed1 signed2
+   | DIV0 (rs2,rs1,rd,s) => execute_DIV rs2 rs1 rd s
+   | REM (rs2,rs1,rd,s) => execute_REM rs2 rs1 rd s
+   | MULW (rs2,rs1,rd) => execute_MULW rs2 rs1 rd
+   | DIVW (rs2,rs1,rd,s) => execute_DIVW rs2 rs1 rd s
+   | REMW (rs2,rs1,rd,s) => execute_REMW rs2 rs1 rd s
+   | FENCE (pred,succ) => execute_FENCE pred succ
+   | FENCEI (g__105) => execute_FENCEI g__105
+   | ECALL (g__106) => execute_ECALL g__106
+   | MRET (g__107) => execute_MRET g__107
+   | SRET (g__108) => execute_SRET g__108
+   | EBREAK (g__109) => execute_EBREAK g__109
+   | WFI (g__110) => execute_WFI g__110
+   | SFENCE_VMA (rs1,rs2) => execute_SFENCE_VMA rs1 rs2
+   | LOADRES (aq,rl,rs1,width,rd) => execute_LOADRES aq rl rs1 width rd
+   | STORECON (aq,rl,rs2,rs1,width,rd) => execute_STORECON aq rl rs2 rs1 width rd
+   | AMO (op,aq,rl,rs2,rs1,width,rd) => execute_AMO op aq rl rs2 rs1 width rd
+   | CSR (csr,rs1,rd,is_imm,op) => execute_CSR csr rs1 rd is_imm op
+   | NOP (g__111) => returnS ((execute_NOP g__111))
+   | ILLEGAL (g__112) => execute_ILLEGAL g__112
+   | C_ADDIW (imm,rsd) => execute_C_ADDIW imm rsd
+   )))`;
+
+val _ = Lib.with_flag (computeLib.auto_import_definitions, false) Defn.save_defn execute_defn;
+
+val _ = Define `
+ ((print_insn:riscv_sequential_types$ast -> string) merge_var=   
+ ((case merge_var of
+     UTYPE (imm,rd,op) =>
+      (case op of
+        RISCV_LUI =>
+         STRCAT "lui   "
+           ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+      | RISCV_AUIPC =>
+         STRCAT "auipc "
+           ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+      )
+   | RISCV_JAL (imm,rd) =>
+      STRCAT "jal   "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+   | RISCV_JALR (imm,rs1,rd) =>
+      STRCAT "jalr  "
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | BTYPE (imm,rs2,rs1,op) =>
+      let (insn : string) =        
+((case op of
+          RISCV_BEQ => "beq   "
+        | RISCV_BNE => "bne   "
+        | RISCV_BLT => "blt   "
+        | RISCV_BGE => "bge   "
+        | RISCV_BLTU => "bltu  "
+        | RISCV_BGEU => "bgeu  "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rs1))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs2)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | ITYPE (imm,rs1,rd,op) =>
+      let (insn : string) =        
+((case op of
+          RISCV_ADDI => "addi  "
+        | RISCV_SLTI => "slti  "
+        | RISCV_SLTIU => "sltiu "
+        | RISCV_XORI => "xori  "
+        | RISCV_ORI => "ori   "
+        | RISCV_ANDI => "andi  "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | SHIFTIOP (shamt,rs1,rd,op) =>
+      let (insn : string) =        
+((case op of   RISCV_SLLI => "slli  " | RISCV_SRLI => "srli  " | RISCV_SRAI => "srai  " )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt))))))))))
+   | RTYPE (rs2,rs1,rd,op) =>
+      let (insn : string) =        
+((case op of
+          RISCV_ADD => "add   "
+        | RISCV_SUB => "sub   "
+        | RISCV_SLL => "sll   "
+        | RISCV_SLT => "slt   "
+        | RISCV_SLTU => "sltu  "
+        | RISCV_XOR => "xor   "
+        | RISCV_SRL => "srl   "
+        | RISCV_SRA => "sra   "
+        | RISCV_OR => "or    "
+        | RISCV_AND => "and   "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | LOAD (imm,rs1,rd,is_unsigned,width,aq,rl) =>
+      let (insn : string) =        
+((case (width, is_unsigned) of
+          (BYTE, F) => "lb    "
+        | (BYTE, T) => "lbu   "
+        | (HALF, F) => "lh    "
+        | (HALF, T) => "lhu   "
+        | (WORD, F) => "lw    "
+        | (WORD, T) => "lwu   "
+        | (_, _) => "ld.bad "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | STORE (imm,rs2,rs1,width,aq,rl) =>
+      let (insn : string) =        
+((case width of
+          BYTE => "sb    "
+        | HALF => "sh    "
+        | WORD => "sw    "
+        | DOUBLE => "sd    "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rs2))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | ADDIW (imm,rs1,rd) =>
+      STRCAT "addiw "
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec imm))))))))))
+   | SHIFTW (shamt,rs1,rd,op) =>
+      let (insn : string) =        
+((case op of   RISCV_SLLI => "slli  " | RISCV_SRLI => "srli  " | RISCV_SRAI => "srai  " )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((string_of_vec shamt))))))))))
+   | RTYPEW (rs2,rs1,rd,op) =>
+      let (insn : string) =        
+((case op of
+          RISCV_ADDW => "addw  "
+        | RISCV_SUBW => "subw  "
+        | RISCV_SLLW => "sllw  "
+        | RISCV_SRLW => "srlw  "
+        | RISCV_SRAW => "sraw  "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | MUL (rs2,rs1,rd,high,signed1,signed2) =>
+      let (insn : string) =        
+((case (high, signed1, signed2) of
+          (F, T, T) => "mul   "
+        | (T, T, T) => "mulh  "
+        | (T, T, F) => "mulhsu "
+        | (T, F, F) => "mulhu"
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | DIV0 (rs2,rs1,rd,s) =>
+      let (insn : string) = (if s then "div   " else "divu  ") in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | REM (rs2,rs1,rd,s) =>
+      let (insn : string) = (if s then "rem   " else "remu  ") in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | MULW (rs2,rs1,rd) =>
+      STRCAT "mulw  "
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | DIVW (rs2,rs1,rd,s) =>
+      let (insn : string) = (if s then "divw  " else "divuw ") in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | REMW (rs2,rs1,rd,s) =>
+      let (insn : string) = (if s then "remw  " else "remuw ") in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | FENCE (pred,succ) => "fence"
+   | FENCEI (g__93) => "fence.i"
+   | ECALL (g__94) => "ecall"
+   | MRET (g__95) => "mret"
+   | SRET (g__96) => "sret"
+   | EBREAK (g__97) => "ebreak"
+   | WFI (g__98) => "wfi"
+   | SFENCE_VMA (rs1,rs2) =>
+      STRCAT "sfence.vma "
+        ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))
+   | LOADRES (aq,rl,rs1,width,rd) =>
+      let (insn : string) =        
+((case width of   WORD => "lr.w  " | DOUBLE => "lr.d  " | _ => "lr.bad " )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs1))))))
+   | STORECON (aq,rl,rs2,rs1,width,rd) =>
+      let (insn : string) =        
+((case width of   WORD => "sc.w  " | DOUBLE => "sc.d  " | _ => "sc.bad " )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | AMO (op,aq,rl,rs2,rs1,width,rd) =>
+      let (insn : string) =        
+((case (op, width) of
+          (AMOSWAP, WORD) => "amoswap.w "
+        | (AMOADD, WORD) => "amoadd.w  "
+        | (AMOXOR, WORD) => "amoxor.w  "
+        | (AMOAND, WORD) => "amoand.w  "
+        | (AMOOR, WORD) => "amoor.w   "
+        | (AMOMIN, WORD) => "amomin.w  "
+        | (AMOMAX, WORD) => "amomax.w  "
+        | (AMOMINU, WORD) => "amominu.w "
+        | (AMOMAXU, WORD) => "amomaxu.w "
+        | (AMOSWAP, DOUBLE) => "amoswap.d "
+        | (AMOADD, DOUBLE) => "amoadd.d  "
+        | (AMOXOR, DOUBLE) => "amoxor.d  "
+        | (AMOAND, DOUBLE) => "amoand.d  "
+        | (AMOOR, DOUBLE) => "amoor.d   "
+        | (AMOMIN, DOUBLE) => "amomin.d  "
+        | (AMOMAX, DOUBLE) => "amomax.d  "
+        | (AMOMINU, DOUBLE) => "amominu.d "
+        | (AMOMAXU, DOUBLE) => "amomaxu.d "
+        | (_, _) => "amo.bad "
+        )) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi rs1)) ((STRCAT ", " ((reg_name_abi rs2))))))))))
+   | CSR (csr,rs1,rd,is_imm,op) =>
+      let (insn : string) =        
+((case (op, is_imm) of
+          (CSRRW, T) => "csrrwi "
+        | (CSRRW, F) => "csrrw  "
+        | (CSRRS, T) => "csrrsi "
+        | (CSRRS, F) => "csrrs  "
+        | (CSRRC, T) => "csrrci "
+        | (CSRRC, F) => "csrrc  "
+        )) in
+      let (rs1_str : string) = (if is_imm then string_of_vec rs1 else reg_name_abi rs1) in
+      STRCAT insn
+        ((STRCAT ((reg_name_abi rd))
+            ((STRCAT ", " ((STRCAT rs1_str ((STRCAT ", " ((csr_name csr))))))))))
+   | NOP (g__99) => "nop"
+   | ILLEGAL (g__100) => "illegal"
+   | C_ADDI4SPN (rdc,nzimm) =>
+      STRCAT "c.addi4spn "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec nzimm))))))
+   | C_LW (uimm,rsc,rdc) =>
+      STRCAT "c.lw   "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi ((creg2reg_bits rsc  :  5 words$word))))
+                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+   | C_LD (uimm,rsc,rdc) =>
+      STRCAT "c.ld   "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rdc  :  5 words$word))))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi ((creg2reg_bits rsc  :  5 words$word))))
+                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+   | C_SW (uimm,rsc1,rsc2) =>
+      STRCAT "c.sw   "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1  :  5 words$word))))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2  :  5 words$word))))
+                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+   | C_SD (uimm,rsc1,rsc2) =>
+      STRCAT "c.sd   "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsc1  :  5 words$word))))
+            ((STRCAT ", "
+                ((STRCAT ((reg_name_abi ((creg2reg_bits rsc2  :  5 words$word))))
+                    ((STRCAT ", " ((string_of_vec uimm))))))))))
+   | C_ADDI (nzi,rsd) =>
+      STRCAT "c.addi   "
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec nzi))))))
+   | C_JAL (imm) => STRCAT "c.jal   " ((string_of_vec imm))
+   | C_ADDIW (imm,rsd) =>
+      STRCAT "c.addiw "
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec imm))))))
+   | C_LI (imm,rd) =>
+      STRCAT "c.li  "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+   | C_ADDI16SP (imm) => STRCAT "c.addi16sp  " ((string_of_vec imm))
+   | C_LUI (imm,rd) =>
+      STRCAT "c.lui  "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec imm))))))
+   | C_SRLI (shamt,rsd) =>
+      STRCAT "c.srli  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec shamt))))))
+   | C_SRAI (shamt,rsd) =>
+      STRCAT "c.srai  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec shamt))))))
+   | C_ANDI (imm,rsd) =>
+      STRCAT "c.andi  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec imm))))))
+   | C_SUB (rsd,rs2) =>
+      STRCAT "c.sub  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_XOR (rsd,rs2) =>
+      STRCAT "c.xor  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_OR (rsd,rs2) =>
+      STRCAT "c.or   "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_AND (rsd,rs2) =>
+      STRCAT "c.and  "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_SUBW (rsd,rs2) =>
+      STRCAT "c.subw "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_ADDW (rsd,rs2) =>
+      STRCAT "c.addw "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rsd  :  5 words$word))))
+            ((STRCAT ", " ((reg_name_abi ((creg2reg_bits rs2  :  5 words$word))))))))
+   | C_J (imm) => STRCAT "c.j    " ((string_of_vec imm))
+   | C_BEQZ (imm,rs) =>
+      STRCAT "c.beqz "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rs  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec imm))))))
+   | C_BNEZ (imm,rs) =>
+      STRCAT "c.bnez "
+        ((STRCAT ((reg_name_abi ((creg2reg_bits rs  :  5 words$word))))
+            ((STRCAT ", " ((string_of_vec imm))))))
+   | C_SLLI (shamt,rsd) =>
+      STRCAT "c.slli "
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((string_of_vec shamt))))))
+   | C_LWSP (uimm,rd) =>
+      STRCAT "c.lwsp "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+   | C_LDSP (uimm,rd) =>
+      STRCAT "c.ldsp "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+   | C_SWSP (uimm,rd) =>
+      STRCAT "c.swsp "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+   | C_SDSP (uimm,rd) =>
+      STRCAT "c.sdsp "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((string_of_vec uimm))))))
+   | C_JR (rs1) => STRCAT "c.jr  " ((reg_name_abi rs1))
+   | C_JALR (rs1) => STRCAT "c.jalr  " ((reg_name_abi rs1))
+   | C_MV (rd,rs2) =>
+      STRCAT "c.mv  "
+        ((STRCAT ((reg_name_abi rd)) ((STRCAT ", " ((reg_name_abi rs2))))))
+   | C_ADD (rsd,rs2) =>
+      STRCAT "c.add  "
+        ((STRCAT ((reg_name_abi rsd)) ((STRCAT ", " ((reg_name_abi rs2))))))
+   )))`;
+
+
+(*val isRVC : Machine_word.mword Machine_word.ty16 -> bool*)
+
+val _ = Define `
+ ((isRVC:(16)words$word -> bool) h=   
+ (~ (((((subrange_vec_dec h (( 1 : int):sail_values$ii) (( 0 : int):sail_values$ii)  :  2 words$word)) = (vec_of_bits [B1;B1]  :  2 words$word))))))`;
+
+
+(*val fetch : unit -> Riscv_sequential_types.M Riscv_sequential_types.FetchResult*)
+
+val _ = Define `
+ ((fetch:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((riscv_sequential_types$FetchResult),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__0 : riscv_sequential_types$xlenbits) .  bindS
+   (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__1 : riscv_sequential_types$xlenbits) .  bindS   
+(haveRVC () ) (\ (w__2 : bool) . 
+   if ((((((((cast_unit_vec0 ((access_vec_dec w__0 (( 0 : int):sail_values$ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word)))) \/ ((((((((cast_unit_vec0 ((access_vec_dec w__1 (( 1 : int):sail_values$ii)))  :  1 words$word)) <> (vec_of_bits [B0]  :  1 words$word)))) /\ ((~ w__2)))))))) then bindS
+     (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__3 :  64 words$word) . 
+     returnS (F_Error (E_Fetch_Addr_Align,w__3)))
+   else bindS
+     (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 :  64 words$word) .  bindS     
+(translateAddr w__4 Execute Instruction) (\ (w__5 : riscv_sequential_types$TR_Result) . 
+     (case w__5 of
+       TR_Failure (e) => bindS
+        (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 :  64 words$word) . 
+        returnS (F_Error (e,w__6)))
+     | TR_Address (ppclo) => bindS
+        (checked_mem_read Instruction ppclo (( 2 : int):sail_values$ii)  : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__7 : ( 16 words$word)
+          riscv_sequential_types$MemoryOpResult) . 
+        (case w__7 of
+          MemException (e) => bindS
+           (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 :  64 words$word) . 
+           returnS (F_Error (E_Fetch_Access_Fault,w__8)))
+        | MemValue (ilo) =>
+           if ((isRVC ilo)) then returnS (F_RVC ilo)
+           else bindS
+             (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__9 :  64 words$word) . 
+             let (PChi : riscv_sequential_types$xlenbits) = ((add_vec_int w__9 (( 2 : int):sail_values$ii)  :  64 words$word)) in bindS             
+(translateAddr PChi Execute Instruction) (\ (w__10 : riscv_sequential_types$TR_Result) . 
+             (case w__10 of
+               TR_Failure (e) => returnS (F_Error (e,PChi))
+             | TR_Address (ppchi) => bindS
+                (checked_mem_read Instruction ppchi (( 2 : int):sail_values$ii)  : ( ( 16 words$word)riscv_sequential_types$MemoryOpResult) riscv_sequential_types$M) (\ (w__11 : ( 16 words$word)
+                  riscv_sequential_types$MemoryOpResult) . 
+                returnS ((case w__11 of
+                           MemException (e) => F_Error (E_Fetch_Access_Fault,PChi)
+                         | MemValue (ihi) => F_Base ((concat_vec ihi ilo  :  32 words$word))
+                         )))
+             )))
+        ))
+     ))))))))`;
+
+
+(*val step : unit -> Riscv_sequential_types.M bool*)
+
+val _ = Define `
+ ((step:unit ->(riscv_sequential_types$regstate)state_monad$sequential_state ->(((bool),(riscv_sequential_types$exception))state_monad$result#(riscv_sequential_types$regstate)state_monad$sequential_state)set) () =  (bindS   
+(read_regS mip_ref) (\ (w__0 : riscv_sequential_types$Minterrupts) .  bindS   
+(read_regS mie_ref) (\ (w__1 : riscv_sequential_types$Minterrupts) .  bindS   
+(read_regS mideleg_ref) (\ (w__2 : riscv_sequential_types$Minterrupts) .  bindS   
+(curInterrupt w__0 w__1 w__2) (\ (w__3 :  ((riscv_sequential_types$InterruptType # riscv_sequential_types$Privilege))option) . 
+   (case w__3 of
+     SOME (intr,priv) =>
+      let (_ : unit) = (print_bits "Handling interrupt: " ((interruptType_to_bits intr  :  4 words$word))) in seqS      
+(handle_interrupt intr priv) (returnS F)
+   | NONE => bindS
+      (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__4 : riscv_sequential_types$xlenbits) . 
+      let (_ : unit) = (print_bits "PC: " w__4) in bindS      
+(fetch () ) (\ (w__5 : riscv_sequential_types$FetchResult) . 
+      (case w__5 of
+        F_Error (e,addr) => seqS (handle_mem_exception addr e) (returnS F)
+      | F_RVC (h) =>
+         (case ((decodeCompressed h)) of
+           NONE =>
+            let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec h)) " :  <no-decode>"))) in seqS            
+(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) h  :  64 words$word))) (returnS F)
+         | SOME (ast) =>
+            let (_ : unit) =              
+(prerr_endline
+                ((STRCAT ((string_of_vec h)) ((STRCAT " :  " ((print_insn ast))))))) in bindS
+            (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__6 :  64 words$word) .  seqS (seqS            
+(write_regS nextPC_ref ((add_vec_int w__6 (( 2 : int):sail_values$ii)  :  64 words$word)))            
+(execute ast)) (returnS T))
+         )
+      | F_Base (w) =>
+         (case ((decode w)) of
+           NONE =>
+            let (_ : unit) = (prerr_endline ((STRCAT ((string_of_vec w)) " :  <no-decode>"))) in seqS            
+(handle_decode_exception ((EXTZ (( 64 : int):sail_values$ii) w  :  64 words$word))) (returnS F)
+         | SOME (ast) =>
+            let (_ : unit) =              
+(prerr_endline
+                ((STRCAT ((string_of_vec w)) ((STRCAT " :  " ((print_insn ast))))))) in bindS
+            (read_regS PC_ref  : ( 64 words$word) riscv_sequential_types$M) (\ (w__8 :  64 words$word) .  seqS (seqS            
+(write_regS nextPC_ref ((add_vec_int w__8 (( 4 : int):sail_values$ii)  :  64 words$word)))            
+(execute ast)) (returnS T))
+         )
+      )))
+   )))))))`;
+
+
+
+val _ = export_theory()
+
diff --git a/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml b/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml
new file mode 100644
index 00000000..e9b73fd8
--- /dev/null
+++ b/snapshots/hol4/sail/riscv/riscv_sequential_typesScript.sml
@@ -0,0 +1,1078 @@
+(*Generated by Lem from riscv_sequential_types.lem.*)
+open HolKernel Parse boolLib bossLib;
+open lem_pervasives_extraTheory sail_instr_kindsTheory sail_valuesTheory sail_operators_mwordsTheory state_monadTheory stateTheory;
+
+val _ = numLib.prefer_num();
+
+
+
+val _ = new_theory "riscv_sequential_types"
+
+(*Generated by Sail from riscv_sequential.*)
+(*open import Pervasives_extra*)
+(*open import Sail_instr_kinds*)
+(*open import Sail_values*)
+(*open import Sail_operators_mwords*)
+(*open import State_monad*)
+(*open import State*)
+val _ = type_abbrev((*  'n *) "bits" , ``:  'n words$word``);
+
+
+
+val _ = type_abbrev( "xlenbits"  , ``: 64 bits``);
+
+val _ = type_abbrev( "half"  , ``: 16 bits``);
+
+val _ = type_abbrev( "word"  , ``: 32 bits``);
+
+val _ = type_abbrev((*  'n *) "regno"  , ``: int``);
+
+val _ = type_abbrev( "regbits"  , ``: 5 bits``);
+
+val _ = type_abbrev( "cregbits"  , ``: 3 bits``);
+
+val _ = type_abbrev( "csreg"  , ``: 12 bits``);
+
+val _ = type_abbrev( "opcode"  , ``: 7 bits``);
+
+val _ = type_abbrev( "imm12"  , ``: 12 bits``);
+
+val _ = type_abbrev( "imm20"  , ``: 20 bits``);
+
+val _ = type_abbrev( "amo"  , ``: 1 bits``);
+
+val _ = Hol_datatype `
+ Architecture = RV32 | RV64 | RV128`;
+
+
+
+
+val _ = type_abbrev( "arch_xlen"  , ``: 2 bits``);
+
+val _ = type_abbrev( "priv_level"  , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ Privilege = User | Supervisor | Machine`;
+
+
+
+
+val _ = Hol_datatype `
+ AccessType = Read | Write | ReadWrite | Execute`;
+
+
+
+
+val _ = Hol_datatype `
+ ReadType = Instruction | Data`;
+
+
+
+
+val _ = type_abbrev( "exc_code"  , ``: 4 bits``);
+
+val _ = Hol_datatype `
+ ExceptionType =
+  E_Fetch_Addr_Align
+  | E_Fetch_Access_Fault
+  | E_Illegal_Instr
+  | E_Breakpoint
+  | E_Load_Addr_Align
+  | E_Load_Access_Fault
+  | E_SAMO_Addr_Align
+  | E_SAMO_Access_Fault
+  | E_U_EnvCall
+  | E_S_EnvCall
+  | E_Reserved_10
+  | E_M_EnvCall
+  | E_Fetch_Page_Fault
+  | E_Load_Page_Fault
+  | E_Reserved_14
+  | E_SAMO_Page_Fault`;
+
+
+
+
+val _ = Hol_datatype `
+ InterruptType =
+  I_U_Software
+  | I_S_Software
+  | I_M_Software
+  | I_U_Timer
+  | I_S_Timer
+  | I_M_Timer
+  | I_U_External
+  | I_S_External
+  | I_M_External`;
+
+
+
+
+val _ = type_abbrev( "tv_mode"  , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ TrapVectorMode = TV_Direct | TV_Vector | TV_Reserved`;
+
+
+
+
+val _ = Hol_datatype `
+ exception  =
+    Error_not_implemented of (string)
+  | Error_misaligned_access of (unit)
+  | Error_EBREAK of (unit)
+  | Error_internal_error of (unit)`;
+
+
+
+
+val _ = type_abbrev( "ext_status"  , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ ExtStatus = Off | Initial | Clean | Dirty`;
+
+
+
+
+val _ = type_abbrev( "satp_mode"  , ``: 4 bits``);
+
+val _ = Hol_datatype `
+ SATPMode = Sbare | Sv32 | Sv39`;
+
+
+
+
+val _ = type_abbrev( "csrRW"  , ``: 2 bits``);
+
+val _ = Hol_datatype `
+ uop = RISCV_LUI | RISCV_AUIPC`;
+
+
+
+
+val _ = Hol_datatype `
+ bop = RISCV_BEQ | RISCV_BNE | RISCV_BLT | RISCV_BGE | RISCV_BLTU | RISCV_BGEU`;
+
+
+
+
+val _ = Hol_datatype `
+ iop = RISCV_ADDI | RISCV_SLTI | RISCV_SLTIU | RISCV_XORI | RISCV_ORI | RISCV_ANDI`;
+
+
+
+
+val _ = Hol_datatype `
+ sop = RISCV_SLLI | RISCV_SRLI | RISCV_SRAI`;
+
+
+
+
+val _ = Hol_datatype `
+ rop =
+  RISCV_ADD
+  | RISCV_SUB
+  | RISCV_SLL
+  | RISCV_SLT
+  | RISCV_SLTU
+  | RISCV_XOR
+  | RISCV_SRL
+  | RISCV_SRA
+  | RISCV_OR
+  | RISCV_AND`;
+
+
+
+
+val _ = Hol_datatype `
+ ropw = RISCV_ADDW | RISCV_SUBW | RISCV_SLLW | RISCV_SRLW | RISCV_SRAW`;
+
+
+
+
+val _ = Hol_datatype `
+ amoop = AMOSWAP | AMOADD | AMOXOR | AMOAND | AMOOR | AMOMIN | AMOMAX | AMOMINU | AMOMAXU`;
+
+
+
+
+val _ = Hol_datatype `
+ csrop = CSRRW | CSRRS | CSRRC`;
+
+
+
+
+val _ = Hol_datatype `
+ word_width = BYTE | HALF | WORD | DOUBLE`;
+
+
+
+
+val _ = Hol_datatype `
+ MemoryOpResult =   MemValue of ('a) | MemException of (ExceptionType)`;
+
+
+
+
+val _ = Hol_datatype `
+ Misa  =   Mk_Misa of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ SV39_PTE  =   Mk_SV39_PTE of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ PTE_Bits  =   Mk_PTE_Bits of ( 8 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Mstatus  =   Mk_Mstatus of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Sstatus  =   Mk_Sstatus of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Minterrupts  =   Mk_Minterrupts of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Sinterrupts  =   Mk_Sinterrupts of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Medeleg  =   Mk_Medeleg of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Sedeleg  =   Mk_Sedeleg of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Mtvec  =   Mk_Mtvec of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Satp64  =   Mk_Satp64 of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ Mcause  =   Mk_Mcause of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ sync_exception  =
+  <| sync_exception_trap : ExceptionType; sync_exception_excinfo :  xlenbits option  |>`;
+
+
+
+val _ = Hol_datatype `
+ ctl_result  =   CTL_TRAP of (sync_exception) | CTL_SRET of (unit) | CTL_MRET of (unit)`;
+
+
+
+
+val _ = type_abbrev( "pteAttribs"  , ``: 8 bits``);
+
+val _ = Hol_datatype `
+ PTW_Error = PTW_Access | PTW_Invalid_PTE | PTW_No_Permission | PTW_Misaligned | PTW_PTE_Update`;
+
+
+
+
+val _ = type_abbrev( "vaddr39"  , ``: 39 bits``);
+
+val _ = type_abbrev( "paddr39"  , ``: 56 bits``);
+
+val _ = type_abbrev( "pte39"  , ``: xlenbits``);
+
+val _ = Hol_datatype `
+ SV39_Vaddr  =   Mk_SV39_Vaddr of ( 39 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ SV39_Paddr  =   Mk_SV39_Paddr of ( 56 words$word)`;
+
+
+
+
+val _ = type_abbrev( "asid64"  , ``: 16 bits``);
+
+val _ = Hol_datatype `
+ PTW_Result  =
+    PTW_Success of ((paddr39 # SV39_PTE # paddr39 # sail_values$ii # bool)) | PTW_Failure of (PTW_Error)`;
+
+
+
+
+val _ = Hol_datatype `
+ TLB39_Entry  =
+  <| TLB39_Entry_asid : asid64;
+     TLB39_Entry_global : bool;
+     TLB39_Entry_vAddr : vaddr39;
+     TLB39_Entry_pAddr : paddr39;
+     TLB39_Entry_vMatchMask : vaddr39;
+     TLB39_Entry_vAddrMask : vaddr39;
+     TLB39_Entry_pte : SV39_PTE;
+     TLB39_Entry_pteAddr : paddr39;
+     TLB39_Entry_age : xlenbits  |>`;
+
+
+
+val _ = Hol_datatype `
+ TR39_Result  =   TR39_Address of (paddr39) | TR39_Failure of (PTW_Error)`;
+
+
+
+
+val _ = Hol_datatype `
+ TR_Result  =   TR_Address of (xlenbits) | TR_Failure of (ExceptionType)`;
+
+
+
+
+val _ = Hol_datatype `
+ ast  =
+    UTYPE of (( 20 bits # regbits # uop))
+  | RISCV_JAL of (( 21 bits # regbits))
+  | RISCV_JALR of (( 12 bits # regbits # regbits))
+  | BTYPE of (( 13 bits # regbits # regbits # bop))
+  | ITYPE of (( 12 bits # regbits # regbits # iop))
+  | SHIFTIOP of (( 6 bits # regbits # regbits # sop))
+  | RTYPE of ((regbits # regbits # regbits # rop))
+  | LOAD of (( 12 bits # regbits # regbits # bool # word_width # bool # bool))
+  | STORE of (( 12 bits # regbits # regbits # word_width # bool # bool))
+  | ADDIW of (( 12 bits # regbits # regbits))
+  | SHIFTW of (( 5 bits # regbits # regbits # sop))
+  | RTYPEW of ((regbits # regbits # regbits # ropw))
+  | MUL of ((regbits # regbits # regbits # bool # bool # bool))
+  | DIV0 of ((regbits # regbits # regbits # bool))
+  | REM of ((regbits # regbits # regbits # bool))
+  | MULW of ((regbits # regbits # regbits))
+  | DIVW of ((regbits # regbits # regbits # bool))
+  | REMW of ((regbits # regbits # regbits # bool))
+  | FENCE of (( 4 bits # 4 bits))
+  | FENCEI of (unit)
+  | ECALL of (unit)
+  | MRET of (unit)
+  | SRET of (unit)
+  | EBREAK of (unit)
+  | WFI of (unit)
+  | SFENCE_VMA of ((regbits # regbits))
+  | LOADRES of ((bool # bool # regbits # word_width # regbits))
+  | STORECON of ((bool # bool # regbits # regbits # word_width # regbits))
+  | AMO of ((amoop # bool # bool # regbits # regbits # word_width # regbits))
+  | CSR of (( 12 bits # regbits # regbits # bool # csrop))
+  | NOP of (unit)
+  | ILLEGAL of (unit)
+  | C_ADDI4SPN of ((cregbits # 8 bits))
+  | C_LW of (( 5 bits # cregbits # cregbits))
+  | C_LD of (( 5 bits # cregbits # cregbits))
+  | C_SW of (( 5 bits # cregbits # cregbits))
+  | C_SD of (( 5 bits # cregbits # cregbits))
+  | C_ADDI of (( 6 bits # regbits))
+  | C_JAL of ( 11 bits)
+  | C_ADDIW of (( 6 bits # regbits))
+  | C_LI of (( 6 bits # regbits))
+  | C_ADDI16SP of ( 6 bits)
+  | C_LUI of (( 6 bits # regbits))
+  | C_SRLI of (( 6 bits # cregbits))
+  | C_SRAI of (( 6 bits # cregbits))
+  | C_ANDI of (( 6 bits # cregbits))
+  | C_SUB of ((cregbits # cregbits))
+  | C_XOR of ((cregbits # cregbits))
+  | C_OR of ((cregbits # cregbits))
+  | C_AND of ((cregbits # cregbits))
+  | C_SUBW of ((cregbits # cregbits))
+  | C_ADDW of ((cregbits # cregbits))
+  | C_J of ( 11 bits)
+  | C_BEQZ of (( 8 bits # cregbits))
+  | C_BNEZ of (( 8 bits # cregbits))
+  | C_SLLI of (( 6 bits # regbits))
+  | C_LWSP of (( 6 bits # regbits))
+  | C_LDSP of (( 6 bits # regbits))
+  | C_SWSP of (( 6 bits # regbits))
+  | C_SDSP of (( 6 bits # regbits))
+  | C_JR of (regbits)
+  | C_JALR of (regbits)
+  | C_MV of ((regbits # regbits))
+  | C_ADD of ((regbits # regbits))`;
+
+
+
+
+val _ = Hol_datatype `
+ FetchResult  =   F_Base of (word) | F_RVC of (half) | F_Error of ((ExceptionType # xlenbits))`;
+
+
+
+
+val _ = Hol_datatype `
+ register_value  =
+    Regval_vector of ((sail_values$ii # bool # register_value list))
+  | Regval_list of ( register_value list)
+  | Regval_option of ( register_value option)
+  | Regval_Mcause of (Mcause)
+  | Regval_Medeleg of (Medeleg)
+  | Regval_Minterrupts of (Minterrupts)
+  | Regval_Misa of (Misa)
+  | Regval_Mstatus of (Mstatus)
+  | Regval_Mtvec of (Mtvec)
+  | Regval_Privilege of (Privilege)
+  | Regval_Sedeleg of (Sedeleg)
+  | Regval_Sinterrupts of (Sinterrupts)
+  | Regval_TLB39_Entry of (TLB39_Entry)
+  | Regval_vector_64_dec_bit of ( 64 words$word)`;
+
+
+
+
+val _ = Hol_datatype `
+ regstate  =
+  <| tlb39 :  TLB39_Entry option;
+     stval :  64 words$word;
+     scause : Mcause;
+     sepc :  64 words$word;
+     sscratch :  64 words$word;
+     stvec : Mtvec;
+     satp :  64 words$word;
+     sideleg : Sinterrupts;
+     sedeleg : Sedeleg;
+     pmpcfg0 :  64 words$word;
+     pmpaddr0 :  64 words$word;
+     mhartid :  64 words$word;
+     marchid :  64 words$word;
+     mimpid :  64 words$word;
+     mvendorid :  64 words$word;
+     minstret :  64 words$word;
+     mtime :  64 words$word;
+     mcycle :  64 words$word;
+     mscratch :  64 words$word;
+     mtval :  64 words$word;
+     mepc :  64 words$word;
+     mcause : Mcause;
+     mtvec : Mtvec;
+     medeleg : Medeleg;
+     mideleg : Minterrupts;
+     mie : Minterrupts;
+     mip : Minterrupts;
+     mstatus : Mstatus;
+     misa : Misa;
+     cur_inst :  64 words$word;
+     cur_privilege : Privilege;
+     Xs : ( 64 words$word) list;
+     nextPC :  64 words$word;
+     PC :  64 words$word  |>`;
+
+
+
+
+
+(*val Mcause_of_regval : register_value -> Maybe.maybe Mcause*)
+
+val _ = Define `
+ ((Mcause_of_regval:register_value ->(Mcause)option) merge_var=   
+ ((case merge_var of   Regval_Mcause (v) => SOME v | g__92 => NONE )))`;
+
+
+(*val regval_of_Mcause : Mcause -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mcause:Mcause -> register_value) v=  (Regval_Mcause v))`;
+
+
+(*val Medeleg_of_regval : register_value -> Maybe.maybe Medeleg*)
+
+val _ = Define `
+ ((Medeleg_of_regval:register_value ->(Medeleg)option) merge_var=   
+ ((case merge_var of   Regval_Medeleg (v) => SOME v | g__91 => NONE )))`;
+
+
+(*val regval_of_Medeleg : Medeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Medeleg:Medeleg -> register_value) v=  (Regval_Medeleg v))`;
+
+
+(*val Minterrupts_of_regval : register_value -> Maybe.maybe Minterrupts*)
+
+val _ = Define `
+ ((Minterrupts_of_regval:register_value ->(Minterrupts)option) merge_var=   
+ ((case merge_var of   Regval_Minterrupts (v) => SOME v | g__90 => NONE )))`;
+
+
+(*val regval_of_Minterrupts : Minterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Minterrupts:Minterrupts -> register_value) v=  (Regval_Minterrupts v))`;
+
+
+(*val Misa_of_regval : register_value -> Maybe.maybe Misa*)
+
+val _ = Define `
+ ((Misa_of_regval:register_value ->(Misa)option) merge_var=   
+ ((case merge_var of   Regval_Misa (v) => SOME v | g__89 => NONE )))`;
+
+
+(*val regval_of_Misa : Misa -> register_value*)
+
+val _ = Define `
+ ((regval_of_Misa:Misa -> register_value) v=  (Regval_Misa v))`;
+
+
+(*val Mstatus_of_regval : register_value -> Maybe.maybe Mstatus*)
+
+val _ = Define `
+ ((Mstatus_of_regval:register_value ->(Mstatus)option) merge_var=   
+ ((case merge_var of   Regval_Mstatus (v) => SOME v | g__88 => NONE )))`;
+
+
+(*val regval_of_Mstatus : Mstatus -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mstatus:Mstatus -> register_value) v=  (Regval_Mstatus v))`;
+
+
+(*val Mtvec_of_regval : register_value -> Maybe.maybe Mtvec*)
+
+val _ = Define `
+ ((Mtvec_of_regval:register_value ->(Mtvec)option) merge_var=   
+ ((case merge_var of   Regval_Mtvec (v) => SOME v | g__87 => NONE )))`;
+
+
+(*val regval_of_Mtvec : Mtvec -> register_value*)
+
+val _ = Define `
+ ((regval_of_Mtvec:Mtvec -> register_value) v=  (Regval_Mtvec v))`;
+
+
+(*val Privilege_of_regval : register_value -> Maybe.maybe Privilege*)
+
+val _ = Define `
+ ((Privilege_of_regval:register_value ->(Privilege)option) merge_var=   
+ ((case merge_var of   Regval_Privilege (v) => SOME v | g__86 => NONE )))`;
+
+
+(*val regval_of_Privilege : Privilege -> register_value*)
+
+val _ = Define `
+ ((regval_of_Privilege:Privilege -> register_value) v=  (Regval_Privilege v))`;
+
+
+(*val Sedeleg_of_regval : register_value -> Maybe.maybe Sedeleg*)
+
+val _ = Define `
+ ((Sedeleg_of_regval:register_value ->(Sedeleg)option) merge_var=   
+ ((case merge_var of   Regval_Sedeleg (v) => SOME v | g__85 => NONE )))`;
+
+
+(*val regval_of_Sedeleg : Sedeleg -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sedeleg:Sedeleg -> register_value) v=  (Regval_Sedeleg v))`;
+
+
+(*val Sinterrupts_of_regval : register_value -> Maybe.maybe Sinterrupts*)
+
+val _ = Define `
+ ((Sinterrupts_of_regval:register_value ->(Sinterrupts)option) merge_var=   
+ ((case merge_var of   Regval_Sinterrupts (v) => SOME v | g__84 => NONE )))`;
+
+
+(*val regval_of_Sinterrupts : Sinterrupts -> register_value*)
+
+val _ = Define `
+ ((regval_of_Sinterrupts:Sinterrupts -> register_value) v=  (Regval_Sinterrupts v))`;
+
+
+(*val TLB39_Entry_of_regval : register_value -> Maybe.maybe TLB39_Entry*)
+
+val _ = Define `
+ ((TLB39_Entry_of_regval:register_value ->(TLB39_Entry)option) merge_var=   
+ ((case merge_var of   Regval_TLB39_Entry (v) => SOME v | g__83 => NONE )))`;
+
+
+(*val regval_of_TLB39_Entry : TLB39_Entry -> register_value*)
+
+val _ = Define `
+ ((regval_of_TLB39_Entry:TLB39_Entry -> register_value) v=  (Regval_TLB39_Entry v))`;
+
+
+(*val vector_64_dec_bit_of_regval : register_value -> Maybe.maybe (Machine_word.mword Machine_word.ty64)*)
+
+val _ = Define `
+ ((vector_64_dec_bit_of_regval:register_value ->((64)words$word)option) merge_var=   
+ ((case merge_var of   Regval_vector_64_dec_bit (v) => SOME v | g__82 => NONE )))`;
+
+
+(*val regval_of_vector_64_dec_bit : Machine_word.mword Machine_word.ty64 -> register_value*)
+
+val _ = Define `
+ ((regval_of_vector_64_dec_bit:(64)words$word -> register_value) v=  (Regval_vector_64_dec_bit v))`;
+
+
+
+
+(*val vector_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*)
+val _ = Define `
+ ((vector_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+  (\x .  (case x of
+               Regval_vector (_, _, v) => just_list (MAP of_regval v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_vector : forall 'a. ('a -> register_value) -> Num.integer -> bool -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_vector:('a -> register_value) -> int -> bool -> 'a list -> register_value) regval_of size1 is_inc xs=  (Regval_vector (size1, is_inc, MAP regval_of xs)))`;
+
+
+(*val list_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (list 'a)*)
+val _ = Define `
+ ((list_of_regval:(register_value -> 'a option) -> register_value ->('a list)option) of_regval= 
+  (\x .  (case x of
+               Regval_list v => just_list (MAP of_regval v)
+           | _ => NONE
+         )))`;
+
+
+(*val regval_of_list : forall 'a. ('a -> register_value) -> list 'a -> register_value*)
+val _ = Define `
+ ((regval_of_list:('a -> register_value) -> 'a list -> register_value) regval_of xs=  (Regval_list (MAP regval_of xs)))`;
+
+
+(*val option_of_regval : forall 'a. (register_value -> Maybe.maybe 'a) -> register_value -> Maybe.maybe (Maybe.maybe 'a)*)
+val _ = Define `
+ ((option_of_regval:(register_value -> 'a option) -> register_value ->('a option)option) of_regval= 
+  (\x .  (case x of   Regval_option v => OPTION_MAP of_regval v | _ => NONE )))`;
+
+
+(*val regval_of_option : forall 'a. ('a -> register_value) -> Maybe.maybe 'a -> register_value*)
+val _ = Define `
+ ((regval_of_option:('a -> register_value) -> 'a option -> register_value) regval_of v=  (Regval_option (OPTION_MAP regval_of v)))`;
+
+
+
+val _ = Define `
+ ((tlb39_ref:((regstate),(register_value),((TLB39_Entry)option))sail_values$register_ref)=  (<|
+  name := "tlb39";
+  read_from := (\ s .  s.tlb39);
+  write_to := (\ v s .  (( s with<| tlb39 := v |>)));
+  of_regval := (\ v .  option_of_regval (\ v .  TLB39_Entry_of_regval v) v);
+  regval_of := (\ v .  regval_of_option (\ v .  regval_of_TLB39_Entry v) v) |>))`;
+
+
+val _ = Define `
+ ((stval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "stval";
+  read_from := (\ s .  s.stval);
+  write_to := (\ v s .  (( s with<| stval := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((scause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)=  (<|
+  name := "scause";
+  read_from := (\ s .  s.scause);
+  write_to := (\ v s .  (( s with<| scause := v |>)));
+  of_regval := (\ v .  Mcause_of_regval v);
+  regval_of := (\ v .  regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((sepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "sepc";
+  read_from := (\ s .  s.sepc);
+  write_to := (\ v s .  (( s with<| sepc := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((sscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "sscratch";
+  read_from := (\ s .  s.sscratch);
+  write_to := (\ v s .  (( s with<| sscratch := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((stvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)=  (<|
+  name := "stvec";
+  read_from := (\ s .  s.stvec);
+  write_to := (\ v s .  (( s with<| stvec := v |>)));
+  of_regval := (\ v .  Mtvec_of_regval v);
+  regval_of := (\ v .  regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((satp_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "satp";
+  read_from := (\ s .  s.satp);
+  write_to := (\ v s .  (( s with<| satp := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((sideleg_ref:((regstate),(register_value),(Sinterrupts))sail_values$register_ref)=  (<|
+  name := "sideleg";
+  read_from := (\ s .  s.sideleg);
+  write_to := (\ v s .  (( s with<| sideleg := v |>)));
+  of_regval := (\ v .  Sinterrupts_of_regval v);
+  regval_of := (\ v .  regval_of_Sinterrupts v) |>))`;
+
+
+val _ = Define `
+ ((sedeleg_ref:((regstate),(register_value),(Sedeleg))sail_values$register_ref)=  (<|
+  name := "sedeleg";
+  read_from := (\ s .  s.sedeleg);
+  write_to := (\ v s .  (( s with<| sedeleg := v |>)));
+  of_regval := (\ v .  Sedeleg_of_regval v);
+  regval_of := (\ v .  regval_of_Sedeleg v) |>))`;
+
+
+val _ = Define `
+ ((pmpcfg0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "pmpcfg0";
+  read_from := (\ s .  s.pmpcfg0);
+  write_to := (\ v s .  (( s with<| pmpcfg0 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((pmpaddr0_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "pmpaddr0";
+  read_from := (\ s .  s.pmpaddr0);
+  write_to := (\ v s .  (( s with<| pmpaddr0 := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mhartid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mhartid";
+  read_from := (\ s .  s.mhartid);
+  write_to := (\ v s .  (( s with<| mhartid := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((marchid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "marchid";
+  read_from := (\ s .  s.marchid);
+  write_to := (\ v s .  (( s with<| marchid := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mimpid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mimpid";
+  read_from := (\ s .  s.mimpid);
+  write_to := (\ v s .  (( s with<| mimpid := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mvendorid_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mvendorid";
+  read_from := (\ s .  s.mvendorid);
+  write_to := (\ v s .  (( s with<| mvendorid := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((minstret_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "minstret";
+  read_from := (\ s .  s.minstret);
+  write_to := (\ v s .  (( s with<| minstret := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtime_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mtime";
+  read_from := (\ s .  s.mtime);
+  write_to := (\ v s .  (( s with<| mtime := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcycle_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mcycle";
+  read_from := (\ s .  s.mcycle);
+  write_to := (\ v s .  (( s with<| mcycle := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mscratch_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mscratch";
+  read_from := (\ s .  s.mscratch);
+  write_to := (\ v s .  (( s with<| mscratch := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mtval_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mtval";
+  read_from := (\ s .  s.mtval);
+  write_to := (\ v s .  (( s with<| mtval := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mepc_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "mepc";
+  read_from := (\ s .  s.mepc);
+  write_to := (\ v s .  (( s with<| mepc := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((mcause_ref:((regstate),(register_value),(Mcause))sail_values$register_ref)=  (<|
+  name := "mcause";
+  read_from := (\ s .  s.mcause);
+  write_to := (\ v s .  (( s with<| mcause := v |>)));
+  of_regval := (\ v .  Mcause_of_regval v);
+  regval_of := (\ v .  regval_of_Mcause v) |>))`;
+
+
+val _ = Define `
+ ((mtvec_ref:((regstate),(register_value),(Mtvec))sail_values$register_ref)=  (<|
+  name := "mtvec";
+  read_from := (\ s .  s.mtvec);
+  write_to := (\ v s .  (( s with<| mtvec := v |>)));
+  of_regval := (\ v .  Mtvec_of_regval v);
+  regval_of := (\ v .  regval_of_Mtvec v) |>))`;
+
+
+val _ = Define `
+ ((medeleg_ref:((regstate),(register_value),(Medeleg))sail_values$register_ref)=  (<|
+  name := "medeleg";
+  read_from := (\ s .  s.medeleg);
+  write_to := (\ v s .  (( s with<| medeleg := v |>)));
+  of_regval := (\ v .  Medeleg_of_regval v);
+  regval_of := (\ v .  regval_of_Medeleg v) |>))`;
+
+
+val _ = Define `
+ ((mideleg_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)=  (<|
+  name := "mideleg";
+  read_from := (\ s .  s.mideleg);
+  write_to := (\ v s .  (( s with<| mideleg := v |>)));
+  of_regval := (\ v .  Minterrupts_of_regval v);
+  regval_of := (\ v .  regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mie_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)=  (<|
+  name := "mie";
+  read_from := (\ s .  s.mie);
+  write_to := (\ v s .  (( s with<| mie := v |>)));
+  of_regval := (\ v .  Minterrupts_of_regval v);
+  regval_of := (\ v .  regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mip_ref:((regstate),(register_value),(Minterrupts))sail_values$register_ref)=  (<|
+  name := "mip";
+  read_from := (\ s .  s.mip);
+  write_to := (\ v s .  (( s with<| mip := v |>)));
+  of_regval := (\ v .  Minterrupts_of_regval v);
+  regval_of := (\ v .  regval_of_Minterrupts v) |>))`;
+
+
+val _ = Define `
+ ((mstatus_ref:((regstate),(register_value),(Mstatus))sail_values$register_ref)=  (<|
+  name := "mstatus";
+  read_from := (\ s .  s.mstatus);
+  write_to := (\ v s .  (( s with<| mstatus := v |>)));
+  of_regval := (\ v .  Mstatus_of_regval v);
+  regval_of := (\ v .  regval_of_Mstatus v) |>))`;
+
+
+val _ = Define `
+ ((misa_ref:((regstate),(register_value),(Misa))sail_values$register_ref)=  (<|
+  name := "misa";
+  read_from := (\ s .  s.misa);
+  write_to := (\ v s .  (( s with<| misa := v |>)));
+  of_regval := (\ v .  Misa_of_regval v);
+  regval_of := (\ v .  regval_of_Misa v) |>))`;
+
+
+val _ = Define `
+ ((cur_inst_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "cur_inst";
+  read_from := (\ s .  s.cur_inst);
+  write_to := (\ v s .  (( s with<| cur_inst := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((cur_privilege_ref:((regstate),(register_value),(Privilege))sail_values$register_ref)=  (<|
+  name := "cur_privilege";
+  read_from := (\ s .  s.cur_privilege);
+  write_to := (\ v s .  (( s with<| cur_privilege := v |>)));
+  of_regval := (\ v .  Privilege_of_regval v);
+  regval_of := (\ v .  regval_of_Privilege v) |>))`;
+
+
+val _ = Define `
+ ((Xs_ref:((regstate),(register_value),(((64)words$word)list))sail_values$register_ref)=  (<|
+  name := "Xs";
+  read_from := (\ s .  s.Xs);
+  write_to := (\ v s .  (( s with<| Xs := v |>)));
+  of_regval := (\ v .  vector_of_regval (\ v .  vector_64_dec_bit_of_regval v) v);
+  regval_of := (\ v .  regval_of_vector (\ v .  regval_of_vector_64_dec_bit v)(( 32 : int)) F v) |>))`;
+
+
+val _ = Define `
+ ((nextPC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "nextPC";
+  read_from := (\ s .  s.nextPC);
+  write_to := (\ v s .  (( s with<| nextPC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+val _ = Define `
+ ((PC_ref:((regstate),(register_value),((64)words$word))sail_values$register_ref)=  (<|
+  name := "PC";
+  read_from := (\ s .  s.PC);
+  write_to := (\ v s .  (( s with<| PC := v |>)));
+  of_regval := (\ v .  vector_64_dec_bit_of_regval v);
+  regval_of := (\ v .  regval_of_vector_64_dec_bit v) |>))`;
+
+
+(*val get_regval : string -> regstate -> Maybe.maybe register_value*)
+val _ = Define `
+ ((get_regval:string -> regstate ->(register_value)option) reg_name s=  
+ (if reg_name = "tlb39" then SOME (tlb39_ref.regval_of (tlb39_ref.read_from s)) else
+  if reg_name = "stval" then SOME (stval_ref.regval_of (stval_ref.read_from s)) else
+  if reg_name = "scause" then SOME (scause_ref.regval_of (scause_ref.read_from s)) else
+  if reg_name = "sepc" then SOME (sepc_ref.regval_of (sepc_ref.read_from s)) else
+  if reg_name = "sscratch" then SOME (sscratch_ref.regval_of (sscratch_ref.read_from s)) else
+  if reg_name = "stvec" then SOME (stvec_ref.regval_of (stvec_ref.read_from s)) else
+  if reg_name = "satp" then SOME (satp_ref.regval_of (satp_ref.read_from s)) else
+  if reg_name = "sideleg" then SOME (sideleg_ref.regval_of (sideleg_ref.read_from s)) else
+  if reg_name = "sedeleg" then SOME (sedeleg_ref.regval_of (sedeleg_ref.read_from s)) else
+  if reg_name = "pmpcfg0" then SOME (pmpcfg0_ref.regval_of (pmpcfg0_ref.read_from s)) else
+  if reg_name = "pmpaddr0" then SOME (pmpaddr0_ref.regval_of (pmpaddr0_ref.read_from s)) else
+  if reg_name = "mhartid" then SOME (mhartid_ref.regval_of (mhartid_ref.read_from s)) else
+  if reg_name = "marchid" then SOME (marchid_ref.regval_of (marchid_ref.read_from s)) else
+  if reg_name = "mimpid" then SOME (mimpid_ref.regval_of (mimpid_ref.read_from s)) else
+  if reg_name = "mvendorid" then SOME (mvendorid_ref.regval_of (mvendorid_ref.read_from s)) else
+  if reg_name = "minstret" then SOME (minstret_ref.regval_of (minstret_ref.read_from s)) else
+  if reg_name = "mtime" then SOME (mtime_ref.regval_of (mtime_ref.read_from s)) else
+  if reg_name = "mcycle" then SOME (mcycle_ref.regval_of (mcycle_ref.read_from s)) else
+  if reg_name = "mscratch" then SOME (mscratch_ref.regval_of (mscratch_ref.read_from s)) else
+  if reg_name = "mtval" then SOME (mtval_ref.regval_of (mtval_ref.read_from s)) else
+  if reg_name = "mepc" then SOME (mepc_ref.regval_of (mepc_ref.read_from s)) else
+  if reg_name = "mcause" then SOME (mcause_ref.regval_of (mcause_ref.read_from s)) else
+  if reg_name = "mtvec" then SOME (mtvec_ref.regval_of (mtvec_ref.read_from s)) else
+  if reg_name = "medeleg" then SOME (medeleg_ref.regval_of (medeleg_ref.read_from s)) else
+  if reg_name = "mideleg" then SOME (mideleg_ref.regval_of (mideleg_ref.read_from s)) else
+  if reg_name = "mie" then SOME (mie_ref.regval_of (mie_ref.read_from s)) else
+  if reg_name = "mip" then SOME (mip_ref.regval_of (mip_ref.read_from s)) else
+  if reg_name = "mstatus" then SOME (mstatus_ref.regval_of (mstatus_ref.read_from s)) else
+  if reg_name = "misa" then SOME (misa_ref.regval_of (misa_ref.read_from s)) else
+  if reg_name = "cur_inst" then SOME (cur_inst_ref.regval_of (cur_inst_ref.read_from s)) else
+  if reg_name = "cur_privilege" then SOME (cur_privilege_ref.regval_of (cur_privilege_ref.read_from s)) else
+  if reg_name = "Xs" then SOME (Xs_ref.regval_of (Xs_ref.read_from s)) else
+  if reg_name = "nextPC" then SOME (nextPC_ref.regval_of (nextPC_ref.read_from s)) else
+  if reg_name = "PC" then SOME (PC_ref.regval_of (PC_ref.read_from s)) else
+  NONE))`;
+
+
+(*val set_regval : string -> register_value -> regstate -> Maybe.maybe regstate*)
+val _ = Define `
+ ((set_regval:string -> register_value -> regstate ->(regstate)option) reg_name v s=  
+ (if reg_name = "tlb39" then OPTION_MAP (\ v .  tlb39_ref.write_to v s) (tlb39_ref.of_regval v) else
+  if reg_name = "stval" then OPTION_MAP (\ v .  stval_ref.write_to v s) (stval_ref.of_regval v) else
+  if reg_name = "scause" then OPTION_MAP (\ v .  scause_ref.write_to v s) (scause_ref.of_regval v) else
+  if reg_name = "sepc" then OPTION_MAP (\ v .  sepc_ref.write_to v s) (sepc_ref.of_regval v) else
+  if reg_name = "sscratch" then OPTION_MAP (\ v .  sscratch_ref.write_to v s) (sscratch_ref.of_regval v) else
+  if reg_name = "stvec" then OPTION_MAP (\ v .  stvec_ref.write_to v s) (stvec_ref.of_regval v) else
+  if reg_name = "satp" then OPTION_MAP (\ v .  satp_ref.write_to v s) (satp_ref.of_regval v) else
+  if reg_name = "sideleg" then OPTION_MAP (\ v .  sideleg_ref.write_to v s) (sideleg_ref.of_regval v) else
+  if reg_name = "sedeleg" then OPTION_MAP (\ v .  sedeleg_ref.write_to v s) (sedeleg_ref.of_regval v) else
+  if reg_name = "pmpcfg0" then OPTION_MAP (\ v .  pmpcfg0_ref.write_to v s) (pmpcfg0_ref.of_regval v) else
+  if reg_name = "pmpaddr0" then OPTION_MAP (\ v .  pmpaddr0_ref.write_to v s) (pmpaddr0_ref.of_regval v) else
+  if reg_name = "mhartid" then OPTION_MAP (\ v .  mhartid_ref.write_to v s) (mhartid_ref.of_regval v) else
+  if reg_name = "marchid" then OPTION_MAP (\ v .  marchid_ref.write_to v s) (marchid_ref.of_regval v) else
+  if reg_name = "mimpid" then OPTION_MAP (\ v .  mimpid_ref.write_to v s) (mimpid_ref.of_regval v) else
+  if reg_name = "mvendorid" then OPTION_MAP (\ v .  mvendorid_ref.write_to v s) (mvendorid_ref.of_regval v) else
+  if reg_name = "minstret" then OPTION_MAP (\ v .  minstret_ref.write_to v s) (minstret_ref.of_regval v) else
+  if reg_name = "mtime" then OPTION_MAP (\ v .  mtime_ref.write_to v s) (mtime_ref.of_regval v) else
+  if reg_name = "mcycle" then OPTION_MAP (\ v .  mcycle_ref.write_to v s) (mcycle_ref.of_regval v) else
+  if reg_name = "mscratch" then OPTION_MAP (\ v .  mscratch_ref.write_to v s) (mscratch_ref.of_regval v) else
+  if reg_name = "mtval" then OPTION_MAP (\ v .  mtval_ref.write_to v s) (mtval_ref.of_regval v) else
+  if reg_name = "mepc" then OPTION_MAP (\ v .  mepc_ref.write_to v s) (mepc_ref.of_regval v) else
+  if reg_name = "mcause" then OPTION_MAP (\ v .  mcause_ref.write_to v s) (mcause_ref.of_regval v) else
+  if reg_name = "mtvec" then OPTION_MAP (\ v .  mtvec_ref.write_to v s) (mtvec_ref.of_regval v) else
+  if reg_name = "medeleg" then OPTION_MAP (\ v .  medeleg_ref.write_to v s) (medeleg_ref.of_regval v) else
+  if reg_name = "mideleg" then OPTION_MAP (\ v .  mideleg_ref.write_to v s) (mideleg_ref.of_regval v) else
+  if reg_name = "mie" then OPTION_MAP (\ v .  mie_ref.write_to v s) (mie_ref.of_regval v) else
+  if reg_name = "mip" then OPTION_MAP (\ v .  mip_ref.write_to v s) (mip_ref.of_regval v) else
+  if reg_name = "mstatus" then OPTION_MAP (\ v .  mstatus_ref.write_to v s) (mstatus_ref.of_regval v) else
+  if reg_name = "misa" then OPTION_MAP (\ v .  misa_ref.write_to v s) (misa_ref.of_regval v) else
+  if reg_name = "cur_inst" then OPTION_MAP (\ v .  cur_inst_ref.write_to v s) (cur_inst_ref.of_regval v) else
+  if reg_name = "cur_privilege" then OPTION_MAP (\ v .  cur_privilege_ref.write_to v s) (cur_privilege_ref.of_regval v) else
+  if reg_name = "Xs" then OPTION_MAP (\ v .  Xs_ref.write_to v s) (Xs_ref.of_regval v) else
+  if reg_name = "nextPC" then OPTION_MAP (\ v .  nextPC_ref.write_to v s) (nextPC_ref.of_regval v) else
+  if reg_name = "PC" then OPTION_MAP (\ v .  PC_ref.write_to v s) (PC_ref.of_regval v) else
+  NONE))`;
+
+
+val _ = Define `
+ ((register_accessors:(string -> regstate ->(register_value)option)#(string -> register_value -> regstate ->(regstate)option))=  (get_regval, set_regval))`;
+
+
+
+val _ = type_abbrev((* ( 'a, 'r) *) "MR" , ``: (regstate, 'a, 'r, exception) state_monad$monadRS``);
+val _ = type_abbrev((*  'a *) "M" , ``: (regstate, 'a, exception) state_monad$monadS``);
+val _ = export_theory()
+