diff options
| author | Thomas Bauereiss | 2018-08-29 15:35:44 +0100 |
|---|---|---|
| committer | Thomas Bauereiss | 2018-08-29 15:35:44 +0100 |
| commit | 07e3591e2427db2d9407d554ac57984ca566c6ed (patch) | |
| tree | 9fdd56300b7b0fde4ddecfaed2587bb937cb69ff /snapshots/isabelle/aarch64/Aarch64.thy | |
| parent | 6860b871787df1341c94f4239904fef1743f8625 (diff) | |
Updated snapshots for Isabelle 2018
Diffstat (limited to 'snapshots/isabelle/aarch64/Aarch64.thy')
| -rw-r--r-- | snapshots/isabelle/aarch64/Aarch64.thy | 2195 |
1 files changed, 1118 insertions, 1077 deletions
diff --git a/snapshots/isabelle/aarch64/Aarch64.thy b/snapshots/isabelle/aarch64/Aarch64.thy index 55125942..a2156632 100644 --- a/snapshots/isabelle/aarch64/Aarch64.thy +++ b/snapshots/isabelle/aarch64/Aarch64.thy @@ -1,18 +1,18 @@ -chapter \<open>Generated by Lem from aarch64.lem.\<close> +chapter \<open>Generated by Lem from \<open>aarch64.lem\<close>.\<close> theory "Aarch64" -imports - Main - "Lem_pervasives_extra" - "Sail2_instr_kinds" - "Sail2_values" - "Sail2_operators_mwords" - "Sail2_prompt_monad" - "Sail2_prompt" - "Sail2_string" - "Aarch64_types" - "Aarch64_extras" +imports + Main + "LEM.Lem_pervasives_extra" + "Sail.Sail2_instr_kinds" + "Sail.Sail2_values" + "Sail.Sail2_operators_mwords" + "Sail.Sail2_prompt_monad" + "Sail.Sail2_prompt" + "Sail.Sail2_string" + "Aarch64_types" + "Aarch64_extras" begin @@ -27,6 +27,12 @@ begin (*open import Aarch64_types*) (*open import Aarch64_extras*) +(*val eq_unit : unit -> unit -> bool*) + +definition eq_unit :: " unit \<Rightarrow> unit \<Rightarrow> bool " where + " eq_unit g__306 g__307 = ( True )" + + @@ -141,7 +147,7 @@ definition ReadRAM :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len) definition WriteRAM :: "('m::len)itself \<Rightarrow> int \<Rightarrow>('m::len)Word.word \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow>((register_value),(unit),(exception))monad " where " WriteRAM addr_length bytes hex_ram addr data = ( (let addr_length = (size_itself_int addr_length) in - write_ram addr_length bytes hex_ram addr data))" + write_ram addr_length bytes hex_ram addr data \<then> return () ))" definition TraceMemoryWrite :: " int \<Rightarrow>('m::len)Word.word \<Rightarrow>('p8_times_n_::len)Word.word \<Rightarrow> unit " where @@ -170,7 +176,7 @@ definition extsv :: " int \<Rightarrow>('n::len)Word.word \<Rightarrow>('m::len definition slice_mask :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where " slice_mask (n__tv :: int) i l = ( - (let (one :: 'n bits) = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (let one = ((extzv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in (shiftl ((sub_vec ((shiftl one l :: ( 'n::len)Word.word)) one :: ( 'n::len)Word.word)) i :: ( 'n::len)Word.word)))" @@ -187,8 +193,7 @@ definition is_zero_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarr definition is_ones_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow> bool " where " is_ones_subrange xs i j = ( - (let (m :: 'n bits) = - ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) in + (let m = ((slice_mask ((int (size xs))) j ((((j - i)) + (( 1 :: int)::ii))) :: ( 'n::len)Word.word)) in (((and_vec xs m :: ( 'n::len)Word.word)) = m)))" @@ -325,7 +330,7 @@ definition unsigned_subrange :: "('n::len)Word.word \<Rightarrow> int \<Rightar definition zext_ones :: " int \<Rightarrow> int \<Rightarrow>('n::len)Word.word " where " zext_ones (n__tv :: int) m = ( - (let (v :: 'n bits) = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in + (let v = ((extsv n__tv (vec_of_bits [B1] :: 1 Word.word) :: ( 'n::len)Word.word)) in (shiftr v ((((int (size v))) - m)) :: ( 'n::len)Word.word)))" @@ -733,28 +738,28 @@ definition undefined_InstrSet :: " unit \<Rightarrow>((register_value),(InstrSe definition undefined_ProcState :: " unit \<Rightarrow>((register_value),(ProcState),(exception))monad " where " undefined_ProcState _ = ( - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__4 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__5 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__6 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__7 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__8 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__9 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__10 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__11 :: 1 bits) . - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__12 :: 2 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__13 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__14 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__15 :: 1 bits) . - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__16 :: 4 bits) . - (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__17 :: 8 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__18 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__19 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__20 :: 1 bits) . - (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__21 :: 5 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__0 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__4 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__5 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__6 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__7 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__8 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__9 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__10 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__11 :: 1 Word.word) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__12 :: 2 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__13 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__14 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__15 :: 1 Word.word) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__16 :: 4 Word.word) . + (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__17 :: 8 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__18 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__19 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__20 :: 1 Word.word) . + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__21 :: 5 Word.word) . return ((| ProcState_N = w__0, ProcState_Z = w__1, ProcState_C = w__2, @@ -818,10 +823,10 @@ definition undefined_BranchType :: " unit \<Rightarrow>((register_value),(Branc definition undefined_ExceptionRecord :: " unit \<Rightarrow>((register_value),(ExceptionRecord),(exception))monad " where " undefined_ExceptionRecord _ = ( undefined_Exception () \<bind> (\<lambda> (w__0 :: Exception) . - (undefined_bitvector (( 25 :: int)::ii) :: ( 25 Word.word) M) \<bind> (\<lambda> (w__1 :: 25 bits) . - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + (undefined_bitvector (( 25 :: int)::ii) :: ( 25 Word.word) M) \<bind> (\<lambda> (w__1 :: 25 Word.word) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . undefined_bool () \<bind> (\<lambda> (w__3 :: bool) . - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__4 :: 52 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__4 :: 52 Word.word) . return ((| ExceptionRecord_typ = w__0, ExceptionRecord_syndrome = w__1, ExceptionRecord_vaddress = w__2, @@ -945,15 +950,15 @@ definition undefined_FaultRecord :: " unit \<Rightarrow>((register_value),(Faul " undefined_FaultRecord _ = ( undefined_Fault () \<bind> (\<lambda> (w__0 :: Fault) . undefined_AccType () \<bind> (\<lambda> (w__1 :: AccType) . - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__2 :: 52 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__2 :: 52 Word.word) . undefined_bool () \<bind> (\<lambda> (w__3 :: bool) . undefined_bool () \<bind> (\<lambda> (w__4 :: bool) . undefined_int () \<bind> (\<lambda> (w__5 :: ii) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__6 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__6 :: 1 Word.word) . undefined_bool () \<bind> (\<lambda> (w__7 :: bool) . - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 :: 4 bits) . - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__9 :: 2 bits) . - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__10 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 :: 4 Word.word) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__9 :: 2 Word.word) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__10 :: 4 Word.word) . return ((| FaultRecord_typ = w__0, FaultRecord_acctype = w__1, FaultRecord_ipaddress = w__2, @@ -1072,8 +1077,8 @@ definition undefined_DeviceType :: " unit \<Rightarrow>((register_value),(Devic definition undefined_MemAttrHints :: " unit \<Rightarrow>((register_value),(MemAttrHints),(exception))monad " where " undefined_MemAttrHints _ = ( - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 bits) . - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__1 :: 2 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 Word.word) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__1 :: 2 Word.word) . undefined_bool () \<bind> (\<lambda> (w__2 :: bool) . return ((| MemAttrHints_attrs = w__0, MemAttrHints_hints = w__1, @@ -1102,8 +1107,8 @@ definition undefined_MemoryAttributes :: " unit \<Rightarrow>((register_value), definition undefined_FullAddress :: " unit \<Rightarrow>((register_value),(FullAddress),(exception))monad " where " undefined_FullAddress _ = ( - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__0 :: 52 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__0 :: 52 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . return ((| FullAddress_physicaladdress = w__0, FullAddress_NS = w__1 |)))))" @@ -1115,7 +1120,7 @@ definition undefined_AddressDescriptor :: " unit \<Rightarrow>((register_value) undefined_FaultRecord () \<bind> (\<lambda> (w__0 :: FaultRecord) . undefined_MemoryAttributes () \<bind> (\<lambda> (w__1 :: MemoryAttributes) . undefined_FullAddress () \<bind> (\<lambda> (w__2 :: FullAddress) . - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . return ((| AddressDescriptor_fault = w__0, AddressDescriptor_memattrs = w__1, AddressDescriptor_paddress = w__2, @@ -1519,10 +1524,10 @@ definition undefined_AccessDescriptor :: " unit \<Rightarrow>((register_value), definition undefined_Permissions :: " unit \<Rightarrow>((register_value),(Permissions),(exception))monad " where " undefined_Permissions _ = ( - (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__0 :: 3 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 bits) . + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__0 :: 3 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 Word.word) . return ((| Permissions_ap = w__0, Permissions_xn = w__1, Permissions_xxn = w__2, @@ -1534,13 +1539,13 @@ definition undefined_Permissions :: " unit \<Rightarrow>((register_value),(Perm definition undefined_TLBRecord :: " unit \<Rightarrow>((register_value),(TLBRecord),(exception))monad " where " undefined_TLBRecord _ = ( undefined_Permissions () \<bind> (\<lambda> (w__0 :: Permissions) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: 4 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__2 :: 4 Word.word) . undefined_bool () \<bind> (\<lambda> (w__3 :: bool) . undefined_int () \<bind> (\<lambda> (w__4 :: ii) . undefined_int () \<bind> (\<lambda> (w__5 :: ii) . undefined_DescriptorUpdate () \<bind> (\<lambda> (w__6 :: DescriptorUpdate) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__7 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__7 :: 1 Word.word) . undefined_AddressDescriptor () \<bind> (\<lambda> (w__8 :: AddressDescriptor) . return ((| TLBRecord_perms = w__0, TLBRecord_nG = w__1, @@ -1709,8 +1714,8 @@ definition undefined_PrivilegeLevel :: " unit \<Rightarrow>((register_value),(P definition undefined_AArch32_SErrorSyndrome :: " unit \<Rightarrow>((register_value),(AArch32_SErrorSyndrome),(exception))monad " where " undefined_AArch32_SErrorSyndrome _ = ( - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . return ((| AArch32_SErrorSyndrome_AET = w__0, AArch32_SErrorSyndrome_ExT = w__1 |)))))" @@ -1748,13 +1753,13 @@ definition undefined_SystemOp :: " unit \<Rightarrow>((register_value),(SystemO definition undefined_PCSample :: " unit \<Rightarrow>((register_value),(PCSample),(exception))monad " where " undefined_PCSample _ = ( undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__2 :: 2 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 bits) . - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__4 :: 1 bits) . - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 bits) . - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . - (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__2 :: 2 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 Word.word) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__4 :: 1 Word.word) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . return ((| PCSample_valid_name = w__0, PCSample_pc = w__1, PCSample_el = w__2, @@ -3288,9 +3293,9 @@ definition AArch64_CreateFaultRecord :: " Fault \<Rightarrow>(52)Word.word \<Ri " AArch64_CreateFaultRecord typ1 ipaddress level acctype write1 extflag errortype secondstage s2fs1walk = ( undefined_FaultRecord () \<bind> (\<lambda> (fault :: FaultRecord) . (let fault = ((fault (| FaultRecord_typ := typ1 |))) in - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__0 :: 4 Word.word) . (let fault = ((fault (| FaultRecord_domain := w__0 |))) in - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 Word.word) . (let (fault :: FaultRecord) = ((fault (| FaultRecord_debugmoe := w__1 |))) in (let (fault :: FaultRecord) = ((fault (| FaultRecord_errortype := errortype |))) in (let (fault :: FaultRecord) = ((fault (| FaultRecord_ipaddress := ipaddress |))) in @@ -3747,7 +3752,7 @@ definition CombineS1S2AttrHints :: " MemAttrHints \<Rightarrow> MemAttrHints \< " CombineS1S2AttrHints s1desc s2desc = ( undefined_MemAttrHints () \<bind> (\<lambda> (result :: MemAttrHints) . (if (((((((MemAttrHints_attrs s2desc) = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> ((((MemAttrHints_attrs s1desc) = (vec_of_bits [B0,B1] :: 2 Word.word))))))) then - (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 bits) . + (undefined_bitvector (( 2 :: int)::ii) :: ( 2 Word.word) M) \<bind> (\<lambda> (w__0 :: 2 Word.word) . (let (result :: MemAttrHints) = ((result (| MemAttrHints_attrs := w__0 |))) in return result)) else @@ -3814,7 +3819,7 @@ definition aget_Vpart :: " int \<Rightarrow> int \<Rightarrow> int \<Rightarrow (assert_exp (((width__tv = (( 64 :: int)::ii)))) (''(width == 64)'') \<then> read_reg V_ref) \<bind> (\<lambda> (w__1 :: ( 128 bits) list) . return ((Word.ucast - ((slice ((access_list_dec w__1 n :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: ( 'width::len)Word.word)) + ((slice ((access_list_dec w__1 n :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 'width::len)Word.word)))))" @@ -3885,8 +3890,8 @@ definition CountLeadingSignBits :: "('N::len)Word.word \<Rightarrow>((register_ definition BitReverse :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " BitReverse data = ( - (undefined_bitvector ((int (size data))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . - (let (result :: 'N bits) = + (undefined_bitvector ((int (size data))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . + (let result = (foreach (index_list (( 0 :: int)::ii) ((((int (size data))) - (( 1 :: int)::ii))) (( 1 :: int)::ii)) result (\<lambda> i result . (set_slice ((int (size data))) (( 1 :: int)::ii) result @@ -4012,7 +4017,7 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le :: 1 Word.word) :: 1 Word.word)) ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) - :: ( 'N::len)Word.word)) + :: 16 Word.word)) :: ( 'N::len)Word.word))) else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in @@ -4024,7 +4029,7 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le :: 1 Word.word) :: 1 Word.word)) ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) - :: ( 'N::len)Word.word)) + :: 32 Word.word)) :: ( 'N::len)Word.word))) else if (((p00 = (( 64 :: int)::ii)))) then (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in @@ -4036,7 +4041,7 @@ definition FPNeg :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le :: 1 Word.word) :: 1 Word.word)) ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) - :: ( 'N::len)Word.word)) + :: 64 Word.word)) :: ( 'N::len)Word.word))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4052,7 +4057,7 @@ definition FPAbs :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) ((slice op1 (( 0 :: int)::ii) (((( 16 :: int)::ii) - (( 1 :: int)::ii))) :: 15 Word.word)) - :: ( 'N::len)Word.word)) + :: 16 Word.word)) :: ( 'N::len)Word.word))) else if (((p00 = (( 32 :: int)::ii)))) then (let (op1 :: 32 Word.word) = ((Word.ucast op1 :: 32 Word.word)) in @@ -4060,7 +4065,7 @@ definition FPAbs :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) ((slice op1 (( 0 :: int)::ii) (((( 32 :: int)::ii) - (( 1 :: int)::ii))) :: 31 Word.word)) - :: ( 'N::len)Word.word)) + :: 32 Word.word)) :: ( 'N::len)Word.word))) else if (((p00 = (( 64 :: int)::ii)))) then (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in @@ -4068,7 +4073,7 @@ definition FPAbs :: "('N::len)Word.word \<Rightarrow>((register_value),(('N::le return ((Word.ucast ((concat_vec (vec_of_bits [B0] :: 1 Word.word) ((slice op1 (( 0 :: int)::ii) (((( 64 :: int)::ii) - (( 1 :: int)::ii))) :: 63 Word.word)) - :: ( 'N::len)Word.word)) + :: 64 Word.word)) :: ( 'N::len)Word.word))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4178,22 +4183,22 @@ definition AArch32_ReportHypEntry :: " ExceptionRecord \<Rightarrow>((register_ :: 32 Word.word)) \<then> (if ((((((typ1 = Exception_InstructionAbort))) \<or> (((typ1 = Exception_PCAlignment)))))) then (write_reg HIFAR_ref ((slice(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__0 :: 32 Word.word) . write_reg HDFAR_ref w__0) else if (((typ1 = Exception_DataAbort))) then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . write_reg HIFAR_ref w__1 \<then> write_reg HDFAR_ref ((slice(ExceptionRecord_vaddress exception) (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word))) else return () )) \<then> (if(ExceptionRecord_ipavalid exception) then - (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . write_reg HPFAR_ref ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__2 (( 4 :: int)::ii) ((slice(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 28 :: int)::ii) :: 28 Word.word)) :: 32 Word.word))) else - (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (read_reg HPFAR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . (undefined_bitvector (( 28 :: int)::ii) :: ( 28 Word.word) M) \<bind> (\<lambda> (w__4 :: 28 Word.word) . write_reg HPFAR_ref ((set_slice (( 32 :: int)::ii) (( 28 :: int)::ii) w__3 (( 4 :: int)::ii) w__4 :: 32 Word.word)))))))))))))))" @@ -4216,8 +4221,7 @@ definition aset_Elem__0 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>( definition aset_Elem__1 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>('size::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " aset_Elem__1 vector_name__arg e value_name = ( (let vector_name = vector_name__arg in - (aset_Elem__0 vector_name e ((make_the_value ((int (size value_name))) :: ( 'size::len)itself)) value_name - :: (( 'N::len)Word.word) M)))" + (aset_Elem__0 vector_name e ((make_the_value ((int (size value_name))) )) value_name :: (( 'N::len)Word.word) M)))" (*val aget_Elem__0 : forall 'N 'size . Size 'N, Size 'size => mword 'N -> ii -> itself 'size -> M (mword 'size)*) @@ -4233,7 +4237,7 @@ definition aget_Elem__0 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>( definition aget_Elem__1 :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('size::len)Word.word),(exception))monad " where " aget_Elem__1 (size__tv :: int) vector_name e = ( - (aget_Elem__0 vector_name e ((make_the_value size__tv :: ( 'size::len)itself)) :: (( 'size::len)Word.word) M))" + (aget_Elem__0 vector_name e ((make_the_value size__tv )) :: (( 'size::len)Word.word) M))" (*val UnsignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) @@ -4259,7 +4263,7 @@ definition UnsignedSatQ :: " int \<Rightarrow>('N::len)itself \<Rightarrow>((re (let (saturated :: bool) = False in (result, saturated)))) in (result, saturated))) in - return ((GetSlice_int ((make_the_value N :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" + return ((GetSlice_int ((make_the_value N )) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" (*val SignedSatQ : forall 'N . Size 'N => ii -> itself 'N -> M (mword 'N * bool)*) @@ -4285,7 +4289,7 @@ definition SignedSatQ :: " int \<Rightarrow>('N::len)itself \<Rightarrow>((regi (let (saturated :: bool) = False in (result, saturated)))) in (result, saturated))) in - return ((GetSlice_int ((make_the_value N :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" + return ((GetSlice_int ((make_the_value N )) result (( 0 :: int)::ii) :: ( 'N::len)Word.word), saturated))))))" (*val SatQ : forall 'N . Size 'N => ii -> itself 'N -> bool -> M (mword 'N * bool)*) @@ -4294,10 +4298,10 @@ definition SatQ :: " int \<Rightarrow>('N::len)itself \<Rightarrow> bool \<Righ " SatQ i N unsigned = ( (let N = (size_itself_int N) in undefined_bool () \<bind> (\<lambda> (sat :: bool) . - (undefined_bitvector N :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . - (if unsigned then (UnsignedSatQ i ((make_the_value N :: ( 'N::len)itself)) :: ((( 'N::len)Word.word * bool)) M) - else (SignedSatQ i ((make_the_value N :: ( 'N::len)itself)) :: ((( 'N::len)Word.word * bool)) M)) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in - (let (result :: 'N bits) = tup__0 in + (undefined_bitvector N :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . + (if unsigned then (UnsignedSatQ i ((make_the_value N )) ) + else (SignedSatQ i ((make_the_value N )) )) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in (let (sat :: bool) = tup__1 in return (result, sat)))))))))" @@ -4308,7 +4312,7 @@ definition Replicate :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>((re " Replicate (N__tv :: int) x = ( assert_exp (((((N__tv mod ((int (size x))))) = (( 0 :: int)::ii)))) (''((N MOD M) == 0)'') \<then> ((let O1 = (N__tv div ((int (size x)))) in - assert_exp True ('''') \<then> return ((replicate_bits x ((N__tv div ((int (size x))))) :: ( 'N::len)Word.word)))))" + assert_exp True ('''') \<then> return ((replicate_bits x ((N__tv div ((int (size x))))))))))" (*val Zeros__0 : forall 'N . Size 'N => itself 'N -> mword 'N*) @@ -4322,14 +4326,14 @@ definition Zeros__0 :: "('N::len)itself \<Rightarrow>('N::len)Word.word " wher definition Zeros__1 :: " int \<Rightarrow> unit \<Rightarrow>('N::len)Word.word " where - " Zeros__1 (N__tv :: int) _ = ( (Zeros__0 ((make_the_value N__tv :: ( 'N::len)itself)) :: ( 'N::len)Word.word))" + " Zeros__1 (N__tv :: int) _ = ( (Zeros__0 ((make_the_value N__tv )) :: ( 'N::len)Word.word))" (*val __ResetMemoryState : unit -> M unit*) definition ResetMemoryState :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " ResetMemoryState _ = ( - (read_reg Memory_ref :: ( 52 Word.word) M) \<bind> (\<lambda> (w__0 :: 52 Word.word) . + (read_reg Memory_ref :: ( 52 Word.word) M) \<bind> (\<lambda> (w__0 :: 52 bits) . (let (_ :: unit) = (InitRAM (( 52 :: int)::ii) (( 1 :: int)::ii) w__0 ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word))) in write_reg ExclusiveLocal_ref False)))" @@ -4346,8 +4350,7 @@ definition ZeroExtend__0 :: "('M::len)Word.word \<Rightarrow>('N::len)itself \< definition ZeroExtend__1 :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where - " ZeroExtend__1 (N__tv :: int) x = ( - (ZeroExtend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M))" + " ZeroExtend__1 (N__tv :: int) x = ( (ZeroExtend__0 x ((make_the_value N__tv )) :: (( 'N::len)Word.word) M))" (*val aset_Vpart : forall 'width . Size 'width => ii -> ii -> mword 'width -> M unit*) @@ -4358,8 +4361,8 @@ definition aset_Vpart :: " int \<Rightarrow> int \<Rightarrow>('width::len)Word assert_exp ((((((part = (( 0 :: int)::ii)))) \<or> (((part = (( 1 :: int)::ii))))))) (''((part == 0) || (part == 1))'')) \<then> (if (((part = (( 0 :: int)::ii)))) then (assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 64 :: int)::ii))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || (width == 64))))'') \<then> - read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 Word.word) list) . - (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \<bind> (\<lambda> (w__1 :: 128 bits) . + read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . + (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \<bind> (\<lambda> (w__1 :: 128 Word.word) . write_reg V_ref ((update_list_dec w__0 n w__1 :: ( 128 Word.word) list)))) else (assert_exp (((((int (size value_name))) = (( 64 :: int)::ii)))) (''(width == 64)'') \<then> @@ -4369,7 +4372,7 @@ definition aset_Vpart :: " int \<Rightarrow> int \<Rightarrow>('width::len)Word ((update_subrange_vec_dec tmp_2870 (( 127 :: int)::ii) (( 64 :: int)::ii) ((subrange_vec_dec value_name (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) :: 128 Word.word)) in - read_reg V_ref \<bind> (\<lambda> (w__3 :: ( 128 Word.word) list) . + read_reg V_ref \<bind> (\<lambda> (w__3 :: ( 128 bits) list) . write_reg V_ref ((update_list_dec w__3 n tmp_2870 :: ( 128 Word.word) list))))))))" @@ -4379,8 +4382,8 @@ definition aset_V :: " int \<Rightarrow>('width::len)Word.word \<Rightarrow>((r " aset_V n value_name = ( ((assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \<then> assert_exp ((((((((int (size value_name))) = (( 8 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> ((((((((int (size value_name))) = (( 64 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 128 :: int)::ii)))))))))))))))) (''((width == 8) || ((width == 16) || ((width == 32) || ((width == 64) || (width == 128)))))'')) \<then> - read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 Word.word) list) . - (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \<bind> (\<lambda> (w__1 :: 128 bits) . + read_reg V_ref) \<bind> (\<lambda> (w__0 :: ( 128 bits) list) . + (ZeroExtend__1 (( 128 :: int)::ii) value_name :: ( 128 Word.word) M) \<bind> (\<lambda> (w__1 :: 128 Word.word) . write_reg V_ref ((update_list_dec w__0 n w__1 :: ( 128 Word.word) list)))))" @@ -4390,7 +4393,7 @@ definition AArch64_ResetSIMDFPRegisters :: " unit \<Rightarrow>((register_value " AArch64_ResetSIMDFPRegisters _ = ( (foreachM (index_list (( 0 :: int)::ii) (( 31 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . aset_V i w__0))))" + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . aset_V i w__0))))" (*val aset_SP : forall 'width . Size 'width => mword 'width -> M unit*) @@ -4400,23 +4403,23 @@ definition aset_SP :: "('width::len)Word.word \<Rightarrow>((register_value),(u (assert_exp ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 64 :: int)::ii))))))) (''((width == 32) || (width == 64))'') \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__0 :: ProcState) . if ((((ProcState_SP w__0) = (vec_of_bits [B0] :: 1 Word.word)))) then - (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . write_reg SP_EL0_ref w__1) else read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . (let p__299 = ((ProcState_EL w__2)) in (let pat0 = p__299 in if (((pat0 = EL0))) then - (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . write_reg SP_EL0_ref w__3) else if (((pat0 = EL1))) then - (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . write_reg SP_EL1_ref w__4) else if (((pat0 = EL2))) then - (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) . write_reg SP_EL2_ref w__5) else - (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) value_name :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . write_reg SP_EL3_ref w__6))))))" @@ -4425,7 +4428,7 @@ definition aset_SP :: "('width::len)Word.word \<Rightarrow>((register_value),(u definition LSR_C :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where " LSR_C x shift = ( assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \<then> - ((let (result :: 'N bits) = ((shiftr x shift :: ( 'N::len)Word.word)) in + ((let result = ((shiftr x shift :: ( 'N::len)Word.word)) in (let (carry_out :: 1 bits) = (if ((shift > ((int (size result))))) then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [access_vec_dec x ((shift - (( 1 :: int)::ii)))] :: 1 Word.word)) in @@ -4438,11 +4441,11 @@ definition LSR :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register " LSR x shift = ( (assert_exp ((shift \<ge> (( 0 :: int)::ii))) (''(shift >= 0)'') \<then> (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (anon10 :: 1 bits) . - (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if (((shift = (( 0 :: int)::ii)))) then return x else - (LSR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in - (let (result :: 'N bits) = tup__0 in + (LSR_C x shift ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in (let (anon10 :: 1 bits) = tup__1 in return result)))))))" @@ -4453,7 +4456,7 @@ definition Poly32Mod2 :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right " Poly32Mod2 data__arg poly = ( (let data = data__arg in assert_exp ((((int (size data))) > (( 32 :: int)::ii))) (''(N > 32)'') \<then> - ((let (poly' :: 'N bits) = ((extzv ((int (size data))) poly :: ( 'N::len)Word.word)) in + ((let poly' = ((extzv ((int (size data))) poly :: ( 'N::len)Word.word)) in (let (data :: ( 'N::len)Word.word) = (foreach (index_list ((((int (size data))) - (( 1 :: int)::ii))) (( 32 :: int)::ii) (- (( 1 :: int)::ii))) data (\<lambda> i data . @@ -4469,7 +4472,7 @@ definition Poly32Mod2 :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right definition LSL_C :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where " LSL_C x shift = ( assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \<then> - ((let (result :: 'N bits) = ((shiftl x shift :: ( 'N::len)Word.word)) in + ((let result = ((shiftl x shift :: ( 'N::len)Word.word)) in (let (carry_out :: 1 bits) = (if ((shift > ((int (size result))))) then (vec_of_bits [B0] :: 1 Word.word) else (vec_of_bits [access_vec_dec x ((((int (size result))) - shift))] :: 1 Word.word)) in @@ -4482,11 +4485,11 @@ definition LSL :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register " LSL x shift = ( (assert_exp ((shift \<ge> (( 0 :: int)::ii))) (''(shift >= 0)'') \<then> (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (anon10 :: 1 bits) . - (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if (((shift = (( 0 :: int)::ii)))) then return x else - (LSL_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in - (let (result :: 'N bits) = tup__0 in + (LSL_C x shift ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in (let (anon10 :: 1 bits) = tup__1 in return result)))))))" @@ -4523,7 +4526,7 @@ definition LSInstructionSyndrome :: " unit \<Rightarrow>((register_value),((11) (*val IsZero : forall 'N . Size 'N => mword 'N -> bool*) definition IsZero :: "('N::len)Word.word \<Rightarrow> bool " where - " IsZero x = ( (x = ((Zeros__0 ((make_the_value ((int (size x))) :: ( 'N::len)itself)) :: ( 'N::len)Word.word))))" + " IsZero x = ( (x = ((Zeros__0 ((make_the_value ((int (size x))) )) :: ( 'N::len)Word.word))))" (*val IsZeroBit : forall 'N . Size 'N => mword 'N -> mword ty1*) @@ -4540,8 +4543,7 @@ definition AddWithCarry :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word " AddWithCarry x y carry_in = ( (let (unsigned_sum :: ii) = (((((Word.uint x)) + ((Word.uint y)))) + ((Word.uint carry_in))) in (let (signed_sum :: ii) = (((((Word.sint x)) + ((Word.sint y)))) + ((Word.uint carry_in))) in - (let (result :: 'N bits) = - ((GetSlice_int ((make_the_value ((int (size x))) :: ( 'N::len)itself)) unsigned_sum (( 0 :: int)::ii) :: ( 'N::len)Word.word)) in + (let result = ((GetSlice_int ((make_the_value ((int (size x))) )) unsigned_sum (( 0 :: int)::ii) :: ( 'N::len)Word.word)) in (let (n :: 1 bits) = ((vec_of_bits [access_vec_dec result ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in (let (z :: 1 bits) = @@ -4634,23 +4636,23 @@ definition FPZero :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((register_va if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 5 bits) = ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (exp1 :: 5 bits) = ((Zeros__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 6 Word.word)) frac :: 16 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 8 bits) = ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (exp1 :: 8 bits) = ((Zeros__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 9 Word.word)) frac :: 32 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 11 bits) = ((Zeros__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (exp1 :: 11 bits) = ((Zeros__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in (let (frac :: 52 bits) = ((Zeros__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 12 Word.word)) frac :: 64 Word.word)) :: ( 'N::len)Word.word)))))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4677,7 +4679,7 @@ definition ConstrainUnpredictableBits :: " int \<Rightarrow> Unpredictable \<Ri " ConstrainUnpredictableBits (width__tv :: int) which = ( (let (c :: Constraint) = (ConstrainUnpredictable which) in if (((c = Constraint_UNKNOWN))) then - return (c, (Zeros__0 ((make_the_value width__tv :: ( 'width::len)itself)) :: ( 'width::len)Word.word)) + return (c, (Zeros__0 ((make_the_value width__tv )) :: ( 'width::len)Word.word)) else (undefined_bitvector width__tv :: (( 'width::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'width::len)Word.word) . return (c, w__0))))" @@ -4725,7 +4727,7 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in - (let (exp :: 5 bits) = + (let (exp1 :: 5 bits) = ((concat_vec ((concat_vec ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -4738,13 +4740,13 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 6 itself)) :: 6 Word.word)) :: 10 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 6 Word.word)) frac :: 16 Word.word)) :: ( 'N::len)Word.word))))))) else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in - (let (exp :: 8 bits) = + (let (exp1 :: 8 bits) = ((concat_vec ((concat_vec ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -4757,13 +4759,13 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 19 itself)) :: 19 Word.word)) :: 23 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 9 Word.word)) frac :: 32 Word.word)) :: ( 'N::len)Word.word))))))) else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec imm8 (( 7 :: int)::ii)] :: 1 Word.word)) in - (let (exp :: 11 bits) = + (let (exp1 :: 11 bits) = ((concat_vec ((concat_vec ((not_vec (vec_of_bits [access_vec_dec imm8 (( 6 :: int)::ii)] :: 1 Word.word) :: 1 Word.word)) @@ -4776,7 +4778,7 @@ definition VFPExpandImm :: " int \<Rightarrow>(8)Word.word \<Rightarrow>((regis ((concat_vec ((subrange_vec_dec imm8 (( 3 :: int)::ii) (( 0 :: int)::ii) :: 4 Word.word)) ((Zeros__0 ((make_the_value ((F - (( 4 :: int)::ii))) :: 48 itself)) :: 48 Word.word)) :: 52 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 12 Word.word)) frac :: 64 Word.word)) :: ( 'N::len)Word.word))))))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4792,8 +4794,7 @@ definition SignExtend__0 :: "('M::len)Word.word \<Rightarrow>('N::len)itself \< definition SignExtend__1 :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where - " SignExtend__1 (N__tv :: int) x = ( - (SignExtend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M))" + " SignExtend__1 (N__tv :: int) x = ( (SignExtend__0 x ((make_the_value N__tv )) :: (( 'N::len)Word.word) M))" (*val Extend__0 : forall 'M 'N . Size 'M, Size 'N => mword 'M -> itself 'N -> bool -> M (mword 'N)*) @@ -4803,13 +4804,13 @@ definition SignExtend__1 :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow> definition Extend__0 :: "('M::len)Word.word \<Rightarrow>('N::len)itself \<Rightarrow> bool \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " Extend__0 x N unsigned = ( (let N = (size_itself_int N) in - if unsigned then (ZeroExtend__0 x ((make_the_value N :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M) - else (SignExtend__0 x ((make_the_value N :: ( 'N::len)itself)) :: (( 'N::len)Word.word) M)))" + if unsigned then (ZeroExtend__0 x ((make_the_value N )) :: (( 'N::len)Word.word) M) + else (SignExtend__0 x ((make_the_value N )) :: (( 'N::len)Word.word) M)))" definition Extend__1 :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow> bool \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " Extend__1 (N__tv :: int) x unsigned = ( - (Extend__0 x ((make_the_value N__tv :: ( 'N::len)itself)) unsigned :: (( 'N::len)Word.word) M))" + (Extend__0 x ((make_the_value N__tv )) unsigned :: (( 'N::len)Word.word) M))" (*val ASR_C : forall 'N . Size 'N => mword 'N -> ii -> M (mword 'N * mword ty1)*) @@ -4817,7 +4818,7 @@ definition Extend__1 :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow> boo definition ASR_C :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register_value),(('N::len)Word.word*(1)Word.word),(exception))monad " where " ASR_C x shift = ( assert_exp ((shift > (( 0 :: int)::ii))) (''(shift > 0)'') \<then> - ((let (result :: 'N bits) = ((arith_shiftr x shift :: ( 'N::len)Word.word)) in + ((let result = ((arith_shiftr x shift :: ( 'N::len)Word.word)) in (let (carry_out :: 1 bits) = (if ((shift > ((int (size result))))) then (vec_of_bits [access_vec_dec x ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word) @@ -4831,11 +4832,11 @@ definition ASR :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register " ASR x shift = ( (assert_exp ((shift \<ge> (( 0 :: int)::ii))) (''(shift >= 0)'') \<then> (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (anon10 :: 1 bits) . - (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if (((shift = (( 0 :: int)::ii)))) then return x else - (ASR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in - (let (result :: 'N bits) = tup__0 in + (ASR_C x shift ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in (let (anon10 :: 1 bits) = tup__1 in return result)))))))" @@ -4851,13 +4852,13 @@ definition Ones__0 :: "('N::len)itself \<Rightarrow>('N::len)Word.word " where definition Ones__1 :: " int \<Rightarrow> unit \<Rightarrow>('N::len)Word.word " where - " Ones__1 (N__tv :: int) _ = ( (Ones__0 ((make_the_value N__tv :: ( 'N::len)itself)) :: ( 'N::len)Word.word))" + " Ones__1 (N__tv :: int) _ = ( (Ones__0 ((make_the_value N__tv )) :: ( 'N::len)Word.word))" (*val IsOnes : forall 'N . Size 'N => mword 'N -> bool*) definition IsOnes :: "('N::len)Word.word \<Rightarrow> bool " where - " IsOnes x = ( (x = ((Ones__0 ((make_the_value ((int (size x))) :: ( 'N::len)itself)) :: ( 'N::len)Word.word))))" + " IsOnes x = ( (x = ((Ones__0 ((make_the_value ((int (size x))) )) :: ( 'N::len)Word.word))))" (*val FPMaxNormal : forall 'N . Size 'N => integer -> mword ty1 -> M (mword 'N)*) @@ -4868,35 +4869,35 @@ definition FPMaxNormal :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((regist if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 5 bits) = + (let (exp1 :: 5 bits) = ((concat_vec ((Ones__0 ((make_the_value (((( 5 :: int)::ii) - (( 1 :: int)::ii))) :: 4 itself)) :: 4 Word.word)) (vec_of_bits [B0] :: 1 Word.word) :: 5 Word.word)) in (let (frac :: 10 bits) = ((Ones__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 6 Word.word)) frac :: 16 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 8 bits) = + (let (exp1 :: 8 bits) = ((concat_vec ((Ones__0 ((make_the_value (((( 8 :: int)::ii) - (( 1 :: int)::ii))) :: 7 itself)) :: 7 Word.word)) (vec_of_bits [B0] :: 1 Word.word) :: 8 Word.word)) in (let (frac :: 23 bits) = ((Ones__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 9 Word.word)) frac :: 32 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 11 bits) = + (let (exp1 :: 11 bits) = ((concat_vec ((Ones__0 ((make_the_value (((( 11 :: int)::ii) - (( 1 :: int)::ii))) :: 10 itself)) :: 10 Word.word)) (vec_of_bits [B0] :: 1 Word.word) :: 11 Word.word)) in (let (frac :: 52 bits) = ((Ones__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 12 Word.word)) frac :: 64 Word.word)) :: ( 'N::len)Word.word)))))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4909,23 +4910,23 @@ definition FPInfinity :: " int \<Rightarrow>(1)Word.word \<Rightarrow>((registe if (((p00 = (( 16 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (exp1 :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in (let (frac :: 10 bits) = ((Zeros__0 ((make_the_value F :: 10 itself)) :: 10 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 6 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 6 Word.word)) frac :: 16 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (exp1 :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in (let (frac :: 23 bits) = ((Zeros__0 ((make_the_value F :: 23 itself)) :: 23 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 9 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 9 Word.word)) frac :: 32 Word.word)) :: ( 'N::len)Word.word)))))) else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in - (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (exp1 :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in (let (frac :: 52 bits) = ((Zeros__0 ((make_the_value F :: 52 itself)) :: 52 Word.word)) in - return ((Word.ucast ((concat_vec ((concat_vec sign exp :: 12 Word.word)) frac :: ( 'N::len)Word.word)) + return ((Word.ucast ((concat_vec ((concat_vec sign exp1 :: 12 Word.word)) frac :: 64 Word.word)) :: ( 'N::len)Word.word)))))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4939,40 +4940,40 @@ definition FPDefaultNaN :: " int \<Rightarrow> unit \<Rightarrow>((register_val assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 16 :: int)::ii) - (( 5 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in - (let (exp :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in + (let (exp1 :: 5 bits) = ((Ones__0 ((make_the_value (( 5 :: int)::ii) :: 5 itself)) :: 5 Word.word)) in (let (frac :: 10 bits) = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 9 itself)) :: 9 Word.word)) :: 10 Word.word)) in return ((Word.ucast - ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 6 Word.word)) frac - :: ( 'N::len)Word.word)) + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp1 :: 6 Word.word)) frac + :: 16 Word.word)) :: ( 'N::len)Word.word))))))) else if (((p00 = (( 32 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 32 :: int)::ii) - (( 8 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in - (let (exp :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in + (let (exp1 :: 8 bits) = ((Ones__0 ((make_the_value (( 8 :: int)::ii) :: 8 itself)) :: 8 Word.word)) in (let (frac :: 23 bits) = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 22 itself)) :: 22 Word.word)) :: 23 Word.word)) in return ((Word.ucast - ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 9 Word.word)) frac - :: ( 'N::len)Word.word)) + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp1 :: 9 Word.word)) frac + :: 32 Word.word)) :: ( 'N::len)Word.word))))))) else if (((p00 = (( 64 :: int)::ii)))) then assert_exp True (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> ((let (F :: int) = ((((( 64 :: int)::ii) - (( 11 :: int)::ii))) - (( 1 :: int)::ii)) in (let (sign :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in - (let (exp :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in + (let (exp1 :: 11 bits) = ((Ones__0 ((make_the_value (( 11 :: int)::ii) :: 11 itself)) :: 11 Word.word)) in (let (frac :: 52 bits) = ((concat_vec (vec_of_bits [B1] :: 1 Word.word) ((Zeros__0 ((make_the_value ((F - (( 1 :: int)::ii))) :: 51 itself)) :: 51 Word.word)) :: 52 Word.word)) in return ((Word.ucast - ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp :: 12 Word.word)) frac - :: ( 'N::len)Word.word)) + ((concat_vec ((concat_vec (vec_of_bits [B0] :: 1 Word.word) exp1 :: 12 Word.word)) frac + :: 64 Word.word)) :: ( 'N::len)Word.word))))))) else assert_exp False (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> exit0 () ))" @@ -4983,7 +4984,7 @@ definition FPConvertNaN :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( " FPConvertNaN (M__tv :: int) op1 = ( ((assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> assert_exp ((((((M__tv = (( 16 :: int)::ii)))) \<or> ((((((M__tv = (( 32 :: int)::ii)))) \<or> (((M__tv = (( 64 :: int)::ii)))))))))) (''((M == 16) || ((M == 32) || (M == 64)))'')) \<then> - (undefined_bitvector M__tv :: (( 'M::len)Word.word) M)) \<bind> (\<lambda> (result :: 'M bits) . + (undefined_bitvector M__tv :: (( 'M::len)Word.word) M)) \<bind> (\<lambda> result . (undefined_bitvector (( 51 :: int)::ii) :: ( 51 Word.word) M) \<bind> (\<lambda> (frac :: 51 bits) . (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec op1 ((((int (size op1))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in @@ -5003,24 +5004,30 @@ definition FPConvertNaN :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow>( ((Zeros__0 ((make_the_value (( 42 :: int)::ii) :: 42 itself)) :: 42 Word.word)) :: 51 Word.word))) in (let p00 = (int (size result)) in - (let (result :: 'M bits) = + (let result = (if (((p00 = (( 64 :: int)::ii)))) then - (concat_vec - ((concat_vec sign - ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 52 :: int)::ii))) )) :: 12 Word.word)) - :: 13 Word.word)) frac + (Word.ucast + ((concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 64 :: int)::ii) - (( 52 :: int)::ii))) )) :: 12 Word.word)) + :: 13 Word.word)) frac + :: 64 Word.word)) :: ( 'M::len)Word.word) else if (((p00 = (( 32 :: int)::ii)))) then - (concat_vec - ((concat_vec sign - ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 23 :: int)::ii))) )) :: 9 Word.word)) - :: 10 Word.word)) ((slice frac (( 29 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + (Word.ucast + ((concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value (((( 32 :: int)::ii) - (( 23 :: int)::ii))) )) :: 9 Word.word)) + :: 10 Word.word)) ((slice frac (( 29 :: int)::ii) (( 22 :: int)::ii) :: 22 Word.word)) + :: 32 Word.word)) :: ( 'M::len)Word.word) else - (concat_vec - ((concat_vec sign - ((Ones__0 ((make_the_value ((p00 - (( 10 :: int)::ii))) )) :: 6 Word.word)) - :: 7 Word.word)) ((slice frac (( 42 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + (Word.ucast + ((concat_vec + ((concat_vec sign + ((Ones__0 ((make_the_value ((p00 - (( 10 :: int)::ii))) )) :: 6 Word.word)) + :: 7 Word.word)) ((slice frac (( 42 :: int)::ii) (( 9 :: int)::ii) :: 9 Word.word)) + :: 16 Word.word)) :: ( 'M::len)Word.word)) in return result))))))))" @@ -5287,19 +5294,19 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (roundkey :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (modk0 :: 64 bits) . (hex_slice (''0xC0AC29B7C97C50DD'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (Alpha :: 64 bits) . - read_reg RC_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + read_reg RC_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . (hex_slice (''0x0'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (write_reg RC_ref ((update_list_dec w__0 (( 0 :: int)::ii) w__1 :: ( 64 Word.word) list)) \<then> - read_reg RC_ref) \<bind> (\<lambda> (w__2 :: ( 64 Word.word) list) . + read_reg RC_ref) \<bind> (\<lambda> (w__2 :: ( 64 bits) list) . (hex_slice (''0x13198A2E03707344'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . (write_reg RC_ref ((update_list_dec w__2 (( 1 :: int)::ii) w__3 :: ( 64 Word.word) list)) \<then> - read_reg RC_ref) \<bind> (\<lambda> (w__4 :: ( 64 Word.word) list) . + read_reg RC_ref) \<bind> (\<lambda> (w__4 :: ( 64 bits) list) . (hex_slice (''0xA493822299F31D0'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) . (write_reg RC_ref ((update_list_dec w__4 (( 2 :: int)::ii) w__5 :: ( 64 Word.word) list)) \<then> - read_reg RC_ref) \<bind> (\<lambda> (w__6 :: ( 64 Word.word) list) . + read_reg RC_ref) \<bind> (\<lambda> (w__6 :: ( 64 bits) list) . (hex_slice (''0x82EFA98EC4E6C89'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . (write_reg RC_ref ((update_list_dec w__6 (( 3 :: int)::ii) w__7 :: ( 64 Word.word) list)) \<then> - read_reg RC_ref) \<bind> (\<lambda> (w__8 :: ( 64 Word.word) list) . + read_reg RC_ref) \<bind> (\<lambda> (w__8 :: ( 64 bits) list) . (hex_slice (''0x452821E638D01377'') (( 64 :: int)::ii) (( 0 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__9 :: 64 Word.word) . write_reg RC_ref ((update_list_dec w__8 (( 4 :: int)::ii) w__9 :: ( 64 Word.word) list)) \<then> ((let modk0 = @@ -5320,51 +5327,51 @@ definition ComputePAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow read_reg RC_ref \<bind> (\<lambda> (w__10 :: ( 64 bits) list) . (let workingval = ((xor_vec workingval ((access_list_dec w__10 i :: 64 Word.word)) :: 64 Word.word)) in (if ((i > (( 0 :: int)::ii))) then - (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 bits) . + (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__11 :: 64 Word.word) . (let workingval = w__11 in (PACMult workingval :: ( 64 Word.word) M))) else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . - (PACSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 bits) . + (PACSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__13 :: 64 Word.word) . (let workingval = w__13 in - (TweakShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 - bits) . + (TweakShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: + 64 Word.word) . (let (runningmod :: 64 bits) = w__14 in return (roundkey, runningmod, workingval))))))))))))) \<bind> (\<lambda> varstup . (let ((roundkey :: 64 bits), (runningmod :: 64 bits), (workingval :: 64 bits)) = varstup in (let roundkey = ((xor_vec modk0 runningmod :: 64 Word.word)) in (let workingval = ((xor_vec workingval roundkey :: 64 Word.word)) in - (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 bits) . + (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 Word.word) . (let workingval = w__15 in - (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: 64 bits) . + (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__16 :: 64 Word.word) . (let workingval = w__16 in - (PACSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 bits) . + (PACSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 Word.word) . (let workingval = w__17 in - (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + (PACCellShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 Word.word) . (let workingval = w__18 in - (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 Word.word) . (let workingval = w__19 in (let workingval = ((xor_vec key1 workingval :: 64 Word.word)) in - (PACCellInvShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__20 :: 64 bits) . + (PACCellInvShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__20 :: 64 Word.word) . (let workingval = w__20 in - (PACInvSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__21 :: 64 bits) . + (PACInvSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__21 :: 64 Word.word) . (let workingval = w__21 in - (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__22 :: 64 bits) . + (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__22 :: 64 Word.word) . (let workingval = w__22 in - (PACCellInvShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__23 :: 64 bits) . + (PACCellInvShuffle workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__23 :: 64 Word.word) . (let workingval = w__23 in (let workingval = ((xor_vec workingval key0 :: 64 Word.word)) in (let workingval = ((xor_vec workingval runningmod :: 64 Word.word)) in (foreachM (index_list (( 0 :: int)::ii) (( 4 :: int)::ii) (( 1 :: int)::ii)) (roundkey, runningmod, workingval) (\<lambda> i varstup . (let (roundkey, runningmod, workingval) = varstup in - (PACInvSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 bits) . + (PACInvSub workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 Word.word) . (let workingval = w__24 in (if ((i < (( 4 :: int)::ii))) then - (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__25 :: 64 bits) . + (PACMult workingval :: ( 64 Word.word) M) \<bind> (\<lambda> (w__25 :: 64 Word.word) . (let workingval = w__25 in (PACCellInvShuffle workingval :: ( 64 Word.word) M))) else return workingval) \<bind> (\<lambda> (workingval :: 64 bits) . - (TweakInvShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 - bits) . + (TweakInvShuffle ((slice runningmod (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: + 64 Word.word) . (let runningmod = w__27 in (let roundkey = ((xor_vec key1 runningmod :: 64 Word.word)) in read_reg RC_ref \<bind> (\<lambda> (w__28 :: ( 64 bits) list) . @@ -5389,8 +5396,7 @@ definition Align__0 :: " int \<Rightarrow> int \<Rightarrow> int " where definition Align__1 :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>('N::len)Word.word " where " Align__1 x y = ( - (GetSlice_int ((make_the_value ((int (size x))) :: ( 'N::len)itself)) ((Align__0 ((Word.uint x)) y)) (( 0 :: int)::ii) - :: ( 'N::len)Word.word))" + (GetSlice_int ((make_the_value ((int (size x))) )) ((Align__0 ((Word.uint x)) y)) (( 0 :: int)::ii) :: ( 'N::len)Word.word))" (*val aset__Mem : forall 'p8_times_size_ . Size 'p8_times_size_ => AddressDescriptor -> integer -> AccessDescriptor -> mword 'p8_times_size_ -> M unit*) @@ -5403,11 +5409,11 @@ definition aset__Mem :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc (hex_slice (''0x13000000'') (( 52 :: int)::ii) (( 0 :: int)::ii) :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 :: 52 Word.word) . if (((address = w__0))) then if (((((Word.uint value_name)) = (( 4 :: int)::ii)))) then - (let (_ :: unit) = (prerr ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (char_of_nat 10)])) in + (let (_ :: unit) = (prerr ([(CHR ''P''), (CHR ''r''), (CHR ''o''), (CHR ''g''), (CHR ''r''), (CHR ''a''), (CHR ''m''), (CHR '' ''), (CHR ''e''), (CHR ''x''), (CHR ''i''), (CHR ''t''), (CHR ''e''), (CHR ''d''), (CHR '' ''), (CHR ''b''), (CHR ''y''), (CHR '' ''), (CHR ''w''), (CHR ''r''), (CHR ''i''), (CHR ''t''), (CHR ''i''), (CHR ''n''), (CHR ''g''), (CHR '' ''), (CHR ''^''), (CHR ''D''), (CHR '' ''), (CHR ''t''), (CHR ''o''), (CHR '' ''), (CHR ''T''), (CHR ''U''), (CHR ''B''), (CHR ''E''), (CHR 0x27)])) in exit0 () ) else return ((putchar ((Word.uint ((slice value_name (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)))))) else - (read_reg Memory_ref :: ( 52 Word.word) M) \<bind> (\<lambda> (w__1 :: 52 Word.word) . + (read_reg Memory_ref :: ( 52 Word.word) M) \<bind> (\<lambda> (w__1 :: 52 bits) . WriteRAM ((make_the_value (( 52 :: int)::ii) :: 52 itself)) size1 w__1 address value_name)))))" @@ -5418,7 +5424,7 @@ definition aget__Mem :: " AddressDescriptor \<Rightarrow> int \<Rightarrow> Acc assert_exp ((((((size1 = (( 1 :: int)::ii)))) \<or> ((((((size1 = (( 2 :: int)::ii)))) \<or> ((((((size1 = (( 4 :: int)::ii)))) \<or> ((((((size1 = (( 8 :: int)::ii)))) \<or> (((size1 = (( 16 :: int)::ii)))))))))))))))) (''((size == 1) || ((size == 2) || ((size == 4) || ((size == 8) || (size == 16)))))'') \<then> ((let (address :: 52 bits) = ((FullAddress_physicaladdress (AddressDescriptor_paddress desc))) in (assert_exp (((address = ((Align__1 address size1 :: 52 Word.word))))) (''(address == Align(address, size))'') \<then> - (read_reg Memory_ref :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 :: 52 Word.word) . + (read_reg Memory_ref :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__0 :: 52 bits) . (ReadRAM ((make_the_value (( 52 :: int)::ii) :: 52 itself)) size1 w__0 address :: (( 'p8_times_size_::len)Word.word) M)))))" @@ -5430,7 +5436,7 @@ definition aset_X :: " int \<Rightarrow>('width::len)Word.word \<Rightarrow>((r (assert_exp (((((n \<ge> (( 0 :: int)::ii))) \<and> ((n \<le> (( 31 :: int)::ii)))))) (''((n >= 0) && (n <= 31))'') \<then> assert_exp ((((((((int (size value_name))) = (( 32 :: int)::ii)))) \<or> (((((int (size value_name))) = (( 64 :: int)::ii))))))) (''((width == 32) || (width == 64))'')) \<then> (if (((n \<noteq> (( 31 :: int)::ii)))) then - read_reg R_ref \<bind> (\<lambda> (w__0 :: ( 64 Word.word) list) . + read_reg R_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . (ZeroExtend__0 value_name ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . write_reg R_ref ((update_list_dec w__0 n w__1 :: ( 64 Word.word) list)))) @@ -5478,7 +5484,7 @@ definition AArch64_ResetGeneralRegisters :: " unit \<Rightarrow>((register_valu " AArch64_ResetGeneralRegisters _ = ( (foreachM (index_list (( 0 :: int)::ii) (( 30 :: int)::ii) (( 1 :: int)::ii)) () (\<lambda> i unit_var . - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . aset_X i w__0))))" + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . aset_X i w__0))))" (*val aset_ELR__0 : mword ty2 -> mword ty64 -> M unit*) @@ -5511,7 +5517,7 @@ definition aget_X :: " int \<Rightarrow> int \<Rightarrow>((register_value),((' (if (((n \<noteq> (( 31 :: int)::ii)))) then read_reg R_ref \<bind> (\<lambda> (w__0 :: ( 64 bits) list) . return ((slice ((access_list_dec w__0 n :: 64 Word.word)) (( 0 :: int)::ii) width__tv :: ( 'width::len)Word.word))) - else return ((Zeros__0 ((make_the_value width__tv :: ( 'width::len)itself)) :: ( 'width::len)Word.word))))" + else return ((Zeros__0 ((make_the_value width__tv )) :: ( 'width::len)Word.word))))" (*val aarch64_system_sysops : bool -> ii -> ii -> ii -> ii -> ii -> ii -> M unit*) @@ -6783,7 +6789,7 @@ definition integer_arithmetic_addsub_carry_decode :: "(1)Word.word \<Rightarrow definition ExtendReg :: " int \<Rightarrow> int \<Rightarrow> ExtendType \<Rightarrow> int \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " ExtendReg (N__tv :: int) reg typ1 shift = ( (assert_exp (((((shift \<ge> (( 0 :: int)::ii))) \<and> ((shift \<le> (( 4 :: int)::ii)))))) (''((shift >= 0) && (shift <= 4))'') \<then> - (aget_X N__tv reg :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (val_name :: 'N bits) . + (aget_X N__tv reg :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> val_name . undefined_bool () \<bind> (\<lambda> (unsigned :: bool) . undefined_int () \<bind> (\<lambda> (len :: ii) . (let (len :: ii) = @@ -6852,7 +6858,7 @@ definition ROR_C :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((regist ((let (m :: ii) = (shift mod ((int (size x)))) in (LSR x m :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (LSL x ((((int (size x))) - ((ex_int m)))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'N::len)Word.word) . - (let (result :: 'N bits) = ((or_vec w__0 w__1 :: ( 'N::len)Word.word)) in + (let result = ((or_vec w__0 w__1 :: ( 'N::len)Word.word)) in (let (carry_out :: 1 bits) = ((vec_of_bits [access_vec_dec result ((((int (size result))) - (( 1 :: int)::ii)))] :: 1 Word.word)) in return (result, carry_out))))))))" @@ -6864,11 +6870,11 @@ definition ROR :: "('N::len)Word.word \<Rightarrow> int \<Rightarrow>((register " ROR x shift = ( (assert_exp ((shift \<ge> (( 0 :: int)::ii))) (''(shift >= 0)'') \<then> (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (anon10 :: 1 bits) . - (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size x))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if (((shift = (( 0 :: int)::ii)))) then return x else - (ROR_C x shift :: ((( 'N::len)Word.word * 1 Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in - (let (result :: 'N bits) = tup__0 in + (ROR_C x shift ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (let result = tup__0 in (let (anon10 :: 1 bits) = tup__1 in return result)))))))" @@ -6882,17 +6888,17 @@ definition aarch64_integer_bitfield :: " int \<Rightarrow> int \<Rightarrow> in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> (if inzero then return ((Zeros__1 datasize () :: ( 'datasize::len)Word.word)) - else (aget_X datasize d :: (( 'datasize::len)Word.word) M))) \<bind> (\<lambda> (dst :: 'datasize bits) . - (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (src :: 'datasize bits) . + else (aget_X datasize d :: (( 'datasize::len)Word.word) M))) \<bind> (\<lambda> dst . + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> src . (ROR src R1 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'datasize::len)Word.word) . - (let (bot :: 'datasize bits) = + (let bot = ((or_vec ((and_vec dst ((not_vec wmask :: ( 'datasize::len)Word.word)) :: ( 'datasize::len)Word.word)) ((and_vec w__1 wmask :: ( 'datasize::len)Word.word)) :: ( 'datasize::len)Word.word)) in (if extend1 then (Replicate ((int (size bot))) (vec_of_bits [access_vec_dec src S] :: 1 Word.word) :: (( 'datasize::len)Word.word) M) - else return dst) \<bind> (\<lambda> (top1 :: 'datasize bits) . + else return dst) \<bind> (\<lambda> top1 . aset_X d ((or_vec ((and_vec top1 ((not_vec tmask :: ( 'datasize::len)Word.word)) :: ( 'datasize::len)Word.word)) ((and_vec bot tmask :: ( 'datasize::len)Word.word)) @@ -6903,7 +6909,7 @@ definition aarch64_integer_bitfield :: " int \<Rightarrow> int \<Rightarrow> in definition ShiftReg :: " int \<Rightarrow> int \<Rightarrow> ShiftType \<Rightarrow> int \<Rightarrow>((register_value),(('N::len)Word.word),(exception))monad " where " ShiftReg (N__tv :: int) reg typ1 amount = ( - (aget_X N__tv reg :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (aget_X N__tv reg :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . (case typ1 of ShiftType_LSL => (LSL result amount :: (( 'N::len)Word.word) M) | ShiftType_LSR => (LSR result amount :: (( 'N::len)Word.word) M) @@ -6922,8 +6928,8 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (result :: 8 bits) . (aget_X (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . - (ShiftReg (( 8 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 8 :: int)::ii))) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 - bits) . + (ShiftReg (( 8 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 8 :: int)::ii))) :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: + 8 Word.word) . (let result = w__0 in aset_X d result))))) else if (((l__173 = (( 16 :: int)::ii)))) then @@ -6932,8 +6938,8 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . (aget_X (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . - (ShiftReg (( 16 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 16 :: int)::ii))) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__1 :: 16 - bits) . + (ShiftReg (( 16 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 16 :: int)::ii))) :: ( 16 Word.word) M) \<bind> (\<lambda> (w__1 :: + 16 Word.word) . (let result = w__1 in aset_X d result))))) else if (((l__173 = (( 32 :: int)::ii)))) then @@ -6942,8 +6948,8 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . (aget_X (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . - (ShiftReg (( 32 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 32 :: int)::ii))) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 - bits) . + (ShiftReg (( 32 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 32 :: int)::ii))) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: + 32 Word.word) . (let result = w__2 in aset_X d result))))) else if (((l__173 = (( 64 :: int)::ii)))) then @@ -6952,8 +6958,8 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . - (ShiftReg (( 64 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 64 :: int)::ii))) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 - bits) . + (ShiftReg (( 64 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 64 :: int)::ii))) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: + 64 Word.word) . (let result = w__3 in aset_X d result))))) else if (((l__173 = (( 128 :: int)::ii)))) then @@ -6962,8 +6968,8 @@ definition aarch64_integer_shift_variable :: " int \<Rightarrow> int \<Rightarr assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \<bind> (\<lambda> (result :: 128 bits) . (aget_X (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . - (ShiftReg (( 128 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 128 :: int)::ii))) :: ( 128 Word.word) M) \<bind> (\<lambda> (w__4 :: 128 - bits) . + (ShiftReg (( 128 :: int)::ii) n shift_type ((((Word.uint operand2)) mod (( 128 :: int)::ii))) :: ( 128 Word.word) M) \<bind> (\<lambda> (w__4 :: + 128 Word.word) . (let result = w__4 in aset_X d result))))) else @@ -7529,10 +7535,10 @@ definition aarch64_integer_logical_immediate :: " int \<Rightarrow>('datasize:: (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (result :: 'datasize bits) . - (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (operand1 :: 'datasize bits) . - (let (operand2 :: 'datasize bits) = imm in - (let (result :: 'datasize bits) = + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> result . + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> operand1 . + (let operand2 = imm in + (let result = ((case op1 of LogicalOp_AND => (and_vec operand1 operand2 :: ( 'datasize::len)Word.word) | LogicalOp_ORR => (or_vec operand1 operand2 :: ( 'datasize::len)Word.word) @@ -7572,21 +7578,21 @@ definition aarch64_integer_arithmetic_addsub_immediate :: " int \<Rightarrow>(' (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (result :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> result . (if (((n = (( 31 :: int)::ii)))) then (aget_SP datasize () :: (( 'datasize::len)Word.word) M) - else (aget_X datasize n :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (operand1 :: 'datasize bits) . - (let (operand2 :: 'datasize bits) = imm in + else (aget_X datasize n :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> operand1 . + (let operand2 = imm in (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (nzcv :: 4 bits) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (carry_in :: 1 bits) . - (let ((carry_in :: 1 bits), (operand2 :: 'datasize bits)) = + (let ((carry_in :: 1 bits), operand2) = (if sub_op then - (let (operand2 :: 'datasize bits) = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in + (let operand2 = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in (carry_in, operand2))) else (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in (carry_in, operand2))) in - (let (tup__0, tup__1) = ((AddWithCarry operand1 operand2 carry_in :: (( 'datasize::len)Word.word * 4 Word.word))) in + (let (tup__0, tup__1) = (AddWithCarry operand1 operand2 carry_in ) in (let result = tup__0 in (let nzcv = tup__1 in (if setflags then @@ -8044,7 +8050,7 @@ definition Auth :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(128) :: 64 Word.word)) in (ComputePAC original_ptr modifier ((subrange_vec_dec K (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((subrange_vec_dec K (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (PAC :: 64 bits) = w__1 in (let (result :: 64 bits) = (if tbi then @@ -8213,12 +8219,12 @@ definition FPProcessException :: " FPExc \<Rightarrow>(32)Word.word \<Rightarro else UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . if w__0 then - (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . write_reg FPSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else - (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . write_reg FPSR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 cumul (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))))))))" @@ -8270,16 +8276,16 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> False))) \<or> (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> True)))))) \<and> ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . ((if w__0 then - (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . write_reg FPSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__1 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else - (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . write_reg FPSR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> - (FPZero (( 16 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . + (FPZero (( 16 :: int)::ii) sign :: ( 16 Word.word) M)) \<bind> (\<lambda> (w__3 :: 16 Word.word) . return ((Word.ucast w__3 :: ( 'N::len)Word.word)))) else (let (biased_exp :: ii) = @@ -8433,16 +8439,16 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> True))) \<or> (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> False)))))) \<and> ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then UsingAArch32 () \<bind> (\<lambda> (w__8 :: bool) . ((if w__8 then - (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . + (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . write_reg FPSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__9 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else - (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . + (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . write_reg FPSR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__10 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> - (FPZero (( 32 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__11 :: ( 'N::len)Word.word) . + (FPZero (( 32 :: int)::ii) sign :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__11 :: 32 Word.word) . return ((Word.ucast w__11 :: ( 'N::len)Word.word)))) else (let (biased_exp :: ii) = @@ -8573,16 +8579,16 @@ definition FPRoundBase :: " int \<Rightarrow> real \<Rightarrow>(32)Word.word \ if (((((((((((((vec_of_bits [access_vec_dec fpcr (( 24 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> True))) \<or> (((((((vec_of_bits [access_vec_dec fpcr (( 19 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) \<and> False)))))) \<and> ((((ex_int exponent)) < ((ex_int minimum_exp))))))) then UsingAArch32 () \<bind> (\<lambda> (w__16 :: bool) . ((if w__16 then - (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 Word.word) . + (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__17 :: 32 bits) . write_reg FPSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__17 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word))) else - (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . + (read_reg FPSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . write_reg FPSR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 3 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)))) \<then> - (FPZero (( 64 :: int)::ii) sign :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'N::len)Word.word) . + (FPZero (( 64 :: int)::ii) sign :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 :: 64 Word.word) . return ((Word.ucast w__19 :: ( 'N::len)Word.word)))) else (let (biased_exp :: ii) = @@ -8706,7 +8712,7 @@ definition FixedToFP :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow> int " FixedToFP (N__tv :: int) op1 fbits unsigned fpcr rounding = ( ((assert_exp ((((((N__tv = (( 16 :: int)::ii)))) \<or> ((((((N__tv = (( 32 :: int)::ii)))) \<or> (((N__tv = (( 64 :: int)::ii)))))))))) ('''') \<then> assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) ('''')) \<then> - (undefined_bitvector N__tv :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector N__tv :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> result . (assert_exp ((fbits \<ge> (( 0 :: int)::ii))) ('''') \<then> assert_exp (((rounding \<noteq> FPRounding_ODD))) ('''')) \<then> ((let (int_operand :: ii) = (asl_Int op1 unsigned) in @@ -8735,12 +8741,12 @@ definition FPProcessNaN :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro else (let (op1 :: 64 Word.word) = ((Word.ucast op1 :: 64 Word.word)) in (( 51 :: int)::ii))) in - (let (result :: 'N bits) = op1 in + (let result = op1 in (if (((typ1 = FPType_SNaN))) then (let result = ((set_slice ((int (size op1))) (( 1 :: int)::ii) result topfrac (vec_of_bits [B1] :: 1 Word.word) :: ( 'N::len)Word.word)) in FPProcessException FPExc_InvalidOp fpcr \<then> return result) - else return result) \<bind> (\<lambda> (result :: 'N bits) . + else return result) \<bind> (\<lambda> result . if ((((vec_of_bits [access_vec_dec fpcr (( 25 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) then (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) else return result))))))" @@ -8751,41 +8757,41 @@ definition FPProcessNaN :: " FPType \<Rightarrow>('N::len)Word.word \<Rightarro definition FPProcessNaNs3 :: " FPType \<Rightarrow> FPType \<Rightarrow> FPType \<Rightarrow>('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(bool*('N::len)Word.word),(exception))monad " where " FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr = ( (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . if (((type1 = FPType_SNaN))) then (let done1 = True in - (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . - (let (result :: 'N bits) = w__0 in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . + (let result = w__0 in return (done1, result)))) else if (((type2 = FPType_SNaN))) then (let done1 = True in - (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: 'N bits) . - (let (result :: 'N bits) = w__1 in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'N::len)Word.word) . + (let result = w__1 in return (done1, result)))) else if (((type3 = FPType_SNaN))) then (let done1 = True in - (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'N bits) . - (let (result :: 'N bits) = w__2 in + (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'N::len)Word.word) . + (let result = w__2 in return (done1, result)))) else if (((type1 = FPType_QNaN))) then (let done1 = True in - (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'N bits) . - (let (result :: 'N bits) = w__3 in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . + (let result = w__3 in return (done1, result)))) else if (((type2 = FPType_QNaN))) then (let done1 = True in - (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'N bits) . - (let (result :: 'N bits) = w__4 in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__4 :: ( 'N::len)Word.word) . + (let result = w__4 in return (done1, result)))) else if (((type3 = FPType_QNaN))) then (let done1 = True in - (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__5 :: 'N bits) . - (let (result :: 'N bits) = w__5 in + (FPProcessNaN type3 op3 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'N::len)Word.word) . + (let result = w__5 in return (done1, result)))) else (let (done1 :: bool) = False in - (let (result :: 'N bits) = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in + (let result = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in return (done1, result))))))" @@ -8794,31 +8800,31 @@ definition FPProcessNaNs3 :: " FPType \<Rightarrow> FPType \<Rightarrow> FPType definition FPProcessNaNs :: " FPType \<Rightarrow> FPType \<Rightarrow>('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarrow>((register_value),(bool*('N::len)Word.word),(exception))monad " where " FPProcessNaNs type1 type2 op1 op2 fpcr = ( (assert_exp ((((((((int (size op1))) = (( 16 :: int)::ii)))) \<or> ((((((((int (size op1))) = (( 32 :: int)::ii)))) \<or> (((((int (size op1))) = (( 64 :: int)::ii)))))))))) (''((N == 16) || ((N == 32) || (N == 64)))'') \<then> - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . if (((type1 = FPType_SNaN))) then (let done1 = True in - (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . - (let (result :: 'N bits) = w__0 in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . + (let result = w__0 in return (done1, result)))) else if (((type2 = FPType_SNaN))) then (let done1 = True in - (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: 'N bits) . - (let (result :: 'N bits) = w__1 in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'N::len)Word.word) . + (let result = w__1 in return (done1, result)))) else if (((type1 = FPType_QNaN))) then (let done1 = True in - (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'N bits) . - (let (result :: 'N bits) = w__2 in + (FPProcessNaN type1 op1 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'N::len)Word.word) . + (let result = w__2 in return (done1, result)))) else if (((type2 = FPType_QNaN))) then (let done1 = True in - (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'N bits) . - (let (result :: 'N bits) = w__3 in + (FPProcessNaN type2 op2 fpcr :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . + (let result = w__3 in return (done1, result)))) else (let (done1 :: bool) = False in - (let (result :: 'N bits) = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in + (let result = ((Zeros__1 ((int (size op1))) () :: ( 'N::len)Word.word)) in return (done1, result))))))" @@ -8946,43 +8952,43 @@ definition HaveAArch32EL :: "(2)Word.word \<Rightarrow> bool " where definition AArch64_ResetSpecialRegisters :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " AArch64_ResetSpecialRegisters _ = ( - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (write_reg SP_EL0_ref w__0 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (write_reg SP_EL1_ref w__1 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . (write_reg SPSR_EL1_ref w__2 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) . ((((write_reg ELR_EL1_ref w__3 \<then> (if ((HaveEL EL2)) then - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . (write_reg SP_EL2_ref w__4 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 Word.word) . (write_reg SPSR_EL2_ref w__5 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 Word.word) . write_reg ELR_EL2_ref w__6))) else return () )) \<then> (if ((HaveEL EL3)) then - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . (write_reg SP_EL3_ref w__7 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__8 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__8 :: 32 Word.word) . (write_reg SPSR_EL3_ref w__8 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__9 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__9 :: 64 Word.word) . write_reg ELR_EL3_ref w__9))) else return () )) \<then> (if ((HaveAArch32EL EL1)) then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (write_reg SPSR_fiq_ref w__10 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__11 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__11 :: 32 Word.word) . (write_reg SPSR_irq_ref w__11 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__12 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__12 :: 32 Word.word) . (write_reg SPSR_abt_ref w__12 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__13 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__13 :: 32 Word.word) . write_reg SPSR_und_ref w__13)))) else return () )) \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) . (write_reg DLR_EL0_ref w__14 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__15 :: 32 Word.word) . write_reg DSPSR_EL0_ref w__15)))))))" @@ -9013,6 +9019,7 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (exp16 :: 5 bits) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (sign :: 1 bits) . (if (((((int (size fpval))) = (( 16 :: int)::ii)))) then + (let (fpval :: 16 Word.word) = ((Word.ucast fpval :: 16 Word.word)) in (let (sign :: 1 bits) = ((vec_of_bits [access_vec_dec fpval (( 15 :: int)::ii)] :: 1 Word.word)) in (let (exp16 :: 5 bits) = ((slice fpval (( 10 :: int)::ii) (( 5 :: int)::ii) :: 5 Word.word)) in (let (frac16 :: 10 bits) = ((slice fpval (( 0 :: int)::ii) (( 10 :: int)::ii) :: 10 Word.word)) in @@ -9057,8 +9064,9 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 10 :: int)::ii)))))))))) in (typ1, value_name)))) in (typ1, value_name))) in - return (sign, typ1, value_name))))) + return (sign, typ1, value_name)))))) else if (((((int (size fpval))) = (( 32 :: int)::ii)))) then + (let (fpval :: 32 Word.word) = ((Word.ucast fpval :: 32 Word.word)) in (let sign = ((vec_of_bits [access_vec_dec fpval (( 31 :: int)::ii)] :: 1 Word.word)) in (let exp32 = ((slice fpval (( 23 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) in (let frac32 = ((slice fpval (( 0 :: int)::ii) (( 23 :: int)::ii) :: 23 Word.word)) in @@ -9102,7 +9110,7 @@ definition FPUnpackBase :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rig ((realPowInteger (realFromFrac(( 20 :: int))(( 10 :: int))) ((- (( 23 :: int)::ii)))))))))) in (typ1, value_name)))) in return (typ1, value_name))) \<bind> (\<lambda> varstup . (let ((typ1 :: FPType), (value_name :: real)) = varstup in - return (sign, typ1, value_name)))))) + return (sign, typ1, value_name))))))) else (let sign = ((vec_of_bits [access_vec_dec fpval (( 63 :: int)::ii)] :: 1 Word.word)) in (let exp64 = ((slice fpval (( 52 :: int)::ii) (( 11 :: int)::ii) :: 11 Word.word)) in @@ -9376,7 +9384,7 @@ definition FPToFixedJS :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>(3 read_reg PSTATE_ref) \<bind> (\<lambda> (w__3 :: ProcState) . write_reg PSTATE_ref (w__3 (| ProcState_V := tup__3 |)))))))) else - (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg FPSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . write_reg FPSCR_ref ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 28 :: int)::ii) @@ -9385,7 +9393,7 @@ definition FPToFixedJS :: " int \<Rightarrow>('M::len)Word.word \<Rightarrow>(3 :: 4 Word.word)) :: 32 Word.word)))) \<then> return ((Word.ucast - ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: ( 'N::len)itself)) result (( 0 :: int)::ii) :: ( 'N::len)Word.word)) + ((GetSlice_int ((make_the_value (( 32 :: int)::ii) :: 32 itself)) result (( 0 :: int)::ii) :: 32 Word.word)) :: ( 'N::len)Word.word))))))))))))))))))))))" @@ -9425,9 +9433,8 @@ definition FPToFixed :: " int \<Rightarrow>('N::len)Word.word \<Rightarrow> int )) in (let (int_result :: ii) = (if round_up then ((ex_int int_result)) + (( 1 :: int)::ii) else int_result) in undefined_bool () \<bind> (\<lambda> (overflow :: bool) . - (undefined_bitvector M__tv :: (( 'M::len)Word.word) M) \<bind> (\<lambda> (result :: 'M bits) . - (SatQ int_result ((make_the_value ((int (size result))) :: ( 'M::len)itself)) unsigned - :: ((( 'M::len)Word.word * bool)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (undefined_bitvector M__tv :: (( 'M::len)Word.word) M) \<bind> (\<lambda> result . + (SatQ int_result ((make_the_value ((int (size result))) )) unsigned ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let result = tup__0 in (let overflow = tup__1 in (if overflow then FPProcessException FPExc_InvalidOp fpcr @@ -9448,7 +9455,7 @@ definition FPSqrt :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarro (let typ1 = tup__0 in (let sign = tup__1 in (let value_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if ((((((typ1 = FPType_SNaN))) \<or> (((typ1 = FPType_QNaN)))))) then (FPProcessNaN typ1 op1 fpcr :: (( 'N::len)Word.word) M) else if (((typ1 = FPType_Zero))) then (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M) @@ -9456,7 +9463,7 @@ definition FPSqrt :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Rightarro then (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) else if (((sign = (vec_of_bits [B1] :: 1 Word.word)))) then - (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'N bits) . + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'N::len)Word.word) . (let result = w__3 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else (FPRound__1 ((int (size op1))) ((sqrt value_name)) fpcr :: (( 'N::len)Word.word) M)))))))))))" @@ -9479,7 +9486,7 @@ definition FPRoundInt :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right undefined_bool () \<bind> (\<lambda> (round_up :: bool) . undefined_real () \<bind> (\<lambda> (error :: real) . undefined_int () \<bind> (\<lambda> (int_result :: ii) . - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . if ((((((typ1 = FPType_SNaN))) \<or> (((typ1 = FPType_QNaN)))))) then (FPProcessNaN typ1 op1 fpcr :: (( 'N::len)Word.word) M) else if (((typ1 = FPType_Infinity))) then (FPInfinity ((int (size op1))) sign :: (( 'N::len)Word.word) M) @@ -9504,8 +9511,7 @@ definition FPRoundInt :: "('N::len)Word.word \<Rightarrow>(32)Word.word \<Right else int_result) in (let real_result = ((real_of_int int_result)) in (if (((real_result = (realFromFrac(( 0 :: int))(( 10 :: int)))))) then (FPZero ((int (size op1))) sign :: (( 'N::len)Word.word) M) - else (FPRound__0 ((int (size op1))) real_result fpcr FPRounding_ZERO :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> (result :: 'N - bits) . + else (FPRound__0 ((int (size op1))) real_result fpcr FPRounding_ZERO :: (( 'N::len)Word.word) M)) \<bind> (\<lambda> result . (if ((((((error \<noteq> (realFromFrac(( 0 :: int))(( 10 :: int)))))) \<and> exact))) then FPProcessException FPExc_Inexact fpcr else return () ) \<then> @@ -9566,9 +9572,9 @@ definition FPSub :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (result_sign :: 1 bits) . @@ -9583,7 +9589,7 @@ definition FPSub :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let zero1 = (type1 = FPType_Zero) in (let zero2 = (type2 = FPType_Zero) in if ((((((inf1 \<and> inf2))) \<and> (((sign1 = sign2)))))) then - (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (let result = w__0 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else if ((((((inf1 \<and> (((sign1 = (vec_of_bits [B0] :: 1 Word.word))))))) \<or> (((inf2 \<and> (((sign2 = (vec_of_bits [B1] :: 1 Word.word)))))))))) then @@ -9635,16 +9641,16 @@ definition FPMulAdd :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Ri (let (zero1 :: bool) = (type1 = FPType_Zero) in (let (inf2 :: bool) = (type2 = FPType_Infinity) in (let (zero2 :: bool) = (type2 = FPType_Zero) in - (undefined_bitvector ((int (size addend))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size addend))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs3 typeA type1 type2 addend op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs3 typeA type1 type2 addend op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in (if ((((((typeA = FPType_QNaN))) \<and> ((((((inf1 \<and> zero2))) \<or> (((zero1 \<and> inf2))))))))) then - (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . + (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (let result = w__0 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) - else return result) \<bind> (\<lambda> (result :: 'N bits) . + else return result) \<bind> (\<lambda> result . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (result_sign :: 1 bits) . undefined_real () \<bind> (\<lambda> (result_value :: real) . undefined_bool () \<bind> (\<lambda> (zeroP :: bool) . @@ -9659,7 +9665,7 @@ definition FPMulAdd :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Ri (let infP = (inf1 \<or> inf2) in (let zeroP = (zero1 \<or> zero2) in if (((((((((inf1 \<and> zero2))) \<or> (((zero1 \<and> inf2)))))) \<or> ((((((infA \<and> infP))) \<and> (((signA \<noteq> signP))))))))) then - (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: 'N bits) . + (FPDefaultNaN ((int (size addend))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'N::len)Word.word) . (let result = w__1 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else if ((((((infA \<and> (((signA = (vec_of_bits [B0] :: 1 Word.word))))))) \<or> (((infP \<and> (((signP = (vec_of_bits [B0] :: 1 Word.word)))))))))) then @@ -9698,9 +9704,9 @@ definition FPMul :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in undefined_bool () \<bind> (\<lambda> (zero2 :: bool) . @@ -9713,7 +9719,7 @@ definition FPMul :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let zero1 = (type1 = FPType_Zero) in (let zero2 = (type2 = FPType_Zero) in if ((((((inf1 \<and> zero2))) \<or> (((zero1 \<and> inf2)))))) then - (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (let result = w__0 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else if (((inf1 \<or> inf2))) then @@ -9743,9 +9749,9 @@ definition FPMin :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in undefined_real () \<bind> (\<lambda> (value_name :: real) . @@ -9826,9 +9832,9 @@ definition FPMax :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in undefined_real () \<bind> (\<lambda> (value_name :: real) . @@ -9909,9 +9915,9 @@ definition FPDiv :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in undefined_bool () \<bind> (\<lambda> (zero2 :: bool) . @@ -9924,12 +9930,12 @@ definition FPDiv :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let zero1 = (type1 = FPType_Zero) in (let zero2 = (type2 = FPType_Zero) in if ((((((inf1 \<and> inf2))) \<or> (((zero1 \<and> zero2)))))) then - (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (let result = w__0 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else if (((inf1 \<or> zero2))) then - (FPInfinity ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: 'N - bits) . + (FPInfinity ((int (size op1))) ((xor_vec sign1 sign2 :: 1 Word.word)) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__1 :: + ( 'N::len)Word.word) . (let result = w__1 in (if ((\<not> inf1)) then FPProcessException FPExc_DivideByZero fpcr else return () ) \<then> @@ -9960,9 +9966,9 @@ definition FPAdd :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let type2 = tup__0 in (let sign2 = tup__1 in (let value2_name = tup__2 in - (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (result :: 'N bits) . + (undefined_bitvector ((int (size op1))) :: (( 'N::len)Word.word) M) \<bind> (\<lambda> result . undefined_bool () \<bind> (\<lambda> (done1 :: bool) . - (FPProcessNaNs type1 type2 op1 op2 fpcr :: ((bool * ( 'N::len)Word.word)) M) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in + (FPProcessNaNs type1 type2 op1 op2 fpcr ) \<bind> (\<lambda> varstup . (let (tup__0, tup__1) = varstup in (let done1 = tup__0 in (let result = tup__1 in (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (result_sign :: 1 bits) . @@ -9977,7 +9983,7 @@ definition FPAdd :: "('N::len)Word.word \<Rightarrow>('N::len)Word.word \<Right (let zero1 = (type1 = FPType_Zero) in (let zero2 = (type2 = FPType_Zero) in if ((((((inf1 \<and> inf2))) \<and> (((sign1 = ((not_vec sign2 :: 1 Word.word)))))))) then - (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'N bits) . + (FPDefaultNaN ((int (size op1))) () :: (( 'N::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'N::len)Word.word) . (let result = w__0 in FPProcessException FPExc_InvalidOp fpcr \<then> return result)) else if ((((((inf1 \<and> (((sign1 = (vec_of_bits [B0] :: 1 Word.word))))))) \<or> (((inf2 \<and> (((sign2 = (vec_of_bits [B0] :: 1 Word.word)))))))))) then @@ -10122,23 +10128,23 @@ definition UpdateEDSCRFields :: " unit \<Rightarrow>((register_value),(unit),(e " UpdateEDSCRFields _ = ( Halted () \<bind> (\<lambda> (w__0 :: bool) . if ((\<not> w__0)) then - (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__1 (( 8 :: int)::ii) (vec_of_bits [B0,B0] :: 2 Word.word) :: 32 Word.word)) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 bits) . (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__3 :: 1 Word.word) . (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__2 (( 18 :: int)::ii) w__3 :: 32 Word.word)) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__4 :: 32 bits) . write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__4 (( 10 :: int)::ii) (vec_of_bits [B1,B1,B1,B1] :: 4 Word.word) :: 32 Word.word)))))) else - (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 bits) . read_reg PSTATE_ref \<bind> (\<lambda> (w__6 :: ProcState) . (write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 2 :: int)::ii) w__5 (( 8 :: int)::ii)(ProcState_EL w__6) :: 32 Word.word)) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 bits) . IsSecure () \<bind> (\<lambda> (w__8 :: bool) . (write_reg EDSCR_ref @@ -10210,7 +10216,7 @@ definition UpdateEDSCRFields :: " unit \<Rightarrow>((register_value),(unit),(e (let (RW :: 4 bits) = ((set_slice (( 4 :: int)::ii) (( 1 :: int)::ii) RW (( 0 :: int)::ii) w__19 :: 4 Word.word)) in return RW)) else return RW) \<bind> (\<lambda> (RW :: 4 bits) . - (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . write_reg EDSCR_ref ((set_slice (( 32 :: int)::ii) (( 4 :: int)::ii) w__20 (( 10 :: int)::ii) RW :: 32 Word.word))))))))))))))))))" @@ -10221,42 +10227,42 @@ definition Halt :: "(6)Word.word \<Rightarrow>((register_value),(unit),(excepti (CTI_SignalEvent CrossTriggerIn_CrossHalt \<then> UsingAArch32 () ) \<bind> (\<lambda> (w__0 :: bool) . ((if w__0 then - (ThisInstrAddr (( 32 :: int)::ii) () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (ThisInstrAddr (( 32 :: int)::ii) () :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . (write_reg DLR_ref w__1 \<then> - (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 bits) . + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__2 :: 32 Word.word) . (write_reg DSPSR_ref w__2 \<then> - (read_reg DSPSR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (read_reg DSPSR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__3 :: 32 bits) . read_reg PSTATE_ref \<bind> (\<lambda> (w__4 :: ProcState) . write_reg DSPSR_ref ((update_subrange_vec_dec w__3 (( 21 :: int)::ii) (( 21 :: int)::ii)(ProcState_SS w__4) :: 32 Word.word)))))) else - (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 bits) . + (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__5 :: 64 Word.word) . (write_reg DLR_EL0_ref w__5 \<then> - (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__6 :: 32 bits) . + (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__6 :: 32 Word.word) . (write_reg DSPSR_EL0_ref w__6 \<then> - (read_reg DSPSR_EL0_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 Word.word) . + (read_reg DSPSR_EL0_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 bits) . read_reg PSTATE_ref \<bind> (\<lambda> (w__8 :: ProcState) . write_reg DSPSR_EL0_ref ((update_subrange_vec_dec w__7 (( 21 :: int)::ii) (( 21 :: int)::ii)(ProcState_SS w__8) :: 32 Word.word))))))) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__9 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__9 :: 32 bits) . (write_reg EDSCR_ref ((update_subrange_vec_dec w__9 (( 24 :: int)::ii) (( 24 :: int)::ii) (vec_of_bits [B1] :: 1 Word.word) :: 32 Word.word)) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__10 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__10 :: 32 bits) . (write_reg EDSCR_ref ((update_subrange_vec_dec w__10 (( 28 :: int)::ii) (( 28 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) \<then> IsSecure () ) \<bind> (\<lambda> (w__11 :: bool) . ((if w__11 then - (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 bits) . write_reg EDSCR_ref ((update_subrange_vec_dec w__12 (( 16 :: int)::ii) (( 16 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) else if ((HaveEL EL3)) then - (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . ExternalSecureInvasiveDebugEnabled () \<bind> (\<lambda> (w__14 :: bool) . write_reg EDSCR_ref @@ -10266,14 +10272,14 @@ definition Halt :: "(6)Word.word \<Rightarrow>((register_value),(unit),(excepti :: 32 Word.word)))) else (read_reg EDSCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . - assert_exp ((((vec_of_bits [access_vec_dec w__15 (( 16 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) ([(CHR ''(''), (CHR ''(''), (CHR ''E''), (CHR ''D''), (CHR ''S''), (CHR ''C''), (CHR ''R''), (CHR '')''), (CHR ''.''), (CHR ''S''), (CHR ''D''), (CHR ''D''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')'')]))) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 Word.word) . + assert_exp ((((vec_of_bits [access_vec_dec w__15 (( 16 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))) ([(CHR ''(''), (CHR ''(''), (CHR ''E''), (CHR ''D''), (CHR ''S''), (CHR ''C''), (CHR ''R''), (CHR '')''), (CHR ''.''), (CHR ''S''), (CHR ''D''), (CHR ''D''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (CHR 0x27), (CHR ''1''), (CHR 0x27), (CHR '')'')]))) \<then> + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 bits) . (write_reg EDSCR_ref ((update_subrange_vec_dec w__16 (( 20 :: int)::ii) (( 20 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word)) \<then> UsingAArch32 () ) \<bind> (\<lambda> (w__17 :: bool) . ((if w__17 then - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__18 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__18 :: 4 Word.word) . (let split_vec = w__18 in (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -10295,7 +10301,7 @@ definition Halt :: "(6)Word.word \<Rightarrow>((register_value),(unit),(excepti read_reg PSTATE_ref) \<bind> (\<lambda> (w__24 :: ProcState) . write_reg PSTATE_ref (w__24 (| ProcState_T := ((vec_of_bits [B1] :: 1 Word.word))|))))))))))) else - (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__25 :: 5 bits) . + (undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M) \<bind> (\<lambda> (w__25 :: 5 Word.word) . (let split_vec = w__25 in (let (tup__0, tup__1, tup__2, tup__3, tup__4) = ((subrange_vec_dec split_vec (( 4 :: int)::ii) (( 4 :: int)::ii) :: 1 Word.word), @@ -10316,7 +10322,7 @@ definition Halt :: "(6)Word.word \<Rightarrow>((register_value),(unit),(excepti read_reg PSTATE_ref) \<bind> (\<lambda> (w__31 :: ProcState) . ((write_reg PSTATE_ref (w__31 (| ProcState_IL := ((vec_of_bits [B0] :: 1 Word.word))|)) \<then> StopInstructionPrefetchAndEnableITR () ) \<then> - (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 Word.word) . + (read_reg EDSCR_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 bits) . write_reg EDSCR_ref ((update_subrange_vec_dec w__32 (( 5 :: int)::ii) (( 0 :: int)::ii) reason :: 32 Word.word)) \<then> UpdateEDSCRFields () )))))))))" @@ -10709,7 +10715,7 @@ definition AArch64_S1AttrDecode :: "(2)Word.word \<Rightarrow>(3)Word.word \<Ri (vec_of_bits [B0,B0,B1,B1] :: 4 Word.word) :: 4 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0,B0] :: 4 Word.word)))))))))) then (ConstrainUnpredictableBits (( 8 :: int)::ii) Unpredictable_RESMAIR :: ((Constraint * 8 Word.word)) M) \<bind> (\<lambda> (w__0 :: - (Constraint * 8 bits)) . + (Constraint * 8 Word.word)) . (let (tup__0, tup__1) = w__0 in (let (anon10 :: Constraint) = tup__0 in return tup__1))) @@ -10810,7 +10816,7 @@ definition AArch64_CheckAndUpdateDescriptor_SecondStage :: " DescriptorUpdate \ (let descaddr2 = ((DescriptorUpdate_descaddr result)) in CreateAccessDescriptor AccType_ATOMICRW \<bind> (\<lambda> (w__0 :: AccessDescriptor) . (let accdesc = w__0 in - (aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let desc = w__1 in (let (desc :: 64 bits) = (if hw_update_AF then @@ -10891,7 +10897,7 @@ definition AArch64_CheckS2Permission :: " Permissions \<Rightarrow>(64)Word.wor undefined_bool () \<bind> (\<lambda> (secondstage :: bool) . (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (domain1 :: 4 bits) . if fail1 then - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__8 :: 4 Word.word) . (let domain1 = w__8 in (let secondstage = True in AArch64_PermissionFault ipaddress level acctype ((\<not> failedread)) secondstage s2fs1walk))) @@ -10912,9 +10918,9 @@ definition ZeroExtend_slice_append :: " int \<Rightarrow>('n::len)Word.word \<R " ZeroExtend_slice_append (o__tv :: int) xs i l ys = ( assert_exp True ('''') \<then> ((let xs = ((and_vec xs ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) :: ( 'n::len)Word.word)) in - (let (xs :: 'o bits) = + (let xs = ((shiftl ((extzv o__tv ((shiftr xs i :: ( 'n::len)Word.word)) :: ( 'o::len)Word.word)) ((int (size ys))) :: ( 'o::len)Word.word)) in - (let (ys :: 'o bits) = ((extzv ((int (size xs))) ys :: ( 'o::len)Word.word)) in + (let ys = ((extzv ((int (size xs))) ys :: ( 'o::len)Word.word)) in return ((or_vec xs ys :: ( 'o::len)Word.word)))))))" @@ -10958,7 +10964,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar liftR (undefined_bool () ) \<bind> (\<lambda> (midgrain :: bool) . liftR (undefined_bool () ) \<bind> (\<lambda> (largegrain :: bool) . liftR (undefined_int () ) \<bind> (\<lambda> (top1 :: ii) . - liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 bits) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__6 :: 64 Word.word) . (let inputaddr = w__6 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__7 :: 32 bits) . (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__7 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in @@ -11209,13 +11215,13 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (let tmp_220 = ((tmp_220 (| FullAddress_NS := ns_table |))) in (let descaddr = ((descaddr (| AddressDescriptor_paddress := tmp_220 |))) in (let descaddr2 = descaddr in - liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__34 :: 64 bits) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__34 :: 64 Word.word) . (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__34 |))) in liftR (CreateAccessDescriptorPTW acctype True s2fs1walk level) \<bind> (\<lambda> (w__35 :: AccessDescriptor) . (let accdesc = w__35 in - liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 :: 64 - bits) . + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 :: + 64 Word.word) . (let desc = w__36 in (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) else return desc) \<bind> (\<lambda> (desc :: 64 bits) . @@ -11395,7 +11401,7 @@ definition AArch64_TranslationTableWalk_SecondStage :: "(52)Word.word \<Rightar (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in - liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__51 :: 4 bits) . + liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__51 :: 4 Word.word) . (let result = ((result (| TLBRecord_domain := w__51 |))) in (let result = ((result (| TLBRecord_level := level |))) in (let result = @@ -12014,22 +12020,21 @@ definition aarch64_integer_conditional_compare_immediate :: "(4)Word.word \<Rig (assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> ((let flags = flags__arg in - (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (operand1 :: 'datasize bits) . - (let (operand2 :: 'datasize bits) = imm in + (aget_X datasize n :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> operand1 . + (let operand2 = imm in (let (carry_in :: 1 bits) = ((vec_of_bits [B0] :: 1 Word.word)) in - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (anon10 :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> anon10 . ConditionHolds condition \<bind> (\<lambda> (w__0 :: bool) . (let (flags :: 4 Word.word) = (if w__0 then - (let ((carry_in :: 1 bits), (operand2 :: 'datasize bits)) = + (let ((carry_in :: 1 bits), operand2) = (if sub_op then - (let (operand2 :: 'datasize bits) = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in + (let operand2 = ((not_vec operand2 :: ( 'datasize::len)Word.word)) in (let (carry_in :: 1 bits) = ((vec_of_bits [B1] :: 1 Word.word)) in (carry_in, operand2))) else (carry_in, operand2)) in - (let (tup__0, tup__1) = - ((AddWithCarry operand1 operand2 carry_in :: (( 'datasize::len)Word.word * 4 Word.word))) in - (let (anon10 :: 'datasize bits) = tup__0 in + (let (tup__0, tup__1) = (AddWithCarry operand1 operand2 carry_in ) in + (let anon10 = tup__0 in tup__1))) else flags) in (let (tup__0, tup__1, tup__2, tup__3) = @@ -12081,7 +12086,7 @@ definition ConditionSyndrome :: " unit \<Rightarrow>((register_value),((5)Word. (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (cond :: 4 bits) . UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . if w__0 then - (AArch32_CurrentCond () :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 bits) . + (AArch32_CurrentCond () :: ( 4 Word.word) M) \<bind> (\<lambda> (w__1 :: 4 Word.word) . (let cond = w__1 in read_reg PSTATE_ref \<bind> (\<lambda> (w__2 :: ProcState) . if ((((ProcState_T w__2) = (vec_of_bits [B0] :: 1 Word.word)))) then @@ -12122,10 +12127,11 @@ definition BranchToAddr :: "('N::len)Word.word \<Rightarrow> BranchType \<Right write_reg BranchTaken_ref True \<then> ((let (_ :: unit) = (Hint_Branch branch_type) in if (((((int (size target))) = (( 32 :: int)::ii)))) then + (let (target :: 32 Word.word) = ((Word.ucast target :: 32 Word.word)) in UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . (assert_exp w__0 (''UsingAArch32()'') \<then> - (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . - write_reg PC_ref w__1)) + (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + write_reg PC_ref w__1))) else and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) (UsingAArch32 () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . @@ -12170,13 +12176,13 @@ definition aset_Rmode :: " int \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word. read_reg R_ref \<bind> (\<lambda> (w__2 :: ( 64 bits) list) . (let (tmp_10 :: 64 bits) = ((access_list_dec w__2 n :: 64 Word.word)) in (let tmp_10 = ((update_subrange_vec_dec tmp_10 (( 31 :: int)::ii) (( 0 :: int)::ii) value_name :: 64 Word.word)) in - read_reg R_ref \<bind> (\<lambda> (w__3 :: ( 64 Word.word) list) . + read_reg R_ref \<bind> (\<lambda> (w__3 :: ( 64 bits) list) . write_reg R_ref ((update_list_dec w__3 n tmp_10 :: ( 64 Word.word) list)))))) else and_boolM (return ((\<not> ((HighestELUsingAArch32 () ))))) ((ConstrainUnpredictableBool Unpredictable_ZEROUPPER)) \<bind> (\<lambda> (w__5 :: bool) . if w__5 then - read_reg R_ref \<bind> (\<lambda> (w__6 :: ( 64 Word.word) list) . + read_reg R_ref \<bind> (\<lambda> (w__6 :: ( 64 bits) list) . LookUpRIndex n mode \<bind> (\<lambda> (w__7 :: ii) . (ZeroExtend__0 value_name ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__8 :: 64 Word.word) . @@ -12186,7 +12192,7 @@ definition aset_Rmode :: " int \<Rightarrow>(5)Word.word \<Rightarrow>(32)Word. LookUpRIndex n mode \<bind> (\<lambda> (w__10 :: ii) . (let (tmp_20 :: 64 bits) = ((access_list_dec w__9 w__10 :: 64 Word.word)) in (let tmp_20 = ((update_subrange_vec_dec tmp_20 (( 31 :: int)::ii) (( 0 :: int)::ii) value_name :: 64 Word.word)) in - read_reg R_ref \<bind> (\<lambda> (w__11 :: ( 64 Word.word) list) . + read_reg R_ref \<bind> (\<lambda> (w__11 :: ( 64 bits) list) . LookUpRIndex n mode \<bind> (\<lambda> (w__12 :: ii) . write_reg R_ref ((update_list_dec w__11 w__12 tmp_20 :: ( 64 Word.word) list)))))))))))))" @@ -12548,7 +12554,7 @@ definition AddPAC :: "(64)Word.word \<Rightarrow>(64)Word.word \<Rightarrow>(12 :: 64 Word.word)) in (ComputePAC ext_ptr modifier ((subrange_vec_dec K (( 127 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((subrange_vec_dec K (( 63 :: int)::ii) (( 0 :: int)::ii) :: 64 Word.word)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__27 :: 64 Word.word) . (let (PAC :: 64 bits) = w__27 in (let (PAC :: 64 bits) = (if (((((\<not> ((is_zero_subrange ptr @@ -12631,16 +12637,16 @@ definition AArch64_vESBOperation :: " unit \<Rightarrow>((register_value),(unit (read_reg VDFSR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . (AArch32_ReportDeferredSError ((slice w__13 (( 14 :: int)::ii) (( 2 :: int)::ii) :: 2 Word.word)) (vec_of_bits [access_vec_dec w__14 (( 12 :: int)::ii)] :: 1 Word.word) - :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . + :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 Word.word) . (let (VDISR :: 32 bits) = w__15 in return () )))) else (read_reg VSESR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . - (AArch64_ReportDeferredSError ((slice w__16 (( 0 :: int)::ii) (( 25 :: int)::ii) :: 25 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 - bits) . + (AArch64_ReportDeferredSError ((slice w__16 (( 0 :: int)::ii) (( 25 :: int)::ii) :: 25 Word.word)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: + 64 Word.word) . (let (VDISR_EL2 :: 64 bits) = w__17 in return () )))) \<then> - (read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__18 :: 64 Word.word) . + (read_reg HCR_EL2_ref :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__18 :: 64 bits) . write_reg HCR_EL2_ref ((set_slice (( 64 :: int)::ii) (( 1 :: int)::ii) w__18 (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 64 Word.word)))) @@ -12757,7 +12763,7 @@ definition AArch64_WatchpointByteMatch :: " int \<Rightarrow>(64)Word.word \<Ri definition IsOnes_slice :: "('n::len)Word.word \<Rightarrow> int \<Rightarrow> int \<Rightarrow>((register_value),(bool),(exception))monad " where " IsOnes_slice xs i l = ( assert_exp True ('''') \<then> - ((let (m :: 'n bits) = ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) in + ((let m = ((slice_mask ((int (size xs))) i l :: ( 'n::len)Word.word)) in return (((((and_vec xs m :: ( 'n::len)Word.word)) = m))))))" @@ -12811,7 +12817,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word liftR (undefined_bool () ) \<bind> (\<lambda> (largegrain :: bool) . liftR (undefined_int () ) \<bind> (\<lambda> (top1 :: ii) . (if ((\<not> secondstage)) then - liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 bits) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__8 :: 64 Word.word) . (let inputaddr = w__8 in liftR (read_reg PSTATE_ref) \<bind> (\<lambda> (w__9 :: ProcState) . liftR (AddrTop inputaddr (((acctype = AccType_IFETCH)))(ProcState_EL w__9)) \<bind> (\<lambda> (w__10 :: @@ -13338,7 +13344,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word update_AF, update_AP)))))))))))) else - liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__115 :: 64 bits) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) ipaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__115 :: 64 Word.word) . (let inputaddr = w__115 in liftR ((read_reg VTCR_EL2_ref :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__116 :: 32 bits) . (let inputsize = ((( 64 :: int)::ii) - ((Word.uint ((slice w__116 (( 0 :: int)::ii) (( 6 :: int)::ii) :: 6 Word.word))))) in @@ -13647,13 +13653,14 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word else return result) \<bind> (\<lambda> (result :: TLBRecord) . return (descaddr2, hwupdatewalk, result)))))) \<bind> (\<lambda> varstup . (let ((descaddr2 :: AddressDescriptor), (hwupdatewalk :: bool), (result :: TLBRecord)) = varstup in - liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__146 :: 64 bits) . + liftR ((ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__146 :: + 64 Word.word) . (let descaddr2 = ((descaddr2 (| AddressDescriptor_vaddress := w__146 |))) in liftR (CreateAccessDescriptorPTW acctype secondstage s2fs1walk level) \<bind> (\<lambda> (w__147 :: AccessDescriptor) . (let accdesc = w__147 in - liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__148 :: 64 - bits) . + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__148 :: + 64 Word.word) . (let desc = w__148 in (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) else return desc) \<bind> (\<lambda> (desc :: 64 bits) . @@ -13934,7 +13941,7 @@ definition AArch64_TranslationTableWalk :: "(52)Word.word \<Rightarrow>(64)Word (vec_of_bits [B1] :: 1 Word.word) :: 3 Word.word)) in (let (memattr :: 4 bits) = ((slice desc (( 2 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word)) in - liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__163 :: 4 bits) . + liftR ((undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__163 :: 4 Word.word) . (let result = ((result (| TLBRecord_domain := w__163 |))) in (let result = ((result (| TLBRecord_level := level |))) in (let result = @@ -14111,7 +14118,7 @@ definition AArch64_TranslateAddressS1Off :: "(64)Word.word \<Rightarrow> AccTyp bool) . if ((\<not> w__3)) then (let level = ((( 0 :: int)::ii)) in - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__4 :: 52 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__4 :: 52 Word.word) . (let ipaddress = w__4 in (let secondstage = False in (let s2fs1walk = False in @@ -14271,7 +14278,7 @@ definition AArch64_TranslateAddressS1Off :: "(64)Word.word \<Rightarrow> AccTyp (let tmp_2370 = ((tmp_2370 (| AddressDescriptor_memattrs := w__10 |))) in (let result = ((result (| TLBRecord_addrdesc := tmp_2370 |))) in (let (tmp_2380 :: Permissions) = ((TLBRecord_perms result)) in - (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__11 :: 3 bits) . + (undefined_bitvector (( 3 :: int)::ii) :: ( 3 Word.word) M) \<bind> (\<lambda> (w__11 :: 3 Word.word) . (let tmp_2380 = ((tmp_2380 (| Permissions_ap := w__11 |))) in (let result = ((result (| TLBRecord_perms := tmp_2380 |))) in (let (tmp_2390 :: Permissions) = ((TLBRecord_perms result)) in @@ -14280,11 +14287,11 @@ definition AArch64_TranslateAddressS1Off :: "(64)Word.word \<Rightarrow> AccTyp (let (tmp_2400 :: Permissions) = ((TLBRecord_perms result)) in (let tmp_2400 = ((tmp_2400 (| Permissions_pxn := ((vec_of_bits [B0] :: 1 Word.word))|))) in (let result = ((result (| TLBRecord_perms := tmp_2400 |))) in - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__12 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__12 :: 1 Word.word) . (let result = ((result (| TLBRecord_nG := w__12 |))) in undefined_bool () \<bind> (\<lambda> (w__13 :: bool) . (let result = ((result (| TLBRecord_contiguous := w__13 |))) in - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__14 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M) \<bind> (\<lambda> (w__14 :: 4 Word.word) . (let result = ((result (| TLBRecord_domain := w__14 |))) in undefined_int () \<bind> (\<lambda> (w__15 :: ii) . (let result = ((result (| TLBRecord_level := w__15 |))) in @@ -14365,7 +14372,7 @@ definition AArch64_MaybeZeroRegisterUppers :: " unit \<Rightarrow>((register_va (let tmp_30 = ((set_slice (( 64 :: int)::ii) (( 32 :: int)::ii) tmp_30 (( 32 :: int)::ii) ((Zeros__1 (( 32 :: int)::ii) () :: 32 Word.word)) :: 64 Word.word)) in - read_reg R_ref \<bind> (\<lambda> (w__15 :: ( 64 Word.word) list) . + read_reg R_ref \<bind> (\<lambda> (w__15 :: ( 64 bits) list) . write_reg R_ref ((update_list_dec w__15 n tmp_30 :: ( 64 Word.word) list)))))) else return () )))))))))))" @@ -14420,7 +14427,7 @@ definition DCPSInstruction :: "(2)Word.word \<Rightarrow>((register_value),(uni (((if w__16 then read_reg PSTATE_ref \<bind> (\<lambda> (w__17 :: ProcState) . ((if ((((ProcState_M w__17) = M32_Monitor))) then - (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . + (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . write_reg SCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__18 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) @@ -14452,9 +14459,9 @@ definition DCPSInstruction :: "(2)Word.word \<Rightarrow>((register_value),(uni else return () ) else return () )) \<then> (if (((handle_el = EL2))) then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 Word.word) . (write_reg ELR_hyp_ref w__26 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__27 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__27 :: 32 Word.word) . write_reg HSR_ref w__27)) else (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__28 :: 32 Word.word) . @@ -14466,9 +14473,9 @@ definition DCPSInstruction :: "(2)Word.word \<Rightarrow>((register_value),(uni (write_reg PSTATE_ref (w__30 (| ProcState_E := ((vec_of_bits [access_vec_dec w__31 (( 25 :: int)::ii)] :: 1 Word.word))|)) \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 Word.word) . (write_reg DLR_ref w__32 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__33 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__33 :: 32 Word.word) . write_reg DSPSR_ref w__33))))))))) else UsingAArch32 () \<bind> (\<lambda> (w__34 :: bool) . @@ -14504,9 +14511,9 @@ definition DCPSInstruction :: "(2)Word.word \<Rightarrow>((register_value),(uni (aset_SPSR w__50 \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__51 :: 32 Word.word) . (aset_ESR__1 w__51 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__52 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__52 :: 64 Word.word) . (write_reg DLR_EL0_ref w__52 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__53 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__53 :: 32 Word.word) . write_reg DSPSR_EL0_ref w__53 \<then> (if ((HaveUAOExt () )) then read_reg PSTATE_ref \<bind> (\<lambda> (w__54 :: ProcState) . @@ -14623,9 +14630,9 @@ definition AArch64_AbortSyndrome :: " Exception \<Rightarrow> FaultRecord \<Rig " AArch64_AbortSyndrome typ1 fault vaddress = ( ExceptionSyndrome typ1 \<bind> (\<lambda> (exception :: ExceptionRecord) . (let (d_side :: bool) = ((((typ1 = Exception_DataAbort))) \<or> (((typ1 = Exception_Watchpoint)))) in - (AArch64_FaultSyndrome d_side fault :: ( 25 Word.word) M) \<bind> (\<lambda> (w__0 :: 25 bits) . + (AArch64_FaultSyndrome d_side fault :: ( 25 Word.word) M) \<bind> (\<lambda> (w__0 :: 25 Word.word) . (let exception = ((exception (| ExceptionRecord_syndrome := w__0 |))) in - (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let exception = ((exception (| ExceptionRecord_vaddress := w__1 |))) in IPAValid fault \<bind> (\<lambda> (w__2 :: bool) . (let (exception :: ExceptionRecord) = @@ -14667,7 +14674,7 @@ definition AArch64_ExceptionClass :: " Exception \<Rightarrow>(2)Word.word \<Ri (if (((((ex_int w__0)) = (( 32 :: int)::ii)))) then (vec_of_bits [B1] :: 1 Word.word) else (vec_of_bits [B0] :: 1 Word.word)) in UsingAArch32 () \<bind> (\<lambda> (from_32 :: bool) . - (assert_exp (((from_32 \<or> (((il = (vec_of_bits [B1] :: 1 Word.word))))))) ([(CHR ''(''), (CHR ''f''), (CHR ''r''), (CHR ''o''), (CHR ''m''), (CHR ''_''), (CHR ''3''), (CHR ''2''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''i''), (CHR ''l''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '')'')]) \<then> + (assert_exp (((from_32 \<or> (((il = (vec_of_bits [B1] :: 1 Word.word))))))) ([(CHR ''(''), (CHR ''f''), (CHR ''r''), (CHR ''o''), (CHR ''m''), (CHR ''_''), (CHR ''3''), (CHR ''2''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''i''), (CHR ''l''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (CHR 0x27), (CHR ''1''), (CHR 0x27), (CHR '')''), (CHR '')'')]) \<then> undefined_int () ) \<bind> (\<lambda> (ec :: ii) . (case typ1 of Exception_Uncategorized => @@ -14797,14 +14804,14 @@ definition AArch64_ReportException :: " ExceptionRecord \<Rightarrow>(2)Word.wo aset_FAR__0 target_el w__0))) \<then> (if (((target_el = EL2))) then if(ExceptionRecord_ipavalid exception) then - (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . write_reg HPFAR_EL2_ref ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__1 (( 4 :: int)::ii) ((slice(ExceptionRecord_ipaddress exception) (( 12 :: int)::ii) (( 40 :: int)::ii) :: 40 Word.word)) :: 64 Word.word))) else - (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . + (read_reg HPFAR_EL2_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . (undefined_bitvector (( 40 :: int)::ii) :: ( 40 Word.word) M) \<bind> (\<lambda> (w__3 :: 40 Word.word) . write_reg HPFAR_EL2_ref ((set_slice (( 64 :: int)::ii) (( 40 :: int)::ii) w__2 (( 4 :: int)::ii) w__3 :: 64 Word.word)))) else return () )))))))))))" @@ -14868,14 +14875,14 @@ definition AArch64_ESBOperation :: " unit \<Rightarrow>((register_value),(unit) (let syndrome32 = w__25 in (AArch32_ReportDeferredSError(AArch32_SErrorSyndrome_AET syndrome32)(AArch32_SErrorSyndrome_ExT syndrome32) - :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 bits) . + :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 Word.word) . (let (DISR :: 32 bits) = w__26 in return () )))) else (let implicit_esb = False in - (AArch64_PhysicalSErrorSyndrome implicit_esb :: ( 25 Word.word) M) \<bind> (\<lambda> (w__27 :: 25 bits) . + (AArch64_PhysicalSErrorSyndrome implicit_esb :: ( 25 Word.word) M) \<bind> (\<lambda> (w__27 :: 25 Word.word) . (let syndrome64 = w__27 in - (AArch64_ReportDeferredSError syndrome64 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 bits) . + (AArch64_ReportDeferredSError syndrome64 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 Word.word) . (let (DISR_EL1 :: 64 bits) = w__28 in return () )))))) \<then> ClearPendingPhysicalSError () )) @@ -14924,7 +14931,7 @@ definition AArch64_CheckAndUpdateDescriptor :: " DescriptorUpdate \<Rightarrow> return descaddr2)))) \<bind> (\<lambda> (descaddr2 :: AddressDescriptor) . liftR (CreateAccessDescriptor AccType_ATOMICRW) \<bind> (\<lambda> (w__4 :: AccessDescriptor) . (let accdesc = w__4 in - liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 bits) . + liftR ((aget__Mem descaddr2 (( 8 :: int)::ii) accdesc :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__5 :: 64 Word.word) . (let desc = w__5 in (if reversedescriptors then liftR ((BigEndianReverse desc :: ( 64 Word.word) M)) else return desc) \<bind> (\<lambda> (desc :: 64 bits) . @@ -14984,7 +14991,7 @@ definition AArch64_StateMatch :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B1,B0] :: 5 Word.word))))))))))))))))))) \<or> (((((((((HMC = (vec_of_bits [B0] :: 1 Word.word)))) \<and> (((PxC = (vec_of_bits [B0,B0] :: 2 Word.word))))))) \<and> (((((\<not> isbreakpnt)) \<or> ((\<not> ((HaveAArch32EL EL1))))))))))))) \<or> (((((((((SSC = (vec_of_bits [B0,B1] :: 2 Word.word)))) \<or> (((SSC = (vec_of_bits [B1,B0] :: 2 Word.word))))))) \<and> ((\<not> ((HaveEL EL3)))))))))) \<or> ((((((((((((((concat_vec HMC SSC :: 3 Word.word)) \<noteq> (vec_of_bits [B0,B0,B0] :: 3 Word.word)))) \<and> (((((concat_vec HMC SSC :: 3 Word.word)) \<noteq> (vec_of_bits [B1,B1,B1] :: 3 Word.word))))))) \<and> ((\<not> ((HaveEL EL3))))))) \<and> ((\<not> ((HaveEL EL2)))))))))) \<or> ((((((((concat_vec ((concat_vec HMC SSC :: 3 Word.word)) PxC :: 5 Word.word)) = (vec_of_bits [B1,B1,B1,B0,B0] :: 5 Word.word)))) \<and> ((\<not> ((HaveEL EL2)))))))))) then liftR ((undefined_bitvector (( 5 :: int)::ii) :: ( 5 Word.word) M)) \<bind> (\<lambda> (tmp_50 :: 5 bits) . liftR ((ConstrainUnpredictableBits (( 5 :: int)::ii) Unpredictable_RESBPWPCTRL - :: ((Constraint * 5 Word.word)) M)) \<bind> (\<lambda> (w__0 :: (Constraint * 5 bits)) . + :: ((Constraint * 5 Word.word)) M)) \<bind> (\<lambda> (w__0 :: (Constraint * 5 Word.word)) . (let (tup__0, tup__1) = w__0 in (let c = tup__0 in (let tmp_50 = tup__1 in @@ -15055,7 +15062,7 @@ definition AArch64_StateMatch :: "(2)Word.word \<Rightarrow>(1)Word.word \<Righ liftR (undefined_bool () ) \<bind> (\<lambda> (linked_to :: bool) . liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (vaddress :: 64 bits) . (if linked then - liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__7 :: 64 bits) . + liftR ((undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__7 :: 64 Word.word) . (let (vaddress :: 64 bits) = w__7 in (let (linked_to :: bool) = True in (let (linked_match :: bool) = (AArch64_BreakpointValueMatch lbn vaddress linked_to) in @@ -15231,16 +15238,17 @@ definition BranchTo :: "('N::len)Word.word \<Rightarrow> BranchType \<Rightarro write_reg BranchTaken_ref True \<then> ((let (_ :: unit) = (Hint_Branch branch_type) in if (((((int (size target))) = (( 32 :: int)::ii)))) then + (let (target :: 32 Word.word) = ((Word.ucast target :: 32 Word.word)) in UsingAArch32 () \<bind> (\<lambda> (w__0 :: bool) . (assert_exp w__0 (''UsingAArch32()'') \<then> - (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 bits) . - write_reg PC_ref w__1)) + (ZeroExtend__1 (( 64 :: int)::ii) target :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__1 :: 64 Word.word) . + write_reg PC_ref w__1))) else and_boolM (return (((((int (size target))) = (( 64 :: int)::ii))))) (UsingAArch32 () \<bind> (\<lambda> (w__2 :: bool) . return ((\<not> w__2)))) \<bind> (\<lambda> (w__3 :: bool) . (assert_exp w__3 (''((N == 64) && !(UsingAArch32()))'') \<then> - (AArch64_BranchAddr ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: 64 - bits) . + (AArch64_BranchAddr ((slice target (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__4 :: + 64 Word.word) . write_reg PC_ref w__4)))))" @@ -16937,7 +16945,7 @@ definition AArch64_VectorCatchException :: " FaultRecord \<Rightarrow>((registe return ((((vec_of_bits [access_vec_dec w__3 (( 27 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))) ((read_reg MDCR_EL2_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . return ((((vec_of_bits [access_vec_dec w__4 (( 8 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)))))))) \<bind> (\<lambda> (w__6 :: bool) . - (assert_exp w__6 ([(CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''a''), (CHR ''v''), (CHR ''e''), (CHR ''E''), (CHR ''L''), (CHR ''(''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''!''), (CHR ''(''), (CHR ''I''), (CHR ''s''), (CHR ''S''), (CHR ''e''), (CHR ''c''), (CHR ''u''), (CHR ''r''), (CHR ''e''), (CHR ''(''), (CHR '')''), (CHR '')''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''G''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''M''), (CHR ''D''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''D''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (char_of_nat 39), (CHR ''1''), (char_of_nat 39), (CHR '')''), (CHR '')''), (CHR '')'')]) \<then> + (assert_exp w__6 ([(CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''a''), (CHR ''v''), (CHR ''e''), (CHR ''E''), (CHR ''L''), (CHR ''(''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''!''), (CHR ''(''), (CHR ''I''), (CHR ''s''), (CHR ''S''), (CHR ''e''), (CHR ''c''), (CHR ''u''), (CHR ''r''), (CHR ''e''), (CHR ''(''), (CHR '')''), (CHR '')''), (CHR '')''), (CHR '' ''), (CHR ''&''), (CHR ''&''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''(''), (CHR ''H''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''G''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (CHR 0x27), (CHR ''1''), (CHR 0x27), (CHR '')''), (CHR '' ''), (CHR ''|''), (CHR ''|''), (CHR '' ''), (CHR ''(''), (CHR ''(''), (CHR ''M''), (CHR ''D''), (CHR ''C''), (CHR ''R''), (CHR ''_''), (CHR ''E''), (CHR ''L''), (CHR ''2''), (CHR '')''), (CHR ''.''), (CHR ''T''), (CHR ''D''), (CHR ''E''), (CHR '' ''), (CHR ''=''), (CHR ''=''), (CHR '' ''), (CHR 0x27), (CHR ''1''), (CHR 0x27), (CHR '')''), (CHR '')''), (CHR '')'')]) \<then> (ThisInstrAddr (( 64 :: int)::ii) () :: ( 64 Word.word) M)) \<bind> (\<lambda> (preferred_exception_return :: 64 bits) . (let (vect_offset :: ii) = ((( 0 :: int)::ii)) in (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (vaddress :: 64 bits) . @@ -17404,7 +17412,7 @@ definition AArch32_EnterMode :: "(5)Word.word \<Rightarrow>(32)Word.word \<Righ (GetPSRFromPSTATE () :: ( 32 Word.word) M)) \<bind> (\<lambda> (spsr :: 32 bits) . read_reg PSTATE_ref \<bind> (\<lambda> (w__3 :: ProcState) . (((((if ((((ProcState_M w__3) = M32_Monitor))) then - (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg SCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . write_reg SCR_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__4 (( 0 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) @@ -17644,42 +17652,42 @@ definition aarch64_float_convert_int :: " int \<Rightarrow>('fltsize::len)itsel (let intsize = (size_itself_int intsize) in (let fltsize = (size_itself_int fltsize) in (CheckFPAdvSIMDEnabled64 () \<then> - (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \<bind> (\<lambda> (fltval :: 'fltsize bits) . - (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (intval :: 'intsize bits) . + (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \<bind> (\<lambda> fltval . + (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> intval . (case op1 of FPConvOp_CVT_FtoI => - (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'fltsize bits) . + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'fltsize::len)Word.word) . (let fltval = w__0 in - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - (FPToFixed intsize fltval (( 0 :: int)::ii) unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'intsize - bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (FPToFixed intsize fltval (( 0 :: int)::ii) unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: + ( 'intsize::len)Word.word) . (let intval = w__2 in aset_X d intval))))) | FPConvOp_CVT_ItoF => - (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'intsize bits) . + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'intsize::len)Word.word) . (let intval = w__3 in - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . - (FixedToFP fltsize intval (( 0 :: int)::ii) unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: 'fltsize - bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . + (FixedToFP fltsize intval (( 0 :: int)::ii) unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + ( 'fltsize::len)Word.word) . (let fltval = w__5 in aset_V d fltval))))) | FPConvOp_MOV_FtoI => - (aget_Vpart fltsize n part :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: 'fltsize bits) . + (aget_Vpart fltsize n part :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'fltsize::len)Word.word) . (let fltval = w__6 in - (ZeroExtend__0 fltval ((make_the_value intsize :: ( 'intsize::len)itself)) :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: 'intsize - bits) . + (ZeroExtend__0 fltval ((make_the_value intsize )) :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: + ( 'intsize::len)Word.word) . (let intval = w__7 in aset_X d intval)))) | FPConvOp_MOV_ItoF => - (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: 'intsize bits) . + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: ( 'intsize::len)Word.word) . (let intval = w__8 in (let fltval = ((slice intval (( 0 :: int)::ii) fltsize :: ( 'fltsize::len)Word.word)) in aset_Vpart d part fltval))) | FPConvOp_CVT_FtoI_JS => - (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: 'fltsize bits) . + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: ( 'fltsize::len)Word.word) . (let fltval = w__9 in - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . - (FPToFixedJS intsize fltval w__10 True :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__11 :: 'intsize bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (FPToFixedJS intsize fltval w__10 True :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__11 :: ( 'intsize::len)Word.word) . (let intval = w__11 in (ZeroExtend__0 ((slice intval (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) @@ -17695,10 +17703,10 @@ definition aarch64_float_convert_fp :: " int \<Rightarrow>('dstsize::len)itself (let srcsize = (size_itself_int srcsize) in (let dstsize = (size_itself_int dstsize) in (CheckFPAdvSIMDEnabled64 () \<then> - (undefined_bitvector dstsize :: (( 'dstsize::len)Word.word) M)) \<bind> (\<lambda> (result :: 'dstsize bits) . - (aget_V srcsize n :: (( 'srcsize::len)Word.word) M) \<bind> (\<lambda> (operand :: 'srcsize bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - (FPConvert__1 dstsize operand w__0 :: (( 'dstsize::len)Word.word) M) \<bind> (\<lambda> (w__1 :: 'dstsize bits) . + (undefined_bitvector dstsize :: (( 'dstsize::len)Word.word) M)) \<bind> (\<lambda> result . + (aget_V srcsize n :: (( 'srcsize::len)Word.word) M) \<bind> (\<lambda> operand . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (FPConvert__1 dstsize operand w__0 :: (( 'dstsize::len)Word.word) M) \<bind> (\<lambda> (w__1 :: ( 'dstsize::len)Word.word) . (let result = w__1 in aset_V d result))))))))" @@ -17710,23 +17718,23 @@ definition aarch64_float_convert_fix :: " int \<Rightarrow>('fltsize::len)itsel (let intsize = (size_itself_int intsize) in (let fltsize = (size_itself_int fltsize) in (CheckFPAdvSIMDEnabled64 () \<then> - (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \<bind> (\<lambda> (fltval :: 'fltsize bits) . - (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (intval :: 'intsize bits) . + (undefined_bitvector fltsize :: (( 'fltsize::len)Word.word) M)) \<bind> (\<lambda> fltval . + (undefined_bitvector intsize :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> intval . (case op1 of FPConvOp_CVT_FtoI => - (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__0 :: 'fltsize bits) . + (aget_V fltsize n :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__0 :: ( 'fltsize::len)Word.word) . (let fltval = w__0 in - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . - (FPToFixed intsize fltval fracbits unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'intsize - bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . + (FPToFixed intsize fltval fracbits unsigned w__1 rounding :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: + ( 'intsize::len)Word.word) . (let intval = w__2 in aset_X d intval))))) | FPConvOp_CVT_ItoF => - (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'intsize bits) . + (aget_X intsize n :: (( 'intsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'intsize::len)Word.word) . (let intval = w__3 in - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . - (FixedToFP fltsize intval fracbits unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: 'fltsize - bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . + (FixedToFP fltsize intval fracbits unsigned w__4 rounding :: (( 'fltsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + ( 'fltsize::len)Word.word) . (let fltval = w__5 in aset_V d fltval))))) ))))))" @@ -17744,7 +17752,7 @@ definition aarch64_float_compare_uncond :: " bool \<Rightarrow> int \<Rightarro (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M)) \<bind> (\<lambda> (operand1 :: 8 bits) . (if cmp_with_zero then (FPZero (( 8 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 8 Word.word) M) else (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M)) \<bind> (\<lambda> (operand2 :: 8 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__2 :: ( 4 Word.word) M) \<bind> (\<lambda> split_vec . (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -17767,7 +17775,7 @@ definition aarch64_float_compare_uncond :: " bool \<Rightarrow> int \<Rightarro (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M)) \<bind> (\<lambda> (operand1 :: 16 bits) . (if cmp_with_zero then (FPZero (( 16 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 16 Word.word) M) else (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M)) \<bind> (\<lambda> (operand2 :: 16 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__9 :: ( 4 Word.word) M) \<bind> (\<lambda> split_vec . (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -17790,7 +17798,7 @@ definition aarch64_float_compare_uncond :: " bool \<Rightarrow> int \<Rightarro (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M)) \<bind> (\<lambda> (operand1 :: 32 bits) . (if cmp_with_zero then (FPZero (( 32 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 32 Word.word) M) else (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M)) \<bind> (\<lambda> (operand2 :: 32 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__16 :: ( 4 Word.word) M) \<bind> (\<lambda> split_vec . (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -17813,7 +17821,7 @@ definition aarch64_float_compare_uncond :: " bool \<Rightarrow> int \<Rightarro (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (operand1 :: 64 bits) . (if cmp_with_zero then (FPZero (( 64 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 64 Word.word) M) else (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M)) \<bind> (\<lambda> (operand2 :: 64 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__23 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__23 :: ( 4 Word.word) M) \<bind> (\<lambda> split_vec . (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -17836,7 +17844,7 @@ definition aarch64_float_compare_uncond :: " bool \<Rightarrow> int \<Rightarro (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M)) \<bind> (\<lambda> (operand1 :: 128 bits) . (if cmp_with_zero then (FPZero (( 128 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: ( 128 Word.word) M) else (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M)) \<bind> (\<lambda> (operand2 :: 128 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__30 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__30 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__30 :: ( 4 Word.word) M) \<bind> (\<lambda> split_vec . (let (tup__0, tup__1, tup__2, tup__3) = ((subrange_vec_dec split_vec (( 3 :: int)::ii) (( 3 :: int)::ii) :: 1 Word.word), @@ -17870,7 +17878,7 @@ definition aarch64_float_compare_cond :: "(4)Word.word \<Rightarrow> int \<Righ (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . ConditionHolds condition \<bind> (\<lambda> (w__0 :: bool) . (if w__0 then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__1 :: ( 4 Word.word) M)) else return flags) \<bind> (\<lambda> (flags :: 4 Word.word) . (let (tup__0, tup__1, tup__2, tup__3) = @@ -17896,7 +17904,7 @@ definition aarch64_float_compare_cond :: "(4)Word.word \<Rightarrow> int \<Righ (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . ConditionHolds condition \<bind> (\<lambda> (w__7 :: bool) . (if w__7 then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__8 :: ( 4 Word.word) M)) else return flags) \<bind> (\<lambda> (flags :: 4 Word.word) . (let (tup__0, tup__1, tup__2, tup__3) = @@ -17922,7 +17930,7 @@ definition aarch64_float_compare_cond :: "(4)Word.word \<Rightarrow> int \<Righ (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . ConditionHolds condition \<bind> (\<lambda> (w__14 :: bool) . (if w__14 then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__15 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__15 :: ( 4 Word.word) M)) else return flags) \<bind> (\<lambda> (flags :: 4 Word.word) . (let (tup__0, tup__1, tup__2, tup__3) = @@ -17948,7 +17956,7 @@ definition aarch64_float_compare_cond :: "(4)Word.word \<Rightarrow> int \<Righ (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . ConditionHolds condition \<bind> (\<lambda> (w__21 :: bool) . (if w__21 then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__22 :: ( 4 Word.word) M)) else return flags) \<bind> (\<lambda> (flags :: 4 Word.word) . (let (tup__0, tup__1, tup__2, tup__3) = @@ -17974,7 +17982,7 @@ definition aarch64_float_compare_cond :: "(4)Word.word \<Rightarrow> int \<Righ (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . ConditionHolds condition \<bind> (\<lambda> (w__28 :: bool) . (if w__28 then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__29 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__29 :: 32 bits) . (FPCompare operand1 operand2 signal_all_nans w__29 :: ( 4 Word.word) M)) else return flags) \<bind> (\<lambda> (flags :: 4 Word.word) . (let (tup__0, tup__1, tup__2, tup__3) = @@ -18011,7 +18019,7 @@ definition aarch64_float_arithmetic_unary :: " int \<Rightarrow> int \<Rightarr | FPUnaryOp_ABS => (FPAbs operand :: ( 8 Word.word) M) | FPUnaryOp_NEG => (FPNeg operand :: ( 8 Word.word) M) | FPUnaryOp_SQRT => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . (FPSqrt operand w__2 :: ( 8 Word.word) M)) ) \<bind> (\<lambda> (result :: 8 bits) . aset_V d result)))) @@ -18027,7 +18035,7 @@ definition aarch64_float_arithmetic_unary :: " int \<Rightarrow> int \<Rightarr | FPUnaryOp_ABS => (FPAbs operand :: ( 16 Word.word) M) | FPUnaryOp_NEG => (FPNeg operand :: ( 16 Word.word) M) | FPUnaryOp_SQRT => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . (FPSqrt operand w__6 :: ( 16 Word.word) M)) ) \<bind> (\<lambda> (result :: 16 bits) . aset_V d result)))) @@ -18043,7 +18051,7 @@ definition aarch64_float_arithmetic_unary :: " int \<Rightarrow> int \<Rightarr | FPUnaryOp_ABS => (FPAbs operand :: ( 32 Word.word) M) | FPUnaryOp_NEG => (FPNeg operand :: ( 32 Word.word) M) | FPUnaryOp_SQRT => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . (FPSqrt operand w__10 :: ( 32 Word.word) M)) ) \<bind> (\<lambda> (result :: 32 bits) . aset_V d result)))) @@ -18059,7 +18067,7 @@ definition aarch64_float_arithmetic_unary :: " int \<Rightarrow> int \<Rightarr | FPUnaryOp_ABS => (FPAbs operand :: ( 64 Word.word) M) | FPUnaryOp_NEG => (FPNeg operand :: ( 64 Word.word) M) | FPUnaryOp_SQRT => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . (FPSqrt operand w__14 :: ( 64 Word.word) M)) ) \<bind> (\<lambda> (result :: 64 bits) . aset_V d result)))) @@ -18075,7 +18083,7 @@ definition aarch64_float_arithmetic_unary :: " int \<Rightarrow> int \<Rightarr | FPUnaryOp_ABS => (FPAbs operand :: ( 128 Word.word) M) | FPUnaryOp_NEG => (FPNeg operand :: ( 128 Word.word) M) | FPUnaryOp_SQRT => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . (FPSqrt operand w__18 :: ( 128 Word.word) M)) ) \<bind> (\<lambda> (result :: 128 bits) . aset_V d result)))) @@ -18095,8 +18103,8 @@ definition aarch64_float_arithmetic_round :: " int \<Rightarrow> int \<Rightarr CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (result :: 8 bits) . (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \<bind> (\<lambda> (operand :: 8 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - (FPRoundInt operand w__0 rounding exact :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (FPRoundInt operand w__0 rounding exact :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . (let result = w__1 in aset_V d result)))))) else if (((l__113 = (( 16 :: int)::ii)))) then @@ -18106,8 +18114,8 @@ definition aarch64_float_arithmetic_round :: " int \<Rightarrow> int \<Rightarr CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \<bind> (\<lambda> (operand :: 16 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - (FPRoundInt operand w__2 rounding exact :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . + (FPRoundInt operand w__2 rounding exact :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . (let result = w__3 in aset_V d result)))))) else if (((l__113 = (( 32 :: int)::ii)))) then @@ -18117,8 +18125,8 @@ definition aarch64_float_arithmetic_round :: " int \<Rightarrow> int \<Rightarr CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \<bind> (\<lambda> (operand :: 32 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . - (FPRoundInt operand w__4 rounding exact :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . + (FPRoundInt operand w__4 rounding exact :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . (let result = w__5 in aset_V d result)))))) else if (((l__113 = (( 64 :: int)::ii)))) then @@ -18128,8 +18136,8 @@ definition aarch64_float_arithmetic_round :: " int \<Rightarrow> int \<Rightarr CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \<bind> (\<lambda> (operand :: 64 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . - (FPRoundInt operand w__6 rounding exact :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + (FPRoundInt operand w__6 rounding exact :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . (let result = w__7 in aset_V d result)))))) else if (((l__113 = (( 128 :: int)::ii)))) then @@ -18139,8 +18147,8 @@ definition aarch64_float_arithmetic_round :: " int \<Rightarrow> int \<Rightarr CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \<bind> (\<lambda> (result :: 128 bits) . (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \<bind> (\<lambda> (operand :: 128 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . - (FPRoundInt operand w__8 rounding exact :: ( 128 Word.word) M) \<bind> (\<lambda> (w__9 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . + (FPRoundInt operand w__8 rounding exact :: ( 128 Word.word) M) \<bind> (\<lambda> (w__9 :: 128 Word.word) . (let result = w__9 in aset_V d result)))))) else @@ -18160,8 +18168,8 @@ definition aarch64_float_arithmetic_mul_product :: " int \<Rightarrow> int \<Ri (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (result :: 8 bits) . (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \<bind> (\<lambda> (operand1 :: 8 bits) . (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - (FPMul operand1 operand2 w__0 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (FPMul operand1 operand2 w__0 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . (let result = w__1 in (if negated then (FPNeg result :: ( 8 Word.word) M) else return result) \<bind> (\<lambda> (result :: 8 bits) . @@ -18174,8 +18182,8 @@ definition aarch64_float_arithmetic_mul_product :: " int \<Rightarrow> int \<Ri (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \<bind> (\<lambda> (operand1 :: 16 bits) . (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . - (FPMul operand1 operand2 w__3 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . + (FPMul operand1 operand2 w__3 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: 16 Word.word) . (let result = w__4 in (if negated then (FPNeg result :: ( 16 Word.word) M) else return result) \<bind> (\<lambda> (result :: 16 bits) . @@ -18188,8 +18196,8 @@ definition aarch64_float_arithmetic_mul_product :: " int \<Rightarrow> int \<Ri (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \<bind> (\<lambda> (operand1 :: 32 bits) . (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . - (FPMul operand1 operand2 w__6 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + (FPMul operand1 operand2 w__6 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) . (let result = w__7 in (if negated then (FPNeg result :: ( 32 Word.word) M) else return result) \<bind> (\<lambda> (result :: 32 bits) . @@ -18202,8 +18210,8 @@ definition aarch64_float_arithmetic_mul_product :: " int \<Rightarrow> int \<Ri (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \<bind> (\<lambda> (operand1 :: 64 bits) . (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . - (FPMul operand1 operand2 w__9 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + (FPMul operand1 operand2 w__9 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) . (let result = w__10 in (if negated then (FPNeg result :: ( 64 Word.word) M) else return result) \<bind> (\<lambda> (result :: 64 bits) . @@ -18216,8 +18224,8 @@ definition aarch64_float_arithmetic_mul_product :: " int \<Rightarrow> int \<Ri (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \<bind> (\<lambda> (result :: 128 bits) . (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \<bind> (\<lambda> (operand1 :: 128 bits) . (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) . - (FPMul operand1 operand2 w__12 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__13 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 bits) . + (FPMul operand1 operand2 w__12 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__13 :: 128 Word.word) . (let result = w__13 in (if negated then (FPNeg result :: ( 128 Word.word) M) else return result) \<bind> (\<lambda> (result :: 128 bits) . @@ -18244,8 +18252,8 @@ definition aarch64_float_arithmetic_mul_addsub :: " int \<Rightarrow> int \<Rig else return operanda) \<bind> (\<lambda> (operanda :: 8 bits) . (if op1_neg then (FPNeg operand1 :: ( 8 Word.word) M) else return operand1) \<bind> (\<lambda> (operand1 :: 8 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - (FPMulAdd operanda operand1 operand2 w__2 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . + (FPMulAdd operanda operand1 operand2 w__2 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 Word.word) . (let result = w__3 in aset_V d result)))))))))) else if (((l__103 = (( 16 :: int)::ii)))) then @@ -18261,8 +18269,8 @@ definition aarch64_float_arithmetic_mul_addsub :: " int \<Rightarrow> int \<Rig else return operanda) \<bind> (\<lambda> (operanda :: 16 bits) . (if op1_neg then (FPNeg operand1 :: ( 16 Word.word) M) else return operand1) \<bind> (\<lambda> (operand1 :: 16 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . - (FPMulAdd operanda operand1 operand2 w__6 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + (FPMulAdd operanda operand1 operand2 w__6 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . (let result = w__7 in aset_V d result)))))))))) else if (((l__103 = (( 32 :: int)::ii)))) then @@ -18278,8 +18286,8 @@ definition aarch64_float_arithmetic_mul_addsub :: " int \<Rightarrow> int \<Rig else return operanda) \<bind> (\<lambda> (operanda :: 32 bits) . (if op1_neg then (FPNeg operand1 :: ( 32 Word.word) M) else return operand1) \<bind> (\<lambda> (operand1 :: 32 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . - (FPMulAdd operanda operand1 operand2 w__10 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (FPMulAdd operanda operand1 operand2 w__10 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 Word.word) . (let result = w__11 in aset_V d result)))))))))) else if (((l__103 = (( 64 :: int)::ii)))) then @@ -18295,8 +18303,8 @@ definition aarch64_float_arithmetic_mul_addsub :: " int \<Rightarrow> int \<Rig else return operanda) \<bind> (\<lambda> (operanda :: 64 bits) . (if op1_neg then (FPNeg operand1 :: ( 64 Word.word) M) else return operand1) \<bind> (\<lambda> (operand1 :: 64 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 Word.word) . - (FPMulAdd operanda operand1 operand2 w__14 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . + (FPMulAdd operanda operand1 operand2 w__14 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 Word.word) . (let result = w__15 in aset_V d result)))))))))) else if (((l__103 = (( 128 :: int)::ii)))) then @@ -18312,8 +18320,8 @@ definition aarch64_float_arithmetic_mul_addsub :: " int \<Rightarrow> int \<Rig else return operanda) \<bind> (\<lambda> (operanda :: 128 bits) . (if op1_neg then (FPNeg operand1 :: ( 128 Word.word) M) else return operand1) \<bind> (\<lambda> (operand1 :: 128 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . - (FPMulAdd operanda operand1 operand2 w__18 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . + (FPMulAdd operanda operand1 operand2 w__18 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 Word.word) . (let result = w__19 in aset_V d result)))))))))) else @@ -18335,16 +18343,16 @@ definition aarch64_float_arithmetic_maxmin :: " int \<Rightarrow> int \<Rightar (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . (case operation of FPMaxMinOp_MAX => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (FPMax operand1 operand2 w__0 :: ( 8 Word.word) M)) | FPMaxMinOp_MIN => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . (FPMin operand1 operand2 w__2 :: ( 8 Word.word) M)) | FPMaxMinOp_MAXNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . (FPMaxNum operand1 operand2 w__4 :: ( 8 Word.word) M)) | FPMaxMinOp_MINNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . (FPMinNum operand1 operand2 w__6 :: ( 8 Word.word) M)) ) \<bind> (\<lambda> (result :: 8 bits) . aset_V d result))))) @@ -18358,16 +18366,16 @@ definition aarch64_float_arithmetic_maxmin :: " int \<Rightarrow> int \<Rightar (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . (case operation of FPMaxMinOp_MAX => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . (FPMax operand1 operand2 w__8 :: ( 16 Word.word) M)) | FPMaxMinOp_MIN => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . (FPMin operand1 operand2 w__10 :: ( 16 Word.word) M)) | FPMaxMinOp_MAXNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 bits) . (FPMaxNum operand1 operand2 w__12 :: ( 16 Word.word) M)) | FPMaxMinOp_MINNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . (FPMinNum operand1 operand2 w__14 :: ( 16 Word.word) M)) ) \<bind> (\<lambda> (result :: 16 bits) . aset_V d result))))) @@ -18381,16 +18389,16 @@ definition aarch64_float_arithmetic_maxmin :: " int \<Rightarrow> int \<Rightar (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . (case operation of FPMaxMinOp_MAX => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . (FPMax operand1 operand2 w__16 :: ( 32 Word.word) M)) | FPMaxMinOp_MIN => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . (FPMin operand1 operand2 w__18 :: ( 32 Word.word) M)) | FPMaxMinOp_MAXNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 bits) . (FPMaxNum operand1 operand2 w__20 :: ( 32 Word.word) M)) | FPMaxMinOp_MINNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__22 :: 32 bits) . (FPMinNum operand1 operand2 w__22 :: ( 32 Word.word) M)) ) \<bind> (\<lambda> (result :: 32 bits) . aset_V d result))))) @@ -18404,16 +18412,16 @@ definition aarch64_float_arithmetic_maxmin :: " int \<Rightarrow> int \<Rightar (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . (case operation of FPMaxMinOp_MAX => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 bits) . (FPMax operand1 operand2 w__24 :: ( 64 Word.word) M)) | FPMaxMinOp_MIN => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__26 :: 32 bits) . (FPMin operand1 operand2 w__26 :: ( 64 Word.word) M)) | FPMaxMinOp_MAXNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__28 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__28 :: 32 bits) . (FPMaxNum operand1 operand2 w__28 :: ( 64 Word.word) M)) | FPMaxMinOp_MINNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__30 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__30 :: 32 bits) . (FPMinNum operand1 operand2 w__30 :: ( 64 Word.word) M)) ) \<bind> (\<lambda> (result :: 64 bits) . aset_V d result))))) @@ -18427,16 +18435,16 @@ definition aarch64_float_arithmetic_maxmin :: " int \<Rightarrow> int \<Rightar (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . (case operation of FPMaxMinOp_MAX => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__32 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__32 :: 32 bits) . (FPMax operand1 operand2 w__32 :: ( 128 Word.word) M)) | FPMaxMinOp_MIN => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__34 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__34 :: 32 bits) . (FPMin operand1 operand2 w__34 :: ( 128 Word.word) M)) | FPMaxMinOp_MAXNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__36 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__36 :: 32 bits) . (FPMaxNum operand1 operand2 w__36 :: ( 128 Word.word) M)) | FPMaxMinOp_MINNUM => - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__38 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__38 :: 32 bits) . (FPMinNum operand1 operand2 w__38 :: ( 128 Word.word) M)) ) \<bind> (\<lambda> (result :: 128 bits) . aset_V d result))))) @@ -18457,8 +18465,8 @@ definition aarch64_float_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M)) \<bind> (\<lambda> (result :: 8 bits) . (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \<bind> (\<lambda> (operand1 :: 8 bits) . (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . - (FPDiv operand1 operand2 w__0 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . + (FPDiv operand1 operand2 w__0 :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . (let result = w__1 in aset_V d result))))))) else if (((l__93 = (( 16 :: int)::ii)))) then @@ -18469,8 +18477,8 @@ definition aarch64_float_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M)) \<bind> (\<lambda> (result :: 16 bits) . (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \<bind> (\<lambda> (operand1 :: 16 bits) . (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . - (FPDiv operand1 operand2 w__2 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . + (FPDiv operand1 operand2 w__2 :: ( 16 Word.word) M) \<bind> (\<lambda> (w__3 :: 16 Word.word) . (let result = w__3 in aset_V d result))))))) else if (((l__93 = (( 32 :: int)::ii)))) then @@ -18481,8 +18489,8 @@ definition aarch64_float_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (result :: 32 bits) . (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \<bind> (\<lambda> (operand1 :: 32 bits) . (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . - (FPDiv operand1 operand2 w__4 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . + (FPDiv operand1 operand2 w__4 :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . (let result = w__5 in aset_V d result))))))) else if (((l__93 = (( 64 :: int)::ii)))) then @@ -18493,8 +18501,8 @@ definition aarch64_float_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (result :: 64 bits) . (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \<bind> (\<lambda> (operand1 :: 64 bits) . (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . - (FPDiv operand1 operand2 w__6 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . + (FPDiv operand1 operand2 w__6 :: ( 64 Word.word) M) \<bind> (\<lambda> (w__7 :: 64 Word.word) . (let result = w__7 in aset_V d result))))))) else if (((l__93 = (( 128 :: int)::ii)))) then @@ -18505,8 +18513,8 @@ definition aarch64_float_arithmetic_div :: " int \<Rightarrow> int \<Rightarrow (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \<bind> (\<lambda> (result :: 128 bits) . (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \<bind> (\<lambda> (operand1 :: 128 bits) . (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . - (FPDiv operand1 operand2 w__8 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__9 :: 128 bits) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . + (FPDiv operand1 operand2 w__8 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__9 :: 128 Word.word) . (let result = w__9 in aset_V d result))))))) else @@ -18527,10 +18535,10 @@ definition aarch64_float_arithmetic_addsub :: " int \<Rightarrow> int \<Rightar (aget_V (( 8 :: int)::ii) n :: ( 8 Word.word) M) \<bind> (\<lambda> (operand1 :: 8 bits) . (aget_V (( 8 :: int)::ii) m :: ( 8 Word.word) M) \<bind> (\<lambda> (operand2 :: 8 bits) . (if sub_op then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (FPSub operand1 operand2 w__0 :: ( 8 Word.word) M)) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . (FPAdd operand1 operand2 w__2 :: ( 8 Word.word) M))) \<bind> (\<lambda> (result :: 8 bits) . aset_V d result))))) else if (((l__88 = (( 16 :: int)::ii)))) then @@ -18542,10 +18550,10 @@ definition aarch64_float_arithmetic_addsub :: " int \<Rightarrow> int \<Rightar (aget_V (( 16 :: int)::ii) n :: ( 16 Word.word) M) \<bind> (\<lambda> (operand1 :: 16 bits) . (aget_V (( 16 :: int)::ii) m :: ( 16 Word.word) M) \<bind> (\<lambda> (operand2 :: 16 bits) . (if sub_op then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . (FPSub operand1 operand2 w__4 :: ( 16 Word.word) M)) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . (FPAdd operand1 operand2 w__6 :: ( 16 Word.word) M))) \<bind> (\<lambda> (result :: 16 bits) . aset_V d result))))) else if (((l__88 = (( 32 :: int)::ii)))) then @@ -18557,10 +18565,10 @@ definition aarch64_float_arithmetic_addsub :: " int \<Rightarrow> int \<Rightar (aget_V (( 32 :: int)::ii) n :: ( 32 Word.word) M) \<bind> (\<lambda> (operand1 :: 32 bits) . (aget_V (( 32 :: int)::ii) m :: ( 32 Word.word) M) \<bind> (\<lambda> (operand2 :: 32 bits) . (if sub_op then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . (FPSub operand1 operand2 w__8 :: ( 32 Word.word) M)) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . (FPAdd operand1 operand2 w__10 :: ( 32 Word.word) M))) \<bind> (\<lambda> (result :: 32 bits) . aset_V d result))))) else if (((l__88 = (( 64 :: int)::ii)))) then @@ -18572,10 +18580,10 @@ definition aarch64_float_arithmetic_addsub :: " int \<Rightarrow> int \<Rightar (aget_V (( 64 :: int)::ii) n :: ( 64 Word.word) M) \<bind> (\<lambda> (operand1 :: 64 bits) . (aget_V (( 64 :: int)::ii) m :: ( 64 Word.word) M) \<bind> (\<lambda> (operand2 :: 64 bits) . (if sub_op then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 bits) . (FPSub operand1 operand2 w__12 :: ( 64 Word.word) M)) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 bits) . (FPAdd operand1 operand2 w__14 :: ( 64 Word.word) M))) \<bind> (\<lambda> (result :: 64 bits) . aset_V d result))))) else if (((l__88 = (( 128 :: int)::ii)))) then @@ -18587,10 +18595,10 @@ definition aarch64_float_arithmetic_addsub :: " int \<Rightarrow> int \<Rightar (aget_V (( 128 :: int)::ii) n :: ( 128 Word.word) M) \<bind> (\<lambda> (operand1 :: 128 bits) . (aget_V (( 128 :: int)::ii) m :: ( 128 Word.word) M) \<bind> (\<lambda> (operand2 :: 128 bits) . (if sub_op then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 bits) . (FPSub operand1 operand2 w__16 :: ( 128 Word.word) M)) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__18 :: 32 bits) . (FPAdd operand1 operand2 w__18 :: ( 128 Word.word) M))) \<bind> (\<lambda> (result :: 128 bits) . aset_V d result))))) else @@ -18793,7 +18801,7 @@ definition AArch64_CheckPermission :: " Permissions \<Rightarrow>(64)Word.word if fail1 then (let secondstage = False in (let s2fs1walk = False in - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__27 :: 52 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M) \<bind> (\<lambda> (w__27 :: 52 Word.word) . (let ipaddress = w__27 in AArch64_PermissionFault ipaddress level acctype ((\<not> failedread)) secondstage s2fs1walk)))) else AArch64_NoFault () )))))))))))))))))))))))))))" @@ -18921,7 +18929,7 @@ definition AArch64_TranslateAddress :: "(64)Word.word \<Rightarrow> AccType \<R (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_fault := w__0 |))) in return result)) else return result) \<bind> (\<lambda> (result :: AddressDescriptor) . - (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + (ZeroExtend__1 (( 64 :: int)::ii) vaddress :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let (result :: AddressDescriptor) = ((result (| AddressDescriptor_vaddress := w__1 |))) in return result)))))" @@ -18980,9 +18988,9 @@ definition aset_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ ((slice value_name (((( 8 :: int)::ii) * i)) (( 8 :: int)::ii) :: 8 Word.word))))) else if ((((((size1 = (( 16 :: int)::ii)))) \<and> ((((((acctype = AccType_VEC))) \<or> (((acctype = AccType_VECSTREAM))))))))) then AArch64_aset_MemSingle address (( 8 :: int)::ii) acctype aligned - ((slice value_name (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> + ((slice ((Word.ucast value_name :: 128 Word.word)) (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) \<then> AArch64_aset_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned - ((slice value_name (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) + ((slice ((Word.ucast value_name :: 128 Word.word)) (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) else AArch64_aset_MemSingle address size1 acctype aligned value_name))))))))))" @@ -19044,12 +19052,18 @@ definition aget_Mem :: "(64)Word.word \<Rightarrow> int \<Rightarrow> AccType \ (AArch64_aget_MemSingle address (( 8 :: int)::ii) acctype aligned :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let value_name = - ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 0 :: int)::ii) w__2 + ((Word.ucast + ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) + ((Word.ucast value_name :: 128 Word.word)) (( 0 :: int)::ii) w__2 + :: 128 Word.word)) :: ( 'p8_times_size_::len)Word.word)) in (AArch64_aget_MemSingle ((add_vec_int address (( 8 :: int)::ii) :: 64 Word.word)) (( 8 :: int)::ii) acctype aligned :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . (let value_name = - ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) value_name (( 64 :: int)::ii) w__3 + ((Word.ucast + ((set_slice (((( 8 :: int)::ii) * (( 16 :: int)::ii))) (( 64 :: int)::ii) + ((Word.ucast value_name :: 128 Word.word)) (( 64 :: int)::ii) w__3 + :: 128 Word.word)) :: ( 'p8_times_size_::len)Word.word)) in return value_name)))) else (AArch64_aget_MemSingle address size1 acctype aligned :: (( 'p8_times_size_::len)Word.word) M)) \<bind> (\<lambda> value_name . @@ -19070,7 +19084,7 @@ definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \<Right (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (offs :: 64 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (rval :: 128 bits) . - (undefined_bitvector esize :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (element :: 'esize bits) . + (undefined_bitvector esize :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> element . undefined_int () \<bind> (\<lambda> (s :: ii) . (let (ebytes :: int) = (ex_int ((esize div (( 8 :: int)::ii)))) in (assert_exp True ('''') \<then> @@ -19080,31 +19094,31 @@ definition aarch64_memory_vector_single_nowb :: "('datasize::len)itself \<Right (if replicate1 then (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (element, offs, t) (\<lambda> s varstup . (let (element, offs, t) = varstup in - (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'esize - bits) . + (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: + ( 'esize::len)Word.word) . (let element = w__2 in (let (v :: int) = (ex_int ((datasize div esize))) in (assert_exp True ('''') \<then> aset_V t ((replicate_bits element v :: ( 'datasize::len)Word.word))) \<then> ((let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in (let (t :: ii) = (((((ex_int t)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in - return (element, offs, t)))))))))) \<bind> (\<lambda> varstup . (let ((element :: 'esize bits), (offs :: 64 - bits), (t :: ii)) = varstup in + return (element, offs, t)))))))))) \<bind> (\<lambda> varstup . (let (element, (offs :: 64 bits), (t :: ii)) = varstup in return offs)) else (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, t) (\<lambda> s varstup . (let (offs, rval, t) = varstup in - (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__3 :: 128 bits) . + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__3 :: 128 Word.word) . (let rval = w__3 in (if (((memop = MemOp_LOAD))) then (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: ( 'esize::len)Word.word) . - (aset_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) w__4 - :: ( 128 Word.word) M) \<bind> (\<lambda> (w__5 :: 128 bits) . + (aset_Elem__0 rval index1 ((make_the_value esize )) w__4 :: ( 128 Word.word) M) \<bind> (\<lambda> (w__5 :: + 128 Word.word) . (let rval = w__5 in aset_V t rval \<then> return rval))) else - (aget_Elem__0 rval index1 ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__6 . + (aget_Elem__0 rval index1 ((make_the_value esize )) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + ( 'esize::len)Word.word) . aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__6 \<then> return rval)) \<bind> (\<lambda> (rval :: 128 bits) . (let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in @@ -19130,7 +19144,7 @@ definition aarch64_memory_vector_multiple_nowb :: "('datasize::len)itself \<Rig CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (offs :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (rval :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> rval . undefined_int () \<bind> (\<lambda> (e :: ii) . undefined_int () \<bind> (\<lambda> (r :: ii) . undefined_int () \<bind> (\<lambda> (s :: ii) . @@ -19147,23 +19161,24 @@ definition aarch64_memory_vector_multiple_nowb :: "('datasize::len)itself \<Rig (let tt = (((t + r)) mod (( 32 :: int)::ii)) in (foreachM (index_list (( 0 :: int)::ii) ((selem - (( 1 :: int)::ii))) (( 1 :: int)::ii)) (offs, rval, tt) (\<lambda> s varstup . (let (offs, rval, tt) = varstup in - (aget_V datasize tt :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . + (aget_V datasize tt :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'datasize::len)Word.word) . (let rval = w__2 in (if (((memop = MemOp_LOAD))) then (aget_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'esize::len)Word.word) . - (aset_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) w__3 - :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'datasize bits) . + (aset_Elem__0 rval e ((make_the_value esize )) w__3 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: + ( 'datasize::len)Word.word) . (let rval = w__4 in aset_V tt rval \<then> return rval))) else - (aget_Elem__0 rval e ((make_the_value esize :: ( 'esize::len)itself)) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> w__5 . + (aget_Elem__0 rval e ((make_the_value esize )) :: (( 'esize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + ( 'esize::len)Word.word) . aset_Mem ((add_vec address offs :: 64 Word.word)) ebytes AccType_VEC w__5 \<then> - return rval)) \<bind> (\<lambda> (rval :: 'datasize bits) . + return rval)) \<bind> (\<lambda> rval . (let (offs :: 64 bits) = ((add_vec_int offs ebytes :: 64 Word.word)) in (let (tt :: ii) = (((((ex_int tt)) + (( 1 :: int)::ii))) mod (( 32 :: int)::ii)) in - return (offs, rval, tt)))))))))))))))) \<bind> (\<lambda> varstup . (let ((offs :: 64 bits), (rval :: 'datasize - bits), (tt :: ii)) = varstup in + return (offs, rval, tt)))))))))))))))) \<bind> (\<lambda> varstup . (let ((offs :: 64 bits), rval, (tt :: + ii)) = varstup in if wback then (if (((m \<noteq> (( 31 :: int)::ii)))) then (aget_X (( 64 :: int)::ii) m :: ( 64 Word.word) M) else return offs) \<bind> (\<lambda> (offs :: 64 bits) . @@ -19191,12 +19206,12 @@ definition aarch64_memory_single_simdfp_register :: " AccType \<Rightarrow> int else address) in (case memop of MemOp_STORE => - (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 bits) . + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 Word.word) . (let data = w__2 in aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: + 8 Word.word) . (let data = w__3 in aset_V t data)) ) \<then> @@ -19222,12 +19237,12 @@ definition aarch64_memory_single_simdfp_register :: " AccType \<Rightarrow> int else address) in (case memop of MemOp_STORE => - (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 bits) . + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . (let data = w__6 in aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: + 16 Word.word) . (let data = w__7 in aset_V t data)) ) \<then> @@ -19253,12 +19268,12 @@ definition aarch64_memory_single_simdfp_register :: " AccType \<Rightarrow> int else address) in (case memop of MemOp_STORE => - (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (let data = w__10 in aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: + 32 Word.word) . (let data = w__11 in aset_V t data)) ) \<then> @@ -19284,12 +19299,12 @@ definition aarch64_memory_single_simdfp_register :: " AccType \<Rightarrow> int else address) in (case memop of MemOp_STORE => - (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 bits) . + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 Word.word) . (let data = w__14 in aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: + 64 Word.word) . (let data = w__15 in aset_V t data)) ) \<then> @@ -19315,12 +19330,12 @@ definition aarch64_memory_single_simdfp_register :: " AccType \<Rightarrow> int else address) in (case memop of MemOp_STORE => - (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 bits) . + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 Word.word) . (let data = w__18 in aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: + 128 Word.word) . (let data = w__19 in aset_V t data)) ) \<then> @@ -19354,12 +19369,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ else address) in (case memop of MemOp_STORE => - (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 bits) . + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 Word.word) . (let data = w__2 in aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: + 8 Word.word) . (let data = w__3 in aset_V t data)) ) \<then> @@ -19384,12 +19399,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ else address) in (case memop of MemOp_STORE => - (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 bits) . + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . (let data = w__6 in aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: + 16 Word.word) . (let data = w__7 in aset_V t data)) ) \<then> @@ -19414,12 +19429,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ else address) in (case memop of MemOp_STORE => - (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (let data = w__10 in aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: + 32 Word.word) . (let data = w__11 in aset_V t data)) ) \<then> @@ -19444,12 +19459,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ else address) in (case memop of MemOp_STORE => - (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 bits) . + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 Word.word) . (let data = w__14 in aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: + 64 Word.word) . (let data = w__15 in aset_V t data)) ) \<then> @@ -19474,12 +19489,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_postidx :: " AccType \ else address) in (case memop of MemOp_STORE => - (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 bits) . + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 Word.word) . (let data = w__18 in aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: + 128 Word.word) . (let data = w__19 in aset_V t data)) ) \<then> @@ -19513,12 +19528,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " Acc else address) in (case memop of MemOp_STORE => - (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 bits) . + (aget_V (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 Word.word) . (let data = w__2 in aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: + 8 Word.word) . (let data = w__3 in aset_V t data)) ) \<then> @@ -19543,12 +19558,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " Acc else address) in (case memop of MemOp_STORE => - (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 bits) . + (aget_V (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . (let data = w__6 in aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: + 16 Word.word) . (let data = w__7 in aset_V t data)) ) \<then> @@ -19573,12 +19588,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " Acc else address) in (case memop of MemOp_STORE => - (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (aget_V (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (let data = w__10 in aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: + 32 Word.word) . (let data = w__11 in aset_V t data)) ) \<then> @@ -19603,12 +19618,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " Acc else address) in (case memop of MemOp_STORE => - (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 bits) . + (aget_V (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__14 :: 64 Word.word) . (let data = w__14 in aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: + 64 Word.word) . (let data = w__15 in aset_V t data)) ) \<then> @@ -19633,12 +19648,12 @@ definition aarch64_memory_single_simdfp_immediate_signed_offset_normal :: " Acc else address) in (case memop of MemOp_STORE => - (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 bits) . + (aget_V (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__18 :: 128 Word.word) . (let data = w__18 in aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data)) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: + 128 Word.word) . (let data = w__19 in aset_V t data)) ) \<then> @@ -19662,20 +19677,20 @@ definition aarch64_memory_ordered :: " AccType \<Rightarrow>('datasize::len)its (let datasize = (size_itself_int datasize) in (assert_exp True (''datasize constraint'') \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data . (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in (assert_exp True ('''') \<then> (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . (case memop of MemOp_STORE => - (aget_X ((int (size data))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . + (aget_X ((int (size data))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'datasize::len)Word.word) . (let data = w__2 in aset_Mem address dbytes acctype data)) | MemOp_LOAD => - (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'datasize bits) . + (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'datasize::len)Word.word) . (let data = w__3 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: ( 'regsize::len)Word.word) . aset_X t w__4))) ))))))))" @@ -19763,14 +19778,14 @@ definition aarch64_memory_orderedrcpc :: " AccType \<Rightarrow>('datasize::len (let datasize = (size_itself_int datasize) in (assert_exp True (''datasize constraint'') \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data . (let dbytes = (ex_int ((datasize div (( 8 :: int)::ii)))) in (assert_exp True ('''') \<then> (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . + (aget_Mem address dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'datasize::len)Word.word) . (let data = w__2 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'regsize::len)Word.word) . aset_X t w__3))))))))))" @@ -19836,7 +19851,7 @@ definition aarch64_memory_literal_simdfp :: "(64)Word.word \<Rightarrow> int \< (let (address :: 64 bits) = ((add_vec w__0 offset :: 64 Word.word)) in (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (data :: 32 bits) . (CheckFPAdvSIMDEnabled64 () \<then> - (aget_Mem address (( 4 :: int)::ii) AccType_VEC :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__1 :: 32 bits) . + (aget_Mem address (( 4 :: int)::ii) AccType_VEC :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__1 :: 32 Word.word) . (let data = w__1 in aset_V t data))))) else if (((l__70 = (( 8 :: int)::ii)))) then @@ -19846,7 +19861,7 @@ definition aarch64_memory_literal_simdfp :: "(64)Word.word \<Rightarrow> int \< (let (address :: 64 bits) = ((add_vec w__2 offset :: 64 Word.word)) in (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (data :: 64 bits) . (CheckFPAdvSIMDEnabled64 () \<then> - (aget_Mem address (( 8 :: int)::ii) AccType_VEC :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 bits) . + (aget_Mem address (( 8 :: int)::ii) AccType_VEC :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__3 :: 64 Word.word) . (let data = w__3 in aset_V t data))))) else if (((l__70 = (( 16 :: int)::ii)))) then @@ -19856,7 +19871,7 @@ definition aarch64_memory_literal_simdfp :: "(64)Word.word \<Rightarrow> int \< (let (address :: 64 bits) = ((add_vec w__4 offset :: 64 Word.word)) in (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (data :: 128 bits) . (CheckFPAdvSIMDEnabled64 () \<then> - (aget_Mem address (( 16 :: int)::ii) AccType_VEC :: ( 128 Word.word) M)) \<bind> (\<lambda> (w__5 :: 128 bits) . + (aget_Mem address (( 16 :: int)::ii) AccType_VEC :: ( 128 Word.word) M)) \<bind> (\<lambda> (w__5 :: 128 Word.word) . (let data = w__5 in aset_V t data))))) else assert_exp True ('''') \<then> assert_exp True (''''))" @@ -19869,13 +19884,13 @@ definition aarch64_memory_literal_general :: " MemOp \<Rightarrow>(64)Word.word (let size1 = (size_itself_int size1) in (aget_PC () :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let (address :: 64 bits) = ((add_vec w__0 offset :: 64 Word.word)) in - (undefined_bitvector size1 :: (( 'size::len)Word.word) M) \<bind> (\<lambda> (data :: 'size bits) . + (undefined_bitvector size1 :: (( 'size::len)Word.word) M) \<bind> (\<lambda> data . (case memop of MemOp_LOAD => assert_exp True ('''') \<then> ((let bytes = (size1 div (( 8 :: int)::ii)) in (assert_exp True ('''') \<then> - (aget_Mem address bytes AccType_NORMAL :: (( 'size::len)Word.word) M)) \<bind> (\<lambda> (w__1 :: 'size bits) . + (aget_Mem address bytes AccType_NORMAL :: (( 'size::len)Word.word) M)) \<bind> (\<lambda> (w__1 :: ( 'size::len)Word.word) . (let data = w__1 in if signed then (SignExtend__0 data ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: @@ -19902,7 +19917,7 @@ definition memory_literal_general_decode :: "(2)Word.word \<Rightarrow>(1)Word. (let size1 = ((( 4 :: int)::ii)) in (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let offset = w__0 in aarch64_memory_literal_general MemOp_LOAD offset False ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t))))))))) @@ -19916,7 +19931,7 @@ definition memory_literal_general_decode :: "(2)Word.word \<Rightarrow>(1)Word. (let size1 = ((( 8 :: int)::ii)) in (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__1 :: 64 Word.word) . (let offset = w__1 in aarch64_memory_literal_general MemOp_LOAD offset False ((make_the_value (( 64 :: int)::ii) :: 64 itself)) t))))))))) @@ -19931,7 +19946,7 @@ definition memory_literal_general_decode :: "(2)Word.word \<Rightarrow>(1)Word. (let signed = True in (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 Word.word) . (let offset = w__2 in aarch64_memory_literal_general MemOp_LOAD offset True ((make_the_value (( 32 :: int)::ii) :: 32 itself)) t)))))))))) @@ -19945,7 +19960,7 @@ definition memory_literal_general_decode :: "(2)Word.word \<Rightarrow>(1)Word. (let memop = MemOp_PREFETCH in (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__3 :: 64 Word.word) . (let offset = w__3 in aarch64_memory_literal_general MemOp_PREFETCH offset False ((make_the_value (((( 8 :: int)::ii) * (( 32 :: int)::ii))) :: 256 itself)) t))))))))))" @@ -19965,12 +19980,12 @@ definition aarch64_memory_atomicops_swp :: " int \<Rightarrow> AccType \<Righta (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (data :: 8 bits) . (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__2 :: + 8 Word.word) . (let data = w__2 in (aget_X ((int (size data))) s :: ( 8 Word.word) M) \<bind> (\<lambda> w__3 . (aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__3 \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__4 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__4 :: ( 'regsize::len)Word.word) . aset_X t w__4)))))))))) else if (((l__65 = (( 16 :: int)::ii)))) then @@ -19983,12 +19998,12 @@ definition aarch64_memory_atomicops_swp :: " int \<Rightarrow> AccType \<Righta (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (data :: 16 bits) . (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: + 16 Word.word) . (let data = w__7 in (aget_X ((int (size data))) s :: ( 16 Word.word) M) \<bind> (\<lambda> w__8 . (aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__8 \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: ( 'regsize::len)Word.word) . aset_X t w__9)))))))))) else if (((l__65 = (( 32 :: int)::ii)))) then @@ -20001,12 +20016,12 @@ definition aarch64_memory_atomicops_swp :: " int \<Rightarrow> AccType \<Righta (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (data :: 32 bits) . (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: + 32 Word.word) . (let data = w__12 in (aget_X ((int (size data))) s :: ( 32 Word.word) M) \<bind> (\<lambda> w__13 . (aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__13 \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14)))))))))) else if (((l__65 = (( 64 :: int)::ii)))) then @@ -20019,12 +20034,12 @@ definition aarch64_memory_atomicops_swp :: " int \<Rightarrow> AccType \<Righta (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (data :: 64 bits) . (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__17 :: + 64 Word.word) . (let data = w__17 in (aget_X ((int (size address))) s :: ( 64 Word.word) M) \<bind> (\<lambda> w__18 . (aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__18 \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'regsize::len)Word.word) . aset_X t w__19)))))))))) else if (((l__65 = (( 128 :: int)::ii)))) then @@ -20037,12 +20052,12 @@ definition aarch64_memory_atomicops_swp :: " int \<Rightarrow> AccType \<Righta (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (data :: 128 bits) . (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__22 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__22 :: + 128 Word.word) . (let data = w__22 in (aget_X ((int (size data))) s :: ( 128 Word.word) M) \<bind> (\<lambda> w__23 . (aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype w__23 \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__24 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__24 :: ( 'regsize::len)Word.word) . aset_X t w__24)))))))))) else @@ -20064,12 +20079,12 @@ definition aarch64_memory_atomicops_st :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (value_name :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (data :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (result :: 8 bits) . - (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 Word.word) . (let value_name = w__0 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: + 8 Word.word) . (let data = w__3 in (let (result :: 8 bits) = ((case op1 of @@ -20091,12 +20106,12 @@ definition aarch64_memory_atomicops_st :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (value_name :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (data :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (result :: 16 bits) . - (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: 16 Word.word) . (let value_name = w__4 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: + 16 Word.word) . (let data = w__7 in (let (result :: 16 bits) = ((case op1 of @@ -20118,12 +20133,12 @@ definition aarch64_memory_atomicops_st :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (value_name :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (data :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (result :: 32 bits) . - (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__8 :: 32 Word.word) . (let value_name = w__8 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__11 :: + 32 Word.word) . (let data = w__11 in (let (result :: 32 bits) = ((case op1 of @@ -20145,12 +20160,12 @@ definition aarch64_memory_atomicops_st :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (value_name :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (data :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (result :: 64 bits) . - (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__12 :: 64 Word.word) . (let value_name = w__12 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: + 64 Word.word) . (let data = w__15 in (let (result :: 64 bits) = ((case op1 of @@ -20172,12 +20187,12 @@ definition aarch64_memory_atomicops_st :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (value_name :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (data :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (result :: 128 bits) . - (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__16 :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__16 :: 128 Word.word) . (let value_name = w__16 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__19 :: + 128 Word.word) . (let data = w__19 in (let (result :: 128 bits) = ((case op1 of @@ -20210,12 +20225,12 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (value_name :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (data :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (result :: 8 bits) . - (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 Word.word) . (let value_name = w__0 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__3 :: + 8 Word.word) . (let data = w__3 in (let (result :: 8 bits) = ((case op1 of @@ -20229,7 +20244,7 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data )) in (aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__4 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__4 :: ( 'regsize::len)Word.word) . aset_X t w__4)))))))))))))) else if (((l__55 = (( 16 :: int)::ii)))) then @@ -20242,12 +20257,12 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (value_name :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (data :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (result :: 16 bits) . - (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__5 :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__5 :: 16 Word.word) . (let value_name = w__5 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__8 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__8 :: + 16 Word.word) . (let data = w__8 in (let (result :: 16 bits) = ((case op1 of @@ -20261,7 +20276,7 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data )) in (aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: ( 'regsize::len)Word.word) . aset_X t w__9)))))))))))))) else if (((l__55 = (( 32 :: int)::ii)))) then @@ -20274,12 +20289,12 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (value_name :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (data :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (result :: 32 bits) . - (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__10 :: 32 Word.word) . (let value_name = w__10 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: + 32 Word.word) . (let data = w__13 in (let (result :: 32 bits) = ((case op1 of @@ -20293,7 +20308,7 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data )) in (aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14)))))))))))))) else if (((l__55 = (( 64 :: int)::ii)))) then @@ -20306,12 +20321,12 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (value_name :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (data :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (result :: 64 bits) . - (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__15 :: 64 Word.word) . (let value_name = w__15 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: + 64 Word.word) . (let data = w__18 in (let (result :: 64 bits) = ((case op1 of @@ -20325,7 +20340,7 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data )) in (aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'regsize::len)Word.word) . aset_X t w__19)))))))))))))) else if (((l__55 = (( 128 :: int)::ii)))) then @@ -20338,12 +20353,12 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (value_name :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (data :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (result :: 128 bits) . - (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__20 :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__20 :: 128 Word.word) . (let value_name = w__20 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__23 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__23 :: + 128 Word.word) . (let data = w__23 in (let (result :: 128 bits) = ((case op1 of @@ -20357,7 +20372,7 @@ definition aarch64_memory_atomicops_ld :: " int \<Rightarrow> AccType \<Rightar | MemAtomicOp_UMIN => if ((((Word.uint data)) > ((Word.uint value_name)))) then value_name else data )) in (aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype result \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__24 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__24 :: ( 'regsize::len)Word.word) . aset_X t w__24)))))))))))))) else @@ -20381,19 +20396,19 @@ definition aarch64_memory_atomicops_cas_single :: " int \<Rightarrow> AccType \ (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (comparevalue :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (newvalue :: 8 bits) . (undefined_bitvector (( 8 :: int)::ii) :: ( 8 Word.word) M) \<bind> (\<lambda> (data :: 8 bits) . - (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 bits) . + (aget_X (( 8 :: int)::ii) s :: ( 8 Word.word) M) \<bind> (\<lambda> (w__0 :: 8 Word.word) . (let comparevalue = w__0 in - (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 bits) . + (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M) \<bind> (\<lambda> (w__1 :: 8 Word.word) . (let newvalue = w__1 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in ((if (((data = comparevalue))) then aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__5 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X s w__5))))))))))))))) else if (((l__50 = (( 16 :: int)::ii)))) then @@ -20406,19 +20421,19 @@ definition aarch64_memory_atomicops_cas_single :: " int \<Rightarrow> AccType \ (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (comparevalue :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (newvalue :: 16 bits) . (undefined_bitvector (( 16 :: int)::ii) :: ( 16 Word.word) M) \<bind> (\<lambda> (data :: 16 bits) . - (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 bits) . + (aget_X (( 16 :: int)::ii) s :: ( 16 Word.word) M) \<bind> (\<lambda> (w__6 :: 16 Word.word) . (let comparevalue = w__6 in - (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 bits) . + (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M) \<bind> (\<lambda> (w__7 :: 16 Word.word) . (let newvalue = w__7 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__10 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__10 :: + 16 Word.word) . (let data = w__10 in ((if (((data = comparevalue))) then aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__11 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__11 :: ( 'regsize::len)Word.word) . aset_X s w__11))))))))))))))) else if (((l__50 = (( 32 :: int)::ii)))) then @@ -20431,19 +20446,19 @@ definition aarch64_memory_atomicops_cas_single :: " int \<Rightarrow> AccType \ (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (comparevalue :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (newvalue :: 32 bits) . (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (data :: 32 bits) . - (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 bits) . + (aget_X (( 32 :: int)::ii) s :: ( 32 Word.word) M) \<bind> (\<lambda> (w__12 :: 32 Word.word) . (let comparevalue = w__12 in - (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 bits) . + (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M) \<bind> (\<lambda> (w__13 :: 32 Word.word) . (let newvalue = w__13 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__16 :: + 32 Word.word) . (let data = w__16 in ((if (((data = comparevalue))) then aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__17 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__17 :: ( 'regsize::len)Word.word) . aset_X s w__17))))))))))))))) else if (((l__50 = (( 64 :: int)::ii)))) then @@ -20456,19 +20471,19 @@ definition aarch64_memory_atomicops_cas_single :: " int \<Rightarrow> AccType \ (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (comparevalue :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (newvalue :: 64 bits) . (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (data :: 64 bits) . - (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 bits) . + (aget_X (( 64 :: int)::ii) s :: ( 64 Word.word) M) \<bind> (\<lambda> (w__18 :: 64 Word.word) . (let comparevalue = w__18 in - (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 bits) . + (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M) \<bind> (\<lambda> (w__19 :: 64 Word.word) . (let newvalue = w__19 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__22 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__22 :: + 64 Word.word) . (let data = w__22 in ((if (((data = comparevalue))) then aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__23 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__23 :: ( 'regsize::len)Word.word) . aset_X s w__23))))))))))))))) else if (((l__50 = (( 128 :: int)::ii)))) then @@ -20481,19 +20496,19 @@ definition aarch64_memory_atomicops_cas_single :: " int \<Rightarrow> AccType \ (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (comparevalue :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (newvalue :: 128 bits) . (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M) \<bind> (\<lambda> (data :: 128 bits) . - (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__24 :: 128 bits) . + (aget_X (( 128 :: int)::ii) s :: ( 128 Word.word) M) \<bind> (\<lambda> (w__24 :: 128 Word.word) . (let comparevalue = w__24 in - (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__25 :: 128 bits) . + (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M) \<bind> (\<lambda> (w__25 :: 128 Word.word) . (let newvalue = w__25 in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__28 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__28 :: + 128 Word.word) . (let data = w__28 in ((if (((data = comparevalue))) then aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__29 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X s w__29))))))))))))))) else @@ -20531,29 +20546,25 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else (concat_vec t2 t1 :: 16 Word.word)) in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__4 :: + 16 Word.word) . (let data = w__4 in ((if (((data = comparevalue))) then aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__5 :: bool) . if w__5 then - (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . (aset_X s w__6 \<then> - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__7 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__7)) else - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: ( 'regsize::len)Word.word) . (aset_X s w__8 \<then> - (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 8 :: int)::ii) (( 8 :: int)::ii) :: 8 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__9 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__9))))))))))))))))))))) else if (((l__45 = (( 16 :: int)::ii)))) then @@ -20580,29 +20591,25 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else (concat_vec t2 t1 :: 32 Word.word)) in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__14 :: + 32 Word.word) . (let data = w__14 in ((if (((data = comparevalue))) then aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__15 :: bool) . if w__15 then - (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__16 :: ( 'regsize::len)Word.word) . (aset_X s w__16 \<then> - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__17 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__17)) else - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__18 :: ( 'regsize::len)Word.word) . (aset_X s w__18 \<then> - (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 16 :: int)::ii) (( 16 :: int)::ii) :: 16 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__19 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__19))))))))))))))))))))) else if (((l__45 = (( 32 :: int)::ii)))) then @@ -20629,29 +20636,25 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else (concat_vec t2 t1 :: 64 Word.word)) in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__24 :: + 64 Word.word) . (let data = w__24 in ((if (((data = comparevalue))) then aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__25 :: bool) . if w__25 then - (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__26 :: ( 'regsize::len)Word.word) . (aset_X s w__26 \<then> - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__27 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__27)) else - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__28 :: ( 'regsize::len)Word.word) . (aset_X s w__28 \<then> - (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 32 :: int)::ii) (( 32 :: int)::ii) :: 32 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__29))))))))))))))))))))) else if (((l__45 = (( 64 :: int)::ii)))) then @@ -20678,29 +20681,25 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else (concat_vec t2 t1 :: 128 Word.word)) in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__34 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__34 :: + 128 Word.word) . (let data = w__34 in ((if (((data = comparevalue))) then aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__35 :: bool) . if w__35 then - (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__36 :: ( 'regsize::len)Word.word) . (aset_X s w__36 \<then> - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__37)) else - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . (aset_X s w__38 \<then> - (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 64 :: int)::ii) (( 64 :: int)::ii) :: 64 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__39 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__39))))))))))))))))))))) else if (((l__45 = (( 128 :: int)::ii)))) then @@ -20727,29 +20726,25 @@ definition aarch64_memory_atomicops_cas_pair :: " int \<Rightarrow> AccType \<R else (concat_vec t2 t1 :: 256 Word.word)) in (if (((n = (( 31 :: int)::ii)))) then CheckSPAlignment () \<then> (aget_SP (( 64 :: int)::ii) () :: ( 64 Word.word) M) else (aget_X (( 64 :: int)::ii) n :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (aget_Mem address (((( 256 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 256 Word.word) M) \<bind> (\<lambda> (w__44 :: 256 - bits) . + (aget_Mem address (((( 256 :: int)::ii) div (( 8 :: int)::ii))) ldacctype :: ( 256 Word.word) M) \<bind> (\<lambda> (w__44 :: + 256 Word.word) . (let data = w__44 in ((if (((data = comparevalue))) then aset_Mem address (((( 256 :: int)::ii) div (( 8 :: int)::ii))) stacctype newvalue else return () ) \<then> BigEndian () ) \<bind> (\<lambda> (w__45 :: bool) . if w__45 then - (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__46 :: ( 'regsize::len)Word.word) . (aset_X s w__46 \<then> - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__47 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__47)) else - (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 0 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__48 :: ( 'regsize::len)Word.word) . (aset_X s w__48 \<then> - (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) - ((make_the_value regsize :: ( 'regsize::len)itself)) + (ZeroExtend__0 ((slice data (( 128 :: int)::ii) (( 128 :: int)::ii) :: 128 Word.word)) ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M)) \<bind> (\<lambda> (w__49 :: ( 'regsize::len)Word.word) . aset_X ((s + (( 1 :: int)::ii))) w__49))))))))))))))))))))) else @@ -20828,7 +20823,7 @@ definition AArch32_GenerateDebugExceptionsFrom :: "(2)Word.word \<Rightarrow> b (ELStateUsingAArch32 EL1 secure \<bind> (\<lambda> (w__0 :: bool) . return ((\<not> w__0)))) \<bind> (\<lambda> (w__1 :: bool) . if w__1 then - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M) \<bind> (\<lambda> (w__2 :: 1 Word.word) . (let mask1 = w__2 in AArch64_GenerateDebugExceptionsFrom from1 secure mask1)) else @@ -20914,7 +20909,7 @@ definition DebugExceptionReturnSS :: "(32)Word.word \<Rightarrow>((register_val else (let mask1 = ((vec_of_bits [access_vec_dec spsr (( 9 :: int)::ii)] :: 1 Word.word)) in AArch64_GenerateDebugExceptionsFrom dest secure mask1)) \<bind> (\<lambda> (enabled_at_dest :: bool) . - (DebugTargetFrom secure :: ( 2 Word.word) M) \<bind> (\<lambda> (w__17 :: 2 bits) . + (DebugTargetFrom secure :: ( 2 Word.word) M) \<bind> (\<lambda> (w__17 :: 2 Word.word) . (let ELd = w__17 in and_boolM (and_boolM (ELUsingAArch32 ELd \<bind> (\<lambda> (w__18 :: bool) . return ((\<not> w__18)))) @@ -20932,7 +20927,7 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u " SetPSTATEFromPSR spsr__arg = ( (let spsr = spsr__arg in read_reg PSTATE_ref \<bind> (\<lambda> (w__0 :: ProcState) . - (DebugExceptionReturnSS spsr :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 bits) . + (DebugExceptionReturnSS spsr :: ( 1 Word.word) M) \<bind> (\<lambda> (w__1 :: 1 Word.word) . (write_reg PSTATE_ref (w__0 (| ProcState_SS := w__1 |)) \<then> IllegalExceptionReturn spsr) \<bind> (\<lambda> (w__2 :: bool) . ((if w__2 then @@ -20988,7 +20983,7 @@ definition SetPSTATEFromPSR :: "(32)Word.word \<Rightarrow>((register_value),(u PSTATE_ref (w__17 (| ProcState_Q := ((vec_of_bits [access_vec_dec spsr (( 27 :: int)::ii)] :: 1 Word.word))|)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__18 :: ProcState) . - (RestoredITBits spsr :: ( 8 Word.word) M) \<bind> (\<lambda> (w__19 :: 8 bits) . + (RestoredITBits spsr :: ( 8 Word.word) M) \<bind> (\<lambda> (w__19 :: 8 Word.word) . (write_reg PSTATE_ref (w__18 (| ProcState_IT := w__19 |)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__20 :: ProcState) . (write_reg PSTATE_ref (w__20 (| ProcState_GE := ((slice spsr (( 16 :: int)::ii) (( 4 :: int)::ii) :: 4 Word.word))|)) \<then> @@ -21057,7 +21052,7 @@ definition DRPSInstruction :: " unit \<Rightarrow>((register_value),(unit),(exc (SetPSTATEFromPSR w__4 \<then> UsingAArch32 () ) \<bind> (\<lambda> (w__5 :: bool) . (if w__5 then - (undefined_bitvector (( 13 :: int)::ii) :: ( 13 Word.word) M) \<bind> (\<lambda> (w__6 :: 13 bits) . + (undefined_bitvector (( 13 :: int)::ii) :: ( 13 Word.word) M) \<bind> (\<lambda> (w__6 :: 13 Word.word) . (let split_vec = w__6 in (let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8, tup__9) = ((subrange_vec_dec split_vec (( 12 :: int)::ii) (( 12 :: int)::ii) :: 1 Word.word), @@ -21096,12 +21091,12 @@ definition DRPSInstruction :: " unit \<Rightarrow>((register_value),(unit),(exc (w__17 (| ProcState_IT := ((vec_of_bits [B0,B0,B0,B0,B0,B0,B0,B0] :: 8 Word.word))|)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__18 :: ProcState) . (write_reg PSTATE_ref (w__18 (| ProcState_T := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__19 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__19 :: 32 Word.word) . (write_reg DLR_ref w__19 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__20 :: 32 Word.word) . write_reg DSPSR_ref w__20))))))))))))))))) else - (undefined_bitvector (( 9 :: int)::ii) :: ( 9 Word.word) M) \<bind> (\<lambda> (w__21 :: 9 bits) . + (undefined_bitvector (( 9 :: int)::ii) :: ( 9 Word.word) M) \<bind> (\<lambda> (w__21 :: 9 Word.word) . (let split_vec = w__21 in (let (tup__0, tup__1, tup__2, tup__3, tup__4, tup__5, tup__6, tup__7, tup__8) = ((subrange_vec_dec split_vec (( 8 :: int)::ii) (( 8 :: int)::ii) :: 1 Word.word), @@ -21131,9 +21126,9 @@ definition DRPSInstruction :: " unit \<Rightarrow>((register_value),(unit),(exc (write_reg PSTATE_ref (w__29 (| ProcState_I := tup__7 |)) \<then> read_reg PSTATE_ref) \<bind> (\<lambda> (w__30 :: ProcState) . (write_reg PSTATE_ref (w__30 (| ProcState_F := tup__8 |)) \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 Word.word) . (write_reg DLR_EL0_ref w__31 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 Word.word) . write_reg DSPSR_EL0_ref w__32))))))))))))))) \<then> UpdateEDSCRFields () ))))))" @@ -21321,7 +21316,7 @@ definition UnallocatedEncoding :: " unit \<Rightarrow>((register_value),(unit), " UnallocatedEncoding _ = ( and_boolM ((UsingAArch32 () )) ((AArch32_ExecutingCP10or11Instr () )) \<bind> (\<lambda> (w__2 :: bool) . ((if w__2 then - (read_reg FPEXC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (read_reg FPEXC_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . write_reg FPEXC_ref ((set_slice (( 32 :: int)::ii) (( 1 :: int)::ii) w__3 (( 29 :: int)::ii) (vec_of_bits [B0] :: 1 Word.word) :: 32 Word.word))) @@ -21406,15 +21401,15 @@ definition aarch64_memory_single_general_register :: " AccType \<Rightarrow> in else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \<bind> (\<lambda> (data :: 8 bits) . aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X t w__5) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . aset_X t w__6))) | MemOp_PREFETCH => @@ -21468,15 +21463,15 @@ definition aarch64_memory_single_general_register :: " AccType \<Rightarrow> in else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \<bind> (\<lambda> (data :: 16 bits) . aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: + 16 Word.word) . (let data = w__12 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: ( 'regsize::len)Word.word) . aset_X t w__13) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14))) | MemOp_PREFETCH => @@ -21530,15 +21525,15 @@ definition aarch64_memory_single_general_register :: " AccType \<Rightarrow> in else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \<bind> (\<lambda> (data :: 32 bits) . aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: + 32 Word.word) . (let data = w__20 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: ( 'regsize::len)Word.word) . aset_X t w__21) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: ( 'regsize::len)Word.word) . aset_X t w__22))) | MemOp_PREFETCH => @@ -21592,15 +21587,15 @@ definition aarch64_memory_single_general_register :: " AccType \<Rightarrow> in else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \<bind> (\<lambda> (data :: 64 bits) . aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: + 64 Word.word) . (let data = w__28 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: ( 'regsize::len)Word.word) . aset_X t w__30))) | MemOp_PREFETCH => @@ -21654,15 +21649,15 @@ definition aarch64_memory_single_general_register :: " AccType \<Rightarrow> in else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \<bind> (\<lambda> (data :: 128 bits) . aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: + 128 Word.word) . (let data = w__36 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X t w__37) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . aset_X t w__38))) | MemOp_PREFETCH => @@ -21726,15 +21721,15 @@ definition aarch64_memory_single_general_immediate_unsigned :: " AccType \<Righ else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \<bind> (\<lambda> (data :: 8 bits) . aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X t w__5) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . aset_X t w__6))) | MemOp_PREFETCH => @@ -21787,15 +21782,15 @@ definition aarch64_memory_single_general_immediate_unsigned :: " AccType \<Righ else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \<bind> (\<lambda> (data :: 16 bits) . aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: + 16 Word.word) . (let data = w__12 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: ( 'regsize::len)Word.word) . aset_X t w__13) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14))) | MemOp_PREFETCH => @@ -21848,15 +21843,15 @@ definition aarch64_memory_single_general_immediate_unsigned :: " AccType \<Righ else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \<bind> (\<lambda> (data :: 32 bits) . aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: + 32 Word.word) . (let data = w__20 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: ( 'regsize::len)Word.word) . aset_X t w__21) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: ( 'regsize::len)Word.word) . aset_X t w__22))) | MemOp_PREFETCH => @@ -21909,15 +21904,15 @@ definition aarch64_memory_single_general_immediate_unsigned :: " AccType \<Righ else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \<bind> (\<lambda> (data :: 64 bits) . aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: + 64 Word.word) . (let data = w__28 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: ( 'regsize::len)Word.word) . aset_X t w__30))) | MemOp_PREFETCH => @@ -21970,15 +21965,15 @@ definition aarch64_memory_single_general_immediate_unsigned :: " AccType \<Righ else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \<bind> (\<lambda> (data :: 128 bits) . aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: + 128 Word.word) . (let data = w__36 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X t w__37) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . aset_X t w__38))) | MemOp_PREFETCH => @@ -22042,15 +22037,15 @@ definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \<bind> (\<lambda> (data :: 8 bits) . aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X t w__5) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . aset_X t w__6))) | MemOp_PREFETCH => @@ -22103,15 +22098,15 @@ definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \<bind> (\<lambda> (data :: 16 bits) . aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: + 16 Word.word) . (let data = w__12 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: ( 'regsize::len)Word.word) . aset_X t w__13) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14))) | MemOp_PREFETCH => @@ -22164,15 +22159,15 @@ definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \<bind> (\<lambda> (data :: 32 bits) . aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: + 32 Word.word) . (let data = w__20 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: ( 'regsize::len)Word.word) . aset_X t w__21) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: ( 'regsize::len)Word.word) . aset_X t w__22))) | MemOp_PREFETCH => @@ -22225,15 +22220,15 @@ definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \<bind> (\<lambda> (data :: 64 bits) . aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: + 64 Word.word) . (let data = w__28 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: ( 'regsize::len)Word.word) . aset_X t w__30))) | MemOp_PREFETCH => @@ -22286,15 +22281,15 @@ definition aarch64_memory_single_general_immediate_signed_postidx :: " AccType else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \<bind> (\<lambda> (data :: 128 bits) . aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: + 128 Word.word) . (let data = w__36 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X t w__37) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . aset_X t w__38))) | MemOp_PREFETCH => @@ -22350,7 +22345,7 @@ definition aarch64_memory_single_general_immediate_signed_pac :: " int \<Righta (aget_X (( 64 :: int)::ii) (( 31 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__4 :: 64 Word.word) . (AuthDB address w__4 :: ( 64 Word.word) M))) \<bind> (\<lambda> (address :: 64 bits) . (let address = ((add_vec address offset :: 64 Word.word)) in - (aget_Mem address (( 8 :: int)::ii) AccType_NORMAL :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 bits) . + (aget_Mem address (( 8 :: int)::ii) AccType_NORMAL :: ( 64 Word.word) M) \<bind> (\<lambda> (w__6 :: 64 Word.word) . (let data = w__6 in aset_X t data \<then> (if wback then @@ -22401,15 +22396,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " Ac else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \<bind> (\<lambda> (data :: 8 bits) . aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X t w__5) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . aset_X t w__6))) | MemOp_PREFETCH => @@ -22462,15 +22457,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " Ac else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \<bind> (\<lambda> (data :: 16 bits) . aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: + 16 Word.word) . (let data = w__12 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: ( 'regsize::len)Word.word) . aset_X t w__13) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14))) | MemOp_PREFETCH => @@ -22523,15 +22518,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " Ac else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \<bind> (\<lambda> (data :: 32 bits) . aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: + 32 Word.word) . (let data = w__20 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: ( 'regsize::len)Word.word) . aset_X t w__21) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: ( 'regsize::len)Word.word) . aset_X t w__22))) | MemOp_PREFETCH => @@ -22584,15 +22579,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " Ac else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \<bind> (\<lambda> (data :: 64 bits) . aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: + 64 Word.word) . (let data = w__28 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: ( 'regsize::len)Word.word) . aset_X t w__30))) | MemOp_PREFETCH => @@ -22645,15 +22640,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_unpriv :: " Ac else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \<bind> (\<lambda> (data :: 128 bits) . aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: + 128 Word.word) . (let data = w__36 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X t w__37) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . aset_X t w__38))) | MemOp_PREFETCH => @@ -22717,15 +22712,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_normal :: " Ac else (aget_X (( 8 :: int)::ii) t :: ( 8 Word.word) M)) \<bind> (\<lambda> (data :: 8 bits) . aset_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: 8 - bits) . + (aget_Mem address (((( 8 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__4 :: + 8 Word.word) . (let data = w__4 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: ( 'regsize::len)Word.word) . aset_X t w__5) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: ( 'regsize::len)Word.word) . aset_X t w__6))) | MemOp_PREFETCH => @@ -22778,15 +22773,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_normal :: " Ac else (aget_X (( 16 :: int)::ii) t :: ( 16 Word.word) M)) \<bind> (\<lambda> (data :: 16 bits) . aset_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: 16 - bits) . + (aget_Mem address (((( 16 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__12 :: + 16 Word.word) . (let data = w__12 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__13 :: ( 'regsize::len)Word.word) . aset_X t w__13) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14))) | MemOp_PREFETCH => @@ -22839,15 +22834,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_normal :: " Ac else (aget_X (( 32 :: int)::ii) t :: ( 32 Word.word) M)) \<bind> (\<lambda> (data :: 32 bits) . aset_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: 32 - bits) . + (aget_Mem address (((( 32 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__20 :: + 32 Word.word) . (let data = w__20 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__21 :: ( 'regsize::len)Word.word) . aset_X t w__21) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__22 :: ( 'regsize::len)Word.word) . aset_X t w__22))) | MemOp_PREFETCH => @@ -22900,15 +22895,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_normal :: " Ac else (aget_X (( 64 :: int)::ii) t :: ( 64 Word.word) M)) \<bind> (\<lambda> (data :: 64 bits) . aset_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: 64 - bits) . + (aget_Mem address (((( 64 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__28 :: + 64 Word.word) . (let data = w__28 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__30 :: ( 'regsize::len)Word.word) . aset_X t w__30))) | MemOp_PREFETCH => @@ -22961,15 +22956,15 @@ definition aarch64_memory_single_general_immediate_signed_offset_normal :: " Ac else (aget_X (( 128 :: int)::ii) t :: ( 128 Word.word) M)) \<bind> (\<lambda> (data :: 128 bits) . aset_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype data) | MemOp_LOAD => - (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: 128 - bits) . + (aget_Mem address (((( 128 :: int)::ii) div (( 8 :: int)::ii))) acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__36 :: + 128 Word.word) . (let data = w__36 in if signed then - (SignExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: + (SignExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__37 :: ( 'regsize::len)Word.word) . aset_X t w__37) else - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__38 :: ( 'regsize::len)Word.word) . aset_X t w__38))) | MemOp_PREFETCH => @@ -23003,8 +22998,8 @@ definition aarch64_memory_pair_simdfp_postidx :: " AccType \<Rightarrow>('datas assert_exp True (''dbytes constraint'')) \<then> CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data1 :: 'datasize bits) . - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data2 :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data1 . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data2 . (let (rt_unknown :: bool) = False in (if ((((((memop = MemOp_LOAD))) \<and> (((t = t2)))))) then (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in @@ -23022,29 +23017,28 @@ definition aarch64_memory_pair_simdfp_postidx :: " AccType \<Rightarrow>('datas else address) in (case memop of MemOp_STORE => - (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . + (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'datasize::len)Word.word) . (let data1 = w__2 in - (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'datasize bits) . + (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'datasize::len)Word.word) . (let data2 = w__3 in aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \<then> aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)))) | MemOp_LOAD => - (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: + ( 'datasize::len)Word.word) . (let data1 = w__4 in - (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + ( 'datasize::len)Word.word) . (let data2 = w__5 in (if rt_unknown then - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: 'datasize - bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + ( 'datasize::len)Word.word) . (let data1 = w__6 in - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: 'datasize - bits) . - (let (data2 :: 'datasize bits) = w__7 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: + ( 'datasize::len)Word.word) . + (let data2 = w__7 in return (data1, data2))))) - else return (data1, data2)) \<bind> (\<lambda> varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize - bits)) = varstup in + else return (data1, data2)) \<bind> (\<lambda> varstup . (let (data1, data2) = varstup in aset_V t data1 \<then> aset_V t2 data2)))))) ) \<then> (if wback then @@ -23066,8 +23060,8 @@ definition aarch64_memory_pair_simdfp_noalloc :: " AccType \<Rightarrow>('datas assert_exp True (''dbytes constraint'')) \<then> CheckFPAdvSIMDEnabled64 () ) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data1 :: 'datasize bits) . - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data2 :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data1 . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data2 . (let (rt_unknown :: bool) = False in (if ((((((memop = MemOp_LOAD))) \<and> (((t = t2)))))) then (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in @@ -23085,29 +23079,28 @@ definition aarch64_memory_pair_simdfp_noalloc :: " AccType \<Rightarrow>('datas else address) in (case memop of MemOp_STORE => - (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: 'datasize bits) . + (aget_V ((int (size data1))) t :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__2 :: ( 'datasize::len)Word.word) . (let data1 = w__2 in - (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: 'datasize bits) . + (aget_V ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__3 :: ( 'datasize::len)Word.word) . (let data2 = w__3 in aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \<then> aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)))) | MemOp_LOAD => - (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__4 :: + ( 'datasize::len)Word.word) . (let data1 = w__4 in - (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__5 :: + ( 'datasize::len)Word.word) . (let data2 = w__5 in (if rt_unknown then - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: 'datasize - bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + ( 'datasize::len)Word.word) . (let data1 = w__6 in - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: 'datasize - bits) . - (let (data2 :: 'datasize bits) = w__7 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: + ( 'datasize::len)Word.word) . + (let data2 = w__7 in return (data1, data2))))) - else return (data1, data2)) \<bind> (\<lambda> varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize - bits)) = varstup in + else return (data1, data2)) \<bind> (\<lambda> varstup . (let (data1, data2) = varstup in aset_V t data1 \<then> aset_V t2 data2)))))) ) \<then> (if wback then @@ -23129,8 +23122,8 @@ definition aarch64_memory_pair_general_postidx :: " AccType \<Rightarrow>('data assert_exp True (''dbytes constraint'')) \<then> ((let wback = wback__arg in (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data1 :: 'datasize bits) . - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data2 :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data1 . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data2 . (let (rt_unknown :: bool) = False in (let (wb_unknown :: bool) = False in (if ((((((((((((memop = MemOp_LOAD))) \<and> wback))) \<and> ((((((t = n))) \<or> (((t2 = n))))))))) \<and> (((n \<noteq> (( 31 :: int)::ii))))))) then @@ -23175,29 +23168,28 @@ definition aarch64_memory_pair_general_postidx :: " AccType \<Rightarrow>('data MemOp_STORE => (if (((rt_unknown \<and> (((t = n)))))) then (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) - else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (data1 :: 'datasize bits) . + else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> data1 . (if (((rt_unknown \<and> (((t2 = n)))))) then (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) - else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (data2 :: 'datasize bits) . + else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> data2 . aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \<then> aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)) | MemOp_LOAD => - (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + ( 'datasize::len)Word.word) . (let data1 = w__6 in - (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: + ( 'datasize::len)Word.word) . (let data2 = w__7 in (if rt_unknown then - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: 'datasize - bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: + ( 'datasize::len)Word.word) . (let data1 = w__8 in - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: 'datasize - bits) . - (let (data2 :: 'datasize bits) = w__9 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: + ( 'datasize::len)Word.word) . + (let data2 = w__9 in return (data1, data2))))) - else return (data1, data2)) \<bind> (\<lambda> varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize - bits)) = varstup in + else return (data1, data2)) \<bind> (\<lambda> varstup . (let (data1, data2) = varstup in if signed then (SignExtend__0 data1 ((make_the_value (( 64 :: int)::ii) :: 64 itself)) :: ( 64 Word.word) M) \<bind> (\<lambda> (w__10 :: 64 Word.word) . @@ -23228,8 +23220,8 @@ definition aarch64_memory_pair_general_noalloc :: " AccType \<Rightarrow>('data ((assert_exp True (''datasize constraint'') \<then> assert_exp True (''dbytes constraint'')) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (address :: 64 bits) . - (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data1 :: 'datasize bits) . - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (data2 :: 'datasize bits) . + (undefined_bitvector datasize :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data1 . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> data2 . (let (rt_unknown :: bool) = False in (if ((((((memop = MemOp_LOAD))) \<and> (((t = t2)))))) then (let (c :: Constraint) = (ConstrainUnpredictable Unpredictable_LDPOVERLAP) in @@ -23249,29 +23241,28 @@ definition aarch64_memory_pair_general_noalloc :: " AccType \<Rightarrow>('data MemOp_STORE => (if (((rt_unknown \<and> (((t = n)))))) then (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) - else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (data1 :: 'datasize bits) . + else (aget_X ((int (size data1))) t :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> data1 . (if (((rt_unknown \<and> (((t2 = n)))))) then (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) - else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> (data2 :: 'datasize bits) . + else (aget_X ((int (size data1))) t2 :: (( 'datasize::len)Word.word) M)) \<bind> (\<lambda> data2 . aset_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype data1 \<then> aset_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype data2)) | MemOp_LOAD => - (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address (( 0 :: int)::ii) :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__6 :: + ( 'datasize::len)Word.word) . (let data1 = w__6 in - (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: 'datasize - bits) . + (aget_Mem ((add_vec_int address dbytes :: 64 Word.word)) dbytes acctype :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__7 :: + ( 'datasize::len)Word.word) . (let data2 = w__7 in (if rt_unknown then - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: 'datasize - bits) . + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__8 :: + ( 'datasize::len)Word.word) . (let data1 = w__8 in - (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: 'datasize - bits) . - (let (data2 :: 'datasize bits) = w__9 in + (undefined_bitvector ((int (size data1))) :: (( 'datasize::len)Word.word) M) \<bind> (\<lambda> (w__9 :: + ( 'datasize::len)Word.word) . + (let data2 = w__9 in return (data1, data2))))) - else return (data1, data2)) \<bind> (\<lambda> varstup . (let ((data1 :: 'datasize bits), (data2 :: 'datasize - bits)) = varstup in + else return (data1, data2)) \<bind> (\<lambda> varstup . (let (data1, data2) = varstup in aset_X t data1 \<then> aset_X t2 data2)))))) ) \<then> (if wback then @@ -23348,7 +23339,7 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize (if pair then assert_exp True ('''') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . aset_X t w__9) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -23364,9 +23355,9 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize 64 Word.word) . aset_X t2 w__12))) else - (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__13 :: 8 bits) . + (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__13 :: 8 Word.word) . (let data = w__13 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14)))) ))))))))))))) @@ -23431,7 +23422,7 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize (if pair then assert_exp True ('''') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 Word.word) . aset_X t w__24) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -23447,9 +23438,9 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize 64 Word.word) . aset_X t2 w__27))) else - (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__28 :: 16 bits) . + (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__28 :: 16 Word.word) . (let data = w__28 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29)))) ))))))))))))) @@ -23514,7 +23505,7 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize (if pair then assert_exp True ('''') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__39 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__39 :: 32 Word.word) . aset_X t w__39) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -23530,9 +23521,9 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize 64 Word.word) . aset_X t2 w__42))) else - (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__43 :: 32 bits) . + (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__43 :: 32 Word.word) . (let data = w__43 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__44 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__44 :: ( 'regsize::len)Word.word) . aset_X t w__44)))) ))))))))))))) @@ -23597,10 +23588,10 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize (if pair then assert_exp True ('''') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__54 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__54 :: 32 Word.word) . aset_X t w__54) else if (((elsize = (( 32 :: int)::ii)))) then - (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__55 :: 64 bits) . + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__55 :: 64 Word.word) . (let data = w__55 in BigEndian () \<bind> (\<lambda> (w__56 :: bool) . if w__56 then @@ -23625,9 +23616,9 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize 64 Word.word) . aset_X t2 w__59))) else - (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 bits) . + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 Word.word) . (let data = w__60 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__61 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__61 :: ( 'regsize::len)Word.word) . aset_X t w__61)))) ))))))))))))) @@ -23692,10 +23683,10 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize (if pair then assert_exp True ('''') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__71 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__71 :: 32 Word.word) . aset_X t w__71) else if (((elsize = (( 32 :: int)::ii)))) then - (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__72 :: 128 bits) . + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__72 :: 128 Word.word) . (let data = w__72 in BigEndian () \<bind> (\<lambda> (w__73 :: bool) . if w__73 then @@ -23720,9 +23711,9 @@ definition aarch64_memory_exclusive_single :: " AccType \<Rightarrow>('datasize 64 Word.word) . aset_X t2 w__76))) else - (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__77 :: 128 bits) . + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__77 :: 128 Word.word) . (let data = w__77 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__78 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__78 :: ( 'regsize::len)Word.word) . aset_X t w__78)))) ))))))))))))) @@ -23877,7 +23868,7 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: (if pair then assert_exp True (''datasize constraint'') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__9 :: 32 Word.word) . aset_X t w__9) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -23893,9 +23884,9 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: 64 Word.word) . aset_X t2 w__12))) else - (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__13 :: 8 bits) . + (aget_Mem address dbytes acctype :: ( 8 Word.word) M) \<bind> (\<lambda> (w__13 :: 8 Word.word) . (let data = w__13 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__14 :: ( 'regsize::len)Word.word) . aset_X t w__14)))) ))))))))))))) @@ -23960,7 +23951,7 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: (if pair then assert_exp True (''datasize constraint'') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__24 :: 32 Word.word) . aset_X t w__24) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -23976,9 +23967,9 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: 64 Word.word) . aset_X t2 w__27))) else - (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__28 :: 16 bits) . + (aget_Mem address dbytes acctype :: ( 16 Word.word) M) \<bind> (\<lambda> (w__28 :: 16 Word.word) . (let data = w__28 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__29 :: ( 'regsize::len)Word.word) . aset_X t w__29)))) ))))))))))))) @@ -24043,7 +24034,7 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: (if pair then assert_exp True (''datasize constraint'') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__39 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__39 :: 32 Word.word) . aset_X t w__39) else ((if (((address \<noteq> ((Align__1 address dbytes :: 64 Word.word))))) then @@ -24059,9 +24050,9 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: 64 Word.word) . aset_X t2 w__42))) else - (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__43 :: 32 bits) . + (aget_Mem address dbytes acctype :: ( 32 Word.word) M) \<bind> (\<lambda> (w__43 :: 32 Word.word) . (let data = w__43 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__44 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__44 :: ( 'regsize::len)Word.word) . aset_X t w__44)))) ))))))))))))) @@ -24126,10 +24117,10 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: (if pair then assert_exp True (''datasize constraint'') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__54 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__54 :: 32 Word.word) . aset_X t w__54) else if (((elsize = (( 32 :: int)::ii)))) then - (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__55 :: 64 bits) . + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__55 :: 64 Word.word) . (let data = w__55 in BigEndian () \<bind> (\<lambda> (w__56 :: bool) . if w__56 then @@ -24154,9 +24145,9 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: 64 Word.word) . aset_X t2 w__59))) else - (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 bits) . + (aget_Mem address dbytes acctype :: ( 64 Word.word) M) \<bind> (\<lambda> (w__60 :: 64 Word.word) . (let data = w__60 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__61 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__61 :: ( 'regsize::len)Word.word) . aset_X t w__61)))) ))))))))))))) @@ -24221,10 +24212,10 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: (if pair then assert_exp True (''datasize constraint'') \<then> (if rt_unknown then - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__71 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M) \<bind> (\<lambda> (w__71 :: 32 Word.word) . aset_X t w__71) else if (((elsize = (( 32 :: int)::ii)))) then - (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__72 :: 128 bits) . + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__72 :: 128 Word.word) . (let data = w__72 in BigEndian () \<bind> (\<lambda> (w__73 :: bool) . if w__73 then @@ -24249,9 +24240,9 @@ definition aarch64_memory_exclusive_pair :: " AccType \<Rightarrow>('datasize:: 64 Word.word) . aset_X t2 w__76))) else - (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__77 :: 128 bits) . + (aget_Mem address dbytes acctype :: ( 128 Word.word) M) \<bind> (\<lambda> (w__77 :: 128 Word.word) . (let data = w__77 in - (ZeroExtend__0 data ((make_the_value regsize :: ( 'regsize::len)itself)) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__78 :: + (ZeroExtend__0 data ((make_the_value regsize )) :: (( 'regsize::len)Word.word) M) \<bind> (\<lambda> (w__78 :: ( 'regsize::len)Word.word) . aset_X t w__78)))) ))))))))))))) @@ -30572,7 +30563,7 @@ definition memory_literal_simdfp_decode :: "(2)Word.word \<Rightarrow>(1)Word.w else UnallocatedEncoding () \<then> return size1) \<bind> (\<lambda> (size1 :: ii) . (SignExtend__0 ((concat_vec imm19 (vec_of_bits [B0,B0] :: 2 Word.word) :: 21 Word.word)) ((make_the_value (( 64 :: int)::ii) :: 64 itself)) - :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 Word.word) . (let offset = w__0 in aarch64_memory_literal_simdfp offset ((ex_int size1)) t)))))))))" @@ -31348,7 +31339,7 @@ definition float_convert_int_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (fltsize, op1, part, rounding, unsigned)))) else if (((v__98 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__0) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31611,7 +31602,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__2 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__0) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31644,7 +31635,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__6 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__1) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31677,7 +31668,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__10 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__2 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__2) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31710,7 +31701,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__14 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__3 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__3) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31743,7 +31734,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__18 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__4 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__4) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31776,7 +31767,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__22 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__5 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__5) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31809,7 +31800,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__26 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__6 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__6) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31842,7 +31833,7 @@ definition float_convert_fix_decode :: "(1)Word.word \<Rightarrow>(1)Word.word (let (op1 :: FPConvOp) = FPConvOp_CVT_FtoI in return (op1, rounding, unsigned)))) else if (((b__30 = (vec_of_bits [B0,B1,B0,B0] :: 4 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__7 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__7) in (let (unsigned :: bool) = ((vec_of_bits [access_vec_dec opcode (( 0 :: int)::ii)] :: 1 Word.word) = (vec_of_bits [B1] :: 1 Word.word)) in @@ -31950,12 +31941,12 @@ definition float_arithmetic_round_decode :: "(1)Word.word \<Rightarrow>(1)Word. else if (((v__101 = (vec_of_bits [B1,B0,B1] :: 3 Word.word)))) then UnallocatedEncoding () \<then> return (exact, rounding) else if (((v__101 = (vec_of_bits [B1,B1,B0] :: 3 Word.word)))) then - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__0 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__0) in (let (exact :: bool) = True in return (exact, rounding)))) else - (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 Word.word) . + (read_reg FPCR_ref :: ( 32 Word.word) M) \<bind> (\<lambda> (w__1 :: 32 bits) . (let (rounding :: FPRounding) = (FPRoundingMode w__1) in return (exact, rounding)))) \<bind> (\<lambda> varstup . (let ((exact :: bool), (rounding :: FPRounding)) = varstup in aarch64_float_arithmetic_round d datasize exact n rounding))))))))))))" @@ -33643,7 +33634,7 @@ definition integer_logical_immediate_decode :: "(1)Word.word \<Rightarrow>(2)Wo else return () ) \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (anon10 :: 32 bits) . (DecodeBitMasks (( 32 :: int)::ii) N imms immr True :: (( 32 Word.word * 32 Word.word)) M) \<bind> (\<lambda> (w__0 :: - ( 32 bits * 32 bits)) . + ( 32 Word.word * 32 Word.word)) . (let (tup__0, tup__1) = w__0 in (let imm = tup__0 in (let anon10 = tup__1 in @@ -33683,7 +33674,7 @@ definition integer_logical_immediate_decode :: "(1)Word.word \<Rightarrow>(2)Wo else return () ) \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (anon10 :: 64 bits) . (DecodeBitMasks (( 64 :: int)::ii) N imms immr True :: (( 64 Word.word * 64 Word.word)) M) \<bind> (\<lambda> (w__1 :: - ( 64 bits * 64 bits)) . + ( 64 Word.word * 64 Word.word)) . (let (tup__0, tup__1) = w__1 in (let imm = tup__0 in (let anon10 = tup__1 in @@ -33727,7 +33718,7 @@ definition integer_bitfield_decode :: "(1)Word.word \<Rightarrow>(2)Word.word \ ((let R1 = (Word.uint immr) in (let S = (Word.uint imms) in (DecodeBitMasks (( 32 :: int)::ii) N imms immr False :: (( 32 Word.word * 32 Word.word)) M) \<bind> (\<lambda> (w__0 :: - ( 32 bits * 32 bits)) . + ( 32 Word.word * 32 Word.word)) . (let (tup__0, tup__1) = w__0 in (let wmask = tup__0 in (let tmask = tup__1 in @@ -33766,7 +33757,7 @@ definition integer_bitfield_decode :: "(1)Word.word \<Rightarrow>(2)Word.word \ ((let R1 = (Word.uint immr) in (let S = (Word.uint imms) in (DecodeBitMasks (( 64 :: int)::ii) N imms immr False :: (( 64 Word.word * 64 Word.word)) M) \<bind> (\<lambda> (w__1 :: - ( 64 bits * 64 bits)) . + ( 64 Word.word * 64 Word.word)) . (let (tup__0, tup__1) = w__1 in (let wmask = tup__0 in (let tmask = tup__1 in @@ -34746,17 +34737,67 @@ definition decode :: "(32)Word.word \<Rightarrow>((register_value),(unit),(exce integer_arithmetic_div_decode sf op1 S Rm opcode2 o1 Rn Rd)))))))))" +(*val fetch_and_execute : unit -> M unit*) + +definition fetch_and_execute :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " fetch_and_execute _ = ( + (whileM () + (\<lambda> unit_var . return True) + (\<lambda> unit_var . + (try_catch ((read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__0 :: 64 bits) . + (aget_Mem w__0 (( 4 :: int)::ii) AccType_IFETCH :: ( 32 Word.word) M) \<bind> (\<lambda> instr . + decode instr))) (\<lambda>x . + (case x of + Error_Undefined _ => exit0 () + | Error_See s => + if(s = (''HINT'')) then (return () ) else (exit0 () ) + | Error_Implementation_Defined _ => exit0 () + | Error_ReservedEncoding _ => exit0 () + | Error_ExceptionTaken _ => exit0 () + )) \<then> + read_reg BranchTaken_ref) \<bind> (\<lambda> (w__1 :: bool) . + if w__1 then write_reg BranchTaken_ref False + else + (read_reg PC_ref :: ( 64 Word.word) M) \<bind> (\<lambda> (w__2 :: 64 bits) . + write_reg PC_ref ((add_vec_int w__2 (( 4 :: int)::ii) :: 64 Word.word)))))))" + + +(*val main : unit -> M unit*) + +definition main :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where + " main _ = ( + (write_reg + PC_ref + ((GetSlice_int ((make_the_value (( 64 :: int)::ii) :: 64 itself)) ((elf_entry () )) (( 0 :: int)::ii) + :: 64 Word.word)) \<then> + (ZeroExtend__0 (vec_of_bits [B0,B0,B1,B1,B1,B1,B0,B0,B0,B0,B0,B0,B0,B0,B0,B0] :: 16 Word.word) + ((make_the_value (( 64 :: int)::ii) :: 64 itself)) + :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__0 :: 64 Word.word) . + (write_reg SP_EL0_ref w__0 \<then> + read_reg PSTATE_ref) \<bind> (\<lambda> (w__1 :: ProcState) . + (write_reg PSTATE_ref (w__1 (| ProcState_D := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> + read_reg PSTATE_ref) \<bind> (\<lambda> (w__2 :: ProcState) . + (write_reg PSTATE_ref (w__2 (| ProcState_A := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> + read_reg PSTATE_ref) \<bind> (\<lambda> (w__3 :: ProcState) . + (write_reg PSTATE_ref (w__3 (| ProcState_I := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> + read_reg PSTATE_ref) \<bind> (\<lambda> (w__4 :: ProcState) . + (write_reg PSTATE_ref (w__4 (| ProcState_F := ((vec_of_bits [B1] :: 1 Word.word))|)) \<then> + (ZeroExtend__0 (vec_of_bits [B1,B0] :: 2 Word.word) ((make_the_value (( 32 :: int)::ii) :: 32 itself)) + :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__5 :: 32 Word.word) . + (write_reg OSLSR_EL1_ref w__5 \<then> write_reg BranchTaken_ref False) \<then> fetch_and_execute () )))))))" + + (*val initialize_registers : unit -> M unit*) definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit),(exception))monad " where " initialize_registers _ = ( undefined_bool () \<bind> (\<lambda> (w__0 :: bool) . (write_reg unconditional_ref w__0 \<then> - (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__1 :: 4 bits) . + (undefined_bitvector (( 4 :: int)::ii) :: ( 4 Word.word) M)) \<bind> (\<lambda> (w__1 :: 4 Word.word) . (write_reg currentCond_ref w__1 \<then> undefined___InstrEnc () ) \<bind> (\<lambda> (w__2 :: InstrEnc) . (write_reg ThisInstrEnc_ref w__2 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__3 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__3 :: 32 Word.word) . (write_reg ThisInstr_ref w__3 \<then> undefined_bool () ) \<bind> (\<lambda> (w__4 :: bool) . (write_reg Sleeping_ref w__4 \<then> @@ -34764,246 +34805,246 @@ definition initialize_registers :: " unit \<Rightarrow>((register_value),(unit) (write_reg PendingPhysicalSError_ref w__5 \<then> undefined_bool () ) \<bind> (\<lambda> (w__6 :: bool) . (write_reg PendingInterrupt_ref w__6 \<then> - (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__7 :: 52 bits) . + (undefined_bitvector (( 52 :: int)::ii) :: ( 52 Word.word) M)) \<bind> (\<lambda> (w__7 :: 52 Word.word) . (write_reg Memory_ref w__7 \<then> undefined_bool () ) \<bind> (\<lambda> (w__8 :: bool) . (write_reg ExclusiveLocal_ref w__8 \<then> undefined_bool () ) \<bind> (\<lambda> (w__9 :: bool) . (write_reg BranchTaken_ref w__9 \<then> (undefined_bitvector (( 128 :: int)::ii) :: ( 128 Word.word) M)) \<bind> (\<lambda> (w__10 :: 128 Word.word) . - (undefined_vector (( 32 :: int)::ii) w__10 :: ( ( 128 Word.word)list) M) \<bind> (\<lambda> (w__11 :: ( 128 bits) list) . + (undefined_vector (( 32 :: int)::ii) w__10 :: ( ( 128 Word.word)list) M) \<bind> (\<lambda> (w__11 :: ( 128 Word.word) list) . (write_reg V_ref w__11 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__12 :: 64 Word.word) . - (undefined_vector (( 31 :: int)::ii) w__12 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__13 :: ( 64 bits) list) . + (undefined_vector (( 31 :: int)::ii) w__12 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__13 :: ( 64 Word.word) list) . (write_reg R_ref w__13 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__14 :: 64 Word.word) . (write_reg PC_ref w__14 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__15 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__15 :: 64 Word.word) . (write_reg VTTBR_EL2_ref w__15 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__16 :: 32 Word.word) . (write_reg VTCR_EL2_ref w__16 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__17 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__17 :: 32 Word.word) . (write_reg VSESR_EL2_ref w__17 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__18 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__18 :: 32 Word.word) . (write_reg VDFSR_ref w__18 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__19 :: 64 Word.word) . (write_reg VBAR_EL3_ref w__19 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__20 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__20 :: 64 Word.word) . (write_reg VBAR_EL2_ref w__20 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__21 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__21 :: 64 Word.word) . (write_reg VBAR_EL1_ref w__21 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__22 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__22 :: 32 Word.word) . (write_reg VBAR_ref w__22 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__23 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__23 :: 64 Word.word) . (write_reg TTBR1_EL2_ref w__23 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__24 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__24 :: 64 Word.word) . (write_reg TTBR1_EL1_ref w__24 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__25 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__25 :: 64 Word.word) . (write_reg TTBR0_EL3_ref w__25 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__26 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__26 :: 64 Word.word) . (write_reg TTBR0_EL2_ref w__26 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__27 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__27 :: 64 Word.word) . (write_reg TTBR0_EL1_ref w__27 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__28 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__28 :: 32 Word.word) . (write_reg TTBCR_ref w__28 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__29 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__29 :: 32 Word.word) . (write_reg TCR_EL3_ref w__29 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__30 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__30 :: 64 Word.word) . (write_reg TCR_EL2_ref w__30 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__31 :: 64 Word.word) . (write_reg TCR_EL1_ref w__31 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__32 :: 32 Word.word) . (write_reg SP_mon_ref w__32 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__33 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__33 :: 64 Word.word) . (write_reg SP_EL3_ref w__33 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__34 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__34 :: 64 Word.word) . (write_reg SP_EL2_ref w__34 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__35 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__35 :: 64 Word.word) . (write_reg SP_EL1_ref w__35 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__36 :: 64 Word.word) . (write_reg SP_EL0_ref w__36 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__37 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__37 :: 32 Word.word) . (write_reg SPSR_und_ref w__37 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__38 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__38 :: 32 Word.word) . (write_reg SPSR_svc_ref w__38 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__39 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__39 :: 32 Word.word) . (write_reg SPSR_mon_ref w__39 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__40 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__40 :: 32 Word.word) . (write_reg SPSR_irq_ref w__40 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__41 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__41 :: 32 Word.word) . (write_reg SPSR_hyp_ref w__41 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__42 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__42 :: 32 Word.word) . (write_reg SPSR_fiq_ref w__42 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__43 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__43 :: 32 Word.word) . (write_reg SPSR_abt_ref w__43 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__44 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__44 :: 32 Word.word) . (write_reg SPSR_EL3_ref w__44 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__45 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__45 :: 32 Word.word) . (write_reg SPSR_EL2_ref w__45 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__46 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__46 :: 32 Word.word) . (write_reg SPSR_EL1_ref w__46 \<then> undefined_signal () ) \<bind> (\<lambda> (w__47 :: signal) . (write_reg SPIDEN_ref w__47 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__48 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__48 :: 32 Word.word) . (write_reg SDER_ref w__48 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__49 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__49 :: 32 Word.word) . (write_reg SDCR_ref w__49 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__50 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__50 :: 32 Word.word) . (write_reg SCTLR_EL3_ref w__50 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__51 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__51 :: 32 Word.word) . (write_reg SCTLR_EL2_ref w__51 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__52 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__52 :: 32 Word.word) . (write_reg SCTLR_EL1_ref w__52 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__53 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__53 :: 32 Word.word) . (write_reg SCTLR_ref w__53 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__54 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__54 :: 32 Word.word) . (write_reg SCR_EL3_ref w__54 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__55 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__55 :: 32 Word.word) . (write_reg SCR_ref w__55 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__56 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__56 :: 64 Word.word) . (write_reg RVBAR_EL3_ref w__56 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__57 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__57 :: 64 Word.word) . (write_reg RVBAR_EL2_ref w__57 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__58 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__58 :: 64 Word.word) . (write_reg RVBAR_EL1_ref w__58 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__59 :: 64 Word.word) . - (undefined_vector (( 5 :: int)::ii) w__59 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__60 :: ( 64 bits) list) . + (undefined_vector (( 5 :: int)::ii) w__59 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__60 :: ( 64 Word.word) list) . (write_reg RC_ref w__60 \<then> undefined_ProcState () ) \<bind> (\<lambda> (w__61 :: ProcState) . (write_reg PSTATE_ref w__61 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__62 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__62 :: 32 Word.word) . (write_reg OSLSR_EL1_ref w__62 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__63 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__63 :: 32 Word.word) . (write_reg OSDLR_EL1_ref w__63 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__64 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__64 :: 32 Word.word) . (write_reg MDSCR_EL1_ref w__64 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__65 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__65 :: 32 Word.word) . (write_reg MDCR_EL3_ref w__65 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__66 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__66 :: 32 Word.word) . (write_reg MDCR_EL2_ref w__66 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__67 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__67 :: 64 Word.word) . (write_reg MAIR_EL3_ref w__67 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__68 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__68 :: 64 Word.word) . (write_reg MAIR_EL2_ref w__68 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__69 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__69 :: 64 Word.word) . (write_reg MAIR_EL1_ref w__69 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__70 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__70 :: 32 Word.word) . (write_reg LR_mon_ref w__70 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__71 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__71 :: 64 Word.word) . (write_reg ID_AA64DFR0_EL1_ref w__71 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__72 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__72 :: 32 Word.word) . (write_reg HVBAR_ref w__72 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__73 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__73 :: 32 Word.word) . (write_reg HSR_ref w__73 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__74 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__74 :: 32 Word.word) . (write_reg HSCTLR_ref w__74 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__75 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__75 :: 64 Word.word) . (write_reg HPFAR_EL2_ref w__75 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__76 :: 32 Word.word) . (write_reg HPFAR_ref w__76 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__77 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__77 :: 32 Word.word) . (write_reg HIFAR_ref w__77 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__78 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__78 :: 32 Word.word) . (write_reg HDFAR_ref w__78 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__79 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__79 :: 32 Word.word) . (write_reg HDCR_ref w__79 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__80 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__80 :: 64 Word.word) . (write_reg HCR_EL2_ref w__80 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__81 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__81 :: 32 Word.word) . (write_reg HCR2_ref w__81 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__82 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__82 :: 32 Word.word) . (write_reg HCR_ref w__82 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__83 :: 32 Word.word) . (write_reg FPSR_ref w__83 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__84 :: 32 Word.word) . (write_reg FPSCR_ref w__84 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__85 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__85 :: 32 Word.word) . (write_reg FPEXC_ref w__85 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__86 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__86 :: 32 Word.word) . (write_reg FPCR_ref w__86 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__87 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__87 :: 64 Word.word) . (write_reg FAR_EL3_ref w__87 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__88 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__88 :: 64 Word.word) . (write_reg FAR_EL2_ref w__88 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__89 :: 64 Word.word) . (write_reg FAR_EL1_ref w__89 \<then> - (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__90 :: 1 bits) . + (undefined_bitvector (( 1 :: int)::ii) :: ( 1 Word.word) M)) \<bind> (\<lambda> (w__90 :: 1 Word.word) . (write_reg EventRegister_ref w__90 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__91 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__91 :: 32 Word.word) . (write_reg ESR_EL3_ref w__91 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__92 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__92 :: 32 Word.word) . (write_reg ESR_EL2_ref w__92 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__93 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__93 :: 32 Word.word) . (write_reg ESR_EL1_ref w__93 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__94 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__94 :: 32 Word.word) . (write_reg ELR_hyp_ref w__94 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__95 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__95 :: 64 Word.word) . (write_reg ELR_EL3_ref w__95 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__96 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__96 :: 64 Word.word) . (write_reg ELR_EL2_ref w__96 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__97 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__97 :: 64 Word.word) . (write_reg ELR_EL1_ref w__97 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__98 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__98 :: 32 Word.word) . (write_reg EDSCR_ref w__98 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__99 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__99 :: 32 Word.word) . (write_reg DSPSR_EL0_ref w__99 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__100 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__100 :: 32 Word.word) . (write_reg DSPSR_ref w__100 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__101 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__101 :: 64 Word.word) . (write_reg DLR_EL0_ref w__101 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__102 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__102 :: 32 Word.word) . (write_reg DLR_ref w__102 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__103 :: 64 Word.word) . - (undefined_vector (( 16 :: int)::ii) w__103 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__104 :: ( 64 bits) list) . + (undefined_vector (( 16 :: int)::ii) w__103 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__104 :: ( 64 Word.word) list) . (write_reg DBGWVR_EL1_ref w__104 \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__105 :: 32 Word.word) . - (undefined_vector (( 16 :: int)::ii) w__105 :: ( ( 32 Word.word)list) M) \<bind> (\<lambda> (w__106 :: ( 32 bits) list) . + (undefined_vector (( 16 :: int)::ii) w__105 :: ( ( 32 Word.word)list) M) \<bind> (\<lambda> (w__106 :: ( 32 Word.word) list) . (write_reg DBGWCR_EL1_ref w__106 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__107 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__107 :: 32 Word.word) . (write_reg DBGPRCR_EL1_ref w__107 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__108 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__108 :: 32 Word.word) . (write_reg DBGPRCR_ref w__108 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__109 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__109 :: 32 Word.word) . (write_reg DBGOSLSR_ref w__109 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__110 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__110 :: 32 Word.word) . (write_reg DBGOSDLR_ref w__110 \<then> undefined_signal () ) \<bind> (\<lambda> (w__111 :: signal) . (write_reg DBGEN_ref w__111 \<then> (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__112 :: 64 Word.word) . - (undefined_vector (( 16 :: int)::ii) w__112 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__113 :: ( 64 bits) list) . + (undefined_vector (( 16 :: int)::ii) w__112 :: ( ( 64 Word.word)list) M) \<bind> (\<lambda> (w__113 :: ( 64 Word.word) list) . (write_reg DBGBVR_EL1_ref w__113 \<then> (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__114 :: 32 Word.word) . - (undefined_vector (( 16 :: int)::ii) w__114 :: ( ( 32 Word.word)list) M) \<bind> (\<lambda> (w__115 :: ( 32 bits) list) . + (undefined_vector (( 16 :: int)::ii) w__114 :: ( ( 32 Word.word)list) M) \<bind> (\<lambda> (w__115 :: ( 32 Word.word) list) . (write_reg DBGBCR_EL1_ref w__115 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__116 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__116 :: 32 Word.word) . (write_reg CPTR_EL3_ref w__116 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__117 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__117 :: 32 Word.word) . (write_reg CPTR_EL2_ref w__117 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__118 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__118 :: 32 Word.word) . (write_reg CPACR_EL1_ref w__118 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__119 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__119 :: 32 Word.word) . (write_reg CONTEXTIDR_EL2_ref w__119 \<then> - (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__120 :: 32 bits) . + (undefined_bitvector (( 32 :: int)::ii) :: ( 32 Word.word) M)) \<bind> (\<lambda> (w__120 :: 32 Word.word) . (write_reg CONTEXTIDR_EL1_ref w__120 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__121 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__121 :: 64 Word.word) . (write_reg APIBKeyLo_EL1_ref w__121 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__122 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__122 :: 64 Word.word) . (write_reg APIBKeyHi_EL1_ref w__122 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__123 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__123 :: 64 Word.word) . (write_reg APIAKeyLo_EL1_ref w__123 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__124 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__124 :: 64 Word.word) . (write_reg APIAKeyHi_EL1_ref w__124 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__125 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__125 :: 64 Word.word) . (write_reg APGAKeyLo_EL1_ref w__125 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__126 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__126 :: 64 Word.word) . (write_reg APGAKeyHi_EL1_ref w__126 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__127 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__127 :: 64 Word.word) . (write_reg APDBKeyLo_EL1_ref w__127 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__128 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__128 :: 64 Word.word) . (write_reg APDBKeyHi_EL1_ref w__128 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__129 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__129 :: 64 Word.word) . (write_reg APDAKeyLo_EL1_ref w__129 \<then> - (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__130 :: 64 bits) . + (undefined_bitvector (( 64 :: int)::ii) :: ( 64 Word.word) M)) \<bind> (\<lambda> (w__130 :: 64 Word.word) . write_reg APDAKeyHi_EL1_ref w__130))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))" |