diff options
| author | Prashanth Mundkur | 2018-04-13 16:59:24 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-04-13 17:40:09 -0700 |
| commit | f8dc91b187ea3995b9f0a34a3d82028e568c273c (patch) | |
| tree | 0b6cf17096edcbe4b12a88272af1071d3416d644 /riscv | |
| parent | bf91deb909304c0c5d4f679f770e7c9f52dd0cd2 (diff) | |
Add <=_u to riscv prelude.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/prelude.sail | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/prelude.sail b/riscv/prelude.sail index 59f1b23e..d90d7f2c 100644 --- a/riscv/prelude.sail +++ b/riscv/prelude.sail @@ -345,16 +345,19 @@ infix 4 <_s infix 4 >=_s infix 4 <_u infix 4 >=_u +infix 4 <=_u val operator <_s = {lem: "slt_vec"} : forall 'n. (bits('n), bits('n)) -> bool val operator >=_s = {lem: "sgteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool val operator <_u = {lem: "ult_vec"} : forall 'n. (bits('n), bits('n)) -> bool val operator >=_u = {lem: "ugteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool +val operator <=_u = {lem: "ulteq_vec"} : forall 'n. (bits('n), bits('n)) -> bool function operator <_s (x, y) = signed(x) < signed(y) function operator >=_s (x, y) = signed(x) >= signed(y) function operator <_u (x, y) = unsigned(x) < unsigned(y) function operator >=_u (x, y) = unsigned(x) >= unsigned(y) +function operator <=_u (x, y) = unsigned(x) <= unsigned(y) val cast bool_to_bits : bool -> bits(1) function bool_to_bits x = if x then 0b1 else 0b0 |