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authorPrashanth Mundkur2018-05-02 11:42:57 -0700
committerPrashanth Mundkur2018-05-02 11:42:57 -0700
commitf439a12639b23ffbf86c440431b632019d298d7f (patch)
tree08881f74f89b34d05ceaccbcc71f7d8e66331058 /riscv
parent47b02bcbf94c24f258cb7d5c67c11d020352b34c (diff)
Tick cycle counter in execute loop.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/main.sail1
-rw-r--r--riscv/riscv_sys.sail4
2 files changed, 5 insertions, 0 deletions
diff --git a/riscv/main.sail b/riscv/main.sail
index b6484755..80a637a0 100644
--- a/riscv/main.sail
+++ b/riscv/main.sail
@@ -8,6 +8,7 @@ val elf_tohost = {
function fetch_and_execute () =
let tohost = __GetSlice_int(64, elf_tohost(), 0) in
while true do {
+ tick_clock();
print_bits("\nPC: ", PC);
/* for now, always fetch a 32-bit value. this would need to
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index e9428448..f0b655f3 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -701,3 +701,7 @@ function init_sys() -> unit = {
mhartid = EXTZ(0b0);
}
+
+function tick_clock() -> unit = {
+ mcycle = mcycle + 1
+}