diff options
| author | Prashanth Mundkur | 2018-06-09 17:25:34 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-09 19:27:24 -0700 |
| commit | ee44f49cf6180734ecfb749a8868b4f146a4bc41 (patch) | |
| tree | c672f396a70391512207081403a54f28fdf16a5d /riscv | |
| parent | 6b98912c895a72e436d0e3b6a72bd751ad29f156 (diff) | |
Some fixes to counteren handling.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 8 | ||||
| -rw-r--r-- | riscv/riscv_sys.sail | 6 |
2 files changed, 8 insertions, 6 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 91af45cf..2b388f7c 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -829,7 +829,7 @@ function readCSR csr : csreg -> xlenbits = 0x303 => mideleg.bits(), 0x304 => mie.bits(), 0x305 => mtvec.bits(), - 0x306 => EXTS(mcounteren.bits()), + 0x306 => EXTZ(mcounteren.bits()), 0x340 => mscratch, 0x341 => mepc, 0x342 => mcause.bits(), @@ -842,7 +842,7 @@ function readCSR csr : csreg -> xlenbits = 0x103 => sideleg.bits(), 0x104 => lower_mie(mie, mideleg).bits(), 0x105 => stvec.bits(), - 0x106 => EXTS(scounteren.bits()), + 0x106 => EXTZ(scounteren.bits()), 0x140 => sscratch, 0x141 => sepc, 0x142 => scause.bits(), @@ -871,7 +871,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = 0x303 => { mideleg = legalize_mideleg(mideleg, value); Some(mideleg.bits()) }, 0x304 => { mie = legalize_mie(mie, value); Some(mie.bits()) }, 0x305 => { mtvec = legalize_tvec(mtvec, value); Some(mtvec.bits()) }, - 0x306 => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTS(mcounteren.bits())) }, + 0x306 => { mcounteren = legalize_mcounteren(mcounteren, value); Some(EXTZ(mcounteren.bits())) }, 0x340 => { mscratch = value; Some(mscratch) }, 0x341 => { mepc = legalize_xepc(value); Some(mepc) }, 0x342 => { mcause->bits() = value; Some(mcause.bits()) }, @@ -884,7 +884,7 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = 0x103 => { sideleg->bits() = value; Some(sideleg.bits()) }, /* TODO: does this need legalization? */ 0x104 => { mie = legalize_sie(mie, mideleg, value); Some(mie.bits()) }, 0x105 => { stvec = legalize_tvec(stvec, value); Some(stvec.bits()) }, - 0x106 => { scounteren = legalize_scounteren(scounteren, value); Some(EXTS(scounteren.bits())) }, + 0x106 => { scounteren = legalize_scounteren(scounteren, value); Some(EXTZ(scounteren.bits())) }, 0x140 => { sscratch = value; Some(sscratch) }, 0x141 => { sepc = legalize_xepc(value); Some(sepc) }, 0x142 => { scause->bits() = value; Some(scause.bits()) }, diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail index fee13dee..b423b08f 100644 --- a/riscv/riscv_sys.sail +++ b/riscv/riscv_sys.sail @@ -571,7 +571,10 @@ function check_Counteren(csr : csreg, p : Privilege) -> bool = (0xC01, User) => scounteren.TM() == true, (0xC02, User) => scounteren.IR() == true, - (_, _) => true + (_, _) => /* no HPM counters for now */ + if 0xC03 <=_u csr & csr <=_u 0xC1F + then false + else true } function check_CSR(csr : csreg, p : Privilege, isWrite : bool) -> bool = @@ -782,7 +785,6 @@ function init_sys() -> unit = { mhartid = EXTZ(0b0); mcounteren->bits() = EXTZ(0b0); - scounteren->bits() = EXTZ(0b0); } function tick_clock() -> unit = { |