diff options
| author | Prashanth Mundkur | 2018-05-07 17:53:00 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-07 17:53:00 -0700 |
| commit | e865a47422dc186d9721cb208ebab1f1a7d7624e (patch) | |
| tree | 691a3c9b09b4c17916893b12509fc1c3bb88c3d1 /riscv | |
| parent | 5322e93e4bf762a1c2bc111956462dcf64cd1083 (diff) | |
Adjust default pte update setting to match spike's default.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_vmem.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail index cc365769..26282d3e 100644 --- a/riscv/riscv_vmem.sail +++ b/riscv/riscv_vmem.sail @@ -255,7 +255,7 @@ union TR39_Result = { TR39_Failure : PTW_Error } -let enable_dirty_update = true +let enable_dirty_update = false val translate39 : (vaddr39, AccessType, Privilege, bool, bool, nat) -> TR39_Result effect {rreg, wreg, wmv, escape, rmem} function translate39(vAddr, ac, priv, mxr, sum, level) = { |