diff options
| author | Prashanth Mundkur | 2018-06-24 10:44:21 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-25 15:36:08 -0700 |
| commit | e80a971905e6f8cf3f9f593bb48d43ad3b7d8702 (patch) | |
| tree | f40b8d674f7aedbdd60128b579f54976ebb00b26 /riscv | |
| parent | ca63a6335856bf41889c51729be0b8a5254968bd (diff) | |
Fix a missed fixme for the sstatus view of mstatus.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index aa68991e..2d3441d7 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1101,7 +1101,7 @@ function readCSR csr : csreg -> xlenbits = 0x3B0 => pmpaddr0, /* supervisor mode */ - 0x100 => mstatus.bits(), /* FIXME: legalize view*/ + 0x100 => lower_mstatus(mstatus).bits(), 0x102 => sedeleg.bits(), 0x103 => sideleg.bits(), 0x104 => lower_mie(mie, mideleg).bits(), |