diff options
| author | Prashanth Mundkur | 2018-10-08 08:43:31 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-10-23 15:32:15 -0700 |
| commit | e3490924e6bce23d3d4b236fdc61c7345a17e814 (patch) | |
| tree | 20b74c110f3c30875a188c671c9e078645c9e516 /riscv | |
| parent | 666128be44e51d6b781aedb6fdc97cd90fa59c3c (diff) | |
RISC-V: various fixes
- add mstatus to cross-check
- fix typo in assembly mapping for lr/sc
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 4 | ||||
| -rw-r--r-- | riscv/riscv_sail.h | 1 | ||||
| -rw-r--r-- | riscv/riscv_sim.c | 1 |
3 files changed, 4 insertions, 2 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index 2cad614e..71ad0137 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -851,7 +851,7 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = } mapping clause assembly = LOADRES(aq, rl, rs1, size, rd) - <-> "lr." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) + <-> "lr" ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) /* ****************************************************************** */ union clause ast = STORECON : (bool, bool, regbits, regbits, word_width, regbits) @@ -916,7 +916,7 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = { } } -mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc." ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) +mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd) <-> "sc" ^ maybe_aq(aq) ^ maybe_rl(rl) ^ size_mnemonic(size) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2) /* ****************************************************************** */ union clause ast = AMO : (amoop, bool, bool, regbits, regbits, word_width, regbits) diff --git a/riscv/riscv_sail.h b/riscv/riscv_sail.h index 17afedbd..f2569b3b 100644 --- a/riscv/riscv_sail.h +++ b/riscv/riscv_sail.h @@ -31,6 +31,7 @@ extern mach_bits zx16, zx17, zx18, zx19, zx20, zx21, zx22, zx23, zx24, zx25, zx26, zx27, zx28, zx29, zx30, zx31; +extern mach_bits zmstatus; extern mach_bits zmepc, zmtval; extern mach_bits zsepc, zstval; diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c index 17e426eb..79c353f9 100644 --- a/riscv/riscv_sim.c +++ b/riscv/riscv_sim.c @@ -247,6 +247,7 @@ int compare_states(struct tv_spike_t *s) passed &= tv_check_csr(s, CSR_MCAUSE, zmcause.zMcause_chunk_0); passed &= tv_check_csr(s, CSR_MEPC, zmepc); passed &= tv_check_csr(s, CSR_MTVAL, zmtval); + passed &= tv_check_csr(s, CSR_MSTATUS, zmstatus); passed &= tv_check_csr(s, CSR_SCAUSE, zscause.zMcause_chunk_0); passed &= tv_check_csr(s, CSR_SEPC, zsepc); |