diff options
| author | Robert Norton | 2018-01-29 15:44:49 +0000 |
|---|---|---|
| committer | Robert Norton | 2018-01-29 15:44:49 +0000 |
| commit | db08fe9880de7f22079a62dc19b0b4f3471cde30 (patch) | |
| tree | 8a9622b9eb0edc5d4b299a128d021874ff33c213 /riscv | |
| parent | b01ce0bcf98f9d20b8abaa8905f1384d5fb29a3a (diff) | |
riscv: add tracing of register writes.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_types.sail | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail index dbec6266..bfb80b49 100644 --- a/riscv/riscv_types.sail +++ b/riscv/riscv_types.sail @@ -66,8 +66,12 @@ and rGPR (r if r > 0) = reg_deref(GPRs[r - 1]) /*val wGPR : forall 'n, 0 <= 'n < 32. (regno('n), regval) -> unit effect {wreg}*/ val wGPR : forall 'n, 0 <= 'n < 32. (regno('n), regval) -> unit effect {wreg} -function wGPR (r, v) = - if (r != 0) then (*GPRs[r - 1]) = v +function wGPR (r, v) = + if (r != 0) then { + (*GPRs[r - 1]) = v; + print_int("GPR ", r); + print_bits("<- ", v); + } function check_alignment (addr : bits(64), width : atom('n)) -> forall 'n. unit = if unsigned(addr) % width != 0 then throw(Error_misaligned_access) else () |