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authorRobert Norton2018-01-30 13:05:17 +0000
committerRobert Norton2018-01-30 13:05:17 +0000
commitcc7f32144f5080eb28cb97ab3c1bb8ae114e84dc (patch)
treec9be133edecd043d28f7d666d939f60ae5ffaa8b /riscv
parent2eafe7b1c5e93c375ffc42f0a9e8efbd64b69f54 (diff)
riscv prelude: add a to_bits function for converting ints to bits of given length.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/prelude.sail3
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/prelude.sail b/riscv/prelude.sail
index dacde107..19b8abd8 100644
--- a/riscv/prelude.sail
+++ b/riscv/prelude.sail
@@ -376,6 +376,9 @@ val vector64 : int -> bits(64)
function vector64 n = __raw_GetSlice_int(64, n, 0)
+val to_bits : forall 'l.(atom('l), int) -> bits('l)
+function to_bits (l, n) = __raw_GetSlice_int(l, n, 0)
+
function break () : unit -> unit = ()
val vector_update_subrange_dec = {ocaml: "update_subrange", lem: "update_subrange_vec_dec"} : forall 'n 'm 'o.