diff options
| author | Brian Campbell | 2018-11-29 16:27:42 +0000 |
|---|---|---|
| committer | Brian Campbell | 2018-11-29 16:27:42 +0000 |
| commit | c9ce945c2bab025b840dc84ca67cfa2395144dae (patch) | |
| tree | bb9ca5a7c564d5c7cf9e28a263f81b6d9c56f241 /riscv | |
| parent | 8ea0e3a21975066207349b83f642b327cd72cb3f (diff) | |
RISC-V: add some missing constraints on compressed instruction encodings
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index ffe862d7..44c2d88c 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -1225,7 +1225,7 @@ union clause ast = C_ADDIW : (bits(6), regbits) /* FIXME: decoding differs for RVC32/RVC64. Below, we are assuming * RV64, and C_JAL is RV32 only. */ -mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd) <-> 0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01 +mapping clause encdec_compressed = C_ADDIW(imm5 @ imm40, rsd) if rsd != zreg <-> 0b001 @ imm5 : bits(1) @ rsd : regbits @ imm40 : bits(5) @ 0b01 if rsd != zreg function clause execute (C_JAL(imm)) = execute(RISCV_JAL(EXTS(imm @ 0b0), ra)) @@ -1270,13 +1270,13 @@ mapping clause assembly = C_ADDI16SP(imm) if imm != 0b000000 <-> "c.addi16sp" ^ /* ****************************************************************** */ union clause ast = C_LUI : (bits(6), regbits) -mapping clause encdec_compressed = C_LUI(imm17 @ imm1612, rd) if rd != zreg & rd != sp <-> 0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01 if rd != zreg & rd != sp +mapping clause encdec_compressed = C_LUI(imm17 @ imm1612, rd) if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 <-> 0b011 @ imm17 : bits(1) @ rd : regbits @ imm1612 : bits(5) @ 0b01 if rd != zreg & rd != sp & imm17 @ imm1612 != 0b000000 function clause execute (C_LUI(imm, rd)) = let res : bits(20) = EXTS(imm) in execute(UTYPE(res, rd, RISCV_LUI)) -mapping clause assembly = C_LUI(imm, rd) if rd != zreg & rd != sp <-> "c.lui" ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm) if rd != zreg & rd != sp +mapping clause assembly = C_LUI(imm, rd) if rd != zreg & rd != sp & imm != 0b000000 <-> "c.lui" ^ spc() ^ reg_name(rd) ^ sep() ^ hex_bits_6(imm) if rd != zreg & rd != sp & imm != 0b000000 /* ****************************************************************** */ union clause ast = C_SRLI : (bits(6), cregbits) |