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authorJon French2018-05-10 13:14:20 +0100
committerJon French2018-05-10 13:14:20 +0100
commitc197e5808e3a6e52820ac28dc4f12aa8d6ba469f (patch)
tree3c677663b51fc694961d29aecce30541bc23821e /riscv
parent2fd802b56d098f547420621b92e7372ec7f55842 (diff)
rtype mapping clauses
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv.sail16
1 files changed, 16 insertions, 0 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index e80604ac..3431c504 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -224,6 +224,22 @@ function clause print_insn (RTYPE(rs2, rs1, rd, op)) =
} in
insn ^ rd ^ ", " ^ rs1 ^ ", " ^ rs2
+val rtype_operands : (regbits, regbits, regbits) <-> string
+mapping rtype_operands = {
+ (rs2, rs1, rd) <-> spaces() ^^ reg_name(rd) ^^ operand_sep() ^^ reg_name(rs1) ^^ operand_sep() ^^ reg_name(rs2)
+}
+
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_ADD) <-> "add" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SUB) <-> "sub" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SLL) <-> "sll" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SLT) <-> "slt" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SLTU) <-> "sltu" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_XOR) <-> "xor" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SRL) <-> "srl" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_SRA) <-> "sra" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_OR) <-> "or" ^^ rtype_operands(rs2, rs1, rd)
+mapping clause assembly = RTYPE(rs2, rs1, rd, RISCV_AND) <-> "and" ^^ rtype_operands(rs2, rs1, rd)
+
/* ****************************************************************** */
union clause ast = LOAD : (bits(12), regbits, regbits, bool, word_width, bool, bool)