Add some checks of current state, and use for the xepc write legalizer.

3 files changed, 44 insertions, 6 deletions

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 9b33a608..c8b3956a 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -552,7 +552,7 @@ function writeCSR (csr : bits(12), value : xlenbits) -> unit =
     0x304 => mie = legalize_mie(mie, value),
     0x305 => mtvec = legalize_tvec(mtvec, value),
     0x340 => mscratch = value,
-    0x341 => mepc = value,
+    0x341 => mepc = legalize_xepc(value),
     0x342 => mcause->bits() = value,
     0x343 => mtval = value,
     0x344 => mip = legalize_mip(mip, value),
@@ -565,7 +565,7 @@ function writeCSR (csr : bits(12), value : xlenbits) -> unit =
     0x104 => sie->bits() = value,
     0x105 => stvec = legalize_tvec(stvec, value),
     0x140 => sscratch = value,
-    0x141 => sepc = value, // FIXME: alignment check/RVC
+    0x141 => sepc = legalize_xepc(value),
     0x142 => scause->bits() = value,
     0x143 => stval = value,
     0x144 => mip->bits() = value,
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 42240e6b..39d611cf 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -1,5 +1,9 @@
 /* machine mode registers */
 
+/* privilege level */
+
+register cur_privilege : Privilege
+
 /* FIXME: currently we have only those used by riscv-tests. */
 
 bitfield Misa : bits(64) = {
@@ -82,6 +86,30 @@ function legalize_mstatus(o : Mstatus, v : xlenbits) -> Mstatus = {
   m
 }
 
+/* machine state utilities */
+
+function cur_Architecture() -> Architecture = {
+  let a : arch_xlen =
+    match (cur_privilege) {
+      Machine => misa.MXL(),
+      Supervisor => mstatus.SXL(),
+      User => mstatus.UXL()
+    };
+  match architecture(a) {
+    Some(a) => a,
+    None()  => internal_error("Invalid current architecture")
+  }
+}
+
+function in32BitMode() -> bool = {
+  cur_Architecture() == RV32
+}
+
+function haveAtomics() -> bool = { misa.A() == true }
+function haveRVC()     -> bool = { misa.C() == true }
+function haveMulDiv()  -> bool = { misa.M() == true }
+function haveFP()      -> bool = { misa.F() == true | misa.D() == true }
+
 /* interrupt registers */
 
 bitfield Minterrupts : bits(64) = {
@@ -190,6 +218,11 @@ function tvec_addr(m : Mtvec, c : Mcause) -> option(xlenbits) = {
 
 /* auxiliary exception registers */
 register mepc : xlenbits
+
+function legalize_xepc(v : xlenbits) -> xlenbits = {
+  v & EXTS(if haveRVC() then 0b110 else 0b100)
+}
+
 register mtval : xlenbits
 register mscratch : xlenbits
 
@@ -372,10 +405,6 @@ union ctl_result = {
   CTL_MRET : unit
 }
 
-/* privilege level */
-
-register cur_privilege : Privilege
-
 /* handle exceptional ctl flow by updating nextPC */
 
 function handle_exception_ctl(cur_priv : Privilege, ctl : ctl_result,
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index 818132c4..1e41133d 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -52,6 +52,15 @@ type amo = bits(1)
 
 /* base architecture definitions */
 enum Architecture = {RV32, RV64, RV128}
+type arch_xlen = bits(2)
+function architecture(a : arch_xlen) -> option(Architecture) = {
+  match (a) {
+    0b01 => Some(RV32),
+    0b10 => Some(RV64),
+    0b11 => Some(RV128),
+    _    => None()
+  }
+}
 
 /* privilege levels */