summaryrefslogtreecommitdiff
path: root/riscv
diff options
context:
space:
mode:
authorPrashanth Mundkur2018-09-17 16:28:30 -0700
committerPrashanth Mundkur2018-10-23 15:32:15 -0700
commitb220094e7f68246cebf528130c3db93081178878 (patch)
tree3324baaeb04b8ccb813d2ec6a2b68bfedbce1725 /riscv
parent7fb28eb35fc7ccca80fcc69c6f727e6d9f383ad1 (diff)
RISC-V: flush logs at each step.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_sim.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c
index c11e6268..982b98f3 100644
--- a/riscv/riscv_sim.c
+++ b/riscv/riscv_sim.c
@@ -182,6 +182,14 @@ int compare_states(struct tv_spike_t *s)
return passed;
}
+void flush_logs(void)
+{
+ fprintf(stderr, "\n");
+ fflush(stderr);
+ fprintf(stdout, "\n");
+ fflush(stdout);
+}
+
void run_sail(void)
{
bool spike_done;
@@ -198,12 +206,14 @@ void run_sail(void)
CONVERT_OF(sail_int, mach_int)(&sail_step, step_no);
stepped = zstep(sail_step);
if (have_exception) goto step_exception;
+ flush_logs();
}
if (stepped) step_no++;
{ /* run a Spike step */
tv_step(s);
spike_done = tv_is_done(s);
+ flush_logs();
}
if (zhtif_done) {