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authorPrashanth Mundkur2018-11-08 09:57:09 -0800
committerPrashanth Mundkur2018-11-08 09:57:09 -0800
commitb00c9423762cc48e56a306159558d0cec92a0085 (patch)
tree84635bf3d191c0d2b2e914709d79fe00384d4c78 /riscv
parent5d102f7f4791bb650652835781ec08f3543063f2 (diff)
RISC-V: fix a typo-induced bug in updating the PTE.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_vmem.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index caafb131..b617d297 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -50,7 +50,7 @@ function update_PTE_Bits(p : PTE_Bits, a : AccessType) -> option(PTE_Bits) = {
let update_a = p.A() == false; // accessed-bit
if update_d | update_a then {
let np = update_A(p, true);
- let np = if update_d then update_D(p, true) else np;
+ let np = if update_d then update_D(np, true) else np;
Some(np)
} else None()
}