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authorPrashanth Mundkur2018-09-18 17:17:36 -0700
committerPrashanth Mundkur2018-10-23 15:32:15 -0700
commita665e2160692e509b75966ceb96b8eb3a84a8375 (patch)
tree9f3ee1e048e8653a3653d9c4c2cca5b093b860c7 /riscv
parentb220094e7f68246cebf528130c3db93081178878 (diff)
RISC-V: Allow Spike linkage to be conditionally enabled.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/Makefile18
-rw-r--r--riscv/riscv_sim.c25
2 files changed, 34 insertions, 9 deletions
diff --git a/riscv/Makefile b/riscv/Makefile
index 88c46823..72abc5da 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -4,14 +4,22 @@ SAIL_DIR ?= $(realpath ..)
SAIL ?= $(SAIL_DIR)/sail
C_WARNINGS ?=
#-Wall -Wextra -Wno-unused-label -Wno-unused-parameter -Wno-unused-but-set-variable -Wno-unused-function
+C_FLAGS = -I ../lib
C_INCS = riscv_prelude.h riscv_platform_impl.h riscv_platform.h
C_SRCS = riscv_prelude.c riscv_platform_impl.c riscv_platform.c
+ENABLE_SPIKE = 0
TV_SPIKE_DIR = /home/mundkur/src/hw/l3/l3riscv
-C_FLAGS = -I $(TV_SPIKE_DIR)/src/cpp -I ../lib
-C_LIBS = -L $(TV_SPIKE_DIR) -ltv_spike -Wl,-rpath=$(TV_SPIKE_DIR)
-C_LIBS += -L $(RISCV)/lib -lfesvr -lriscv -Wl,-rpath=$(RISCV)/lib
-C_LIBS += -lgmp -lz
+SPIKE_FLAGS = -I $(TV_SPIKE_DIR)/src/cpp
+SPIKE_LIBS = -L $(TV_SPIKE_DIR) -ltv_spike -Wl,-rpath=$(TV_SPIKE_DIR)
+SPIKE_LIBS += -L $(RISCV)/lib -lfesvr -lriscv -Wl,-rpath=$(RISCV)/lib
+
+C_LIBS = -lgmp -lz
+
+ifeq ($(ENABLE_SPIKE),1)
+C_FLAGS += $(SPIKE_FLAGS)
+C_LIBS += $(SPIKE_LIBS)
+endif
export SAIL_DIR
@@ -121,6 +129,6 @@ clean:
-rm -f platform_main.native platform coverage.native
-rm -f riscv.vo riscv_types.vo riscv_extras.vo riscv.v riscv_types.v
-rm -f riscv_duopod.vo riscv_duopod_types.vo riscv_duopod.v riscv_duopod_types.v
- -rm -f riscv.c
+ -rm -f riscv.c riscv_model.c riscv_sim
-Holmake cleanAll
ocamlbuild -clean
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c
index 982b98f3..ea6f7377 100644
--- a/riscv/riscv_sim.c
+++ b/riscv/riscv_sim.c
@@ -8,7 +8,12 @@
#include "riscv_platform.h"
#include "riscv_platform_impl.h"
#include "riscv_sail.h"
+
+#ifdef SPIKE
#include "tv_spike_intf.h"
+#else
+struct tv_spike_t;
+#endif
/* Selected CSRs from riscv-isa-sim/riscv/encoding.h */
#define CSR_STVEC 0x105
@@ -27,9 +32,8 @@
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
-struct tv_spike_t *s = NULL;
-
static bool do_dump_dts = false;
+struct tv_spike_t *s = NULL;
static struct option options[] = {
{"enable-dirty", no_argument, 0, 'd'},
@@ -96,13 +100,18 @@ uint64_t load_sail(char *f)
/* for now, override the reset-vector using the elf entry */
void init_spike(const char *f, uint64_t entry)
{
+#ifdef SPIKE
s = tv_init("RV64IMAC");
tv_set_verbose(s, 1);
tv_load_elf(s, f);
tv_reset(s);
tv_set_pc(s, entry);
+#else
+ s = NULL;
+#endif
}
+
void init_sail(uint64_t entry)
{
model_init();
@@ -114,14 +123,18 @@ void init_sail(uint64_t entry)
int init_check(struct tv_spike_t *s)
{
int passed = 1;
+#ifdef SPIKE
passed &= tv_check_csr(s, CSR_MISA, zmisa.zMisa_chunk_0);
+#endif
return passed;
}
void finish(int ec)
{
model_fini();
+#ifdef SPIKE
tv_free(s);
+#endif
exit(ec);
}
@@ -129,6 +142,7 @@ int compare_states(struct tv_spike_t *s)
{
int passed = 1;
+#ifdef SPIKE
// fix default C enum map for cur_privilege
uint8_t priv = (zcur_privilege == 2) ? 3 : zcur_privilege;
passed &= tv_check_priv(s, priv);
@@ -178,6 +192,7 @@ int compare_states(struct tv_spike_t *s)
passed &= tv_check_csr(s, CSR_SCAUSE, zscause.zMcause_chunk_0);
passed &= tv_check_csr(s, CSR_SEPC, zsepc);
passed &= tv_check_csr(s, CSR_STVAL, zstval);
+#endif
return passed;
}
@@ -210,6 +225,7 @@ void run_sail(void)
}
if (stepped) step_no++;
+#ifdef SPIKE
{ /* run a Spike step */
tv_step(s);
spike_done = tv_is_done(s);
@@ -236,9 +252,10 @@ void run_sail(void)
diverged = true;
break;
}
-
- /* TODO: update time */
}
+#endif
+
+ /* TODO: update time */
}
dump_state: