diff options
| author | Prashanth Mundkur | 2018-05-21 20:43:02 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-05-21 20:43:02 -0700 |
| commit | 9c12af3498f4fffc80ef906b343e43a4715dd7e2 (patch) | |
| tree | e47a8a80b8c1fd8d3f496ab02f05250ff4d67a5b /riscv | |
| parent | 3bdbabf5728be48bdceab6958cb7a285c27dbda2 (diff) | |
Add the missed _tags file, and fix a typo.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/_tags | 4 | ||||
| -rw-r--r-- | riscv/riscv_platform.sail | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/riscv/_tags b/riscv/_tags new file mode 100644 index 00000000..56fa3731 --- /dev/null +++ b/riscv/_tags @@ -0,0 +1,4 @@ +<**/*.ml>: bin_annot, annot +"_sbuild": include +<*.m{l,li}>: package(lem), package(linksem), package(zarith) +<platform_main.native>: package(lem), package(linksem), package(zarith) diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail index cfb3b535..75cf9b03 100644 --- a/riscv/riscv_platform.sail +++ b/riscv/riscv_platform.sail @@ -21,7 +21,7 @@ val plat_clint_size = {ocaml: "Platform.clint_size"} : unit -> xlenbits val phys_mem_segments : unit -> (xlenbits, xlenbits) function phys_mem_segments() = // FIXME -// (plat_rom_base (), plat_rom_base ()) :: +// (plat_rom_base (), plat_rom_size ()) :: (plat_ram_base (), plat_ram_size ()) // :: [||] |