diff options
| author | Prashanth Mundkur | 2018-06-07 16:44:59 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-06-07 16:44:59 -0700 |
| commit | 958db3f98da25a435c5fb570309b326f3992ab19 (patch) | |
| tree | a8149b6f27f125a7bc70bc1e90be43e711f2eeb6 /riscv | |
| parent | 910a5d2976e9599cddaaac9549e790b78c1240dd (diff) | |
Fix width guards on htif accesses.
Diffstat (limited to 'riscv')
| -rw-r--r-- | riscv/riscv_mem.sail | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/riscv/riscv_mem.sail b/riscv/riscv_mem.sail index 0fc9ddbc..0cfc3db8 100644 --- a/riscv/riscv_mem.sail +++ b/riscv/riscv_mem.sail @@ -20,10 +20,8 @@ function checked_mem_read(t : ReadType, addr : xlenbits, width : atom('n)) -> fo else if t == Data then { if within_clint(addr, width) then clint_load(addr, width) - /* todo: handle constraint on 'n - else if within_htif_readable(addr, width) + else if within_htif_readable(addr, width) & (1 <= 'n) then htif_load(addr, width) - */ else MemException(E_Load_Access_Fault) } else MemException(E_Load_Access_Fault) @@ -105,7 +103,7 @@ function checked_mem_write(addr : xlenbits, width : atom('n), data: bits(8 * 'n) then phys_mem_write(addr, width, data) else if within_clint(addr, width) then clint_store(addr, width, data) - else if within_htif_writable(addr, width) & sizeof('n) <= 8 // FIXME + else if within_htif_writable(addr, width) & 'n <= 8 then htif_store(addr, width, data) else MemException(E_SAMO_Access_Fault) |