Fix Lem build of RISC-V

2 files changed, 5 insertions, 5 deletions

diff --git a/riscv/riscv_extras.lem b/riscv/riscv_extras.lem
index b93073de..7e217d74 100644
--- a/riscv/riscv_extras.lem
+++ b/riscv/riscv_extras.lem
@@ -76,5 +76,5 @@ let shift_bits_left v m = shiftl v (uint m)
 val print_string : string -> string -> unit
 let print_string msg s = prerr_endline (msg ^ s)
 
-val print_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
-let print_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
+val prerr_bits : forall 'a. Size 'a => string -> bitvector 'a -> unit
+let prerr_bits msg bs = prerr_endline (msg ^ (show_bitlist (bits_of bs)))
diff --git a/riscv/riscv_platform.sail b/riscv/riscv_platform.sail
index 8f4e923a..f3911ba9 100644
--- a/riscv/riscv_platform.sail
+++ b/riscv/riscv_platform.sail
@@ -53,9 +53,9 @@ function clint_load(addr, width) = {
   if addr == MSIP_BASE & ('n == 8 | 'n == 4)
   then MemValue(zero_extend(mip.MSI(), sizeof(8 * 'n)))
   else if addr == MTIMECMP_BASE & ('n == 8)
-  then MemValue(mtimecmp)
+  then MemValue(zero_extend(mtimecmp, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */
   else if addr == MTIME_BASE & ('n == 8)
-  then MemValue(mtime)
+  then MemValue(zero_extend(mtime, 64))
   else MemException(E_Load_Access_Fault)
 }
 
@@ -65,7 +65,7 @@ function clint_store(addr, width, data) = {
     mip->MSI() = data[0] == 0b1;
     MemValue(())
   } else if addr == MTIMECMP_BASE & 'n == 8 then {
-    mtimecmp = data;
+    mtimecmp = zero_extend(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */
     MemValue(())
   } else MemException(E_SAMO_Access_Fault)
 }