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authorPrashanth Mundkur2018-05-03 17:21:39 -0700
committerPrashanth Mundkur2018-05-03 17:21:39 -0700
commit89c7cc3c14ed311553f51f50b1be26fc074b158d (patch)
tree97a93502f0550d1e818d69ebb90ceeb9c9b2dc29 /riscv
parent64a0b2463ac0289f91d8e93384eac93700c074a6 (diff)
Fix a bug in privilege transition, add better transition logging.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_sys.sail19
-rw-r--r--riscv/riscv_types.sail22
2 files changed, 36 insertions, 5 deletions
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 43ca915d..ce5ef321 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -619,7 +619,7 @@ union ctl_result = {
function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : option(xlenbits))
-> xlenbits = {
- cur_privilege = del_priv;
+ print("handling " ^ (if intr then "int#" else "exc#") ^ BitStr(c) ^ " at priv " ^ del_priv);
match (del_priv) {
Machine => {
mcause->IsInterrupt() = intr;
@@ -627,10 +627,12 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
mstatus->MPIE() = mstatus.MIE();
mstatus->MIE() = false;
- mstatus->MPP() = privLevel_to_bits(del_priv);
+ mstatus->MPP() = privLevel_to_bits(cur_privilege);
mtval = tval(info);
mepc = pc;
+ cur_privilege = del_priv;
+
match tvec_addr(mtvec, mcause) {
Some(epc) => epc,
None() => internal_error("Invalid mtvec mode")
@@ -642,7 +644,7 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
mstatus->SPIE() = mstatus.SIE();
mstatus->SIE() = false;
- mstatus->SPP() = match (del_priv) {
+ mstatus->SPP() = match (cur_privilege) {
User => false,
Supervisor => true,
Machine => internal_error("invalid privilege for s-mode trap")
@@ -650,6 +652,8 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
stval = tval(info);
sepc = pc;
+ cur_privilege = del_priv;
+
match tvec_addr(stvec, scause) {
Some(epc) => epc,
None() => internal_error("Invalid stvec mode")
@@ -657,29 +661,34 @@ function handle_trap(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenb
},
User => internal_error("the N extension is currently unsupported")
- }
+ };
}
function handle_exception(cur_priv : Privilege, ctl : ctl_result,
pc: xlenbits) -> xlenbits = {
- print("handling exception ...");
match (cur_priv, ctl) {
(_, CTL_TRAP(e)) => {
let del_priv = exception_delegatee(e.trap, cur_priv);
+ print("trapping from " ^ cur_priv ^ " to " ^ del_priv
+ ^ " to handle " ^ e.trap);
handle_trap(del_priv, false, e.trap, pc, e.excinfo)
},
(_, CTL_MRET()) => {
+ let prev_priv = cur_privilege;
mstatus->MIE() = mstatus.MPIE();
mstatus->MPIE() = true;
cur_privilege = privLevel_of_bits(mstatus.MPP());
mstatus->MPP() = privLevel_to_bits(User);
+ print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
mepc
},
(_, CTL_SRET()) => {
+ let prev_priv = cur_privilege;
mstatus->SIE() = mstatus.SPIE();
mstatus->SPIE() = true;
cur_privilege = if mstatus.SPP() == true then Supervisor else User;
mstatus->SPP() = false;
+ print("ret-ing from " ^ prev_priv ^ " to " ^ cur_privilege);
sepc
}
}
diff --git a/riscv/riscv_types.sail b/riscv/riscv_types.sail
index 5d602d61..2a5a03ec 100644
--- a/riscv/riscv_types.sail
+++ b/riscv/riscv_types.sail
@@ -194,6 +194,28 @@ function exceptionType_to_bits(e) = {
}
}
+val cast exceptionType_to_str : ExceptionType -> string
+function exceptionType_to_str(e) = {
+ match (e) {
+ E_Fetch_Addr_Align => "fisaligned-fetch",
+ E_Fetch_Access_Fault => "fetch-access-fault",
+ E_Illegal_Instr => "illegal-instruction",
+ E_Breakpoint => "breakpoint",
+ E_Load_Addr_Align => "misaligned-load",
+ E_Load_Access_Fault => "load-access-fault",
+ E_SAMO_Addr_Align => "misaliged-store/amo",
+ E_SAMO_Access_Fault => "store/amo-access-fault",
+ E_U_EnvCall => "u-call",
+ E_S_EnvCall => "s-call",
+ E_Reserved_10 => "reserved-0",
+ E_M_EnvCall => "m-call",
+ E_Fetch_Page_Fault => "fetch-page-fault",
+ E_Load_Page_Fault => "load-page-fault",
+ E_Reserved_14 => "reserved-1",
+ E_SAMO_Page_Fault => "store/amo-page-fault"
+ }
+}
+
enum InterruptType = {
I_U_Software,
I_S_Software,