Add a register indicating no trigger/breakpoint support, which allows the breakpoint test to pass.

2 files changed, 14 insertions, 0 deletions

diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index fb8d1c08..8d0f40f8 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -852,6 +852,9 @@ function readCSR csr : csreg -> xlenbits =
     0xC01 => mtime,
     0xC02 => minstret,
 
+    /* trigger/debug */
+    0x7a0 => ~(tselect),    /* this indicates we don't have any trigger support */
+
     _     => { print_bits("unhandled read to CSR ", csr);
                0x0000_0000_0000_0000 }
   }
@@ -884,6 +887,9 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit =
     0x144 => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) },
     0x180 => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) },
 
+    /* trigger/debug */
+    0x7a0 => { tselect = value; Some(tselect) },
+
     _     => None()
   } in
   match res {
diff --git a/riscv/riscv_sys.sail b/riscv/riscv_sys.sail
index 6e5a8844..803531bd 100644
--- a/riscv/riscv_sys.sail
+++ b/riscv/riscv_sys.sail
@@ -404,6 +404,9 @@ register sepc : xlenbits
 register scause : Mcause
 register stval : xlenbits
 
+/* disabled trigger/debug module */
+register tselect : xlenbits
+
 /* csr name printer */
 
 val cast csr_name : csreg -> string
@@ -466,6 +469,8 @@ function csr_name(csr) = {
     0xB80  => "mcycleh",
     0xB82  => "minstreth",
     /* TODO: other hpm counters and events */
+    /* trigger/debug */
+    0x7a0  => "tselect",
     _      => "UNKNOWN"
   }
 }
@@ -515,6 +520,9 @@ function is_CSR_defined (csr : bits(12), p : Privilege) -> bool =
     /* supervisor mode: address translation */
     0x180 => p == Machine | p == Supervisor, // satp
 
+    /* disabled trigger/debug module */
+    0x7a0 => p == Machine,
+
     _     => false
   }