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authorPrashanth Mundkur2018-05-02 09:28:38 -0700
committerPrashanth Mundkur2018-05-02 09:28:38 -0700
commit82ea1539578e6100d9ed5149ab7747d31955688b (patch)
tree5a41d3579f6dcfc79a0c27ac6f94e24b5e931e20 /riscv
parent6e9c2b9d526d81fc0fc28ea3be60ba61436407f1 (diff)
Fix typo in riscv model.
Diffstat (limited to 'riscv')
-rw-r--r--riscv/riscv_vmem.sail2
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/riscv_vmem.sail b/riscv/riscv_vmem.sail
index 4419d5ac..5d209128 100644
--- a/riscv/riscv_vmem.sail
+++ b/riscv/riscv_vmem.sail
@@ -148,7 +148,7 @@ function walk39(vaddr, ac, priv, mxr, sum, ptb, level, global) -> PTW_Result = {
PTW_Success(append(ppn, va.PgOfs()), pte, pte_addr, level, is_global)
}
} else
- PTW_Success(append(pa, va.PgOfs()), pte, pte_addr, level, is_global)
+ PTW_Success(append(pte.PPNi(), va.PgOfs()), pte, pte_addr, level, is_global)
}
}
}